plusargs in verilog

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plusargs are command-line switches supported by the simulator. As per SystemVerilog LRM arguments beginning with the + character will be available using the $test$plusargs and $value$plusargs PLI APIs.

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$test$plusargs (user_string)

$value$plusargs (user_string, variable)

Example

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// tb.v
module tb;
        int a;
        initial begin
                if($test$plusargs("RUNSIM")) begin
                        $display("There is RUNSIM plusargs");
                end else begin
                        $display("There is NO $test$plusargs");
                end
                if($value$plusargs("SEED=%d",a)) begin
                        $display("SEED=%d",a);
                end else begin
                        $display("There is NO $value$plusargs");
                end
        end
endmodule

  • compile

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    $ vlib work
    $ vlog -sv tb.v

  • simulate (QuestaSim)

    • without plusargs

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      $ vsim work.tb -c -do "run; exit"
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      # //
      # Loading sv_std.std
      # Loading work.tb(fast)
      # run
      # There is NO $test$plusargs
      # There is NO $value$plusargs
      #  exit
      # End time: 13:04:23 on Jun 04,2022, Elapsed time: 0:00:01
      # Errors: 0, Warnings: 0

    • with plusargs

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      $ vsim work.tb -c -do "run; exit" +SEED=31 +RUNSIM

      +SEED=31 +RUNSIM

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      # //
      # Loading sv_std.std
      # Loading work.tb(fast)
      # run
      # There is RUNSIM plusargs
      # SEED=         31
      #  exit
      # End time: 13:04:55 on Jun 04,2022, Elapsed time: 0:00:01
      # Errors: 0, Warnings: 0

reference

systemverilog-command-line-input URL: https://www.chipverify.com/systemverilog/systemverilog-command-line-input

PLUSARGS IN SYSTEMVERILOG URL:https://www.theartofverification.com/plusargs-in-systemverilog/