SystemVerilog iff

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@(posedge clk iff(vld));
do_something;

is equivalent to

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forever begin
	@(posedge clk);
    if(vld) break;
end
do_something;

iff is more efficient than if because the expression is recalculated when vld transition rather than clk.

One example, detecting the negative edge of rtr_io.cb.frameo_n[da]

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wait(rtr_io.cb.frameo_n[da] !== 0);
@(rtr_io.cb iff(rtr_io.cb.frameo_n[da] === 0 )); 
$display("[DEBUG HGUO] %0t, rtr_io.cb.frameo_n[da] negedge", $realtime);

image-20220621182019927

[DEBUG HGUO] 6887250.0ns, rtr_io.cb.frameo_n[da] negedge

reference

system verilog中的iff, URL: https://www.francisz.cn/2019/07/18/sv-iff/