Device Aging
Terminology
The most accurate method to calculate the degradation of transistors is the SPICE-level simulation of the whole netlist with application programming interface (API) and industry-standard stress process models
MOSRA: MOSFET reliability analysis Synopsys
RelXpert: Cadence
TMI: TSMC Model Interface, TSMC
OMI: Open Model Interface, Si2 standard,
The Silicon Integration Initiative (Si2) Compact Model Coalition has released the Open Model Interface, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions.OMI allows circuit designers to simulate and analyze such important physical effects as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014.
- TDDB: Time-Dependent Dielectric Breakdown
- HCI: Hot Carrier injection
- BTI: Bias Temperature Instability
- NBTI: Negative Bias Temperature Instability
- PBTI: Positive Bias Temperature Instability
- SHE: Self-Heating Effect
Aging & SHE in FinFET
SHE
Self-Heating & EM
Heat Sink (HS)
guard ring
closer OD help reduce dT
extended gate
source/drain metal stack
BTI
BTI occurs predominantly in PMOS (or p-type or p channel) transistors and causes an increase in the transistor's absolute threshold voltage.
Stress in the case of NBTI means that the PMOS transistor is in inversion; that means that its gate to body potential is substantially below 0 V for analogue circuits or at VGB = −VDD for digital circuits
Higher voltages and higher temperatures both have an exponential impact onto the degradation, induced by NBTI.
NBTI will be accelaerated with thinner gate oxide, at a high temperature and at a high electric field across the oxide region.
During recovery phase where the gate voltage of pMOS is high and stress is removed, the H atoms in the gate oxiede diffuse back to Si-SiO2 interface and the recombination of Si-H bonds reduces the threshold voltage of pMOS.
The net result is an increase in the magnitude of the device threshold voltage |Vt|, and a degradation of the channel carrier mobility.
Caution: The aging model provided by fab may NOT contain recovry effect
HCI
Short-channel MOSFETs may exprience high lateral electric fields if the drain-source voltage is large. while the average velocity of carriers saturate at high fields, the instantaneous velocity and hence the kinetic energy of the carriers continue to increase, especially as they accelerate toward the drain. These are called hot carriers.
In nanometer technologies, hot carrier effects have subsided. This is because the energy required to create an electron-hole pair, \(E_g \simeq 1.12 eV\), is simply not available if the supply voltage is around 1V.
\[ F_E= E \cdot q \]
\[\begin{align} E_k &= F_E \cdot s \\ &= E \cdot q \cdot s \end{align}\]
Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, degrading the current-voltage characteristics of the MOSFET.
The channel hot-electron (CHE) effect is caused by electons flowing in the channel region, from the source to the drain. This effect is more pronounced at large drain-to-source voltage, at which the lateral electric field in the drain end of the channel accelerates the electrons.
Four different hot carrier injectoin mechanisms can be distinguished: - channel hot electron (CHE) injection - drain avalanche hot carrier (DAHC) injection - secondary generated hot electron (SGHE) injection - substrate hot electron (SHE) injection
HCI is more of a drain-localized mechanism, and is primarily a carrier mobility degradation (and a Vt degradation if the device is operated bi-directionally).
For smaller transistor dimensions, CHE dominates the hot carrier degradation effect
The hot-carrier induced damage in nMOS transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both.
The damage caused by hot-carrier injection affects the transistor characteristics by causing a degradation in transconductance, a shift in the threshold voltage, and a general decrease in the drain current capability.
HCI seems to have just a weak temperature dependency. Unlike BTI, it seems to be no or just little recovery. As holes are much "cooler" (i.e. heavier) than electrons, the channel hot carrier effect in nMOS devices is shown to be more significant than in pMOS devices.
Degradation saturation effect
HCI model can reproduce the saturation effect if stress time is long enough
TDDB
TDDB effect is also related to oxide traps. In general, TDDB refers to the loss of isolating properties of a dielectric layer. If this dielectric layer is the gate oxide, TDDB will initially lead to an increase in the gate tunnelling current.
This soft breakdown can already lead to a parametric degradation. After a long accumulation period, TDDB leads to a catastrophic reduction of the channel to gate insulation and thus a functional failure of the transistor.
Scaling drive more concerns in TDDB
waveform-dependent nature
The figure below illustrates the waveform-dependent nature of these mechanisms – as described earlier, BTI and HCI depend upon the region of active device operation. The slew rate of the circuit inputs and output will have a significant impact upon these mechanisms, especially HCI.
- Negative bias temperature instability (NBTI). This is caused by constant electric fields degrading the dielectric, which in turn causes the threshold voltage of the transistor to degrade. That leads to lower switching speeds. This effect depends on the activity level of the circuits, with heavier impact on parts of the design that don’t switch as often, such as gated clocks, control logic, and reset, programming and test circuitry.
- Hot carrier injection (HCI). This is caused by fast-moving electrons inserting themselves into the gate and degrading performance. It primarily occurs on higher-voltage modes and fast switching signals.
- longer channel length help both BTI and HCI
- larger \(V_{ds}\) help BTI, but hurt HCI
- lower temperature help BTI of core device, but hurt that of IO device for 7nm FinFET
MOSRA
MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age analysis
TMI
BTI recovery effect NOT included for N7
Stochastic Nature of Reliability Mechanisms
A fraction of devices will fail
Circuit Simulations
reference
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