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module CN_resetb_sync_cell ( input resetb_in, input clkdst, output resetb_out );
`ifdef USE_VERILOG reg [2:0] resetb_dly; `else wire [2:0] resetb_dly; `endif
`ifdef USE_VERILOG always @(posedge clkdst or negedge resetb_in) if (~resetb_in) resetb_dly <= 3'b000; else resetb_dly <= {resetb_dly[1:0], 1'b1}; `else SDFCNQD4 dont_touch_sync_flop0 ( .SI(1'b0), .SE(1'b0), .CP(clkdst), .CDN(resetb_in), .D(1'b1), .Q(resetb_dly[0]) ); SDFCNQD4 dont_touch_sync_flop1 ( .SI(1'b0), .SE(1'b0), .CP(clkdst), .CDN(resetb_in), .D(resetb_dly[0]), .Q(resetb_dly[1]) ); SDFCNQD4 dont_touch_sync_flop2 ( .SI(1'b0), .SE(1'b0), .CP(clkdst), .CDN(resetb_in), .D(resetb_dly[1]), .Q(resetb_dly[2]) ); `endif
assign resetb_out = resetb_dly[2];
endmodule
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