time format in Verilog
realtime vs time
$realtime
round the current time totimeprecision
$time
round the current time to integer%t
will scale the rounded value to representtimeprecision
,i.e. \([\$\text{realtime}, \$\text{time}]\cdot \$\text{timeunit} / \$\text{timeprecision}\)
https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94062 https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94096
1 | module tb; |
output 1
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6$realtime = 0
$time = 0
$realtime = 1.1002
$time = 1
$realtime %t = 11002
$time %t = 10000
timeunit, timeprecision
The time unit and time precision can be specified in the following
two ways: - Using the compiler directive `timescale
- Using
the keywords timeunit
and timeprecision
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10module D (...);
timeunit 100ps;
timeprecision 10fs;
...
endmodule
module E (...);
timeunit 100ps / 10fs; // timeunit with optional second argument
...
endmodule
The minimum of timeprecision
determine %t
output, the nearest timeunit
and timeprecision
determine the round of $realtime
and $time
. Of
course, the simulator follow the time tick shown by
$realtime
.
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output 1
2
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6
7
8fine: $realtime = 2.7
fine: $time = 3
fine: $realtime %t = 27
fine: $time %t = 30
raw: $realtime = 1.7
raw: $time = 2
raw: $realtime %t = 170
raw: $time %t = 200
questasim cmd
1 | vlib work |