Clocking
excess phase around n-th harmonic
\(\Delta t\) is same for any n-th harmonic
Spurious Tones
Nicola Da Dalt, ISSCC 2012: Jitter Basic and Advanced Concepts, Statistics and Applications [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T5.pdf]
P.E. Allen - 2003 ECE 6440 - Frequency Synthesizers: Lecture 150 β Phase Noise-I [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L150-PhaseNoise-I(2UP).pdf]
Reference Spur
spurs are carrier or clock frequency spectral imperfections measured in the frequency domain just like phase noise. However, unlike phase noise they are discrete frequency components.
Spurs are deterministic
Spur power is independent of bandwidth
Spurs contribute bounded peak jitter in the time domain
Sources of Spurs:
- External (coupling from other noisy block) Supply, substrate, bond wires, etc.
- Internal (int-N/fractional-N operation)
- Frac spur: Fractional divider (multi-modulus and frequency accumulation)
- Ref. spur: PFD/charge pump/analog loop filter non-idealities, clock coupling
Fractional Spur
TODO π
cycle slip
TODO π
frequency divider & phase margin
type-I PLLs
frequency divider weakens the feedback and increases the phase margin
type-II PLLs
frequency divider weakens the feedback and decrease the phase margin
multi-modulus divider
TODO π
Fractional-N
- Dither Feedback Divider Ratio by a delta-sigma modulator
- Frequency Accumulation
Switched Capacitor Banks
Q: why \(R_b\) ?
A: TODO π
Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in RF/millimeter-wave oscillators for 5G communications." PhD diss., 2019.
S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010, pp. 1903-1906
SSC intuition
Due to \(f= K_{vco}V_{ctrl}\), its derivate to \(t\) is
\[ \frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt} \]
For chargepump PLL, \(dV_{ctrl} = \frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[ \frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C} \]
Phase Interpolator (PI)
!!! Clock Edges
And for a phase interpolator, you need those reference clocks to be completely the opposite. Ideally they would be triangular shaped
four input clocks given by the cyan, black, magenta, red
John T. Stonick, ISSCC 2011 tutorial. "DPLL Based Clock and Data Recovery" [https://www.nishanchettri.com/isscc-slides/2011%20ISSCC/TUTORIALS/ISSCC2011Visuals-T5.pdf]
kink problem
B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023.(https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf)
DIV 1.5
TODO π
Xu, Haojie & Luo, Bao & Jin, Gaofeng & Feng, Fei & Guo, Huanan & Gao, Xiang & Deo, Anupama. (2022). A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs. 69. 4238 - 4242. [https://www.researchgate.net/publication/382240520_A_Flexible_073-155_GHz_Single_LC_VCO_Clock_Generator_in_12_nm_CMOS]
False locking
TODO π
- divider failure
- even-stage ring oscillator ( multipath ring oscillators)
- DLL: harmonic locking, stuck locking
clock edge impact
ck1 is div2 of ck0
edge of ck0 is affected differently by ck1
edge of ck1 is affected equally by ck0
Feedback Dividers
- Large values of N lowers the loop BW which is bad for jitter
Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF, Analog and Mixed Signal Circuits and Systems. Aalborg: River Publishers, 2017.
Tri-gate Clock MUX vs Pass-gate Clock MUX
TODO π
Why Type 2 PLL ?
Type: # of integrators within the loop
Order: # of poles in the closed-loop transfer function
Type \(\leq\) Order
- That is, to have a wide bandwidth, a high loop gain is required
- More importantly, the type 1 PLL has the problem of a static phase error for the change of an input frequency
Type 1 PLL with input phase step \(\Delta \phi \cdot u(t)\) \[\begin{align} \Delta \phi\cdot u(t) - K\int_0^{t}\phi _e (\tau)d\tau &= \phi _e (t) \\ \phi _e (0) &= \Delta \phi \end{align}\]
we obtain \(\phi _e (t) = \Delta \phi \cdot e^{-Kt}\cdot u(t)\)
and \(\phi _e(\infty) = 0\)
Divider phase noise & jitter
- Multiplying the frequency of a signal by a factor of N using an ideal frequency multiplier increases the phase noise of the multiplied signal by \(20\log(N)\) dB.
- Similarly dividing a signal frequency by N reduces the phase noise of the output signal by \(20\log(N)\) dB
The sideband offset from the carrier in the frequency multiplied/divided signal is the same as for the original signal.
The 20log(N) Rule
If the carrier frequency of a clock is divided down by a factor of \(N\) then we expect the phase noise to decrease by \(20\log(N)\).The primary assumption here is a noiseless conventional digital divider.
The \(20\log(N)\) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same.
What About Phase Jitter?
We integrate SSB phase noise L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for βbrick wallβ integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.
Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise, L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant.
Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.
[Timing 101: The Case of the Jitterier Divided-Down Clock, Silicon Labs]
[How division impacts spurs, phase noise, and phase]
[Phase Noise Theory: Ideal Frequency Multipliers and Dividers]
PLL bandwidth test
A step response test is an easy way to determine the bandwidth.
Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected response at the output of the loop filter as shown in this block diagram
a first order loop \[ BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)} \] Where \(BW\) is the 3 dB bandwidth in Hz and \(π‘\)β is the 10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7 this relationship is closer to: \[ BW = \frac{0.33}{t}\space\space\space\space \text{(second order system, damping factor = 0.7)} \]
[How can I experimentally find the bandwidth of my PLL?, https://dsp.stackexchange.com/a/73654/59253]
reference
Dennis Fischette, Frequently Asked PLL Questions [https://www.delroy.com/PLL_dir/FAQ/FAQ.htm]
Ian Galton, ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]
Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T6Visuals.pdf]