Digital Equalization & Clock Data Recovery

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Summary of Equalizations

32 to 56 Gbps Serial Link Analysis and Optimization Methods for Pathological Channels [https://docs.keysight.com/eesofapps/files/678068240/678068273/1/1629077956000/tutorial-32-to-56-gbps-serial-link-analysis-optimization-methods-pathological-channels.pdf]

image-20250930160758085

Classification of equalization algorithms

Qasim Chaudhari. A Classification of Equalization Techniques [https://wirelesspi.com/a-classification-of-equalization-techniques/]

CTLE vs. FFE

Keysight Signal Integrity Educational Posts [Post 5: Root Cause of Eye Closure], [Post 6: Eye-opening Experience with CTLE], [Post 7: Eye-opening Experience with FFE]

in the time domain

  • CTLE provide only limited improvement in the pre-cursor ISI, because of the continuous-time, analog nature of CTLE
  • FFE to reduce ISI in both the pre-cursor and post-cursor, because of operating digitally in discrete-time

image-20260227230449898

in the frequency domain

  • CTLE focuses on boosting frequency content at the Nyquist frequency
  • FFE algorithm is selecting taps that effectively amplify the odd harmonics of the Nyquist frequency

image-20260227224843054

In the case of FFE, because of the nature of finite impulse response filter, we would expect amplification and attenuation of different harmonics of Nyquist Frequency

Until 6.5 dB of CTLE DC attenuation, the spread of the single pulse is positive and reaches almost zero at 6.5 dB. As the DC attenuation increases to more than 6.5 dB, the single pulse spectrum is restored too much, resulting in a negative dip at the end of the pulse

image-20260228001551838

the maximum eye opening does not happen at maximum DC attenuation at 9 dB

image-20260228001734379

DFE

Keysight Signal Integrity Educational Posts [Post 8: Eye-opening Experience with DFE]

There are kinks in the eye diagram, the signature of an opened DFE eye is different than other equalizations

DFE algorithm is reducing ISI based on the detected data (symbol)

image-20260228004513829

image-20260228005857811

Since DFE assumes that past symbol decisions are correct. Incorrect decisions from the symbol detector corrupt the filtering of the feedback loop. As a result, the inclusion of the feedforward filter on the front end is crucial in minimizing the probability of error

image

  • because symbol detection is nonlinear, decision feedback equalization is also nonlinear
  • because of the nonlinearity of the DFE response, it must be modeled in the time domain

TX FFE

Jose E. Schutt-Aine, Spring 2024 ECE 546 Lecture - 27 Equalization [http://emlab.uiuc.edu/ece546/Lect_27.pdf]

Sam Palermo. Lecture 7 - Equalization Intro & TX FIR EQ [https://people.engr.tamu.edu/spalermo/ecen689/lecture7_ee720_eq_intro_txeq.pdf]

Kevin Zheng, Boris Murmann, Hongtao Zhang, and Geoff Zhang. Feedforward Equalizer Location Study for High-Speed Serial Systems [https://www.signalintegrityjournal.com/articles/1228-feedforward-equalizer-location-study-for-high-speed-serial-systems]

—, "System-Driven Circuit Design for ADC-Based Wireline Data Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]

Hanumolu, P. K., Wei, G. Y., & Moon, Y. K. (2005). Equalizers for high-speed serial links. International Journal of High Speed Electronics and Systems [https://people.engr.tamu.edu/spalermo/ecen689/hslink_eq_overview_hanumolu_jhses05.pdf]

image-20250928235645823

TX FIR Coefficient Selection with MMSE

Lecture 7: Equalization Introduction & TX FIR Eq [https://people.engr.tamu.edu/spalermo/ecen689/lecture7_ee720_eq_intro_txeq.pdf]

image-20251102114741833

Toeplitz matrix: transforms discrete convolution into \(y=Ax\), where \(x\) is a flattened input vector [Google AI Mode]

tx-ffe-coef-conv.drawio

Lone-Pulse Equalization

image-20251102133644396

tx-ffe-coef-sel.drawio

\[\begin{align} E^TE &=(W^T H^T - Y_{des}^T)(HW-Y_{des})=W^TH^THW+Y_{des}^TY_{des}-W^TH^TY_{des}-Y_{des}^THW \\ &=W^TH^THW+Y_{des}^TY_{des}-2Y_{des}^THW \end{align}\] image-20260116224051584

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h=[0.004, 0.0010, 0.0023, 0.0052, 0.0812, 0.3437, 0.1775, 0.0917, 0.0526,...
    0.0360, 0.0224, 0.0162, 0.0152, 0.0097, 0.0090, 0.0067];
k = length(h);
n = 3;
l = 1;
m2 = 5;
m1 = 1;

H = zeros([k+n+l-2, n+l-1]);
H(1:end-2,1) = h;
H(2:end-1,2) = h;
H(3:end,3) = h;

Ydes = zeros([k+n+l-2, 1]);
Ydes(m1+m2+1,1) = 1;

HT = transpose(H);

Wls = inv(HT*H)*HT*Ydes;

% Wls =
% 
%    -0.8177
%     3.7239
%    -1.7181

Wlsnorm = Wls/sum(norm(Wls,1));

% Wlsnorm =
% 
%    -0.1306
%     0.5949
%    -0.2745

image-20251102154213244

image-20251102154455603

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fcsvf = readtable("hsample_pre10post20.csv");
h= fcsvf.hsample_Design_Point_1_Y;
k = length(h);
n = 8;
l = 1;
m2 = 10;  % channel pre-cursor sample#
m1 = 1;

H = zeros([k+n+l-2, n+l-1]);
for i =1:n
    H(i:i+k-1,i) = h;
end

Ydes = zeros([k+n+l-2, 1]);
Ydes(m1+m2+1,1) = 1;

HT = transpose(H);
Wls = inv(HT*H)*HT*Ydes;


Wlsnorm = Wls/sum(norm(Wls,1));
% Wlsnorm =
% 
%    -0.0926
%     0.6383
%    -0.2691

TX FIR Coefficient Selection with ZFS

Zero Forcing Solution (ZFS)

image-20260208123317710

image-20260208123432755

\(k=-\text{npre}\) \(k=0\); \(y_\text{target}=1\) \(k=\text{npost}\)
\(c_{-\text{npre}}\) \(x_0\) 0
\(c_{-\text{npre}+1}\) \(x_{-1}\) 0
... ... ... ...
\(c_0\) \(x_{-\text{npre}}\) \(x_0\) \(x_{\text{npost}}\)
... ... ... ...
\(c_{\text{npost}-1}\) \(0\) \(x_1\)
\(c_{\text{npost}}\) \(0\) \(x_0\)

image-20260208122312410

image-20260228011345326

image-20260228014012124

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ht = [0.3, 1.0, -0.2, 0.1, 0.0, 0.0];
ytarget = [0;1;0];

x1 = [[1.0 0.3 0.0];
    [-0.2 1.0 0.3];
    [0.1 -0.2 1.0]];

x2 = [[1.0 0.3 0.0];
    [-0.2 1.0 0.3];
    [0.0 -0.2 1.0]];

p1 = inv(x1)*ytarget; % -0.2657    0.8857    0.2037
p2 = inv(x2)*ytarget; % -0.2679    0.8929    0.1786

ht_p1 = conv(ht, p1); % p1 better -> x1
ht_p2 = conv(ht, p2);

% ht_p1 =
%
%    -0.0797         0    1.0000         0    0.0478    0.0204         0         0
%
% ht_p2 =
%
%    -0.0804    0.0000    1.0000   -0.0268    0.0536    0.0179         0         0

subplot(3,1,1)
stem(ht, 'LineWidth', 2); grid on; xlim([0,10])
subplot(3,1,2)
stem(p1, 'LineWidth', 2); hold on; stem(p2, 'LineWidth', 2);
grid on; legend(["p1" "p2"]); xlim([0,10])
subplot(3,1,3)
stem(ht_p1, 'LineWidth', 2); hold on; stem(ht_p2, 'LineWidth', 2)
grid on; legend(["h\_p1" "h\_p2"]); xlim([0,10])

ZFS vs MMSE

minimum mean squared error (MMSE)

There are three major MMSE-based algorithms:

  • least mean square (LMS),
  • normalized least mean square (NLMS)
  • recursive least square (RLS)

image-20260302001712288

image-20260226230127894

  • ZFS eliminates the ISI only at the sampling points that correspond to the equalizer taps. The equalized pulse shows ISI in the intervals between the sample points and at sample points outside the equalizer
  • The Minimum Mean-Square Error Linear Equalizer (MMSE-LE) balances ISI reduction and noise enhancement. The MMSE-LE always performs as well as, or better than, the ZFE

LMS (Least-Mean-Square)

image-20260227221735879

image-20260227222430321

Qasim Chaudhari. Least Mean Square (LMS) Equalizer – A Tutorial [https://wirelesspi.com/least-mean-square-lms-equalizer-a-tutorial/]

image-20260302002909317

CC Chen, Why Background EQ Adaptation? [https://youtu.be/l46OesuNfp4]

image-20260302003217588

TX with SS-LMS

Sam Palermo. ECEN720: High-Speed Links Circuits and Systems Spring 2025 Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq. [https://people.engr.tamu.edu/spalermo/ecen689/lecture8_ee720_rx_adaptive_eq.pdf]

V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012–1026, Apr. 2005 [https://sci-hub.ru/10.1109/JSSC.2004.842863]

—, "Channel-Limited High-Speed Links: Modeling, Analysis and Design," PhD. Thesis, Stanford University, Sep. 2004. [pdf]

—, US7423454B2. High speed signaling system with adaptive transmit pre-emphasis [pdf]

image-20260303003640574

image-20260303004118430

image-20260303004717273 \[ dLev_{n+1} = dLev_n - \frac{\Delta_{dLev}}{2}\left(\frac{\partial e_n^2}{\partial dLev_n}\right) = dLev_n - \Delta _{dLev} e_n\left(\frac{\partial (dLev_n-y_n)}{\partial dLev_n}\right) = \color{red} dLev_n - \Delta _{dLev} e_n \] note \(e_n = dLev_n-y_n\)

Kwangho Lee, SNU phd thesis, Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector [pdf]

image-20260303005850185

note \(e[n] = d[n] - Dlev_n\cdot tx[n]\)

RX with SS-LMS

E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008 [https://sci-hub.ru/10.1109/JSSC.2008.2001871]

Jinhyung Lee, Design of High-Speed Receiver for Video Interface with Adaptive Equalization; Phd thesis, August 2019. [thesis link]

TODO 📅

MLSD (Maximum Likelihood Sequence Detection)

The process is also referred to as Maximum Likelihood Sequence Estimator (MLSE)

image-20240807233152154

image-20240812205534753

image-20240812205613467

[IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s https://static1.squarespace.com/static/5fb343ad64be791dab79a44f/t/63d807441bcd266de258b975/1675102025481/SLIDES_Track02_IBIS_AMI_Modeling_and_Correlation_Tyshchenko.pdf]

M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A. Sheikholeslami, "Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 97-108, 2022, doi: 10.1109/OJCAS.2022.3173686.

Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link. Undergraduate Research Scholars Program. Available electronically from [https://hdl.handle.net/1969.1/166485]

There are several variants of MLSD (Maximum Likelihood Sequence Detection), including:

  • Viterbi Algorithm
  • Decision Feedback Sequence Estimation (DFSE)
  • Soft-Output MLSD

[Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches. https://semiengineering.com/evolution-of-equalization-techniques-in-high-speed-serdes-for-extended-reaches/]

S. Song, K. D. Choo, T. Chen, S. Jang, M. P. Flynn and Z. Zhang, "A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2269-2278, July 2018

[http://contents.kocw.or.kr/document/lec/2012/Korea/KoYoungChai/33.pdf]

David Johns. Partial Response and Viterbi Detecti [https://www.eecg.utoronto.ca/~johns/ece1392/slides/partial_response.pdf]

image-20240824193839108

Leslie Rusch. [https://wcours.gel.ulaval.ca/GEL7114/assets/pdfs/Module4_en_1by1_1.pdf]

Vineel Kumar Veludandi. Maximum likelihood sequence estimation (MLSE) using the Viterbi algorithm [https://github.com/vineel49/mlse]

Bang-Bang CDR

alexander PD or !!PD

The alexander PD locks that edge clock (clkedge) is located at zero crossings of the data. The \(h_{-0.5}\) and \(h_{0.5}\) are equal at the lock point, where the \(h_{-0.5}\) and \(h_{0.5}\) are the cursors located at -0.5 UI and 0.5 UI.

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

Shahramian, Shayan, "Adaptive Decision Feedback Equalization With Continuous-time Infinite Impulse Response Filters" [https://tspace.library.utoronto.ca/bitstream/1807/77861/3/Shahramian_Shayan_201606_PhD_thesis.pdf]

MENIN, DAVIDE, "Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization" [https://air.uniud.it/retrieve/e27ce0ca-15f7-055e-e053-6605fe0a7873/Modelling%20and%20Design%20of%20High-Speed%20Wireline%20Transceivers%20with%20Fully-Adaptive%20Equalization.pdf]

Mueller-Muller CDR

Faisal A. Musa. "HIGH-SPEED BAUD-RATE CLOCK RECOVERY" [https://www.eecg.utoronto.ca/~tcc/thesis-musa-final.pdf]

—."CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS" [https://www.eecg.utoronto.ca/~tcc/faisal_iscas03.pdf]

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9910561]

Jaeduk Han, "Design and Automatic Generation of 60Gb/s Wireline Transceivers" [https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.pdf]

S. Kim, K. K. Tokgoz and G. Kim, "Modeling and Simulation of Mueller-Muller Clock Data Recovery System for PAM-4 Wireline Transceivers," 2025 IEEE/IEIE International Conference on Consumer Electronics-Asia (ICCE-Asia), Busan, Korea, Republic of, 2025, pp. 1-3, doi: 10.1109/ICCE-Asia67487.2025.11263607

image-20240812222307061

Suppose 1-precursor, 1-postcursor — \(y_k = d_{k-1}h_1 + d_k h_0 + d_{k+1}h_{-1}\) \[ \color{red}E[y_k\cdot d_{k-1}] - E[y_k\cdot d_{k+1}] = E[|d_{k-1}|^2h_{1}] - E[|d_{k+1}|^2h_{-1}] =h_1-h_{-1} \] MMPD infers the channel response from baud-rate samples of the received data, the adaptation aligns the sampling clock such that pre-cursor is equal to the post-cursor in the pulse response

image-20260112220639499

note \(E[y_k\cdot d_{k+1}] = E[y_{k-1}\cdot d_{k}] = h_{-1}\)

SS-MMPD

F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010, pp. 366-367, [https://sci-hub.ru/10.1109/ISSCC.2010.5433823]

Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin & Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao & Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits. Electronics. [10. 1888. 10.3390/electronics10161888.]

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. [10.21203/rs.3.rs-1817774/v1]

image-20260112225032307

Suppose \(x_k = d_{k-1}h_1 + d_k h_0 + d_{k+1}h_{-1}\) and \(x_{k-1} = d_{k-2}h_1 + d_{k-1} h_0 + d_{k}h_{-1}\) \[ \color{red}E\{z_k\} = \frac{1}{2} E\{|d_{k-1}|^2h_1\} - \frac{1}{2} E\{|d_{k}|^2h_{-1}\} = \frac{1}{2}(h_1 - h_{-1}) \] image-20240808001449664

image-20260112221328785

image-20240808001501485

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

\(h_1\) is necessary

  • without DFE

    SS-MMPD locks at the point (\(h_1=h_{-1}\)​)

  • With a 1-tap DFE

    1-tap adaptive DFE that forces the \(h_1\) to be zero, the SS-MMPD locks wherever the \(h_{-1}\)​ is zero and drifts eventually.

    Consequently, it suffers from a severe multiple-locking problem with an adaptive DFE

image-20240812232618238

Pattern filter

pattern main cursor
011 \(s_{011}=-h_1+h_0+h_{-1}\)
110 \(s_{110}=h_1+h_0-h_{-1}\)
100 \(s_{100}=h_1-h_0-h_{-1}\)
001 \(s_{001}=-h_1-h_0+h_{-1}\)

During adapting, we make

  • \(s_{011}\) & \(s_{110}\) are approaching to each other
  • \(s_{100}\) & \(s_{001}\) are approaching to each other

Then, \(h_{-1}\) and \(h_1\) are same, which is desired

Symmetrical Pulse

Avago Technologies, US8649476B2 Adjusting sampling phase in a baud-rate CDR using timing skew [pdf]

Y. Jung, H. -J. Shin, J. Kim, S. Lee, J. -S. Park and K. Park, "A 28-Gb/s Receiver with Baud-Rate CDR Employing Integrated Pattern-Based Phase Detector Achieving ISI Invariant Phase Locking," 2025 IEEE Asian Solid-State Circuits Conference (A-SSCC), Daejeon, Korea, Republic of, 2025,

R. Dokania et al., "10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS," 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.jp/10.1109/ISSCC.2015.7062987]

reference

Hall, Stephen H., and Howard L. Heck. Advanced Signal Integrity for High-speed Digital Designs. Wiley : IEEE, 2009 [pdf]

Oh, Kyung, and Xing Yuan. High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting. 1st edition. Prentice Hall, 2011. [pdf]

John M. Cioffi, [Chapter 3 - Equalization], [Chapter 6 - Fundamentals of Synchronization]

David Johns. ECE1392H - Integrated Circuits for Digital Communications - Fall 2001: [Equalization], [Timing Recovery]

B. Kim, "Tutorial: Basics of Equalization Techniques: Channels, Equalization, and Circuits," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022

Masum Hossain, ISSCC2023 T11: "Digital Equalization and Timing Recovery Techniques for ADC-DSP-based Highspeed Links" [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T11.pdf]

—, "LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/SSCS_invited_talk.pdf]

Vivek Telang, 2012, Equalization for High-Speed Serdes: System-level Comparison of Analog and Digital Techniques [https://ewh.ieee.org/r5/denver/sscs/Presentations/2012_08_Telang.pdf]

Gain Kim, 2023. Equalization, Architecture, and Circuit Design for High-Speed Serial Link Receiver [pdf]

A. Amirkhany, "Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links," in IEEE Solid-State Circuits Magazine, vol. 12, no. 1, pp. 25-38, Winter 2020

A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design Optimization for Wireline SerDes Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers [https://www.eecg.utoronto.ca/~johns/nobots/papers/pdf/2024_bazaragani.pdf]

A. Sharif-Bakhtiar, A. Chan Carusone, "A Methodology for Accurate DFE Characterization," IEEE RFIC Symposium, Philadelphia, Pennsylvania, June 2018. [PDF] [Slides – PDF]

Tony Chan Carusone. High Speed Communications Part 11 – SerDes DSP Interactions [https://youtu.be/YIAwLskuVPc]

—, 2022 Optimization Tools for Future Wireline Transceivers [https://www.ieeetoronto.ca/wp-content/uploads/2022/12/UofT-Future-of-Wireline-Workshop-2022.pdf]

Alphawave IP CEO. How DSP is Killing the Analog in SerDes [https://youtu.be/OY2Dn4EDPiA]

S. Kiran, S. Cai, Y. Zhu, S. Hoyos and S. Palermo, "Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processingin Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers," in IEEE Microwave Magazine, vol. 20, no. 5, pp. 62-79, May 2019 [https://sci-hub.se/10.1109/MMM.2019.2898025]

K. K. Parhi, "Design of multigigabit multiplexer-loop-based decision feedback equalizers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 4, pp. 489-493, April 2005 [http://sci-hub.se/10.1109/TVLSI.2004.842935]

T. Toifl et al., "A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os," ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venice Lido, Italy, 2014 [https://sci-hub.se/10.1109/ESSCIRC.2014.6942120]

Daniel Friedman, 2018 Considerations and Implementations for High data Rate Serial Link Design [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto-Nov-2018.pdf]

Hongtao Zhang, DesignCon 2016. PAM4 Signaling for 56G Serial Link Applications − A Tutorial [https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

Cathy Ye Liu, Broadcom Inc. DesignCon 2019: 100+ Gb/s Ethernet Forward Error Correction (FEC) Analysis

—, Broadcom Inc. DesignCon 2024: 200+ Gbps Ethernet Forward Error Correction (FEC) Analysis

Tony Chan Carusone Integrated Systems Laboratory, University of Toronto [https://isl.utoronto.ca/publications/]

Tony Chan Carusone 2022. Optimization Tools for Future Wireline Transceivers [https://www.ieeetoronto.ca/wp-content/uploads/2022/12/UofT-Future-of-Wireline-Workshop-2022.pdf]

Aleksey Tyshchenko, SeriaLink Systems Clinton Walker, Alphawave IP. DesignCon 2022. IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s [https://static1.squarespace.com/static/5fb343ad64be791dab79a44f/t/63d807441bcd266de258b975/1675102025481/SLIDES_Track02_IBIS_AMI_Modeling_and_Correlation_Tyshchenko.pdf]

[https://ibis.org/summits/apr22/tyshchenko.pdf]

[https://www.mathworks.com/content/dam/mathworks/conference-or-academic-paper/ibis-ami-modeling-and-correlation.pdf]

Ali Sheikholeslami Electronics Group, University of Toronto [https://www.eecg.utoronto.ca/~ali/]