Link Models
Time domain modeling
While many different analysis methods exist, including frequency and statistical analysis, time domain results remain the final sign-off

serdespy
Richard Barrie. serdespy — A python library for system-level SerDes modelling and simulation [https://github.com/richard259/serdespy]
python 3.10, samplerate
ifft of sampling continuous-time transfer function
1 | def freq2impulse(H, f): |
Maybe, the more straightforward method is sampling impulse response of continuous-time transfer function directly

1 | import numpy as np |
JLSD
Kevin Zheng. JLSD — Julia SerDes [https://github.com/kevjzheng/JLSD]
boundary conditions internally, remembering states from the previous (sub-)block
1 | out = conv(ir, vbits)*tui/osr |

1 | #call our convolution function; let's keep the input memory zero for now |

Kronecker product to create oversampled waveform
1 | function gen_wvfm(bits; tui, osr) |
normalized to the time step \[ \frac{\alpha}{s+\alpha} \overset{\mathcal{L}^{-1}}{\longrightarrow} \alpha\cdot e^{-\alpha t} \]
The integral of impulse response of low pass RC filter \(\int_{0}^{+\infty} \alpha\cdot e^{-\alpha t}dt =
1\) — sum(ir*dt)
1 | function gen_ir_rc(dt,bw,t_len) |
sum(ir)*dt = 1, i.e. the step response1
1 | using Plots |

generate PAM symbols
here Big Endian
1 | #generate PAM symbols |
1 | function int2bits(num, nbit) |
Detailed Transmitter

1 | function drv_top!(drv, input) |


1 | Vo_conv::Vector = zeros(param.blk_size_osr+lastindex(ir)-1) |

1 | si = [1,0.3,0.5]; |
eye diagram based on
heatmap
1 | function w_gen_eye_simple_test(input,x_npts_ui, x_npts, y_range, y_npts; osr, x_ofst=0) |
Julia's interpolation return a function object that can operate on any values you throw at it
1 | function u_hist(samples, minval, maxval, nbin) |
FIR filter typically is much shorter (<10 taps) than the symbol vector, using FFT convolution might be an overkill. For optimization, a simple shift-and-add filter function can be written

1 | function u_filt(So_conv, input, fir; Si_mem=Float64[]) |
model jitter with fixed simulation time step
warp or remap a "jittery time grid" onto our "uniform time grid"
1 | prev_nui = 4 |
Δtt* vectors store the jitter information at each
edge location
tt_Vext vector is the jittered time grid vector
tt_uniform is the convience vector to remap the jittered
waveform back to our simulation grid
using intermediate voltages embed jitter information at fractional time steps
1 | drv.Δtt_ext[eachindex(drv.Δtt_prev_nui)] .= drv.Δtt_prev_nui # 1 |
1 | drv.Vext[eachindex(drv.V_prev_nui)] .= drv.V_prev_nui # 1 |
1 | function drv_jitter_tvec!(tt_Vext, Δtt_ext, osr) |

itp = linear_interpolation(drv.tt_Vext, drv.Vext) create
linear interpolation object without extrapolation
extrapolation shall not be used to avoid introducing any error
prev_nuidenotes the number of previous symbols to be stitched to the current block's signal to prevent overflow/underflow when jitter is introducedtt_uniformis shifted byprev_nui/2to give wiggle room for sampling "before" and "after" the current block. This is necessary for sinusoidal jitter
a specialized interpolation function to optimize for performance, which support interpolation only
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16 function drv_interp_jitter!(vo, tt_jitter, vi, tt_uniform)
last_idx = 1
for n = eachindex(tt_uniform)
t = tt_uniform[n]
for m = last_idx:lastindex(tt_jitter)-1
if (t >= tt_jitter[m]) && (t < tt_jitter[m+1])
k = (vi[m+1]-vi[m])/(tt_jitter[m+1]-tt_jitter[m])
vo[n] = vi[m] + k*(t-tt_jitter[m])
last_idx = m
break
end
end
end
return nothing
end
1 | drv.Δtt_ext[eachindex(drv.Δtt_prev_nui)] .= drv.Δtt_prev_nui |
channel
1 | noise_Z::Float64 = 50 # termination impedance with thermal noise |
\[ P_\text{n,dBm/Hz} = 10\times\log_{10} (k_B T / 10^{-3}) = 10\times\log_{10} (k_B T) + 30=-174 \]
Then, \(k_B T = 10^{\frac{-174 - 30}{10}}\)
we have
\[ \sigma_n^2 = 4\cdot k_B T \cdot R \cdot \frac{f_s}{2} = k_B T \cdot R \cdot 2f_s= \frac{\color{red}{2}}{T_s} \cdot 10^{\frac{-174 - 30}{10}} \cdot R \]
noise_rms::Float64 = sqrt(2/param.dt*10^((noise_dbm_hz-30.0)/10)rather thansqrt(0.5/param.dt*10^((noise_dbm_hz-30.0)/10)
run simulation by recursion
1 | function run_blk_iter(trx, idx, n_tot_blk, blk_func::Function) |
Sam Palermo's
continuous time filter (channel, ctle); impulse response
digital filter (FFE, DFE): repmat by samples per UI
Sam Palermo. ECEN 720: High-Speed Links Circuits and Systems [https://people.engr.tamu.edu/spalermo/ecen720.html]
repmat
1 | >> repmat([1,2,3], 3, 1) |
1 | >> reshape(repmat([1,2,3], 3, 1), 1, 3*3) |
Generating an Impulse Response from S-Parameters
ECEN720: High-Speed Links Circuits and Systems Spring 2025 [https://people.engr.tamu.edu/spalermo/ecen689/lecture3_ee720_tdr_spar.pdf]

spline: Cubic spline data interpolation
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6 Hm_ds_interp=spline(fds_m,Hm_ds,f_ds_interp); % Interpolate for FFT point number
figure(Name='spline function')
plot(fds_m, Hm_ds, '-rs', LineWidth=2)
hold on
plot(f_ds_interp, Hm_ds_interp, '--bo', LineWidth=2)
legend('org', 'interpolated'); grid on
impulse response from ifft of interpolated frequency response
1 | % https://people.engr.tamu.edu/spalermo/ecen689/xfr_fn_to_imp.m |

1 | subplot(3,1,1) |
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2 plot(ch1_freqs,20*log10(abs(ch1)),'-b',Freq'*1e-9,20*log10(abs(H21)),'-r');
legend('From Impulse Response','Measured');
plot eye diagram

1 | % https://people.engr.tamu.edu/spalermo/ecen689/channel_data.m |
If your 2D array represents multiple data series (e.g., each column is a separate line series sharing the same x-axis values), the
plot()function is the most straightforward method.
[https://people.engr.tamu.edu/spalermo/ecen689/lecture4_ee720_channel_pulse_model.pdf]

1 | % https://people.engr.tamu.edu/spalermo/ecen689/tx_eq.m |
TX FIR Tap Resolution

1 | % https://people.engr.tamu.edu/spalermo/ecen689/tx_eq.m |
CTLE modeling by impulse response
Given two impulse response \(h_0(t)\), \(h_1(t)\) and \(h_0(t)*h_1(t) = h_{tot}(t)\), we have \[ T_s h_0(kT_s) * T_sh_1(kT_s) = T_s h_{tot}(kT_s) \]
To use the
filterfunction with thebcoefficients from an FIR filter, usey = filter(b,1,x)
CTLE response from frequency response using
ifft
data-driven frequency table
1 | % https://people.engr.tamu.edu/spalermo/ecen689/gen_ctle.m |
CTLE response from pole/zero using
tf & impulse
1 | H21 = tf(); |
CTLE response from pole/zero using
bilinear discretization
analytical pole/zero transfer function, [Google AI Mode]


1 | % https://people.engr.tamu.edu/spalermo/ecen689/gen_ctle.m |
rx dfe
pseudo linear equalizer
1 | % https://people.engr.tamu.edu/spalermo/ecen689/channel_data_pulse_pda_dfe.m |
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7 plot(m_dr, '--', LineWidth=2); hold on
plot(data_channel(channel_delay:end), '--', LineWidth=2)
hold on
plot(data_channel(channel_delay+dfe_fb_offset:channel_delay+dfe_fb_offset+size(m_dfe_dr,2)-1), '--', LineWidth=2)
plot(m_dfe_dr, LineWidth=2); plot(data_channel_dfe, LineWidth=2)
xlim([1000, 3000]); ylim([-0.05, 0.3]); xlabel('samples'); grid on
legend('lshift channel\_delay', 'lshift channel\_delay + 1/2UI', 'dfe filter', 'after dfe')
DaVE
Byongchan Lim. DaVE — tools regarding on analog modeling, validation, and generation, [https://github.com/StanfordVLSI/DaVE]
TODO 📅
Statistical Eye
Sanders, Anthony, Michael Resso and John D'Ambrosia. “Channel Compliance Testing Utilizing Novel Statistical Eye Methodology.” (2004) [https://people.engr.tamu.edu/spalermo/ecen689/stateye_theory_sanders_designcon_2004.pdf]
X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3082208]
HSPICE® User Guide: Signal Integrity Modeling and Analysis, Version Q-2020.03, March 2020
IA Title: Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]
J. Park and D. Kim, "Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review," in IEEE Access, vol. 12, pp. 22880-22891, 2024 [pdf]
StatOpt
Savo Bajic, ECE1392, Integrated Circuits for Digital Communications: StatOpt in Python [https://savobajic.ca/projects/academic/statopt] [https://www.eecg.utoronto.ca/~ali/statopt/main.html]
TODO 📅
pystateye
Chris Li. pystateye - A Python Implementation of Statistical Eye Analysis and Visualization [https://github.com/ChrisZonghaoLi/pystateye]
TODO 📅
other framework
pyBERT
David Banas. pyBERT: Free software for signal-integrity analysis [https://github.com/capn-freako/PyBERT], [intro]
—. Free yourself from IBIS-AMI models with PyBERT [https://www.edn.com/free-yourself-from-ibis-ami-models-with-pybert/]
TODO 📅
PyChOpMarg
David Banas. Python implementation of COM, as per IEEE 802.3-22 Annex 93A. [https://github.com/capn-freako/PyChOpMarg]
CC Chen. Why Channel Operating Margin? [https://youtu.be/mrXur-WbrR8]
TODO 📅
mmse_dfe
Chris Li, jointly optimizing feed-forward equalizer (FFE) and decision-feedback equalizer (DFE) tap weights [https://github.com/ChrisZonghaoLi/mmse_dfe]
John M. Cioffi, Chapter 3 - Equalization [https://cioffi-group.stanford.edu/doc/book/chap3.pdf]
TODO 📅
Helper Functions
int2bits
1 | function int2bits(num, nbit) |
PRBS Generator

1 | # Julia |
1 | %% Matlab |

[https://github.com/kevjzheng/JLSD/blob/main/Pluto%20Notebooks/pdf/JLSD_pt1_background.pdf]
PRBS Checker
previous bit determine current bit
- current LSFR generate
btst - compare
bstwith currentbrcv - push current
brcvinto LSFR
Analog Signals Representation
Ben Yochret Sabrine, 2020, "BEHAVIORAL MODELING WITH SYSTEMVERILOG FOR MIXED-SIGNAL VALIDATION" [https://di.uqo.ca/id/eprint/1224/1/Ben-Yochret_Sabrine_2020_memoire.pdf]


Reference
MATLAB® and Simulink® RF and Mixed Signal [https://www.mathworks.com/help/overview/rf-and-mixed-signal.html]
Lim, Byong Chan, M. Horowitz, "Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1, pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]
—, Ph.D. Dissertation 2012. "Model validation of mixed-signal systems" [https://stacks.stanford.edu/file/druid:xq068rv3398/bclim-thesis-submission-augmented.pdf]
—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog Design: Enabling Mixed-Signal System Validation," in IEEE Design & Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim, Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
S. Liao and M. Horowitz, "A Verilog piecewise-linear analog behavior model for mixed-signal validation," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013 [https://sci-hub.se/10.1109/CICC.2013.6658461]
—, M. Horowitz, "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2229-2235, Aug. 2014 [https://sci-hub.se/10.1109/TCSI.2014.2332265]
—,Ph.D. Dissertation 2012. Verilog Piecewise Linear Behavioral Modeling For Mixed-Signal Validation [https://stacks.stanford.edu/file/druid:pb381vh2919/Thesis_submission-augmented.pdf]
Ji-Eun Jang et al. “True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example”. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. 2012 [https://sci-hub.se/10.1109/CICC.2012.6330558]
—, Si-Jung Yang, and Jaeha Kim. “Event-driven simulation of Volterra series models in SystemVerilog”. In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference. 2013 [https://sci-hub.se/10.1109/CICC.2013.6658460]
—, Ph.D. Dissertation 2015. Event-Driven Simulation Methodology for Analog/Mixed-Signal Systems [file:///home/anon/Downloads/000000028723.pdf]
"Creating Analog Behavioral Models VERILOG-AMS ANALOG MODELING" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/CDN_Creating_Analog_Behavioral_Models.pdf]
Rainer Findenig, Infineon Technologies. "Behavioral Modeling for SoC Simulation Bridging Analog and Firmware Demands" [https://www.coseda-tech.com/files/Files/Dokumente/Behavioral_Modeling_for_SoC_Simulation_COSEDA_UGM_2018.pdf]
CC Chen. Why Efficient SPICE Simulation Techniques for BB CDR Verification? [https://youtu.be/Z54MV9nuGUI]
T. Wen and T. Kwasniewski, "Phase Noise Simulation and Modeling of ADPLL by SystemVerilog," 2008 IEEE International Behavioral Modeling and Simulation Workshop, San Jose, CA, USA, 2008 [slides, paper]
Jaeha Kim,Scientific Analog. UCIe PHY Modeling and Simulation with XMODEL [pdf]
S. Katare, "Novel Framework for Modelling High Speed Interface Using Python for Architecture Evaluation," 2020 IEEE REGION 10 CONFERENCE (TENCON), Osaka, Japan, 2020 [https://sci-hub.se/10.1109/TENCON50793.2020.9293846]
G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link Foundations Standards, Link Budgets & Models," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95 [https://youtu.be/OABG3u2H2J4] [https://picture.iczhiku.com/resource/ieee/SHKhwYfGotkIymBx.pdf]
Mathuranathan Viswanathan. Digital Modulations using Matlab: Build Simulation Models from Scratch



