Physical Layer (PHY)

| Sublayer | Layer Type | Primary Responsibility | Key Processes |
|---|---|---|---|
| PCS | Digital | Data Preparation | Encoding (64b/66b), Scrambling, Alignment |
| PMA | Mixed-Signal | Serialization & Timing | SerDes, Clock Recovery, Data Framing |
| PMD | Analog/Physical | Medium Interface | Signal Conversion (Optics/Electrical), MDI Interface |
RX Elastic Buffer
Joe Winkles, Elastic Buffer Implementations in PCI Express Devices [pdf]
wikibooks, Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Cascades of Buffers and CDRs, delays and tolerance [link]

bridge between Recovered Clock Domain and Local Clock Domain


The periodic slips (under or overflows) depend on buffer depth \(N\) and is approximately given by \[ T_{per} = \frac{N/2 - 1}{\Delta f} \]

1 | f0 = 1; |

Lane-to-Lane Skew
TODO ๐
First In First Out (FIFO)
Clifford E. Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons [pdf]
TODO ๐
Scrambler
TODO ๐
Link Training and Initialization (LTSSM)
TODO ๐
Viterbi-based MLSD
M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A. Sheikholeslami, "Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 97-108, 2022 [https://sci-hub.jp/10.1109/OJCAS.2022.3173686]
Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link. Undergraduate Research Scholars Program. Available electronically from [https://hdl.handle.net/1969.1/166485]
S. Song, K. D. Choo, T. Chen, S. Jang, M. P. Flynn and Z. Zhang, "A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2269-2278, July 2018 [https://sci-hub.jp/10.1109/TCSI.2017.2775619]
Vineel Kumar Veludandi. Maximum likelihood sequence estimation (MLSE) using the Viterbi algorithm [https://github.com/vineel49/mlse]
David Banas, Keysight, DesignCon 2026, Tutorial โ Understanding the Viterbi Decoder
A. C. Singer, N. R. Shanbhag and H. -m. Bae, "Electronic dispersion compensation," in IEEE Signal Processing Magazine, vol. 25, no. 6, pp. 110-130, November 2008 [https://shanbhag.ece.illinois.edu/publications/singer-spm-2008.pdf]
โ, ISSCC2007 T10: Fundamentals of Electronic Dispersion Compensation (EDC)

Maximum-Likelihood Sequence Detection performed by Viterbi on the ISI trellis induced by the channel

Simple soft-decision voting


Simple soft-decision voting can use more information than a slicer, but without a trellis/path-consistency rule, it can create impossible or unstable decision histories.
Viterbi Decoder


Pre-cursor \(h_{-1}=0.3\), Current (main) cursor \(h_0=0.8\), Post-cursor \(h_1=0.2\)


trellis depth = N = 3 (consistent with 8 states); the 4 is the number of observation samples in that particular walk-through, i.e. the time axis โ a different thing that unfortunately shares the label "N" on the slide
David Banas, PyBERT [https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py]
As currently built, ViterbiDecoder_ISI models
post-cursor ISI only. _states[ix][-1]
selecting the last element as the current symbol is consistent with
that
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/bert.py |
- DFE (kept light): recover timing, slice levelsโbits, and optionally trim the far ISI tail beyond the trellis window โ but not aggressively cancel the near post-cursors.
- Viterbi: handle the near post-cursor ISI (the cursor + Nโ1 taps) that was intentionally left in, via MLSE โ which tolerates a closed eye where the DFE's hard decisions would error-propagate
| Group | Members | When set | Role |
|---|---|---|---|
| Static model | _states, _expecteds, _trans,
_sigma, _v_prob |
once, in __init__ |
the time-invariant channel/decoder description |
| Dynamic state | _trellis |
mutated every step_trellis |
the evolving survivor metrics/back-pointers |
All three derive purely from the constructor args
(L, N, pulse_resp_samps):
_statesโ theLแดบsymbol-window combinations (all_combs). Fixed because the alphabet and memory depth don't change._expectedsโ the noiseless expected sample per state,ฮฃ h[n]ยทs[-(n+1)]. Fixed because it bakes inpulse_resp_samps(the ISI taps)._transโ the shift-register adjacency (which state can follow which), as a row-normalized PMF. Fixed because the trellis topology is structural, independent of data.
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py |
\[ \mathcal{N}(v;0,\sigma^2)=\dfrac{1}{\sqrt{2\pi\sigma^2}}e^{-v^2/2\sigma^2} \]
v_prob(ฮด) returns the probability (density) of seeing a
noise voltage error ฮด under a zero-mean Gaussian with
standard deviation sigma. It's the emission
probability of the Viterbi algorithm.
In short: v_prob is the decoder's noise model โ a fast
Gaussian-likelihood lookup that converts "how far is this sample from
what state s predicts?" into "how probable is that?", which
is exactly the data-driven term the Viterbi trellis needs
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py |
| size | set by | |
|---|---|---|
depth (len(trellis), # columns) |
N |
N UIs (cursor + Nโ1 post-cursors) |
width (len(trellis[-1]), # rows) |
Lแดบ = num_states |
L and N via all_combs |
- Length of returned list gives trellis depth
- Length of all inner lists should equal
len(states). - Each location in the trellis matrix contains the
probability and previous state index
for the corresponding state
( probability , prev_state_index )
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py |
The core Viterbi recursion
trellis[-1][r][0] * self.trans[r][s] * self.prob(s, x) โ
the candidate path metric for arriving at current state s
through predecessor r \[
P(r \to s \mid x) = \underbrace{\text{trellis}[-1][r][0]}{\text{(1)
survivor prob of } r} \times \underbrace{\text{trans}[r][s]}{\text{(2)
transition } r\to s} \times \underbrace{\text{prob}(s, x)}_{\text{(3)
emission of } s}
\]
trellis[-1][r][0]โ the survivor probability of the predecessor staterself.trans[r][s]โ the transition probabilityr โ sself.prob(s, x)โ the emission probability of current statesgiven observationx
\[ P(\text{path ending } r{\to}s,\ \text{obs}=x) = P(r)\cdot P(s\mid r)\cdot P(x\mid s) \]
decode() has three phases
| Phase | Samples | Decisions emitted? |
|---|---|---|
| Prime | samps[0 : N] |
No โ just fill the depth-N window |
| Run | samps[N : ] |
Yes โ one decided symbol per step |
| Purge | (none) | Flush the Nโ1 symbols still held in the window |
path performs the back-trace
(trace-back) step of the Viterbi algorithm: starting from the
most-likely state in the newest column, it follows the back-pointers
leftward through the trellis to recover the maximum-likelihood
sequence of states held in the current window.
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py |
At the end you drain the Nโ1 symbols still sitting in
the trellis
1 | # https://github.com/capn-freako/PyBERT/blob/master/src/pybert/models/viterbi.py |
Standalone demo
1 | """ |

Proakis, John G., and Masoud Salehi. Digital Communications. 5th ed. McGraw-Hill, 2008. [pdf]

whitening filter

Partial Response
David Johns, Partial Response and Viterbi Detection [https://www.eecg.utoronto.ca/~johns/ece1392/slides/partial_response.pdf]
Dariush Dabiri , Enabling Improved DSP Based Receivers for 100G Backplane [https://www.ieee802.org/3/bj/public/sep11/dabiri_01_0911.pdf]
Partial Response Signaling (PRS) and Maximum Likelihood Sequence Detection (MLSD) are paired together to maximize data rates in bandwidth-limited, noisy channels like fiber optics, magnetic hard drives, and high-speed backplanes

Flit (flow control unit)
TODO ๐
FBER (First Bit Error Rate)
TODO ๐
1 | FBER is like BER except that, for example, a 10-bit burst error counts as one FBER but would count as 10 BER. |
FEC (Feed-Forward Error Correction)
Cathy Liu, Broadcom. DesignCon 2024: 200+ Gbps Ethernet Forward Error Correction (FEC) Analysis
โ, Broadcom, DesignCon 2026 What is FEC and how do I use it in 200G/400G/800G/1.6T Ethernet?
Leslie A. Rusch , GEL7114 Digital Communications, Module 5 - Error Correcting Codes [https://wcours.gel.ulaval.ca/GEL7114/assets/pdfs/Module5_en_1by1_1.pdf]
1 | Steve Glaser, How to understand FBER? |
TODO ๐
| Feature | Intersymbol Interference (ISI) | Forward Error Correction (FEC) |
|---|---|---|
| Definition | A signal distortion where symbols overlap. | A coding technique to detect/fix bit errors. |
| Origin | Unintentional (caused by channel physics). | Intentional (added by the system designer). |
| Data Impact | Smears pulses together, making them unreadable. | Adds redundant bits to protect original data. |
| Primary Cause | Multipath fading and limited bandwidth. | Noise, interference, and signal attenuation. |
| Relationship | Negative dependency (interference). | Positive dependency (structured redundancy). |
| Typical Solution | Equalization or Pulse Shaping (e.g., Root-Raised Cosine). | Block Codes (Reed-Solomon) or Convolutional Codes (LDPC). |
| Goal | To clean the signal before decoding. | To recover the data after decoding errors. |
Reed-Solomon (RS) codes
RS is a forward error-correction (FEC) algorithm used to correct data corruption after it has been received
ECC (Error Control Coding)
Takayuki Kawahara, ISSCC2007 T5: Error-Correcting Codes for Memories
TODO ๐
PCIeยฎ Retimer Latency
Jay Li, Product Marketing Director, kandou, T3S02_PCIe Retimer Latency



PCI Express Standards Information
CLB: Compliance Load Board (System Board)
CBB: Compliance Base Board (Add-in Card)
NCB (Non-ChangeBar): A clean version of the official specification document that contains the full text of the updated standard
CB (ChangeBar): A version that highlights only the changes and additions made from the previous version of the specification. The added or modified lines typically have a vertical bar (a changebar) in the margin for easy scanning
Base Specification: The PCI Express Base describes the architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
CEM (Card Electromechanical) Specification: The PCI Express CEM specifications define an implementation for small form factor PCI Express cards
reference
John Swindle, PCIe 1.1 Phy Design Considerations
Hidehiro Toyoda, Shinji Nishimura, and Masato Shishikura, PMD architecture with skew compensation mechanism for parallel link [https://www.ieee802.org/3/hssg/public/nov06/nishimura_01_1106.pdf]
Kamesh Velmail, Samsung, Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs [pdf]
Marianne Nourzad (Intel), DesignCon 2022. Transmitter Jitter Measurement Methodologies for PAM-4 IOs