KNOW-HOW

Before inserting sign-off metal fill, stream out a GDSII stream file of the current database. Specify the mapping file and units that match with the rule deck you specify while inserting metal fill. If necessary, include the detailed-cell (-merge option) Graphic Database System (GDS).

PVS:

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streamOut -merge $GDSFile -mode ALL -units $GDSUNITS -mapFile $GDSMAP -outputMacros pvs.fill.gds
run_pvs_metal_fill -ruleFile $DUMMYRULE -defMapFile $DEFMAP -gdsFile pvs.fill.gds -cell [dbgDesignName]

Pegasus:

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streamOut -merge $GDSFile -mode ALL -units $GDSUNITS -mapFile $GDSMAP -outputMacros pegasus.fill.gds
run_pegasus_metal_fill -ruleFile $DUMMYRULE -defMapFile $DEFMAP -gdsFile pegasus.fill.gds -cell [dbgDesignName]

Just replace run_pvs_metal_fill with run_pegasus_metal_fill

Note: Innovus metal fill (e.g. addMetalFill, addViaFill, etc.) does not support 20nm and below node design rules. We strongly recommend the Pegasus/PVS metal fill solution for 20nm and below. If you have sign-off metal fill rule deck for 28nm and above available, we recommend you to move to Pegasus/PVS solution too.

1. trimMetalFillNearNet does not check DRC rules. It only removes the metal fill with specified spacing

2. Do not perform ECO operations after dump in sign-off metal fill (by run_pvs_metal_fill or run_pegasus_metal_fill), especially, at 20nm and below nodes.

3. If you perform an ECO action, the tool cannot get DRC clean because trimMetalFill does not support 20nm and below node design rules.

4. The sign-off metal fill typically does not cause DRC issues with regular wires.

The run_pvs_metal_fill command does the following:

• Runs PVS with the fill rules to create a GDSII output file.
• Converts the GDSII to a DEF format file based on the GDSII to DEF layermap provided.
• Loads the resulting DEF file into Innovus.

Pegasus is similar to PVS, shown as below,

The run_pegasus_metal_fill command does the following:

• Runs Pegasus with the fill rules to create a GDSII output file.
• Converts the GDSII to a DEF format file based on the GDSII to DEF layermap provided.
• Loads the resulting DEF file into Innovus.

Reference:

Innovus User Guide, Product Version 21.12, Last Updated in November 2021

Process Corners

Global/Local Variation

Timing and RC Modeling with Process Corners

Global and Local variation by Gaussian

Local Monte-Carlo (SSG, FFG with Local Gaussian) as Signoff golden

Process Corner Model Limitations

Variation section

• Total corner (TT/SS/FF/SF/FS)
  • E.g. TTMacro_MOS_MOS_MOSCAP
• Global Corner (TTG/SSG/FFG/SFG/FSG) + Local MC
  • E.g. TTGlobalCorner_LocalMC_MOS_MOSCAP
• Local MC
  • E.g. LocalMCOnly_MOS_MOSCAP
• Global MC + Local MC (Total MC)
  • GlobalMC_LocalMC_MOS_MOSCAP

SSGNP, FFGNP:

When N/P global correlation is weak (R^2=0.15), the corner of N/PMOS balance circuit (e.g. inverter) can be tightened (3sigma -> 2.5sgma) due to the cancellation between NMOS and PMOS

SSGNP, FFGNP usually used in Digital STA

• Global variation validation with global corner
  • 3-sigma of global MC simulation is aligned with global corner
• Total variation validation with total corner
  • 3-sigma of global MC + local MC (total) simulation is aligned with total corner

Global Corner

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/20466/monte-carlo-simulation-global-local-vs-local-and-process-vs-mismatch/1365101#1365101

The "total corner" is representative of the maximum device parameter variation including local device variation effects. However, it is not a statistical corner.

The "global" corner is defined as the "total" corner minus the impact of "local variation"

Hence, if you were to examine simulation results for a parameter using a "total" and "global" corner, you would find the range of variation will be less with the "global" corner than with the "total" corner.

The "global" corner is provided for use in statistical simulations. Hence, when performing a Monte-Carlo simulation, the "global" corner is selected - NOT the "total" corner.

\[ \Delta V_{T,\sigma_{total}} = \sqrt{\Delta^2 _{T, \sigma_{global}}+\Delta^2 _{T, \sigma_{local}}} \]

reference

Eric J.-W. Fang, T5: Fundamentals of Process Monitors for Signoff-Oriented Circuit Design, 2022 IEEE International Solid-State Circuits Conference

Alvin Loke, Device and Physical Design Considerations for Circuits in FinFET Technology, ISSCC 2020 Short Course

簡報 Cln16ffcll Sr V1d0 2p1 Usage Guide URL: https://usermanual.wiki/Document/cln16ffcllsrv1d02p1usageguide.1649731847/view

Radojcic, Riko, Dan Perry and Mark Nakamoto. “Design for manufacturability for fabless manufactuers.” IEEE Solid-State Circuits Magazine 1 (2009): n. pag.

How To Reduce Implementation Headaches In FinFET Processes URL: https://semiengineering.com/how-to-reduce-implementation-headaches-in-finfet-processes/

陌上风骑驴看IC, STA | SSGNP, FFGNP. https://mp.weixin.qq.com/s/eJ8fYRJBR1E9XbfH95OUOg

陌上风骑驴看IC, STA | ssg 跟ss corner 的区别——谬误更正版 https://mp.weixin.qq.com/s?__biz=MzUzODczODg2NQ==&mid=2247486225&idx=1&sn=e9c68f6108ae6c9958d47ca0b29373ca&chksm=fad262cfcda5ebd949cc91353c7cbfaf4ba61179306f7d8e98461a4f4ca9d8a9baef5e9f2cc1&scene=178&cur_album_id=1326356275000705025#rd

The Evolution, Pitfalls, and Cargo Cult Engineering of Advanced Digital Timing Sign-off https://www.tauworkshop.com/2021/speaker_slides/christian_l.pdf

Don O'Riordan Cadence Design Systems. Recommended Spectre Monte Carlo modeling methodology [https://designers-guide.org/modeling/montecarlo.pdf]

PrimeTime does not automatically identifies multicycle paths.

specifying multicycle path for setup

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set_multicycle_path 6 -from reg[26]/CP -to reg/D
# or
set_multicycle_path -setup 6 -from reg[26]/CP -to reg/D
# check the exception
report_exception

specifying multicycle path for hold (new data every 6 cycles)

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set_multicycle_path -setup 6 -to [get_pins "*reg[*]/D"]
set_multicycle_path -hold [expr 6-1] -to [get_pins "*reg[*]/D"]

M_H stands for Hold Multiplier, M_S for Setup Multiplier. The Setup multiplier counts up with increasing clock cycles, the Hold Multiplier counts up with decreasing cycles. The origin (0) for the Hold Multiplier is always at the Setup Multiplier - 1 position.

Reporting a multicycle path with report_timing

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report_timing -exceptions all -from *reg[26]/CP -to *reg/D

Timing Exceptions

If certain paths are not intended to operate according to the default setup and hold behavior assumed by the PrimeTime tool, you need to specify those paths as timing exceptions. Otherwise, the tool might incorrectly report those paths as having timing violations.

The PrimeTime tool lets you specify the following types of exceptions:

• False path – A path that is never sensitized due to the logic configuration, expected data sequence, or operating mode.
• Multicycle path – A path designed to take more than one clock cycle from launch to capture.
• Minimum or maximum delay path – A path that must meet a delay constraint that you explicitly specify as a time value.

REF

PrimeTime® User Guide Version O-2018.06-SP4 Chapter 1: Introduction to PrimeTime Overview of Static Timing Analysis - Timing Exceptions

PT picks the most restrictive pair of edges for setup and for hold. It determines which edges to be used as follows:

1. Evaluate waveforms over the smallest common base period

2. For each capture edge, find the closest setup launch edge. Call these the primary pairs

3. Out of the primary pairs, pick the most restrictive setup launch and capture edges.

4. For each primary pair, draw two hold relationships:

   • Launch to (capture - 1)

   • (Launch + 1) to Capture

     From all of these hold relationships, pick the most restrictive.

PrimeTime uses the ideal clock waveform (as reported in report_clock) to determine the appropriate clock edges for inter-clock analysis.

The most restrictive setup pair is from Clk1 8ns to Clk2 9ns

The most restrictive hold pair is from Clk1 0ns to Clk2 0ns

primary clocks

• Primary clocks should be created at input ports and output pins of black boxes.
• Never create clocks on hierarchy pins. Creating clocks on hierarchy will cause problems when reading SDF. The net timing arc becomes segmented at the hierarchy and PrimeTime will be unable to annotate the net successfully.

generated clocks

• Generated clocks are generally created for waveform modifications of a primary clock (not including simple inversions). PrimeTime does not simulate a design and thus will not derive internally generated clocks automatically - these clocks must be created by the user and applied as a constraint.
• PrimeTime caculate source latency for generated clocks if primary clock is propagated, otherwise its source latency is zero.

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# primary clock
create_clock -period 4 [get_ports Clk]
set_clock_latency -source 2 [get_clocks Clk]
set_propagated_clock [get_clocks Clk]
create_generated_clock -divide_by 2 -name div_clk -source [get_ports Clk] FF3/Q

virtual clocks

• Are clock objects without a source
• Do not clock sequential devices within the current_design
• Serve as references of input or output delays

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# create a virtual clock, vclk, for input and output delay constraints
create_clock -period 5 -name vclk
set_input_delay -max 2 -clock vclk [get_ports in1]
set_output_delay -max 1 -clock vclk [get_ports out2]

There is no network latency to calculate, even if a virtual clock is propagated.

Mechanism in UVM-1.1

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function void test_base::start_of_simulation_phase(uvm_phase phase);
	super.start_of_simulation_phase(phase);
	uvm_top.print_topology(); // Will not compile in UVM-1.2
	factory.print(); // Will not compile in UVM-1.2
endfunction

Global handles uvm_top and factory in uvm_pkg have been removed in UVM-1.2 and later

Mechanism in UVM-1.1 and UVM-1.2

Call the get() method of the class to retrieve the singleton handle.

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function void test_base::start_of_simulation_phase(uvm_phase phase);
	super.start_of_simulation_phase(phase);
	uvm_root::get().print_topology(); // Works in UVM-1.1 & UVM-1.2
	uvm_factory::get().print(); // Works in UVM-1.1 & UVM-1.2
endfunction

Mechanism Only in UVM-1.2

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function void test_base::start_of_simulation_phase(uvm_phase phase);
	uvm_coreservice_t cs = uvm_coreservice_t::get();
	cs.get_root().print_topology();
	cs.get_factory().print();
endfunction

uvm_coreservice_t is the uvm-1.2 mechanism for accessing all the central UVM services such as uvm_root,uvm_factory, uvm_report_server, etc.

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// Using the uvm_coreservice_t:
uvm_coreservice_t cs;
uvm_factory f;
uvm_root top;
cs = uvm_coreservice_t::get();
f = cs.get_factory();
top = cs.get_root();

general terminology

DC related

Imax in T*'s DRC document is the maximum allowed DC current, which depends on Length and Width only

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to Imax rules \[ I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau} \] Similarly, Iabsavg rules are identical to Imax rules, too \[ I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau} \]

rms

Irms is the root-mean-square of the current through a metal line, which depends w(in um), the drawn width of the metal line and \(\Delta T\), the temperature rise due to Joule heating. \[ I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2} \]

peak current

Ipeak in T*'s DRC document is the current at which a metal line undergoes excessive Joule heating and can begin to melt. Ipeak is corresponding to EM Current Analysis: max in Voltus-Fi Analysis Setup \[ I_{\text{peak}}=\max(|I(t)|) \] The limit for the peak current is \[ I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r } } \] where r is the duty ratio

The relationship between Ipeak and Ipeak_DC is merged in DRC document so that there is only Ipeak equation in document

\(I_{\text{peak,limit}}\) depends on \(t_D\), r, width and length

\[ r=\frac{t_D}{\tau} \]

where \(t_D\) is equivalent duration \[ t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}} \] or \[ r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}} \]

where the drawn width is 1um, r is 0.1

\[ 9.37*(1-0.004)/\sqrt0.1 = 29.512 \]

acpeak/pwc

It's same with max EM Current Analysis in Voltus-Fi

dynamicACPeak

This option affect how duty ratio r is computed in max and acpeak/pwc EM current Analysis

When the dynamicACPeak variable is set to true or multiPeak \[ r=\frac{T_d}{T_{\text{total}}} \]

​ where \(T_{\text{total}} = \text{EMIR time window}\)

​ \(T_d\) = the time duration in microsecond of the total "On Time" period based on IPWC

Pulse-Wise Constant EM current calculation (IPWC)

where Tau is \(T_d\) in above formula

!!! It seems that t*'s PDK don't support dynamicACPeak=true

IR drop filter layers

EM techfile (qrcTechFile) may take diffusion contact (n_odtap, p_odtap in DSPF file) into account during IR drop analysis. And these segment often dominate IR drop, but we as IC designer can NOT improve them. In general, the IR drop to M1 layer is enough and feasible.

Regular analysis statements in emir configuration

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net name=[I0.vdd I0.vss] analysis=[vmax vavg]
net name=[I0.*] analysis =[imax ivavg irms]

emirreport command

Creating reports for specific nets after simulation using emirreport

Create a new config file as shown below:

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** test.conf**
net name=[I1.VDD I1.VSS] analysis=[iavg]
net name=[I1.VBIAS] analysis=[imax]

Run emirreport on the command line using the emirdatabase (emir*.bin) and test.conf created above in

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% emirreport -64 -c test.conf -db <emirdatabase> -outdir newreport

database

simulation result

• input.emir0_bin: The first EMIR Analysis which is DC or Transient, which depends on Analyses order

• input_tran.emir0_bin: EMIR Analysis in Transient simulation

• input_dcOp.emir0_bin: EMIR Analysis in DC simulation

For example

Two results are generated input.emir0_bin and input_dcOp.emir0_bin and their reports respectly

Fix Electromigration

• Iavg

  The average value of the current, which is the effective DC current

• Irms

  Irms rule relates to the heat or Joule-heating of metal lines

• Ipeak

  The main goal of the Ipeak limits is to ensure that no thermal breakdown could occur on single overshoot events. If the signal may not have a high current density but if it has a very large peak current density, then, local melting will happen and cause failures

QA

1. Q. Why “length” column in EM results form doesn’t show extracted length, it shows “NA”.

   A. Voltus-Fi reports the “length” column only when length rules are present in the emDataFile.

2. Seeing different port currents with and without emir simulations for same dspf included in EMIR Direct method using dspf_include.

   Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the regular spectre flow. Islands patching is only performed in EMIR only

3. Setting temperature for EM analysis

By Default, Voltus-FI and VPS pick up the current density limit for temperature at which simulation has been performed.

By the way, Design Variables - temperature will override the temperature in Setup toolbar which is gray in ADE Explorer

4. AC Peak EM analysis - Voltus-Fi

   The available options within the EM current analysis section in the EMIR Analysis Setup form are:

   max / avg / avgabs / rms.

   In order to enable the AC Peak based information when loading the EM results, both max and avg should be selected when setting up the EMIR Analysis Setup.

   With this configuration, the AC Peak option becomes available and can be used.

5. How to print average, rms, and peak current of device tap in Spectre/Voltus FI EMIR analysis

   The following option enables you to save the average, rms, and peak tap currents in the emir0bin file and report it in the input.rpt_tapi file.

   1	solver report_tapi=true

   Add this option in emir.conf to enable the reporting of tap current after the Spectre EMIR simulation. The input.rpt_tapi file will be saved in the psf/raw directory.

   Note: This feature is supported in SPECTRE20.1 ISR14 and later versions.

6. emir.conf file

   emir.conf file is generated automaticaly after configure EM/IR Analysis in ADE, which is in netlist directory.

   

7. Setting default path for EM rules file in APS EMIR analysis

   • set the following environment variable in your terminal

     1	setenv EMDATAFILE < path to EM rules file>

   • or set in .cdsinit

     1	setShellEnvVar("EMDATAFILE=<path to EM rules file>")

8. Print node names and length associated with parasitic resistors in EM report file

   export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME

   • Printing the parasitic resistor length in the EM report

     1	emirutil reportLength=true

   • Printing nodes that are associated with the parasitic resistor

     1	emirutil reportNodeName=true

     Once these are enabled, you will have the Length, Node_1, and Node_2 columns printed in the EM report file, as shown below:

     

9. Is it possible to run RMS IR Drop analysis using Voltus-Fi?

   Typically, in a simulation, Power/Ground nets are always biased with a constant DC source. Hence, at present, Voltus-Fi only supports Average and Maximum (Peak) IR Drop analysis.

   For a net to have data for IR analysis(vmax/vavg), the net/node must be connected to a DC vsource or a vsource which is constant within the emir time window.

10. Can we change the time window of EM computation after the simulation completed ?

    It is not possible to modify the EM time window without re-running the full simulation.

    However you can specify several time window in the emir conf file for instance for 2 time window [0 to 10n] and [10n 20n]

    1	time window=[0 10n 10n 20n]

    In that case it will create 2 emir_bin files and then 2 different em report files according to the 2 different time windows.

11. How to print segment_W values being used to compute EM limits

    You can use the following option to print segment_W to the report:

    1	emirutil reportSegmentWidth=[true]

    This would print a Segment_w column in the report containing the segment width values used for computing the limit:

    Pass/Fail %	Resistor	layer	Current	Width	PathLength	I limit	X1	Y1	X2	Y2	J/JMAX	Res	ViaArea	No of needed vias	width/#via	J limit	Segment_w
    			(mA)	(um)	(um)		(um)	(um)	(um)	(um)			(nm^2)		(um/#)	(A/um)
    pass-100.0	Rj3292	Met1	9.02376e-12	0.1	42.72	1.10067	0.350	11.568	0.350	11.376	8.19843e-12	0.7382	NA	NA	0.0001	0.0110067	0.1

12. pathLength vs Length in EM report file

    • Length: parasitic resistor length, which is set by emirutil reportLength=true

    • pathlength: Blech length is also known as "Short length" or "Path length", and can be explained as : The longest and continuous centerline path from edge to edge among the connected wire shapes on the same metal layer.

      • For all resistors falling on this shape, same pathLength is reported.
      • After the longest path in shape has been determined the tool applies the same blech length to all the resistor falling on that shape.
      • This resistor length is NOT used in EM analysis because EM rules consider Blech length of the resistor.

      

      where W is the wire width and L is the Blech length.

      • By default the tool will sum all branches of a given metal layer. In other words the path length that will be used to look up the EM density limit is :

        Bl = $l(R1) + $l(R2) + $l(R3) + $l(R4) + $l(R5) + $l(R6) + $l(R7) + $l(R8)

        

13. How to enable EMIR analysis in PSS simualtion ?

    To enable EMIR in PSS, you have to enable DC and/or Tran simulation simultaneously. Two or more binary results file should be generated and select the file based file name or configure text file in psf directory.

    (given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)

reference

AC Peak Analysis Using IPWC Rapid Adoption Kit (RAK) Product Version: IC6.1.8 ISR10, SPECTRE19.1 ISR5 April 2020

Posser, Gracieli & Sapatnekar, Sachin & Reis, Ricardo. (2017). Electromigration Inside Logic Cells. 10.1007/978-3-319-48899-8.

A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts of electromigration awareness," 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp. 527-532, doi: 10.1109/ASPDAC.2013.6509650.

Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling of electromigration in SRAMs.” (2014).

N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical approach to static signal electromigration analysis," Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 572-577, doi: 10.1109/DAC.1998.724536.

Blaauw, David & Oh, Chanhee & Zolotov, Vladimir & Dasgupta, Aurobindo. (2003). Static electromigration analysis for on-chip signal interconnects. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 22. 39 - 48. 10.1109/TCAD.2002.805728.

Topology of the test

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function void test_base::start_of_simulation_phase(uvm_phase phase);
	uvm_root::get().print_topology(); // defaults to table printer
endfunction

The default printer policy is uvm_default_table_printer

There are three default printer policies that the uvm_pkg provides:

uvm_default_table_printer uvm_default_tree_printer uvm_default_line_printer

Check all configuration settings

Check all configuration settings in a components configuration table to determine if the setting has been used, overridden or not used. When recurse is 1 (default), configuration for this and all child components are recursively checked. This function is automatically called in the check phase, but can be manually called at any time.

To get all configuration information prior to the run phase, do something like this in your top object:

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function void start_of_simulation_phase(uvm_phase phase);
	check_config_usage();
endfunction

UVM phase

• Functions are executed bottom-up (Except for build and final phases , which are executed top-down)
• Tasks are forked into concurrent executing threads

Objections are handled in pre/post body decalared in a base sequence class

This is efficient for all sequence execution options:

• Default sequences use body objections

• Test sequences use test objections

• Subsequences use objections of the root sequence which calls them

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class yapp_base_seq extends uvm_sequence#(yapp_packet);
…
    task pre_body();
        if(starting_phase != null);
        	starting_phase.raise_objection(this, get_type_name());
    endtask
    task post_body();
    	if(starting_phase != null);
    		starting_phase.drop_objection(this, get_type_name());	
    endtask
…
class yapp012 extends yapp_base_seq;
…

Set as default sequence of sequencer:

A default sequence is a root sequence, so the pre/post body methods are executed and objection are raised/dropped there

Test sequence:

A test sequence is a root sequence, so the pre/post body methods are executed. However, for a test sequence, starting_phase is null and so the objection is not handled in the sequence. The test must raise and drop objections

Subsequence:

Not a root sequence, so pre/post body methods are not executed. The root sequence which ultimately called the subsequence handles the objections, using one of the two options above.

If a sequence is call via a `uvm_do variant, the it is defined as a subsequence and its pre/post_body() methods are not executed.

objection change in UVM1.2

Raising or dropping objections directly from starting_phase is deprecated

• must use get_starting_phase() method

• prevents modification of phase during sequence

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task pre_body();
    uvm_phase sp = get_starting_phase();
    if (sp != null)
        sp.raise_objection(this, get_type_name());
endtask

All credits to my colleague, Zhang Wenpian.

Planar process vs. FinFet process

Standard Cell Tapcell

Guard Ring in Custom block

Place well tie and substrate tie where they are needed. Redundant guard ring consume area and increase the routing of critical signal net.

Continuous OD

Performance & Matching

current mirror

split diffusion with dummy transistors

cascode structure

off transistor split diffusion

sharing source & drain

Stacked MOSFETs

reference

A. L. S. Loke et al., "Analog/mixed-signal design challenges in 7-nm CMOS and beyond," 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, pp. 1-8, doi: 10.1109/CICC.2018.8357060.

Stacked MOSFETs in analog layout https://pulsic.com/stacked-mosfets-in-analog-layout/