KNOW-HOW

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First place place hard macro and add placement halo, then execute the following code to add endcap and tapcell.

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deleteFill -prefix ENDCAP
deleteFill -prefix WELL

setEndCapMode \
    -leftEdge BOUNDARY_RIGHTBWP16P90CPD \
    -rightEdge BOUNDARY_LEFTBWP16P90CPD \
    -leftBottomCorner BOUNDARY_NCORNERBWP16P90CPD \
    -leftTopCorner BOUNDARY_PCORNERBWP16P90CPD \
    -rightTopEdge FILL3BWP16P90CPD \
    -rightBottomEdge FILL3BWP16P90CPD \
    -topEdge "BOUNDARY_PROW2BWP16P90CPD BOUNDARY_PROW3BWP16P90CPD"
    -bottomEdge "BOUNDARY_NROW2BWP16P90CPD BOUNDARY_NROW3BWP16P90CPD" \
    -boundary_tap true

set_well_tap_mode \
    -rule 33
    -bottom_tap_cell BOUNDARY_NTAPBWP16P90CPD \
    -top_tap_cell BOUNDARY_PTAPBWP16P90CPD \
    -cell TAPCELLBWP16P90CPD

addEndCap
addWellTap -checkerBoard -cell TAPCELLBWP16P90CPD -cellInterval 160

endcap_tapcell_floorplan.drawio

REF: StanfordAHA/PowerDomainDesign

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power/ground bump

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create_bump –cell PAD90UBMBOP –loc_type cell_center –loc $x0 $y  
create_bump –cell PAD90UBMBOP –loc_type cell_center –loc $x1 $y 
...
create_bump –cell PAD90UBMBOP –loc_type cell_center –loc $xn $y 
deselectAll 
select_bump –bum_cell PAD90UBMBOP 
assignPGBumps –nets {vss vdd_dig} -selected –checkboard

pma_dig_bumps.drawio

signal or power/ground bump

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set bump_name [create_bump –cell PAD150PITCH –loc $bump_x $bump_y –loc_type cell_center –return_bumps_name] 
# assign power/ground bump
assignPGBumps –bumps $bump_name –nets $pin_name 
# or assign to signal bump
assignSigToBump –bumps $bump_name –net $pin_name

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$readmemh("hex_memory_file.mem", memory_array, [start_address], [end_address]) $readmemb("bin_memory_file.mem", memory_array, [start_address], [end_address])

The system task has no versions to accept octal data or decimal data.

  • The 1st argument is the data file name.
  • The 2nd argument is the array to receive the data.
  • The 3rd argument is an optional start address, and if you provide it, you can also provide
  • The 4th argument optional end address.

Note, the 3rd and 4th argument address is for array not data file.

If the memory addresses are not specified anywhere, then the system tasks load file data sequentially from the lowest address toward the highest address.

The standard before 2005 specify that the system tasks load file data sequentially from the left memory address bound to the right memory address bound.

readtest.v

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module readfile;
	reg [7:0] array4 [0:3];
	reg [7:0] array7 [6:0];
	reg [7:0] array12 [11:0];

	integer i;

	initial begin
		$readmemb("data.txt", array4);
		$readmemb("data.txt", array7, 2, 5);
		$readmemb("data.txt", array12);

		for (i = 0; i < 4; i = i+1)
			$display("array4[%0d] = %b", i, array4[i]);

		$display("=========================");

		for (i = 0; i < 7; i = i+1)
			$display("array7[%0d] = %b", i, array7[i]);

		$display("=========================");

		for (i = 0; i < 12; i = i+1)
			$display("array12[%0d] = %b", i, array12[i]);
	end
endmodule

data.txt

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00000000 
00000001
00000010
00000011
00000100
00000101
00000110
00001000

result

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array4[0] = 00000000
array4[1] = 00000001
array4[2] = 00000010
array4[3] = 00000011
=========================
array7[0] = xxxxxxxx
array7[1] = xxxxxxxx
array7[2] = 00000000
array7[3] = 00000001
array7[4] = 00000010
array7[5] = 00000011
array7[6] = xxxxxxxx
=========================
array12[0] = 00000000
array12[1] = 00000001
array12[2] = 00000010
array12[3] = 00000011
array12[4] = 00000100
array12[5] = 00000101
array12[6] = 00000110
array12[7] = 00001000
array12[8] = xxxxxxxx
array12[9] = xxxxxxxx
array12[10] = xxxxxxxx
array12[11] = xxxxxxxx

ref

Initialize Memory in Verilog

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A range of contiguous bits can be selected and is known as part-select. There are two types of part-selects, one with a constant part-select and another with an indexed part-select

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reg [31:0] addr;
addr [23:16] = 8'h23; //bits 23 to 16 will be replaced by the new value 'h23 -> constant part-select

Having a variable part-select allows it to be used effectively in loops to select parts of the vector. Although the starting bit can be varied, the width has to be constant.

[<start_bit +: ] // part-select increments from start-bit

[<start_bit -: ] // part-select decrements from start-bit

Example

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logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;
integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

dword[8*sel +: 8] // variable part-select with fixed width

ref

Verilog scalar and vector

What is the "+:" operator called in Verilog?

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VCS with customized UVM version

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# uvm 1.1 customized
$ export VCS_UVM_HOME="path/to/uvm-1.1d/src"
$ vcs -full64 -debug_access+all -kdb -sverilog -ntb_opts uvm -timescale=1ns/1ps -f filelist.f
$ ./simv -gui=verdi

VCS with release UVM

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$ vcs -full64 -debug_access+all -kdb -sverilog -ntb_opts uvm-1.2

VCS compile-time options

-kdb: Enables generating Verdi KDB database

-lca: Enables Limited Customer Availability feature, which is not fully test

+vpi: Enables the use of VPI PLI access routines.

​ Verilog PLI (Programming Language Interface) is a mechanism to invoke C or C++ functions from Verilog code.

-P <pli.tab>: Specifies a PLI table file

​ ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tb

image-20220603221739973

+define+=: Define a text macro, Test for this definition in your Verilog source code using the `ifdef compiler directive

+define+SIMULATION when compiling

`ifdef SIMULATOIN in code

-debug_access: Enables dumping to FSDB/VPD, and limited read/callback capability. Use -debug_access+classs for testbench debug, and debug_access+all for all debug capabilities. Refer the VCS user guide for more granular options for debug control under the switch debug_access and refer to debug_region for region control

-y : Specifies a Verilog library directory to search for module definitons

-v <filename>: Specifies a Verilog library file to search for module definitons

+nospecify: Suppresses module path delays and time checks in specify blocks

-l <filename>: (lower case L) Specifies a log file where VCS records compilation message and runtime messages if you include the -R, -RI, or -RIG option

+vcs+fsdbon: A compile-time substitute for $fsdbDumpvars system task. The +vcs+fsdbon switch enables dumping for the entire design. If you do not add a corresponding -debug_access* switch, then -debug_access is automatically added. Note that you must also set VERDI_HOME.

$ ./simv

FSDB Dumper for VCS, Release Verdi_S-2021.09-SP2-2, Linux x86_64/64bit, 05/22/2022 (C) 1996 - 2022 by Synopsys, Inc. *Verdi* : Create FSDB file 'novas.fsdb' *Verdi* : Begin traversing the scopes, layer (0). *Verdi* : End of traversing.

+vcs+vcdpluson: A compile-time substitute for $vcdpluson system task. The +vcs+vcdpluson switch enables dumping for the entire design. If you do not add a corresponding -debug_access* switch, then -debug_access is automatically added

$ ./simv

VCD+ Writer S-2021.09-SP2-2_Full64 Copyright (c) 1991-2021 by Synopsys Inc.

+incdir+<directory>: Specifies the directories that contain the files you specified with the `include compiler directive. You can specify more than on directory, separating each path name with the + character.

Compile time Use Model

Just add the -kdb option to VCS executables when running simulation

  • Three steps flow:

    • vlogan/vhdlan/syscan -kdb

      Compile design and generate un-resolved KDB to ./work

    • vcs -kdb -debug_access+all <other option>

      Generate elaborated KDB to ./sim.dadir

  • Two steps flow:

    • vcs -kdb -debug_access+all <other option>

      Compile design and generate elaborated KDB to ./simv.dadir

Common simv Option

-gv <gen=value>: override runtime VHDL generics *

-ucli: stop at Tcl prompt upon start-up

-i <run.tcl>: execute specified Tcl script upon start-up

-l <logfile>: create runtime logfile

-gui: create runtime logfile

-xlrm: allow relaxed/non-LRM compliant code

-cm <options>: enable coverate options

verdi binkey

SHIFT+A: Find Signal/Find Instance/Find Instport

SHIFT+S: Find Scope

module traverse

image-20220527165858163

Show Calling

Show Definition

Double-Click instance name is same with click Show Definition

Double-Click module name is same with click Show Calling

signal traverse

image-20220527201122708

Driver

Load

Double-Click signal name is same with click Driver

Verdi options

-ssf fastFile(s)|dumpFile(s)|fastFile list(s): Load FSDB (*.fsdb), virtual FSDB (*.vf) , gzipped FSDB (*.fsdb.gz), bzip2 FSDB (*.fsdb.bz2), waveform dump (*.vcd, *.vcd.gz) files, or FSDB file list (*.flst)

-simBin <simv_executable>: Specify the path of the simulation binary file.

image-20220604220225513

-dbdir: Specify the daidir (simv.daidir ) directory to load

In the VCS two-step flow, the VCS generated KDB (kdb.elab++) is saved under the simv.daidir/ directory (like simv.daidir/kdb.elab++).

-f file_name / -file file_name: Load an ASCII file containing design source files and additional simulator options

Import Design from UFE

Knowledge Database (KDB): As it compiles the design, the Verdi platform uses its internal synthesis technology to recognize and extract specific structural, logical, and functional information about the design and stores the resulting detailed design information in the KDB

The Unified Compiler Flow (UFE) uses VCS with the -kdb option and the generated simv.daidar includes the KDB information

  1. verdi -dbdir simv.daidir

    Use the new -dbdir option to specify the simv.daidir directory

  2. verdi -simBin simv

    Load simv.daidir from the same directory as simv and invoke Verdi if simv.daidir is available

  3. verdi -ssf novas.fsdb

    Load KDB automatically from FSDB,

For 2 and 3, use the -dbdir option to load simv.dadir if you have move it to somewhere else

Reference Design and FSDB on the Command Line

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verdi -f <source_file_name> -ssf <fsdb_file_name>

Where, source_file_name is the source file name and fsdb_file_name is the name of the FSDB file

reference

Verdi使用总结 URL: https://www.wenhui.space/docs/07-ic-verify/tools/verdi_userguide/

Using Verdi for Design Understanding - Driver/Load Tracing in Verdi | Synopsys

Using Verdi for Design Understanding - Connectivity Tracing and FSM Extraction in Verdi | Synopsys

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Using g++ only

conditional.cpp

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#include <iostream>

#define na 4

int main() {
  int a[na];

  a[0] = 2;
  for (int n = 1; n < na; n++) a[n] = a[n-1] + 1;

#ifdef DEBUG
  // Only kept by preprocessor if DEBUG defined
  for (int n = 0; n < na; n++) {
    std::cout << "a[" << n << "] = " << a[n] << std::endl;
  }
#endif 
  
  return 0;
}

-DDEBUG args

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$ g++ -Wall -Wextra -Wconversion conditional.cpp -o conditional
$ ./conditional
$ g++ -Wall -Wextra -Wconversion conditional.cpp -o conditional -DDEBUG
$ ./conditional
a[0] = 2
a[1] = 3
a[2] = 4
a[3] = 5

Using CMakeLists.txt add_definitions

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cmake_minimum_required(VERSION 3.2)

option(DEBUG "Option description" OFF)

if(DEBUG)
    add_definitions(-DDEBUG)
endif(DEBUG)

add_executable(cond conditional.cpp)

without debug

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$ cmake ..
$ make
$ ./cond

with debug

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$ cmake -DDEBUG=ON ..
$ make
$ ./cond
a[0] = 2
a[1] = 3
a[2] = 4
a[3] = 5
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