Data Converter
Top-Plate vs Bottom-Plate Sampling
[https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf]
Bottom-Plate Sampling
Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling
EE 435 Spring 2024 Analog VLSI Circuit Design - Switched-Capacitor Amplifiers Other Integrated Filters, https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf
Top-Plate Sampling
TODO π
Maintain constant common-mode during conversion
D. Pfaff et al., "7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024 [https://iccircle.com/static/upload/img20240529101747.pdf]
β, "A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited)," 2025 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-8, doi: 10.1109/CICC63670.2025.10983461.
E. Swindlehurst et al., "An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch," IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, 2021, [https://sci-hub.se/10.1109/JSSC.2021.3057372]
Relationship Between SFDR and INL
Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input signal frequency
Track Time
TODO π
ADC Calibration
Offset Calibration
long-term average of all 32 sub-ADC samples = 0
Gain Calibration
long-term average of absolute values of all 32 sub-ADC samples should be equal
Background vs. foreground calibration
TODO π
Ahmed Ali, ISSCC 2021 T5: Calibration Techniques in ADCs [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T5.pdf]
Jiang, Xicheng, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015.
Redundancy
Max tolerance of comparator offset is \(\pm V_{FS}/4\)
- \(b_j\) error is \(\pm 1\)
- \(b_{j+1}\) error is \(\pm 2\) , wherein \(b_{j+1}\): \(0\to 2\) or \(1\to -1\)
i.e. complementary analog and digital errors cancel each other, \(V_o +\Delta V_{o}\) should be in over-/under-range comparators (\(-V_{FS}/2 \sim 3V_{FS}/2\))
\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{V_{out,j}+\Delta V_{out,j}}{2} \\ V_{in,{j+1}} &= (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \end{align}\]
with \(V_{in,j+1} = V_{out,j}+\Delta V_{out,j}\)
\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2} \left\{ (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \right\} \\ &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2}(b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2}+ \frac{1}{2}\frac{V_{in,j+2}}{2} \\ &=\tilde{b_j} \cdot \frac{V_{FS}}{2}+ \tilde{b_{j+1}}\cdot \frac{V_{FS}}{4}+ \frac{1}{4}V_{in,j+2} \end{align}\]
where \(b_j\) is 1-bit residue without redundancy and \(\tilde{b_j}\) is redundant bits
Uniform Sub-Radix-2 SAR ADC
Minimal analog complexity, no additional decoding effort
Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." (2013). [https://dspace.mit.edu/bitstream/handle/1721.1/82177/861702792-MIT.pdf]
Kuttner, Franz. "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS." 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 1 (2002): 176-177 vol.1. [https://sci-hub.se/10.1109/ISSCC.2002.992993]
T. Ogawa, H. Kobayashi, et. al., "SAR ADC Algorithm with Redundancy and Digital Error Correction." IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A (2010): 415-423. [paper, slides]
B. Murmann, βOn the use of redundancy in successive approximation A/D converters,β International Conference on Sampling Theory and Applications (SampTA), Bremen, Germany, July 2013. [https://www.eurasip.org/Proceedings/Ext/SampTA2013/papers/p556-murmann.pdf]
KraΜmer, M. et al. (2015) High-resolution SAR A/D converters with loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].
sarthak, "Visualising redundancy in a 1.5 bit pipeline ADCβ [https://electronics.stackexchange.com/a/523489/233816]
Testing
TODO π
Kent H. Lundberg "Analog-to-Digital Converter Testing" [https://www.mit.edu/~klund/A2Dtesting.pdf]
Tai-Haur Kuo, Da-Huei Lee "Analog IC Design: ADC Measurement" [http://msic.ee.ncku.edu.tw/course/aic/202309/ch13%20(20230111).pdf] [http://msic.ee.ncku.edu.tw/course/aic/aic.html]
ESE 6680: Mixed Signal Design and Modeling "Lec 20: April 10, 2023 Data Converter Testing" [https://www.seas.upenn.edu/~ese6680/spring2023/handouts/lec20.pdf]
Degang Chen. "Distortion Analysis" [https://class.ece.iastate.edu/djchen/ee435/2017/Lecture25.pdf]
ADC INL/DNL
TODO π
EndpointmethodBestFitmethod
INL/DNL Measurements for High-Speed Analog-to Digital Converters (ADCs) [https://picture.iczhiku.com/resource/eetop/sYKTSqLfukeHSmMB.pdf]
Code Density Test
Apply a linear ramp to ADC input
Mid-Rise & Mid-Tread Quantizer
The difference between the lowest and highest levels is called the full-scale (FS) of the quantizer
Bootstrapped Switch
A. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to Digital Converter," IEEE J. Solid-State Circuits, pp. 599, May 1999 [https://sci-hub.se/10.1109/4.760369]
Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electronics Letters, Jan. 1999. [https://sci-hub.se/10.1049/EL:19990028]
B. Razavi, "The Bootstrapped Switch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15Switch.pdf]
B. Razavi, "The Design of a bootstrapped Sampling Circuit [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 13, Issue. 1, pp. 7-12, Summer 2021. [http://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_1_2021.pdf]
Quantization Noise & its Spectrum
Quantization noise is less with higher resolution as the input range is divided into a greater number of smaller ranges
This error can be considered a quantization noise with RMS
ENOB & SQNR
The quantization noise power \(P_Q\) for a uniform quantizer with step size \(\Delta\) is given by \[ P_Q = \frac{\Delta ^2}{12} \] For a full-scale sinusoidal input signal with an amplitude equal to \(V_{FS}/2\), the input signal is given by \(x(t) = \frac{V_{FS}}{2}\sin(\omega t)\)
Then input signal power \(P_s\) is \[ P_s = \frac{V_{FS}^2}{8} \] Therefore, the signal-to-quantization noise ratio (SQNR) is given by \[ \text{SQNR} = \frac{P_s}{P_Q} = \frac{V_{FS}^2/8}{\Delta^2/12}=\frac{V_{FS}^2/8}{V_{FS}^2/(12\times 2^{2N})} = \frac{3\times 2^{2N}}{2} \] where \(N\) is the number of quantization bits
When represented in dBs \[ \text{SQNR(dB)} = 10\log(\frac{P_s}{P_Q}) = 10\log(\frac{3\times 2^{2N}}{2})= 20N\log(2) + 10\log(\frac{3}{2})= 6.02N + 1.76 \]
Quantization is NOT Noise
DAC DNL
One difference between ADC and DAC is that DAC DNL can be less than -1 LSB
In a DAC, DNL < -1LSB implies non-monotonicity
DAC INL
The worst INL of three DAC Architecture is same
- \(A = \sum_{j=1}^k I_j\), \(B=\sum_{j=k+1}^N I_j\)
- A and B are independent with \(\sigma_A^2 = k\sigma_u^2\) and \(\sigma_B^2=(N-k)\sigma_u^2\)
Therefore \[ \mathrm{Var}\left(\frac{X}{Y}\right)\simeq \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{\mathrm{cov}(X,Y)}{kNI_u^2}\right) \] and \[\begin{align} \mathrm{cov}(X,Y) &= E[XY] - E[X]E[Y] = E[A(A+B)] - kNI_u^2 \\ &= E[A^2]+E[A]E[B] - kNI_u^2= \sigma_A^2+E[A]^2 + k(N-k)I_u^2 - kNI_u^2\\ &= k\sigma_i^2 + k^2I_u^2+ k(N-k)I_u^2 - kNI_u^2 \\ &= k\sigma_i^2 \end{align}\]
Finally, \[ \mathrm{Var}\left(\frac{X}{Y}\right)\simeq \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{k\sigma_i^2}{kNI_u^2}\right) = \frac{k^2}{N^2}\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 \] i.e. \[ \mathrm{Var(INL(k))} = k^2\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 = k\left(1- \frac{k}{N}\right)\sigma_u^2 \]
Standard deviation of INL is maximum at mid-scale (k=N/2)
Hold Mode Feedthrough
P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 544-634
B. Sedighi, A. T. Huynh and E. Skafidas, "A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 113-116
Tania Khanna, ESE 568: Mixed Signal Circuit Design and Modeling [https://www.seas.upenn.edu/~ese5680/fall2019/handouts/lec11.pdf]
Summing Interleaved Alias
The sampling function - impulse train is \[ s(t) = \sum_{n=-\infty}^{\infty}\left[ \delta(t-n4T_s) + \delta(t-n4T_s-T_s) + \delta(t-n4T_s-2T_s) + \delta(t-n4T_s-3T_s)\right] \]
Its Fourier transform is \[\begin{align} S(f) &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left[\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot T_s}\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot 2T_s}\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot 3T_s}\delta(f-k\frac{f_s}{4}) \right] \\ &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left(1+e^{-j2\pi\frac{f}{f_s}} + e^{-j4\pi\frac{f}{f_s}} + e^{-j6\pi\frac{f}{f_s}} \right) \delta(f-k\frac{f_s}{4}) \\ &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left(1+e^{-jk\frac{\pi}{2}} + e^{-jk\pi} + e^{-jk\frac{3\pi}{2}} \right) \delta(f-k\frac{f_s}{4}) \end{align}\]
We define \(M[k] = 1+e^{-jk\frac{\pi}{2}} + e^{-jk\pi} + e^{-jk\frac{3\pi}{2}}\), which is periodic, i.e. \(M[k]=M[k+4]\) \[ M[k]=\left\{ \begin{array}{cl} 4 & : \ k = 4m \\ 0 & : \ k=4m+1 \\ 0 & : \ k=4m+2 \\ 0 & : \ k=4m+3 \\ \end{array} \right. \]
That is \[ S(f) = \frac{2\pi}{T}\sum_{k=-\infty}^{\infty} \delta(f-kf_s) \]
Alias has same frequency for each slice but different phase: Alias terms sum to zero if all slices match exactly
John P. Keane, ISSCC2020, T5: "Fundamentals of Time-Interleaved ADCs"
Random Chopping in TI-ADC
\[ D_n(kT) = (G_n R(kT) V(kT) + O_n)R(kT)= C_n V(kT) + R(kT)O_n \]
Coherent Sampling
\[ \frac{f_{\text{in}}}{f_{\text{s}}}=\frac{M_C}{N_R} \]
\(f_\text{in}\) and \(f_s\) must be incommensurate (\(f_s/f_{in}\) is irrational number. btw, co-prime is sufficient but not necessary)
\(M_C\) and \(N_R\) must be co-prime
Samples must include integer # of cycles of input signal
An irreducible ratio ensures identical code sequences not to be repeated multiple times.
Given that \(\frac{M_C}{N_R}\) is irreducible, and \(N_R\) is a power of 2, an odd number for \(M_C\) will always produce an irreducible ratio
Assuming there is a common factor \(k\) between \(M_C\) and \(N_R\), i.e. \(\frac{M_C}{N_R}=\frac{k M_C'}{k N_R'}\)
The samples (\(n\in[1, N_R]\))
\[ y[n] = \sin\left( \omega_{\text{in}} \cdot t_n \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_s} \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_{\text{in}}}\frac{M_C}{N_R} \right) = \sin\left( 2\pi n\frac{M_C}{N_R} \right) \]
Then
\[ y[n+N_R'] = \sin\left( 2\pi (n+N_R')\frac{M_C}{N_R} \right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{M_C}{N_R}\right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{kM_C'}{kN_R'} \right) = \sin\left( 2\pi n \frac{M_C}{N_R}\right) \]
So, the samples is repeated \(y[n] = y[n+N_R']\)
\(N_R\) & \(M_C\) irreducible ratio (mutually prime)
- Periodic sampling points result in periodic quantization errors
- Periodic quantization errors result in harmonic distortion
Choosing M/N non-prime repeats the signal quantization periodically and fewer quantization steps are measured. The quantization repeats periodically and creates a line spectrum that can obscure real frequency lines (e.g. the red lines in the images below, created by non-linearities of the ADC).
[https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple]
Thermometer to Binary encoder
Pipeline ADC
CMP reference voltage is 0.5vref, DAC output is 0.5vref or 0
residual error \[ V_{r,n} = (V_{r,n-1}-\frac{1}{2}b_{n})\cdot 2 \] and \(V_{r,-1}=V_i\) \[ V_{r,n-1} = 2^{n}V_i -\sum_{k=0}^{n-1}2^{n-k-1}b_k = 2^{n}\left(V_i - \sum_{k=0}^{n-1}\frac{b_k}{2^{k+1}}\right) \]
here, \(b_0\) is first stage and MSB
It divides the process into several comparison stages, the number of which is proportional to the number of bits
Due to the pipeline structure of both analog and digital signal path, inter-stage residue amplification is needed which consumes considerable power and limits high speed operation
Vishal Saxena, "Pipelined ADC Design - A Tutorial"[https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20NonIdealities%20Slides%20v1_0.pdf] [https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20Slides%20v1_2.pdf]
Bibhu Datta Sahoo, Analog-to-Digital Converter Design From System Architecture to Transistor-level [http://smdpc2sd.gov.in/downloads/IGF/IGF%201/Analog%20to%20Digital%20Converter%20Design.pdf]
Bibhu Datta Sahoo, Associate Professor, IIT, Kharagpur, [https://youtu.be/HiIWEBAYRJY?si=pjQnIdi03i5N7805]
R-2R & C-2C
TODO π
Conceptually, area goes up linearly with number of bit slices
drawback of the R-2R DAC
\(N_b\) bit binary + \(N_t\) bit thermometer DAC
\(N_b\) bit binary can be simplified with Thevenin Equivalent \[ V_B = \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_b-n}} \] with thermometer code
\[\begin{align} V_o &= V_B\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R}+\sum_{n=0}^{2^{N_t}-2}T_n\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R} \\ &= \frac{V_B}{2^{N_t}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \\ &= \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_t+N_b-n}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \end{align}\]
B. Razavi, "The R-2R and C-2C Ladders [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 10-15, Summer 2019 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2019.pdf]
4bit binary R2R DAC with Ru=1kOhm
RVB equivalent R
Binary-Weighted (BW) DAC
During \(\Phi_1\), all capacitor are shorted, the net charge at \(V_x\) is 0
During \(\Phi_2\), the charge at bottom plate of CDAC \[ Q_{DAC,btm} = \sum_{i=0}^{N-1}(b_i\cdot V_R - V_x)\cdot 2^{i}C_u = C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x \] the charge at the internal plate of integrator \[ Q_{intg} = V_x C_p + (V_x - V_o)2^NC_u \] and we know \(-V_x A = V_o\) and \(Q_{DAC,btm} = Q_{intg}\) \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x = V_x C_p + (V_x - V_o)2^NC_u \] i.e. \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i = (2^N-1)C_uV_x + V_x C_p + (V_x - V_o)2^NC_u \] therefore \[ -V_o = \frac{2^N C_u}{\frac{(2^{N+1}-1)C_u+C_p}{A}+2^NC_u}\sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right)\approx \sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right) \]
Midscale (MSB Transition) often is the largest DNL error
\(C_4\) and \(C_1+C_2+C_3\) are independent (can't cancel out) and their variance is two largest (\(16\sigma_u^2\), \(15\sigma_u^2\), ), the total standard deviation is \(\sqrt{16\sigma_u^2+15\sigma_u^2}=\sqrt{31}\sigma_u\)
reference
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