Digital Delta-Sigma Modulators (DDSM)

Posted on 2024-09-09 Edited on 2026-05-12 In analog

linearized model

Noise Cancellation Network

\[\begin{align} v[n] = \{0,1,2,...,M-1\} &\space\Rightarrow\space y[n] = 0 \space\Rightarrow\space e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \\ v[n] = \{M,M+1,M2,...,2M-1\} &\space\Rightarrow\space y[n] = 1 \space\Rightarrow\space e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \end{align}\]

For the three stages of the MASH 1-1-1 DDSM

1st order DDSM (digital accumulator)

assuming $n_0=2$

$x[n]+s[n]$	$v$	$e[n]$	$c[n]$, y
0\|00	0	0	0
0\|01	1	1	0
0\|10	2	2	0
0\|11	3	3	0
1\|00	4	0	1
1\|01	5	1	1
1\|10	6	2	1
1\|11	7	3	1

yield $M=2^{n_0}=4$

2nd order DDSM

In $z$-domain \[ \left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y \right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y \] That is \[ Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2 \] In time domain \[\begin{align} y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\ &= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2] \end{align}\]

LSB Dither

?? integer valued impulse responses

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [pdf]

stability of DSM

accumulator wordlength

Z. Ye and M. P. Kennedy, "Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 112-116, Feb. 2009 [https://sci-hub.se/10.1109/TCSII.2008.2010188]

—, "Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 4, pp. 714-726, April 2009 [https://sci-hub.se/10.1109/TCSI.2008.2003383]

Truncation DAC

accumulator is implicit quantizer

with $\frac{y}{2^{m_2}} + q= v$, where $v = \lfloor\frac{y}{2^{m_2}}\rfloor$

\[ \left\{ \begin{array}{cl} Y + 2^{m_2} Q &= 2^{m_2}V \\ U - z^{-1}2^{m_2}Q &= Y \end{array} \right. \]

The STF & NTF is shown as below \[ V = \frac{1}{2^{m_2}}U + (1-z^{-1})Q \]

To avoid accumulator overflow, stable input range is only of a fraction of the full scale ( $2^{m_1+m_2}-1$) \[ u \leq 2^{m_1+m_2} - 2^{m_2} \]

m1 = 2  # MSBs
m2 = 4  # LSBs

ymax = 2**(m1 + m2)
umax = 2**(m1 + m2) - 2**m2     # int(m1*'1'+m2*'0', 2)
# format(48, '06b')
# Out[4]: '110000'

u = 48
assert u <= umax

ylist = [0]; vlist = [0]
elist = []; outlist = []

Niter = 2**10
for _ in range(Niter):
    ecur = vlist[-1] - ylist[-1]
    elist.append(ecur)
    ycur = (u - ecur)
    assert ycur < ymax, print(ycur)
    ylist.append(ycur)
    ycur_bin = format(ycur, f'0{m1+m2}b')
    vcur = int(ycur_bin[:-m2]+'0'*m2, 2)
    vlist.append(vcur)
    outlist.append(int(ycur_bin[:-m2], 2))

print(vlist); print(ylist)
print(sum(vlist)/len(vlist)); print(sum(outlist)/len(outlist)*2**m2)

acc-wordlength.drawio

To avoid overflow

\[ \log_2(2^k + 2^{N-m}) \leq N \]

Thus \[ N \ge k - \log_2(1 - \frac{1}{2^m}) = k+m -\log_2(2^m-1) \]

suppose $m\in [1,+\infty)$ \[ k < k - \log_2(1 - \frac{1}{2^m}) \leq k + 1 \] $N = k +1$ is sufficient for any $k$

In the above Temes's sides, $N = m_1+m_2$ and $m=m_1$, we have \[ 2^k \leq 2^{m_1+m_2}\cdot (1-\frac{1}{2^{m_1}}) = 2^{m_1+m_2} - 2^{m_2} \]

Generally speaking, $N \propto k$ and $N \propto \frac{1}{m}$, especially $N_{min} = k+1$ if single-bit quantizer $m=1$

DSM Order & Output Range

7.4.1 Delta-Sigma Modulator [https://iic-jku.github.io/radio-frequency-integrated-circuits/rfic.html#sec-pll-delta-sigma]

Google AI Mode [https://share.google/aimode/FTiU7YPjm3tnqEk7t]

Fractional-N PLL

Accumulated Quantization Error (AQE)

\[ (N+\alpha)T_{PLL} - \tau[n-1] +\tau[n] = (N+y[n])T_{PLL} \]

i.e. \[ \tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL} \]

where $\tau[n] = t_{v_{DIV}} - t_{v_{DIV}, desired}$

Y. Zhang et al., "A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602-614, March 2020, [pdf]

X. Wang and M. P. Kennedy, "Unified Analysis of Digital Δ-Σ Modulators (DDSMs) for Fractional-N Frequency Synthesis—Introducing the PASS Family of DDSMs Featuring Independent Shaping of the Probability Density and Spectral Envelope," in IEEE Transactions on Circuits and Systems I: Regular Papers [link]

X. Wang and M. P. Kennedy, "Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs," 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Valencia, Spain, 2023 [link]

$\Delta\Sigma$ Noise in PLL

$ddsm_fracpll_zoh.drawio$

\[\begin{align} S_\phi(f) &= \frac{1}{12F_{ref}}|1-z^{-1}|^{2L}\cdot \left|\frac{2\pi z_{-1}}{1-z^{-1}}\right|^2\cdot \frac{1}{T_{ref}^2} T_{ref}^2 \\ &= \frac{1}{12F_{ref}} |1-z^{-1}|^{2L-2} 4\pi^2 \end{align}\]

with $|1-z^{-1}| = |2\sin\frac{\pi f}{F_{ref}}|$

\[ S_\phi(f) = \frac{1}{12F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)}\cdot 4\pi^2 = \frac{\pi^2}{3F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)} \]

Frequency & Time-Domian Model for Q-noise

metroidman, fractional N量化噪声对系统相位噪声的影响两种分析方法 LTI频域法和时域采样DFT法 [link]

LTI Frequency domain model & analysis

fcw: Frequency Control Word

note

$z=e^{j2\pi f \color{red}T_\text{ref}}$ — model's time tick is reference clock period

$\frac{\Phi}{N}(z)$ — relationship between $\Phi$ and $N$

% --- System Parameters ---
fref = 40e6;
fcw = 360.123;
kvco = 2 * pi * 300e6;
 
% Components
icp = 60e-6; C0 = 40e-12;
R1 = 14000; C1 = 360e-12;
R2 = 1000; C2 = 20e-12;

% --- Frequency Vector ---
f = logspace(2, 9, 1000); 
s = 1i * 2 * pi * f;

% --- Loop Filter Transfer Function ---
num_lf = s .* R1 .* C1 + 1;
den_lf = (s.^3 .* R1 .* R2 .* C0 .* C1 .* C2 + ...
          s.^2 .* (R1.*C1.*C0 + R1.*C1.*C2 + R2.*C2.*C0 + R2.*C2.*C1) + ...
          s .* (C0 + C1 + C2));
loopfilter = num_lf ./ den_lf;

% --- Loop Gain and Noise Transfer Function ---
loopgain = (icp / (2*pi)) .* loopfilter .* (kvco ./ s) .* (1 / fcw);
hfra = (loopgain ./ (1 + loopgain)) .* 2*pi./(exp(s./fref) - 1) .* (1 - exp(-s./fref)).^3;

% --- Spectral Density calculation ---
sfra = 10 * log10((1 / (12 * fref)) .* abs(hfra).^2);

% --- Plot ---
semilogx(f, sfra, LineWidth=2);
ylim([-250, -100]); yticks(-250:10:-100); 
grid on; xlabel('Frequency (Hz)'); ylabel('dB');
title('Quantization Noise Effects', FontSize=14);

Time domain model & DFT analysis

Round in In[24] is redundant and likely unnecessary for the logic to function

$\phi$ and phi is frequency (cycles per second) instead of angular frequency (radians per second)

classic PLL module transient response

initial state is Reset

classic PLL module in Matlab & Simulink

Kai Wang, Is there a way to improve the code speed? [https://www.mathworks.com/matlabcentral/answers/2039821-is-there-a-way-to-improve-the-code-speed]

classic PLL module in Julia

Julia version (Claude Opus 4.7) [https://gist.github.com/raytroop/53f210b2cca18ec77295dc91dbe35818]

classic PLL module in Mathematica

Impulse Train Modulator (ITM)

M. H. Perrott, M. D. Trott and C. G. Sodini, "A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis," in IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002 [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]

$\Delta\Sigma$ DAC

LPF (RC Filter)

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

Sigma-delta digital-to-analog converters (SD DAC’s) are often used for discrete-time signals with sample rate much higher than their bandwidth

Because of the high sample rate relative to signal bandwidth, a very simple DAC reconstruction filter (Analog lowpass filter) suffices, often just a one-pole RC lowpass

R= 4.7e3;                 % ohms resistor value
C= .01e-6;                % F capacitor value
fs= 1e6;                  % Hz DAC sample rate
% input signal
x= [zeros(1,20) .9*ones(1,200) .1*ones(1,200)];
% find output y of SD DAC and output y_filt of RC filter
[y,y_filt]= sd_dacRC(x,R,C,fs);

t = linspace(0,length(x)-1, length(x))*1/fs*1e3;
subplot(3,1,1)
plot(t, x, '.'); title('x'); grid on
subplot(3,1,2)
plot(t, y, '.'); title('y'); grid on
subplot(3,1,3)
plot(t, y_filt); title('y_{filt}'); xlabel('t(ms)'); grid on

% https://www.dsprelated.com/showarticle/1642.php
% Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter

% function [y,y_filt] = sd_dacRC(x,R,C,fs)  2/5/24 Neil Robertson
% 1-bit sigma-delta DAC with RC filter
% Model does not include a zero-order hold.
%
% x = input signal vector, 0 <= x < 1
% R = series resistor value, Ohms.  Normally R > 1000 for 3.3 V logic.
% C = shunt capacitor value, Farads
% fs = sample frequency, Hz
% y = DAC output signal vector, y(n) = 0 or 1
% y_filt = RC filter output signal vector
%
function [y,y_filt] = sd_dacRC(x,R,C,fs)
N= length(x);
x= fix(x*2^16)/2^16;        % quantize x to 16 bits
%I 1-bit Sigma-delta DAC
s= [x(1) zeros(1,N-1)];
for n= 2:N
    u= x(n) + s(n-1);
    s(n)= mod(u,1);        % sum
    y(n)= fix(u);          % carry
end

%II One-pole RC filter model
% Matched z-Transform https://ocw.mit.edu/courses/2-161-signal-processing-continuous-and-discrete-fall-2008/cc00ac6d468dc9dcf2238fc1d1a194d4_lecture_19.pdf
Ts= 1/fs;
Wc= 1/(R*C);               % rad -3 dB frequency
fc= Wc/(2*pi);             % Hz -3 dB frequency
a1= -exp(-Wc*Ts);
b0= 1 + a1;                % numerator coefficient
a= [1 a1];                 % denominator coeffs
y_filt= filter(b0,a,y);    % filter the DAC's output signal y

ZOH (Zero-Order Hold Models)

Neil Robertson, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

The last D2C is in human vision, which connect discrete time $y(m)$ with line, implicitly

Sinc Corrector

Neil Robertson, Design a DAC sinx/x Corrector [https://www.dsprelated.com/showarticle/1191.php]

Dan Boschen. how to make CIC compensation filter [https://dsp.stackexchange.com/a/31596/59253]

—. Core Building Blocks for Software Defined Radio (SDR): DDC, DUC, NCO) [https://lnkd.in/p/e2MtC9QK]

Equalizing Techniques Flatten DAC Frequency Response [https://www.analog.com/en/resources/technical-articles/equalizing-techniques-flatten-dac-frequency-response.html]

aka. Inverse Sinc Compensation

TODO 📅

OSR & NS

maximum output signal 22kHz

\[SNR = 16\times 6.02 + 1.76 = 98.08\]

OSR = 5.65e6/(2*22e3);
Nin = 16;
Nout = 1;

SNR_in = 6.02*Nin + 1.76;

SNR_ds = 6.02*Nout + 1.76 - 10*log10(pi^4/5) + 50*log10(OSR);

QN_in = 1/10^(SNR_in/10);
QN_ds = 1/10^(SNR_ds/10);

SNR_out = 10*log10(1/(QN_in + QN_ds));

Y. Liu, J. Gao and X. Yang, "24-bit low-power low-cost digital audio sigma-delta DAC," in Tsinghua Science and Technology, vol. 16, no. 1, pp. 74-82, Feb. 2011 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6077939]

snr_if = 144;
snr_ds = 135;
snr_ana = 95;

n_if = 1/10^(snr_if/10);
n_ds = 1/10^(snr_ds/10);
n_ana = 1/10^(snr_ana/10);

snr_tot = 10*log10(1/(n_if + n_ds + n_ana))

% 
% snr_tot =
% 
%    94.9995

MASH 1-1-1 Model

J. W. M. Rogers, F. F. Dai, M. S. Cavin and D. G. Rahn, "A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC," in IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 678-689, March 2005 [https://sci-hub.se/10.1109/JSSC.2005.843604]

(a) a fractional accumulator, and (b) a triple-loop $\Delta\Sigma$ accumulator for $N(z) = 100 + 1/32$

$n=5$

import numpy as np
import matplotlib.pyplot as plt
import scipy.fft as fft
import scipy.signal.windows as windows

def acc_nbit(din, nbit=5, ncycles=2**10):
    mod = 2**nbit
    acc = 0
    eq = 0
    colist = []
    eqlist = []
    for i in range(ncycles):
        acc = din[i] + eq
        eq = acc % mod
        #print(acc, eq)
        co_tmp = int(acc >= mod)
        colist.append(co_tmp)
        eqlist.append(eq)
    return colist, eqlist

Ncyl = 2**16
cin1 = [1]*Ncyl

c1,eq1 = acc_nbit(cin1, ncycles=Ncyl)
cin2 = [0,*eq1[:-1]]
#cin2 = eq1

c2,eq2 = acc_nbit(cin2, ncycles=Ncyl)
cin3 = [0,*eq2[:-1]]
#cin3 =  eq2

c3,eq3 = acc_nbit(cin3, ncycles=Ncyl)

ctot = []

for i in range(2, Ncyl):
    # C1(z) + (1 − z^−1)C2(z) + (1 − z^−1)^2 C3(z)
    ctot_cur = c1[i] + c2[i]-c2[i-1] + c3[i]-2*c3[i-1] + c3[i-2]
    ctot.append(ctot_cur)

print(sum(c1)/len(c1))      # 0.03125
print(sum(ctot)/len(ctot))  # 0.03128147221289712

plt.figure(figsize=(20,8))
plt.subplot(1,2,1)
plt.plot(c1[:200], 'o-', label='c1')
plt.legend(loc='upper left'); plt.grid(True)
plt.subplot(1,2,2)
plt.plot(ctot[:200], 'o-', label='ctot')
plt.legend(loc='upper left'); plt.grid(True)


Ntot = int(2**np.floor(np.log2(len(ctot))))
c1_4fft = np.array(c1[:Ntot])
ctot_4fft = np.array(ctot[:Ntot])
whann = windows.hann(Ntot)
Y_c1 = abs(fft.rfft(c1_4fft*whann))/sum(whann)
Y_ctot = abs(fft.rfft(ctot_4fft*whann))/sum(whann)

print(Y_c1[0])      # 0.031250000002717625
print(Y_ctot[0])    # 0.031249999999526525

plt.figure(figsize=(20,8))
plt.subplot(2, 1, 1)
_, stemlines, _ = plt.stem(Y_c1, markerfmt=" ", label='c1')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')
plt.subplot(2, 1, 2)
_, stemlines, _ = plt.stem(Y_ctot, markerfmt=" ", label='ctot')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')

plt.show()

Harald Pretl, Radio-Frequency Integrated Circuits. 7.4 Fractional-N PLL [note] [MASH Modulator (3rd Order) code]

# Stage 1: 1st order modulator with input signal
self.integrator1 += input_value
y1 = 1 if self.integrator1 >= 1.0 else 0
e1 = self.integrator1 - y1  # Quantization error
self.integrator1 = e1  # Store error for next iteration

# Stage 2: 1st order modulator fed with quantization error from stage 1
self.integrator2 += e1
y2 = 1 if self.integrator2 >= 1.0 else 0
e2 = self.integrator2 - y2
self.integrator2 = e2

# Stage 3: 1st order modulator fed with quantization error from stage 2
self.integrator3 += e2
y3 = 1 if self.integrator3 >= 1.0 else 0
e3 = self.integrator3 - y3
self.integrator3 = e3

# Digital noise cancellation logic for MASH 1-1-1
# Output = Y1 + (1-z^-1)*Y2 + (1-z^-1)^2*Y3
# Expanding (1-z^-1)^2 = 1 - 2*z^-1 + z^-2:
# Output = Y1 + Y2 - Y2[z^-1] + Y3 - 2*Y3[z^-1] + Y3[z^-2]

combined = y1 + (y2 - self.y2_prev) + (y3 - 2*self.y3_prev + self.y3_prev2)

for i in range(length):
    dither = rng.uniform(-dither_amplitude, dither_amplitude) if dither_amplitude > 0 else 0.0
    combined, y1, y2, y3 = self.step(input_value + dither)
    combined_output[i] = combined
    y1_output[i] = y1
    y2_output[i] = y2
    y3_output[i] = y3

# Plot 2: Frequency spectrum (with dither)
ax2 = plt.subplot(1, 2, 2)
N = len(mash_combined_with_dither)
fft_freq = np.fft.fftfreq(N)
pos_freq = fft_freq >= 0
fft_no = np.fft.fft(mash_combined_with_dither)
psd_no = 20 * np.log10(np.abs(fft_no) / N + 1e-12)

fig-mash-dither

metroidman, 用Simulink Excel Mathematica三种不同工具从零搭建3阶ΣΔ调制器并进行时域和频率分析 [link]

Simulink

Excel

Mathematica

The code fcwit = Table[fcwi[i], {i, 9999}]; is the command that actually runs the simulation for a set duration.

Here is the breakdown of what is happening:

Table[..., {i, 9999}]: This creates a list by repeating an operation 9,999 times. It acts like a for loop in other programming languages.
fcwi[i]: This calls the function you defined earlier. For every value of i from 1 to 9,999, it calculates the instantaneous integer division ratio produced by the MASH modulator.
fcwit = ...: It stores all 9,999 results into a single long list (an array) named fcwit.
; (Semicolon): This is important—it suppresses the output. Without it, Mathematica would print all 9,999 numbers on your screen, which would be a huge mess!

reference

Michael Peter Kennedy. scv-cas 2014: Digital Delta-Sigma Modulators [pdf,recording]

—, Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators [pdf]

Kaveh Hosseini and Peter Kennedy. 2006 Hardware Efficient Maximum Sequence Length Digital MASH Delta Sigma Modulator [pdf]

Jason Sachs. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

Neil Robertson, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Rick Lyons. How Discrete Signal Interpolation Improves D/A Conversion [https://www.dsprelated.com/showarticle/167.php]

Dan Boschen. sigma delta modulator for DAC [https://dsp.stackexchange.com/a/88357/59253]

Woogeun Rhee. ISCAS 2019 Mini Tutorials: Single-Bit Delta-Sigma Modulation Techniques for Robust Wireless Systems [https://youtu.be/OEyTM4-_OyA]

—, 2001 Phd Thesis: Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers [https://www.ime.tsinghua.edu.cn/Thesis_rhee.pdf]

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2017/05/2007-TCASI-S.-Pamarti-Statistics-of-the-Quantization-Noise-in-1-Bit-Dithered-Single-Quantizer-Digital-Delta-Sigma-Modulators.pdf]

—. "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]

—. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8]

Ian Galton. Delta-Sigma Fractional-N Phase-Locked Loops [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2022/10/fnpll_ieee_tutorial_2003_corrected.pdf]

—. ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]

—. “Delta-Sigma Fractional-N Phase-Locked Loops.” (2003).

Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T6Visuals.pdf]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

John Rogers, Calvin Plett, and Foster Dai. 2006. Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library). Artech House, Inc., USA. [pdf]

K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital Delta-Sigma Modulators (Analog Circuits and Signal Processing). New York, NY, USA: Springer, 2011.

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007.

\(x[n]+s[n]\)	\(v\)	\(e[n]\)	\(c[n]\), y
0\|00	0	0	0
0\|01	1	1	0
0\|10	2	2	0
0\|11	3	3	0
1\|00	4	0	1
1\|01	5	1	1
1\|10	6	2	1
1\|11	7	3	1