Analog Techniques

Posted on Edited on In

Push-Pull

TODO šŸ“…

Rinaldo Castello, "LINEARIZATION TECHNIQUES FOR PUSH-PULL AMPLIFIERS" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/AMPLIFIERS_Stanf_Tor_2016_Last.pdf]

Rail-to-Rail Op amp

[https://mixsignal.wordpress.com/wp-content/uploads/2013/03/689-604rail2rail.pdf]

[https://toshiba.semicon-storage.com/ap-en/semiconductor/knowledge/faq/linear_opamp/what-does-rail-to-rail-mean.html]

TODO šŸ“…

self-biased active loading

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Vishal Saxena "CMOS Comparator Design Extra Slides" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Comparator%20Slides.pdf]

preampSong202412181018

W. Liu, P. Huang and Y. Chiu, "A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010 [https://sci-hub.se/10.1109/ISSCC.2010.5433830]

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Additional notes on the Flipped Voltage Follower Courtesy of Prof. Jaime Ramirezā€ Angulo [https://people.engr.tamu.edu/s-sanchez/607%20Lect%205%20BB%20FVF.pdf]

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Slewing in Folded-Cascode Op Amps

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In practice, we choose \(I_P \simeq I_{SS}\)

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Avoid zero current in cascodes

  • left circuit

    \(I_b \gt I_a\)

  • right circuit

    \(I_b \gt 2I_a\)

Huijsing, J. H. (2017). Operational Amplifiers: Theory and Design. (3 ed.) Springer

[https://bbs.eetop.cn/forum.php?mod=redirect&goto=findpost&ptid=995502&pid=11548528]

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Response Speed in Analog Circuits

Hyun-Sik Kim, KAIST, A-SSCC 2024 Circuit Insights: FT3 Accelerating Response Speed in Analog Circuits [link]

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Bandwidth limitation

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slew rate limitation

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Assume a linear response to a 1 V input step \[ V_o(t) = 1 - e^{-\omega_T t} \]

\[ \frac{\mathrm{d}V_o}{\mathrm{d}t} = \omega_Te^{-\omega_T t} = \frac{g_m}{C_L}e^{-\omega_T t} = \frac{g_m}{I_B}\cdot \frac{I_B}{C_L}\cdot e^{-\omega_T t} \gt \frac{I_B}{C_L} \]

because \(\frac{g_m}{I_B} e^{-\omega_T t} \gt 1\) near \(t = 0\). The slope a linear response requires exceeds what \(I_B\) can supply.

Therefore, the initial response is limited by SR (\(I_B/C_L\)), not by \(G_m\) (or bandwidth)

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MOS parasitic Rd&Rs, Cd&Cs

When reducing parasitic R and C, prioritize the source side: \(R_s\) over \(R_d\), \(C_s\) over \(C_d\)

Source Follower

A. Sheikholeslami, "Voltage Follower, Part 1 [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 14, no. 3, pp. 13-15, Summer 2022, [https://sci-hub.jp/10.1109/MSSC.2022.3182791]

ā€”, "Voltage Follower, Part II [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 1, pp. 17-19, winter 2023, [https://sci-net.xyz/10.1109/MSSC.2022.3218083]

ā€”, "Voltage Follower, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457

ā€”, "Voltage Follower, Part IV [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 3, pp. 6-19, Summer 2023, doi: 10.1109/MSSC.2023.3287342

ā€”, ESSCIRC2023 Circuit Insights [https://youtu.be/2xFIZM5_FPw]

ā€”, CICC2025 Circuit Insights: From Simple to Super Source Follower [https://youtu.be/CWfMKltPIQ8]

Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits (5th. ed.). Wiley Publishing.

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Flipped Voltage Follower (FVF)

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_flipped-voltage-follower-fvf-basics-activity-7118482840803020800-qwyX?utm_source=share&utm_medium=member_desktop]

Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 116-118, [https://sci-net.xyz/10.1109/ISSCC42614.2022.9731650]

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Moving the bias current source from the source to the drain of the follower transistor is called flipping, hence the name FVF

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\[ \boxed{G_m = g_{m1} r_{o1}\cdot g_{m2} \qquad \qquad R_{out} = \frac{1}{g_{m1}r_{o1}\cdot g_{m2}}} \]

Super-source follower (SSF)

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Class AB SSF (AB-SSF)

All three followers (SVF, FVF, SSF) share a major limitation: an asymmetric response to rising and falling input steps

image-20260928201215696 \[ SR^+_{SVF} \gt SR^-_{SVF} \qquad \qquad SR^+_{FVF} \lt SR^-_{FVF} \qquad \qquad SR^+_{SSF} \gt SR^-_{SSF} \]

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Assume RB is very large and CB acts as a short circuit over the frequency range of interest

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Folded Cascode FVF (CA-FVF)

Mao, Xiangyu, Yan Lu, and Rui P. Martins. Fully-Integrated Low-Dropout Regulators. Springer, 2025.

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The basic FVF LDO has limited loop gain. To increase it:

    1. insert a common-gate amplifier (M2, biased by I2) between VD and VG
    1. add a common-source amplifier (M3 with current mirror M4ā€“M5) for further gain

built-in local negative feedback

T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok and M. Chan, "Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 5, pp. 1392-1401, June 2008, doi: 10.1109/TCSI.2008.916568 [https://repository.hkust.edu.hk/ir/bitstream/1783.1-3269/1/044360751.pdf]

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Intuition: building the loop from common-source stages and current mirrors keeps the internal nodes at low impedance, which pushes their poles to high frequency. The FVF can then drive a large capacitive load while its local negative feedback loop stays stable

T&H buffer in ADC

The FVF has the same voltage gain as a simple voltage follower (SVF) but an output resistance \(g_m r_o\) times lower, which gives fast settling at low power

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Differential pair

Todd Brooks, Broadcom "Input Programmable Gain Amplifier (PGA) Design for ADC Signal Conditioning" [https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/OSU%20Classroom%20Presentaton%20042511.ppt]

virtual ground?

image-20260703224921011 \[ \color{blue}V_P = V_{CM} - V_{TH} - \frac{1}{2} \sqrt{ -(2\Delta V)^2 + 4V_{ov,eq}^2 } \] image-20260703225321502

nonlinearity

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Resistive Degeneration

Resistive degeneration is a primary technique for linearizing a differential pair

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Degeneration extends the input linear range by \(\pm I_{SS}R/2\). At the edge, M2 turns off and M1 carries all of \(I_{SS}\), so \(I_{SS}/2\) flows through \(R\): \[ V_{in}^+ -V_{in}^- = V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} = \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \]

Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf

Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]

Biasing Tradeoffs in Resistive-Degenerated Diff Pair

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w/ Currentā€“Mirror Load

S. Pavan, "Revisiting the CMOS Differential Pair With a Currentā€“Mirror Load [CAS Education]," in IEEE Circuits and Systems Magazine, vol. 25, no. 2, pp. 74-78, Secondquarter 2025 [pdf]

TODO šŸ“…

Double Differential pair

\(V_\text{ip}\)/\(V_\text{im}\) are the differential input and \(V_\text{rp}\)/\(V_\text{rm}\) the differential reference \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

2diffpair.drawio

In differential comparison mode, the feedback loop eventually forces \(V_\text{ip} = V_\text{rp}\) and \(V_\text{im} = V_\text{rm}\)

assuming the input and reference common-mode voltages are the same

Pros of (b)

  • wider input range: (a) is limited to \(\pm \sqrt{2}V_\text{ov}\), while (b) still works when one device of a pair is off
  • larger \(g_m\): each pair sees only a small differential input near balance

Cons of (b)

  • sensitive to the common-mode difference between the input (\(V_\text{ip}\), \(V_\text{im}\)) and the reference (\(V_\text{rp}\), \(V_\text{rm}\))

common-mode voltage difference

doublepair_cm.drawio

Repeated from above for convenience \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

(a) sample phase

\(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}= V_\text{cmr}\)

  • \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\)
  • \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

so \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

(b) compare start

  • \(V_\text{ip}= V_\text{im}= V_\text{cmi}\), \(V_\text{rp}= V_\text{cmr}+\Delta\) and \(V_\text{rm}= V_\text{cmr}-\Delta\)
  • \(I_\text{ip}\lt I_\text{ip0}\), \(I_\text{rp} \gt I_\text{rp0}\)
  • \(I_\text{im}\gt I_\text{im0}\), \(I_\text{rm} \lt I_\text{rm0}\)

so \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} \lt 0\), and the loop must raise \(V_\text{ip}\) and lower \(V_\text{im}\)

(c) compare finish

\[\begin{align} V_\text{ip}= V_\text{cmi} + \Delta \\ V_\text{im}= V_\text{cmi} - \Delta \end{align}\]

The currents return to their sample-phase values, \(I_\text{ip}= I_\text{im} = I_\text{i0}\) and \(I_\text{rp}= I_\text{rm} = I_\text{r0}\)

so \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

If \(V_\text{cmr} - V_\text{cmi} = \sqrt{2}V_{OV} + \delta\) with \(\delta \gt 0\), one transistor carries the entire tail current throughout the comparison

  • \(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\)

The loop then settles at \(V_\text{im} = V_\text{cmi} - (\Delta - \delta)\), an error of \(\delta\)

Correct operation therefore requires \(V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV}\)

In practice, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized further because of the finite output impedance of the tail current source and the input-pair offset, giving \[ V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS} \]

Under this condition, all transistors in both pairs stay on at equilibrium

pair mismatch

diff_mismatch_connect.drawio

\[\begin{align} I_{SE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \\ I_{DE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \end{align}\]

The input-referred offset voltage \[\begin{align} V_{os,SE} &= \frac{I_{SE}}{2g_m} = \frac{\sigma_{vth,0} + \sigma_{vth,1}}{2} \\ V_{os,DE} &= \frac{I_{DE}}{g_m} = \sigma_{vth,0} + \sigma_{vth,1} \end{align}\]

With independent mismatch, \(\sigma_{vth,0} = \sigma_{vth,1} = \sigma_{vth}\) \[\begin{align} \sigma_{vos,SE} &= \sqrt{\frac{2\sigma_{vth}^2}{4}} = \frac{\sigma_{vth}}{\sqrt{2}} \\ \sigma_{vos,DE} &= \sqrt{2\sigma_{vth}^2} = \sqrt{2}\sigma_{vth} \end{align}\]

Therefore \[ \sigma_{vos,DE} = 2\sigma_{vos,SE} \]

Gm/ID Approach in Transistor Sizing

Hesham Omran, The Analog Designer's Toolbox (ADT) | Invited Talk by IEEE Santa Clara Valley Section CAS Society [https://youtu.be/FT6kKC5OdE0]

Jespers, P. G. A., & Murmann, B. (2017). Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press.

Boris Murmann, February 26, 2016, Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/20160226toronto_sscs.pdf]

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Use a small \(g_m/I_D\) (strong inversion) for high \(r_o\), i.e., a high Early voltage \(V_A\): the gate controls the channel better, so \(V_{DS}\) has less effect

C/ID Approach in Transistor Sizing

Armin Tajalli, 27 August 2024, Algorithmic Analog Design C/ID: A Design Oriented FET Modeling and Design Approach [https://lcas.ece.utah.edu/wp-content/uploads/sites/91/2024/10/Introduction-to-CID-Algorithm-in-Circuit-Design.pdf]

ā€”, CICC 2026 Circuit Insights, C over ID Approach in Transistor Sizing

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TODO šŸ“