ADC in Instrument & Measurement (I&M)

Posted on Edited on In

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Dual Slope ADC

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\[ V_{IN} = \frac{V_{REF}}{T}t_\text{x} = \frac{V_{REF}}{2^N}\cdot 2^{N_\text{x}} \]

Normal Mode Rejection

a high normal mode rejection ratio (NMRR) for input noise at line frequency

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  • Conversion accuracy is independent of both the capacitance and the clock frequency, because they affect both the up-slope and the down-slope by the same ratio

  • The fixed input signal integration period results in rejection of noise frequencies on the analog input that have periods that are equal to or a sub-multiple of the integration time \(T\)

    Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (\(1/T\)) averaged over a period (\(T\)) is zero

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Linear Circuit Design Handbook, 2008 [https://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter6.pdf]

Precision Analog Front Ends with Dual Slope ADC [https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/21428e.pdf]

Incremental ADC

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\[\begin{align} V &= 2^N V_\text{in} - D_\text{out}V_\text{ref} \\ D_\text{out} \frac{V_\text{ref}}{2^N} &= V_\text{in} - \frac{V}{2^N} \end{align}\]

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feedforward structure

??? TODO 📅

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Discrete-Time Integrators

Delaying Integrator

Delay-free Integrator

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reference

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA?si=_pGb18rhsMUZ-lAf]