Delta-Sigma Modulator
Analog Delta Sigma Modulators (ADSM) are used in the context of analog-to-digital conversion
- In a CT delta-sigma ADC, there is no need for an anti-aliasing filter or a front-end sampler
Digital Delta Sigma Modulators (DDSM) are commonly used in digital to-analog conversion and fractional-N frequency synthesis
- In a DDSM, the input is digital and the filters are implemented digitally
- the input to the DDSM is often a constant digital word, this covers delta-sigma fractional-N synthesizers in the frequency generation application
No delay-free loops
Both integrator and quantizer are delay free
NTF realizability criterion: No delay-free loops in the modulator
linear settling & GBW of amplifier
TODO 📅
Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.
Delta Modulator
\[\begin{align} (V_{in} - V_F) &= D_{out} \\ D_{out} &= s V_F \end{align}\]
Therefore \(V_{in} - \frac{D_{out}}{s} = D_{out}\) \[ D_{out} = \frac{s}{s+1} V_{in} \]
attenuates the low-frequency content of the signal, and amplifies high-frequency noise.
MOD1
\[
V(z) = U(z) +(1-z^{-1})E(z)
\]
- A binary DAC (and hence a binary modulator) is inherently linear
- With a CT loop filter, MOD1 has inherent anti-alising
\[\begin{align}
v[1] &= u - (0) + e[1] \\
v[2] &= 2u - (v[1]) + e[2] \\
v[3] &= 3u - (v[1]+v[2]) + e[3] \\
v[4] &= 4u - (v[1]+v[2]+v[3]) + e[4]
\end{align}\]
That is \[ v[n] = nu - \sum_{k=1}^{n-1}v[k] + e[n] \] Therefore, we have \(v[n-1] = (n-1)u - \sum_{k=1}^{n-2}v[k] + e[n-1]\), then \[\begin{align} v[n] &= nu - \sum_{k=1}^{n-1}v[k] + e[n] \\ &= u + \left((n-1)u - \sum_{k=1}^{n-2}v[k]\right) - v[n-1] + e[n] \\ &= u + v[n-1] - e[n-1] -v[n-1] + e[n] \\ &= u + e[n] - e[n-1] \end{align}\]
Dout, the low frequency component of ADC out is same with Vin
MOD2
decimation filter
The combination of the the digital post-filter and downsampler is called the decimation filter or decimator
\(\text{sinc}\) filter
\(\text{sinc}^2\) filter
Truncation DAC
modulator output is \(v\) and \(y+e = v\), i.e. the quantization or truncation error is \(v-y\)
\[ \left\{ \begin{array}{cl} Y + E &= V \\ U - E z^{-1} &= Y \end{array} \right. \]
The STF and NTF is shown as below \[ V = U + (1-z^{-1})E \]
An implementation of a high-resolution integral path using a digital delta-sigma modulator, low-resolution Nyquist DAC, and a lowpass filter
- \(\Delta \Sigma\) truncates \(n\)-bit accumulator output to \(m\)-bits with \(m\le n\)
- A \(m\)-bit Nyquist DAC outputs current, which is fed into a low pass filter that suppresses \(\Delta \Sigma\)'s quantization noise
The remaining 11 bits are truncated to 3-levels using a second-order delta-sigma modulator (DSM), thus, obviating the need for a high resolution DAC
Hanumolu, Pavan Kumar. "Design techniques for clocking high performance signaling systems" [https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]
1st order DDSM
Mismatch Shaping
Data-Weighted Averaging (DWA)
\[\begin{align}
\sum_{i=0}^{n}v[i] + e_\text{DAC}[n] &= y[n] \\
\sum_{i=0}^{n-1}v[i] + e_\text{DAC}[n-1] &= y[n-1]
\end{align}\]
and we have \(w[n] = y[n] - y[n-1]\), then \[ w[n] = v[n] + e_\text{DAC}[n] - e_\text{DAC}[n-1] \] i.e. \[ W = V + (1-z^{-1})e_\text{DAC} \]
Element Rotation:
[http://individual.utoronto.ca/schreier/lectures/12-2.pdf], [http://individual.utoronto.ca/trevorcaldwell/course/Mismatch.pdf]
LSB Dither
dithering break periodicity and convert them to noise while input is constant
drawback of Integer-N PLL
integer-N PLL frequency synthesizers
the frequency resolution, is equal to the reference frequency, meaning that only integer multiples of the reference frequency can be synthesized
if fine tuning is required, only choice in an integer-N PLL is to decrease the reference frequency
Stability requirements limit the loop bandwidth to about one tenth of the reference frequency; therefore, decreasing the reference frequency increases the settling time as the loop bandwidth also has to be decreased
Another drawback of the integer-N PLL is the trade-off between phase noise and settling time when the divider ratio becomes large (The contributions to the output phase noise of almost all PLL building blocks, except the VCO, are multiplied by the division ratio)
[https://people.engr.tamu.edu/spalermo/ecen620/lecture03_ee620_pll_system.pdf]
if a small reference frequency is chosen, the reference spur in the output phase noise is located at a smaller offset frequency
Fractional-N PLL
\[
\tau[n-1] + (N+y[n])T_{PLL} - (N+\alpha)T_{PLL} = \tau[n]
\]
i.e. \[ \tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL} \]
where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV}, desired}\)
In \(z\)-domain \[ \left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y \right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y \] That is \[ Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2 \] In time domain \[\begin{align} y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\ &= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2] \end{align}\]
quantizer overload
TODO 📅
reference
R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data Converters
Shanthi Pavan, ISSCC2013 T5: Simulation Techniques in Data Converter Design [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T5.pdf]
Bruce A. Wooley , 2012, "The Evolution of Oversampling Analog-to-Digital Converters" [https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf]
B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016. [http://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf]
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
Richard E. Schreier, ECE 1371 Advanced Analog Circuits - 2015 [http://individual.utoronto.ca/schreier/ece1371-2015.html]
Gabor C. Temes. ECE 627-Oversampled Delta-Sigma Data Converters [https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/lecturenotes.html]
Boris Murmann, ISSCC2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [link]
Ian Galton. Delta-Sigma Fractional-N Phase-Locked Loops [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2022/10/fnpll_ieee_tutorial_2003_corrected.pdf]
Sudhakar Pamarti. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8?si=tbav3J2yag38HyZx]
Joshua Reiss. Understanding sigma delta modulation: the solved and unsolved issues
Ian Galton ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]
S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2017/05/2007-TCASI-S.-Pamarti-Statistics-of-the-Quantization-Noise-in-1-Bit-Dithered-Single-Quantizer-Digital-Delta-Sigma-Modulators.pdf]
S. Pamarti and I. Galton, "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]
Michael Peter Kennedy. An Introduction to Digital Delta-Sigma Modulators [https://site.ieee.org/scv-cas/files/2014/07/2014Kennedy.pdf]
Kaveh Hosseini , Michael Peter Kennedy. Springer 2011. Minimizing Spurious Tones in Digital Delta-Sigma Modulators