Wireline Receiver

Posted on Edited on In

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VGA/attenuator: ensure a constant swing at the slicer input regardless of the channel variation

CTLE Linearity

TODO 📅

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Front-End Noise

https://people.engr.tamu.edu/spalermo/ecen689/lecture6_ee720_rx_circuits.pdf

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Decision Feedback Equalizer (DFE)

speculative DFE is also known as loop unrolled DFE, which solve the critical timing on first tap

DFE architecture

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Extensive work on DFEs has produced a multitude of architectures, which can be broadly categorized as "direct"" or "unrolled" (speculative) DFEs with "full-rate" or "half-rate" clocking

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S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for 20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]

S. Ibrahim and B. Razavi, Low-Power DFE Design [https://picture.iczhiku.com/resource/eetop/wykflwIuIQDzYNcB.PDF]

DFE Error Propagation

Geoff Zhang. Preliminary Studies on DFE Error Propagation, Precoding, and their Impact on KP4 FEC Performance for PAM4 Signaling Systems [https://www.ieee802.org/3/ck/public/18_09/zhang_3ck_01a_0918.pdf]

Cathy Liu, The Effect of DFE Error Propagation [https://www.ieee802.org/3/ap/public/nov05/liu_01_1105.pdf]

Yuchun Lu, Huawei, Elimination of DFE Error Propagation and Post-FEC Error Floor (Precoding 2.0) [https://www.ieee802.org/3/ck/public/19_03/lu_3ck_01_0319.pdf]

Z. Wu and J. -R. Guo, "Analysis of UCIe 48/64 GT/s Electrical Links," in IEEE Open Journal of the Solid-State Circuits Society [pdf]

TODO 📅

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PAM4 DFE

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K. -C. Chen, W. W. -T. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 750-762, March 2021 [https://www.mics.caltech.edu/wp-content/uploads/2021/02/JSSC-2020-Xavier-PAM4-Receiver.pdf]

Hongtao Zhang, DesignCon 2016. PAM4 Signaling for 56G Serial Link Applications − A Tutorial [https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

Edge DFE

K. -L. J. Wong, E. -H. Chen and C. -K. K. Yang, "Edge and Data Adaptive Equalization of Serial-Link Transceivers," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2157-2169, Sept. 2008 [[https://sci-hub.ru/10.1109/JSSC.2008.2001876]*https://sci-hub.ru/10.1109/JSSC.2008.2001876]

B. Brunn, “Edge equalization NRZ,” Jul. 2004 [Online]. Available: [http://www.ieee802.org/3/ap/public/jul04/brunn_01_0704.pdf]

CC Chen, "Why Edge DFE?" [https://youtu.be/azkm7A9plyY]

TODO 📅

Peak to Main Ratio (PMR)

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Boesch, et.al., “A 0.003 mm2 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE,” 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016 [https://sci-hub.ru/10.1109/VLSIC.2016.7573522]

—, “Signal preconditioning using feedforward equalizers in ADC-based data links”, Ph.D. Dissertation, Stanford University, 2016 [https://purl.stanford.edu/dk653rc7126]

K. Zheng, “System-Driven Circuit Design for ADC-Based Wireline Data Links”, Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]

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reference

T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M. Mansuri, "Modern Wireline Transceivers," in IEEE Journal of Solid-State Circuits, vol. 61, no. 2, pp. 395-422, Feb. 2026 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=11311714]

S. Jang, J. Lee, Y. Choi, D. Kim and G. Kim, "Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 290-304, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763]

Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes [https://www.youtube.com/live/wHNOlxHFTzY]

Nhat Nguyen and Masum Hossain, ISSCC 2021 Forum F6.7: 112Gb/s-and-Beyond Long-Reach and Short-Reach Electrical Interfaces

Jihwan Kim, Intel, ISSCC 2023 Forum F1.5: Circuit Designs for 200+Gb/s Electrical Transceivers

Ariel Cohen, Intel, ISSCC 2024 Forum F6.3: Beyond 200Gbps Electrical transceivers – Circuit Architecture, Design Implementation and Silicon Results

Heng Zhang, Broadcom, ISSCC 2025 Forum F4.2: High-speed ADCs for 100Gbps+ Wireline Transceivers

E-Hung Chen, MTK, ISSCC 2026 Forum F2.3: State-of-the-Art 200+ Gb/s Electrical and Optical Interconnects