High-Speed ADC for SerDes

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BER with Quantization Noise

image-20240804110522955

\[ \text{Var}(X) = E[X^2] - E[X]^2 \]

image-20240804110235178

reference

Akkaya, A. (2021). High-Speed ADC Design and Optimization for Wireline Links (Publication No. 8453) [PhD thesis, EPFL; Supervised by Y. Leblebici]. [https://doi.org/10.5075/epfl-thesis-8453]

K. Zheng, “System-driven circuit design for ADC-based wireline data links,” Stanford Univ., Stanford, CA, USA, Tech. Rep., 2018 [https://stacks.stanford.edu/file/hw458fp0168/thesis-augmented.pdf]

T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M. Mansuri, "Modern Wireline Transceivers," in IEEE Journal of Solid-State Circuits, vol. 61, no. 2, pp. 395-422, Feb. 2026 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11311714]