The PI-based architecture decouples the high-frequency clock
synthesis and local clock deskew, allowing to optimize the power
consumption and circuit area at a system level
Phase Interpolator (PI)
!!! Clock Edges
And for a phase interpolator, you need those reference clocks to be
completely the opposite. Ideally they would be
triangular shaped
four input clocks given by the cyan, black, magenta, red
John T. Stonick, ISSCC 2011 tutorial. "DPLL Based Clock and Data
Recovery"
the interpolating inverters near the midscale can be made weaker so
as to obtain more uniform phase increments. Alternatively, those at the
top and bottom of the array can be made stronger
Single-Quadrant PI
\[
V_o(t) = m \cdot \sin(\omega t + \frac{\pi}{2}) + p\cdot \sin(\omega t)
= m\cdot \cos(\omega t) + p\cdot \sin(\omega t) = \sqrt{m^2+p^2}
\sin(\omega t + \phi)
\]
where \(\tan \phi = \frac{m}{p} =
\frac{1-p}{p}\) and \(p =
\frac{1}{1+\tan \phi}\)
A constant Output amplitude is desired because the
swing-dependent delay characteristic of the CML-to-CMOS (C2C)
circuit results in AM–PM distortion which eventually manifests
as phase nonlinearity
Current-Mode Phase
Interpolator
Current-mode PIs (CMPIs) can achieve high linearity but at the cost
of digital overhead to generate sinusoidal weights
Thus INL describes the error at a code, while DNL describes the error
in one code-to-code step.
1. Why
\((0.5+|\mathrm{DNL}_p|)T\)?
For an ideal PI, available phases are spaced by \(T\). If the desired transition lies halfway
between two available phases, selecting the nearest phase leaves an
error of
\[
|E_e|\le \frac{T}{2}
\]
That explains the \(0.5\)
With DNL, a particular step has width
\[
t(k+1)-t(k)=[1+\mathrm{DNL}(k)]T
\]
A larger step means a larger gap in which the desired phase might
lie.
So the paper's \(0.5+|\mathrm{DNL}_p|\) is a looser bound
under this model
2. Why does
the data-clock bound become \((1+|\mathrm{DNL}_p|+|\mathrm{INL}_{pp}|)T\)?
\(E_e\) and \(E_d\) are timing errors,
measured in seconds—not the clock times themselves
\(E_e\): edge-sampling
clock error relative to the ideal data-transition time: \[
E_e=t_e-t_{\text{transition}}.
\]
\(E_d\): data-sampling
clock error relative to the ideal data-sampling time, assumed
here to be half a UI after that transition: \[
E_d=t_d-\left(t_{\text{transition}}+\frac{\mathrm{UI}}{2}\right).
\]
Here \(t_e\) and \(t_d\) are the actual sampling
times. A positive error means the clock samples
late; a negative error means it samples
early.
Writing \(H=\mathrm{UI}/2\), these
definitions give
\[
\boxed{E_d=E_e+\underbrace{(t_d-t_e-H)}_{\text{error in edge-to-data
spacing}}.}
\]
Let the desired edge-to-data spacing be
\[
H=\frac{\mathrm{UI}}{2},
\]
and let the data-clock code be \(k+m\) when the edge-clock code is \(k\). Then
\[
t_d-t_e=mT+[I(k+m)-I(k)]T.
\]
Consequently, the data-clock error relative to its ideal sampling
position is
If \(H/T\) is an integer—for
example, a full-period PI with a number of steps divisible by eight can
represent \(45^\circ\) exactly—then
\(mT-H=0\). That extra \(0.5T\) is unnecessary. (If the desired
edge-to-data spacing is exactly representable by an integer number of PI
steps, the spacing-quantization term vanishes, and the constant \(1\) becomes \(0.5\))
The CDR finds an edge-clock code, and the data-clock code is obtained
by adding a fixed code offset
With \(T=T_{\mathrm{LSB}}\) and
\(H=\mathrm{UI}/2\):
The circuit operates continuously: the CDR adjusts \(k_e\), and the data-clock code follows as
\(k_d=k_e+m\). It does not need to
measure a numerical value of \(t_e\)
before generating the data clock.
For nonlinear PIs, adding \(m\) codes does not necessarily add exactly
\(mT\) in time. Assuming a common
timing reference,
A. K. Mishra, Y. Li, P. Agarwal and S. Shekhar, "Improving Linearity
in CMOS Phase Interpolators," in IEEE Journal of Solid-State Circuits,
vol. 58, no. 6, pp. 1623-1635, June 2023 [pdf]
Cortiula A, Menin D, Bandiziol A, Driussi F, Palestri P. Modeling of
Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4
Serial Interfaces. Electronics. 2025; [https://www.mdpi.com/2079-9292/14/10/1979]
G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based
Clock and Data Recovery With Jitter Optimization," in IEEE Open
Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/document/10184121]
T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M.
Mansuri, "Modern Wireline Transceivers," in IEEE Journal of Solid-State
Circuits, vol. 61, no. 2, pp. 395-422, Feb. 2026 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=11311714]
Beer, Salomon & Priel, Michael & Dobkin, Rostislav &
Kolodny, Avinoam. (2010). The Devolution of Synchronizers. Proceedings -
International Symposium on Asynchronous Circuits and Systems. [pdf]
\(T_W\), metastability window is
defined differently among published paper
Some PDK provide \(T_0\) and \(\tau\) for the corresponding cascaded flip
flop synchronizer stdcells \[
\text{MTBF} = \frac{1}{T_W\times f_C\times f_D}\space \space
\text{,where}\space\space T_W = T_0 e^{-T_r/\tau}
\] and \(T_r = T_C - T_{DLY} -
T_{SU}\)
Ran Ginosar
ISCAS 2008 tutorial: Synchronization Circuits for Multiple Clock
Domains SoCs
Enter metastabilty
Exit metastabilty
MTBF (Mean Time Between Failures)
MTBF of Many Synchronizers
Synchronizer
Characterization
I. W. Jones, S. Yang and M. Greenstreet, "Synchronizer Behavior and
Analysis," 2009 15th IEEE Symposium on Asynchronous Circuits and
Systems, Chapel Hill, NC, USA, 2009 [https://sci-hub.ru/10.1109/ASYNC.2009.8]
Xprova. bisect-tau - EDA tool for characterizing the metastability
resolution time constant (Tau) of bistable circuits [https://github.com/xprova/bisect-tau]
For GNU Octave, version 8.4.0, ngspice-42 : Circuit
level simulation program@Ubuntu 24.04.3 LTS x86_64
The typical flip-flops comprise master and slave latches and
decoupling inverters.
In metastability, the voltage levels of nodes A and B of the
master latch are roughly midway between logic 1 (VDD) and 0
(GND)
master latch enter metastability
In fact, one popular definition says that if the output of a
flip-flop changes later than the nominal clock-to-Q propagation
delay, then the flip-flop must have been metastable
Noise Seed—Seed for the random number generator (used by
the simulator to vary the noise sources internally). Specifying the
same seed allows you to reproduce a previous
experiment. The default value is 1.
Kinniment, D. J. Synchronization and arbitration in digital systems.
John Wiley & Sons Ltd (2007).
Synchronizers And Data FlipFlops are Different [pdf]
S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The
Devolution of Synchronizers," 2010 IEEE Symposium on Asynchronous
Circuits and Systems, Grenoble, France, 2010 [pdf]
A dynamical system can be linear or nonlinear. Independently, it can
be deterministic or stochastic. Continuous-time deterministic systems
are commonly modeled by ODEs, while continuous-time stochastic systems
are commonly modeled by SDEs
Deterministic
Stochastic
Linear
Linear ODE
Linear SDE
Nonlinear
Nonlinear ODE
Nonlinear SDE
The two classifications answer different questions:
Linear/nonlinear: How does the state enter the
evolution equation?
Deterministic/stochastic: Does the evolution
include randomness?
For Demir’s oscillator theory, however, the main path is \[
\boxed{
\text{nonlinear deterministic ODE}
\rightarrow
\text{add device noise}
\rightarrow
\text{nonlinear SDE}
}
\]
f = logspace(0, 10, 4000); % 1 Hz ... 10 GHz tau_min = 1e-9; % fastest trap (corner ~160 MHz) tau_max = 1e-2; % slowest trap (corner ~16 Hz) r = tau_max/tau_min; % 7 decades of time constants Nlist = [13300]; % number of superposed traps
figure('Color','w','Position',[10060720800]);
% ------------------------------ spectra ------------------------------ ax1 = subplot(2,1,1); hold(ax1,'on'); for m = 1:numel(Nlist) N = Nlist(m); if N == 1 tau = sqrt(tau_min*tau_max); % mid-band trap else tau = logspace(log10(tau_min), log10(tau_max), N); % log-spaced end S = zeros(size(f)); for k = 1:numel(tau) S = S + tau(k) ./ (1 + (2*pi*f*tau(k)).^2); % c_t = 1 end % Every Lorentzian carries the same total power (integral over f = 1/4 % regardless of tau), so dividing by N keeps the total variance fixed: S = S/N; plot(ax1, f, S, 'LineWidth', 2, 'DisplayName', sprintf('N = %d', N)); end
When sign(Ir) = -1, the argument becomes \[
q(t)=\operatorname{sign}(I_r)P_n=-P_n.
\] A simulator that correctly supports Kundert’s formulation does
not interpret this as a physically negative PSD, nor
does it calculate the ordinary complex square root \(\sqrt{-P_n}\). Instead, the sign selects
the sign of the deterministic noise-modulation amplitude: \[
\boxed{
m(t)=\operatorname{sign}\!\big(q(t)\big)\sqrt{|q(t)|}
}
\] Therefore, when \(q=-P_n\),
\[
m(t)=-\sqrt{P_n}.
\] This is equivalent to
Current BSIM models use compact-model equations standardized through
reference Verilog-A code, but commercial simulators often execute an
optimized built-in implementation rather than the Verilog-A source
directly
flicker noise in
circuit-noise analysis
its power spectral density is approximately \[
S_{i,1/f}(f)=\frac{K}{|f|}.
\]A large amount of its power lies at low
frequencies. Therefore, compared with a GHz oscillation period
\(T_0\), the flicker-noise value
changes very little during one cycle.
For a flicker-noise component at frequency \(f_m\), \[
f_m T_0\ll 1
\] implies \[
i_{1/f}(t+T_0)\approx i_{1/f}(t).
\] Thus, if the noise current is positive at \(t_0\), it will probably remain positive
throughout the following oscillator cycle: \[
i_{1/f}(t_0+\tau)\approx i_{1/f}(t_0),
\qquad 0\leq \tau<T_0.
\] In circuit-noise analysis, the underlying flicker-noise source
is commonly treated as approximately wide-sense
stationary: \[
R_x(t_1,t_2)=R_x(t_1-t_2).
\] This is reasonable when the device bias is constant and the
measurement interval is finite.
The phase perturbations may cancel or leave a nonzero residual: \[
\Delta\phi_{\text{cycle}}
\propto
\int_{0}^{T_0}
\Gamma(\omega_0 t)\,
i_{1/f,\mathrm{cyclo}}(t)\,dt.
\] Since the low-frequency noise is almost constant over \(T_0\), \[
\Delta\phi_{\text{cycle}}
\approx
x_{1/f}(t_0)
\int_{0}^{T_0}
\Gamma(\omega_0 t)a(t)\,dt
\] Therefore, flicker-noise upconversion depends on whether the
phase-delay and phase-advance contributions cancel over one period. A
nonzero weighted average produces low-frequency fluctuations in
oscillator frequency, which commonly appear as the \(1/f^3\) phase-noise region.
Then \[
\Delta\phi_{\text{cycle}}
\approx
\frac{x_{1/f}(t_0)}{q_{\max}}
\Gamma_{\mathrm{eff,DC}}T_0.
\] If \(x_{1/f}\) is already
normalized by \(q_{\max}\), the \(1/q_{\max}\) factor can be omitted.
Therefore, \[
\boxed{\Gamma_{\mathrm{eff,DC}}=0
\quad\Longrightarrow\quad
\Delta\phi_{\text{cycle}}\approx 0}
\] for quasistatic flicker noise. Physically, the phase-delay
contribution on one edge exactly cancels the phase-advance contribution
on the other edge.nce, \[
\boxed{
\Gamma_{\mathrm{eff,DC}}=0
\Rightarrow
\text{no first-order direct }1/f\text{-to-}1/f^3
\text{ phase-noise upconversion from that source.}
}
\]
Integrate across the impulse to find the jump \[
\underbrace{\text{zero state} + \delta(t)\text{ input}}_{t=0^-}
\quad\Longrightarrow\quad \underbrace{\text{zero input} + \text{new ICs
at }t=0^+}_{t>0}
\]
defwien_bridge_rhs(t, state): """Return the state derivative for the normalized Wien bridge response.""" #del t vo, dvo = state ddvo = -(3.0 / RC) * dvo - vo / RC**2 return [dvo, ddvo]
function lorenz!(du,u,p,t) σ,ρ,β = p du[1] = σ*(u[2]-u[1]) du[2] = u[1]*(ρ-u[3]) - u[2] du[3] = u[1]*u[2] - β*u[3] end
u0 = [1.0,0.0,0.0] p = (10,28,8/3) # we could also make this an array, or any other type! tspan = (0.0,100.0)
prob = ODEProblem(lorenz!,u0,tspan,p) sol = solve(prob)
Plots.plot(sol, vars=(1,2,3), size=(1400, 700))
Event Handling & Callback
Functions
In DifferentialEquations.jl, a callback
allows the ODE solver to detect an event and execute some action when
that event occurs. This is useful for hybrid systems, switching
circuits, threshold detection, impacts, resets, stopping conditions,
etc. \[
\boxed{\text{condition} \longrightarrow \text{event} \longrightarrow
\text{affect!}}
\]
function condition(u, t, integrator) u[1] - 0.2 end
function affect!(integrator) terminate!(integrator) end
cb = ContinuousCallback(condition, affect!)
sol = solve(prob, Tsit5(), callback=cb) println(sol.u[end][1]) # This will print the last value of u when the callback is triggered println(sol.t[end]) # This will print the time at which the callback is triggered println(exp(-sol.t[end])) # This will print the expected value of u at that time
Plots.plot(sol, xlims=(0, 2), linewidth=5, title="Solution of ODE with Callback", xlabel="Time", ylabel="u(t)")
DiscreteCallback checks its Boolean condition at
the end of accepted integration steps. It does not use root
finding to locate the exact point where \(u=1\)
DiscreteCallback checks only after each accepted solver
step. Because du/dt = 1 is exactly linear,
Tsit5() takes a large step from approximately
t=0.58 directly to t=5. It therefore does not
check near u=1.
A callback can modify parameters
Callbacks provide the mechanism that connects the continuous ODE
dynamics to this discrete switching behavior
So mathematically two components: \[
\dot{\mathbf{x}} = f(\mathbf{x}, p, t)
\] for the \(\textbf{continuous-time
dynamics}\), and \[
g(\mathbf{x}, t) = 0 \implies (\mathbf{x}, p) \to R(\mathbf{x}, p)
\] for the \(\textbf{event/reset
dynamics}\). \(R(x,p)\) means a
reset map or event update rule
\[
\dot{x} = \begin{cases}
-x, & x > 0.5 \\
-2x, & x < 0.5.
\end{cases}
\]
A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in
oscillators: a unifying theory and numerical methods for
characterization," in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.jp/10.1109/81.847872]
—, "A Reliable and Efficient Procedure for Oscillator PPV
Computation, With Phase Noise Macromodeling Applications," IEEE TCAD,
2003.
— and A. Sangiovanni-Vincentelli, Analysis and Simulation of
Noise in Nonlinear Electronic Circuits and Systems, vol. 425.
Boston, MA, USA: Kluwer Academic Publishers, 1998
A. Mehrotra and A. Sangiovanni-Vincentelli, Noise Analysis of
Radio Frequency Circuits, 1st ed. New York, NY, USA: Springer,
2004
Darabi H. Radio Frequency Integrated Circuits and Systems. 2nd ed.
Cambridge University Press; 2020.
Notice that the requirements of the first stage
are very demanding
replicas suppression
The spectrum of the high resolution digital signal \(u_1\) contains the original
baseband portion and its replicas located at integer
multiples of \(f_{s1}\), plus
a small amount of quantization noise shown as
a solid line
Bourdopoulos, G. I. (2003). Delta-Sigma modulators : modeling,
design and applications. Imperial College Press. [pdf]
DC Gain in IF
DC gain is used to compensate the ratio of sampling rate before and
after upsample
Given \[
X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i}
\] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)
Employ definition of DTFT, \(X(e^{j\hat{\omega}})
=\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set
\(\hat{\omega} = 0\)\[
X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n]
\] That is, \(\sum_{n=-\infty}^{+\infty}x[n] =
\sum_{n=-\infty}^{+\infty}x_e[n]\), so \[
\overline{x_e[n]} = \frac{1}{L} \overline{x[n]}
\] It also indicate that dc gain of upsampling is \(1/L\)
Zero-Order Hold (ZOH)
dc gain = \(N\)
First-Order Hold (FOH)
dc gain = \(N\)
Accumulate-and-dump (AAD)
decimator
accumulating the input for \(N\)
cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input
samples at rate \(1/T\) and delivers
their sum in a single sample at the output. Therefore, the
process comprises a filter (in the accumulation) and a
down-sampler (in the dump)
Let's focus on decimation: if we decimate by a factor 4, we simply
retain one output sample out of every 4 input samples.
In the example below, the downsampler at the right drops those 3
samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input
rate \(x(n)\):
with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[
Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}}
\]
But if we're going to be throwing away 75% of the calculated values,
can't we just move the downsampler from the end of the pipeline to
somewhere in the middle? Right between the integrator stage and the comb
stage? That answer is yes, but to keep the math working, we
also need to divide the number of delay elements in the comb stage by
the decimation rate:
with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[
Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}}
\]
And we can do this just the same with cascaded sections (without
downsampler or updampler) where integrators and combs have been
grouped
for decimation, the integrators come first
and the combs second with the downsampler in between
For interpolation, the reverse is true
the incoming sample rate is fraction of the outgoing sample rate,
the combs must come first and the interpolators second
reference
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016.
Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital
Delta-Sigma Modulators (Analog Circuits and Signal Processing). New
York, NY, USA: Springer, 2011.
a high normal mode
rejection ratio
(NMRR) for input noise at line
frequency
Conversion accuracy is independent of both the capacitance and
the clock frequency, because they affect both the up-slope and the
down-slope by the same ratio
The fixed input signal integration period results in rejection of
noise frequencies on the analog input that have periods that are equal
to or a sub-multiple of the integration time \(T\)
Interference signals with frequencies at integral multiples of the
integration period are, theoretically, completely removed,
since the average value of a sine wave of frequency
(\(1/T\)) averaged
over a period (\(T\)) is
zero
Z. Tan, C. -H. Chen, Y. Chae and G. C. Temes, "Incremental
Delta-Sigma ADCs: A Tutorial Review," in IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp.
4161-4173, Dec. 2020 [https://sci-hub.jp/10.1109/TCSI.2020.3033458]
Why (8.14) means
"sampled at \(T_s\)"\[
X_s(f) = \frac{1}{T_s}\sum_{k=-\infty}^{\infty} X(f - kf_s)
\]
This spectrum is periodic with period \(f_s\): copies of \(X(f)\) sit at every multiple of \(f_s\), with weight \(1/T_s\). That is exactly the spectrum of
uniform sampling at \(T_s\)
Interleaver Architectures
Direct
Interleaver
similar to increase the resolution of the flash ADC with
more parallel comparators
De-multiplexing
Interleaver
it is the front-end samplers that determine
timing/bandwidth mismatch errors
only one front-end channel \(L=1\)
eliminate any timing/bandwidth mismatch errors to the first order
Re-sampling
Interleaver
back-end re-sampling occur after the front-end, two \(\frac{KT}{C}\) contribution in total noise
(De-multiplexing Interleaver only one \(\frac{KT}{C}\))
without buffer, charging distribution reduce signal and reduce SNR,
but buffers give excess noise
Thus, differentiation produces two effects: magnitude scaling
by \(\omega\) and a
\(90^\circ\) phase
advance.
Frequency-dependent: the higher frequency
input signal \(f_\text{in}\), the
larger error becomes
Bandwidth Mismatch
Errors
Clock Generation for
Interleaved ADCs
Note that the falling edge of \(\phi_1\) is determined by the
rising edge of CK and is thus free from jitter and
mismatch in \(X_1\), which
accumulates jitter and phase mismatch
reset mechanism to the latches for nominal order
a clock generator
for an eight-channel ADC
NORed
\(\div 2\)
\(\div 2 \div 2\)
\(\phi_1\)
\(\text{CK}\)
\(I_1\)
\(I_2\)
\(\phi_2\)
\(\overline{\text{CK}}\)
\(Q_1\)
\(I_3\)
\(\phi_3\)
\(\text{CK}\)
\(\overline{I_1}\)
\(Q_2\)
\(\phi_4\)
\(\overline{\text{CK}}\)
\(\overline{Q_1}\)
\(Q_3\)
\(\phi_5\)
\(\text{CK}\)
\(I_1\)
\(\overline{I_2}\)
\(\phi_6\)
\(\overline{\text{CK}}\)
\(Q_1\)
\(\overline{I_3}\)
\(\phi_7\)
\(\text{CK}\)
\(\overline{I_1}\)
\(\overline{Q_2}\)
\(\phi_8\)
\(\overline{\text{CK}}\)
\(\overline{Q_1}\)
\(\overline{Q_3}\)
\(\text{CK}\), \(I/Q_1\) and \(I/Q_{2,3}\) shift by
1UI
resync (alignment)
TODO 📅
Calibration Techniques
Autocorrelation-based
Skew Calibration
S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan
Carusone, “All-Digital Calibration of Timing Mismatch Error in
Time-Interleaved Analog-to-Digital Converters,” IEEE Transactions on
VLSI Systems, Sept. 2017. [PDF, slides]
B. Razavi, "Problem of timing mismatch in interleaved ADCs,"
Proceedings of the IEEE 2012 Custom Integrated Circuits
Conference, San Jose, CA, USA, 2012 [pdf]
Binary-Search Calibration Method & its
limitations
M. Gu, Y. Tao, X. He, Y. Zhong, L. Jie and N. Sun, "A 1-GS/s 11-b
Time-Interleaved SAR ADC With Robust, Fast, and Accurate
Autocorrelation-Based Background Timing-Skew Calibration," in IEEE
Journal of Solid-State Circuits, vol. 60, no. 2, pp. 421-431, Feb.
2025
An autocorrelation-based background timing-skew calibration method,
which uses the correlations between adjacent channels to extract
timing-skew errors, which relaxes the input bandwidth limitation up to
the Nyquist frequency
Analyses Of The Derivative of The
Autocorrelation
MAD (Mean Absolute
Difference) vs. correlation
H. Wei, P. Zhang, B. Datta Sahoo and B. Razavi, "An 8-Bit 4-GS/s
120-mW CMOS ADC," Proceedings of the IEEE 2013 Custom Integrated
Circuits Conference, San Jose, CA, USA, 2013 [pdf]
—, "An 8 Bit 4 GS/s 120 mW CMOS ADC," in IEEE Journal of
Solid-State Circuits, vol. 49, no. 8, pp. 1751-1761, Aug. 2014 [pdf]
M. Gu, Y. Tao, X. He, Y. Zhong, L. Jie and N. Sun, "A 1-GS/s 11-b
Time-Interleaved SAR ADC With Robust, Fast, and Accurate
Autocorrelation-Based Background Timing-Skew Calibration," in IEEE
Journal of Solid-State Circuits, vol. 60, no. 2, pp. 421-431, Feb.
2025
TODO 📅
approximate the absolute value operation by
a squaring function
Overlapping
versus Non-overlapping track time
tracking accuracy stay same, Cin (2Cs) counteract the longer
tracking
Summing Interleaved Alias
The sampling function - impulse train is \[
s(t) = \sum_{n=-\infty}^{\infty}\left[ \delta(t-n4T_s) +
\delta(t-n4T_s-T_s) + \delta(t-n4T_s-2T_s) + \delta(t-n4T_s-3T_s)\right]
\]
Y. Shifman, Y. Krupnik, U. Virobnik, A. Khairi, Y. Sanhedrai and A.
Cohen, "A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz
BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm,"
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC),
Macau, Macao, 2019 [pdf]
E. -H. Chen et al., "7.1 A 212.5Gb/s DSP-Based PAM-4
Transceiver with 50dB Loss Compensation for Large AI System
Interconnects in 4nm FinFET," 2025 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2025
TODO 📅
DNL/INL Benefit
Each sub-ADC has its own physical capacitor array,
so each slice has its own independent, zero-mean mismatch error
Because the sub-ADC are sampled round-robin, a busy input
signal visits all \(N\) sub-ADC
with equal probability over the whole input range. The transfer curve
that the composite output presents is therefore the
ensemble average\[
e_{\mathrm{eff}}(k)
=
\frac{1}{N}\sum_{i=1}^{N} e_i(k)
\quad\Rightarrow\quad
\sigma\!\left\{e_{\mathrm{eff}}(k)\right\}
=
\frac{\sigma\{e_i(k)\}}{\textcolor{red}{\sqrt{N}}}
\] the measured static DNL/INL genuinely improves by \(\sqrt{N}\) at code-density
(histogram) test
The composite result \[
\boxed{\sigma_{DNL,\max}^{TI}
=
\frac{\sigma_{\text{sub},DNL}}{\sqrt{N}},
\qquad
\sigma_{INL,\max}^{TI}
=
\frac{\sigma_{\text{sub},INL}}{\sqrt{N}}}
\] where \(N\) is channel
number
In a VCM-based (top-plate-sampled, tri-level) SAR, the MSB decision
needs no capacitor switching at all — it's a direct
comparison against \(V_{CM}\)\[
\sigma^{VCM}_{DNL,\max}
=
\sqrt{2^{n-1}-1}\,\frac{\sigma_u}{C_u},
\qquad
\sigma^{VCM}_{INL,\max}
=
\frac{\sqrt{2^{n-1}}}{2}\,\frac{\sigma_u}{C_u}
\qquad
\text{at } k=2^{n-2},\,3\cdot 2^{n-2}
\]
Paper from industry
Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022 [https://sci-hub.st/10.1109/ISSCC42614.2022.9731650]
P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with
>45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and
Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025
reference
Poulton, Ken. ISSCC2009 "Time-Interleaved ADCs, Past and Future" (slides)
—. CICC2010 "GHz ADCs: From Exotic to Mainstream", tutorial session,
(slides)
—. ISSCC2015 "Interleaved ADCs Through the Ages", (slides)
ISSCC2015 F1: High-Speed Interleaved ADCs
Ron Kapusta, Analog Devices, CICC2015 ED007: SAR ADCs in parallel
[time-interleaved] converter arrays
Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and
Analysis
Ewout Martens. ESSCIRC 2019 Tutorials: Advanced Techniques for ADCs
for 5G Massive MIMO [https://youtu.be/7hYichGGU6k]
John P. Keane, ISSCC2020 T5: "Fundamentals of Time-Interleaved
ADCs"
Athanasios Ramkaj. January 26, 2022, IEEE SSCS Santa Clara Valley
Section Technical Talk: Design Considerations Towards Optimal
High-Resolution Wide-Bandwidth Time-Interleaved ADCs [video] [slides]
V. Chen, "Tutorial: High-Speed Analog-to-Digital Converters,"
2025 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2025, pp. 1-1, doi:
10.1109/ISSCC49661.2025.11076112.
Ahmed M. A. Ali 2016, "High Speed Data Converters"
Razavi, B. (2025). Analysis and design of data converters.
Cambridge University Press.
speculative DFE is also known as
loop unrolled DFE, which solve the critical
timing on first tap
DFE architecture
Extensive work on DFEs has produced a multitude of architectures,
which can be broadly categorized as "direct"" or
"unrolled" (speculative) DFEs with
"full-rate" or "half-rate"
clocking
S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for
20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol.
46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]
K. -L. J. Wong, E. -H. Chen and C. -K. K. Yang, "Edge and Data
Adaptive Equalization of Serial-Link Transceivers," in IEEE Journal of
Solid-State Circuits, vol. 43, no. 9, pp. 2157-2169, Sept. 2008
[[https://sci-hub.ru/10.1109/JSSC.2008.2001876]*https://sci-hub.ru/10.1109/JSSC.2008.2001876]
—, “Signal preconditioning using feedforward equalizers in ADC-based
data links”, Ph.D. Dissertation, Stanford University, 2016 [https://purl.stanford.edu/dk653rc7126]
K. Zheng, “System-Driven Circuit Design for ADC-Based Wireline Data
Links”, Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]
reference
T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M.
Mansuri, "Modern Wireline Transceivers," in IEEE Journal of
Solid-State Circuits, vol. 61, no. 2, pp. 395-422, Feb. 2026 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=11311714]
S. Jang, J. Lee, Y. Choi, D. Kim and G. Kim, "Recent Advances in
Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers," in
IEEE Open Journal of the Solid-State Circuits Society, vol. 4,
pp. 290-304, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763]
Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of
Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]
Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity
Technologies to Accelerate AI
Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed
Wireline Interconnects: Design Challenges and Innovations in 224G SerDes
[https://www.youtube.com/live/wHNOlxHFTzY]
Nhat Nguyen and Masum Hossain, ISSCC 2021 Forum F6.7:
112Gb/s-and-Beyond Long-Reach and Short-Reach Electrical
Interfaces
Jihwan Kim, Intel, ISSCC 2023 Forum F1.5: Circuit Designs for
200+Gb/s Electrical Transceivers
Ariel Cohen, Intel, ISSCC 2024 Forum F6.3: Beyond 200Gbps
Electrical transceivers – Circuit Architecture, Design Implementation
and Silicon Results
Heng Zhang, Broadcom, ISSCC 2025 Forum F4.2: High-speed ADCs for
100Gbps+ Wireline Transceivers
E-Hung Chen, MTK, ISSCC 2026 Forum F2.3: State-of-the-Art 200+
Gb/s Electrical and Optical Interconnects
Z. Toprak-Deniz et al., "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With
Reconfigurable 3-Tap FFE in 14-nm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 55, no. 1, pp. 19-26, Jan. 2020 [https://sci-hub.st/10.1109/JSSC.2019.2939081]
The source-series terminated (SST) drivers are more power-efficient
than their current mode logic (CML) counterparts due to their lower
termination power
To achieve the same differential output amplitude, CML topologies
consume \(4\) times the current of SST
topologies
Current mode drivers become power competitive at very high data
rates
Dynamic power consumption
scales with frequency\(\Longrightarrow\) SST drivers lose power
advantage
Serialization Approaches
Z. Toprak-Deniz et al., "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With
Reconfigurable 3-Tap FFE in 14-nm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 55, no. 1, pp. 19-26, Jan. 2020 [https://sci-hub.st/10.1109/JSSC.2019.2939081]
triple-stacked 4:1 n-type MUX
2-1 mux
timing
The circuit alone does not fix the bit order. It depends on which
clock edge arrives first:
First edge rising: the a-flop captures first, and
the output is a₀, b₀, a₁, b₁, …
First edge falling: the b-flop captures first, and
the output is b₀, a₀, b₁, a₁, …
The inverter chain sets the hold margin at the mux
The first two inverters delay the flop clocks behind the select,
so each flop updates only after the mux has switched away from
it
The third inverter mainly provides the inverted clock for the
b-flop, and it adds a little extra hold margin to that path
Because t_su + t_hd ≈ T/2, every bit of delay added for hold comes
out of setup. The chain should therefore be just long enough to
guarantee positive hold margin across PVT.
divider
latch timing
The clk_d inverters set where the latch's transparent window sits
inside di's stable window:
d_div is the delay from the clk edge to di changing: t_inv + t_cq,FF
+ t_mux,sel.
d_c is the delay of the clk_d path: 2·t_inv, plus the latch's
internal delay.
From those:
t_hd ≈ d_div − d_c t_su
≈ T/2 +d_c − d_div
The sum is fixed at T/2, so adding clk_d delay buys setup by
spending hold, and removing it does the reverse. The window is
centred (t_su = t_hd = T/4) when d_c ≈ d_div − T/4
Two
latches
1-UI Data Stagger
C. Menolfi et al., "6.2 A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4
SST TX in 14nm CMOS," 2018 IEEE International Solid-State Circuits
Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 104-106 [https://sci-hub.ru/10.1109/ISSCC.2018.8310205]
Z. Toprak-Deniz et al., "6.6 A 128Gb/s 1.3pJ/b PAM-4
Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS," 2019 IEEE
International Solid-State Circuits Conference - (ISSCC), San
Francisco, CA, USA, 2019, pp. 122-124 [https://sci-hub.ru/10.1109/ISSCC.2019.8662479]
—, "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap
FFE in 14-nm CMOS," in IEEE Journal of Solid-State Circuits,
vol. 55, no. 1, pp. 19-26, Jan. 2020 [https://sci-hub.ru/10.1109/JSSC.2019.2939081]
T. O. Dickson et al., "C3.2 A 72GS/s, 8-bit DAC-based
Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links,"
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology
and Circuits), Honolulu, HI, USA, 2022, pp. 28-29 [https://sci-hub.ru/10.1109/VLSITechnologyandCir46769.2022.9830421]
—, "A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET
CMOS for 200+ Gb/s Serial Links," in IEEE Journal of Solid-State
Circuits, vol. 58, no. 4, pp. 1074-1086, April 2023, doi:
10.1109/JSSC.2022.3228632
a.k.a Phase
Aligner, Tap Delay
Generator
D4'<0> is launched by the C4
0° rising edge, <1> by 90°,
<2> by 180° and <3> by
270°
Why the chains have 2, 3, 3 and 4 latches:
each latch passes data on to the next latch to open. That hop can
only be 1 UI (a 90° step) or 2 UI (a 180°
step)
the first 0° latch opens at 2 UI,
and the outputs must launch at 4, 5, 6 and 7 UI.
one hop for <0> (+2)
two for <1> (+1 +2)
two for <2> (+2 +2)
three for <3> (+1 +2 +2)
These match the slide's chains, which are the shortest possible for
those targets
The two hop types also have different margins, which ties back to the
earlier figures:
90° hop: the input changes in the middle of the
next latch's hold phase, so setup and hold are both about 1 UI.
180° hop: this is the master–slave case. The input
changes right after the next latch closes, so hold margin is only
clock-to-Q, while setup gets 2 UI
a tap delay generator retime the incoming data and
provide 1-UI-staggered quarter-rate data (D0-D3)
Fig 9. works for D0–D2, but the D3 path races. So Fig. 9 is probably
simplified
Fix: add one C4_Q latch to the D3 path, giving C4_I
→ C4_Q → C4_QB.
Z. Toprak-Deniz et al., "6.6 A 128Gb/s 1.3pJ/b PAM-4
Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS," 2019 IEEE
International Solid-State Circuits Conference - (ISSCC), San
Francisco, CA, USA, 2019, pp. 122-124 [https://sci-hub.ru/10.1109/ISSCC.2019.8662479]
—, "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap
FFE in 14-nm CMOS," in IEEE Journal of Solid-State Circuits,
vol. 55, no. 1, pp. 19-26, Jan. 2020 [https://sci-hub.ru/10.1109/JSSC.2019.2939081]
Quarter-Rate: A clocking or sampling architecture
where the internal circuit clock runs at one-fourth (1/4) of the total
serial data rate
Quadrature: A relationship between two signals or
clocks that have a 90o phase difference (a
quarter of a complete wave cycle), commonly used for I/Q modulation,
directional tracking in encoders, or generating multi-phase clocks
quadraturequarter-rate (C4)
Fig. 5(c): The 2-UI pulse D1′ is carved by C4IB
alone — it starts on C4IB rising and ends on
C4IB falling. For the D1 → D1′ stage, the margins are
1.5 UI before and 0.5 UI after, which is asymmetric
Fig. 5(d): D1′ is the 1-UI pulse, C4IB isn't the
only reference — It starts on C4IB rising, but it ends
on C4Q falling, as the arrows in the figure show. The
pulse generator is enabled only while C4IB and C4Q are both
high
Case
Window D1 must be stable over
Before
After
(c) D1 → D1′
C4IB high (2 UI)
1.5 UI
0.5 UI
(c) D1 → D_OP
C4IB high and C4Q high (1 UI)
1.5 UI
1.5 UI
(d) D1 → D1′
C4IB high and C4Q high (1 UI)
1 UI
2 UI
The 0.5 UI in Fig. 5(c) is an idealized drawing, not a real delay
value. In silicon, the D1 edge occurs at the launching C4 edge plus the
latch clock-to-Q delay plus wiring delay. The authors
drew it at 0.5 UI to show the ideal centered placement with symmetric
margin
The two sub-figures place D1 differently, which shows the
data-to-clock offset is set by design and illustration choices. The real
requirement is only that D1 is stable, with margin,
whenever its carving gate is enabled
If the natural delay lands too close to an active edge, the designer
can fix it by choosing a different launching clock phase or adding
delay
Half-rate TX architecture
M. Meghelli et al., "A 10Gb/s 5-Tap-DFE/4-Tap-FFE
Transceiver in 90nm CMOS," 2006 IEEE International Solid State
Circuits Conference - Digest of Technical Papers, San Francisco,
CA, USA, 2006, pp. 213-222 [https://sci-hub.ru/10.1109/ISSCC.2006.1696051]
J. F. Bulzacchelli et al., "A 10-Gb/s 5-Tap DFE/4-Tap FFE
Transceiver in 90-nm CMOS Technology," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006 [https://sci-hub.ru/10.1109/JSSC.2006.884342]
The half period that second-half selection "wastes" is deliberate
slack: it lets each input settle fully before it is passed. You're
trading a little latency for robustness, and designers
almost always take that trade. If latency truly mattered, the better
move would be to trim pipeline stages or the FIFO depth elsewhere, not
to remove the settling slack from the highest-speed MUX.
J. Cao et al., "OC-192 transmitter and receiver in standard
0.18-/spl mu/m CMOS," in IEEE Journal of Solid-State Circuits,
vol. 37, no. 12, pp. 1768-1780, Dec. 2002, doi:
With the FFs, latches, and clocks unchanged,
reversing the MUX selection still works, but adds
latency
The bit order is preserved; each bit is selected later.
Reversing both first-stage MUXes adds 2
UI
Reversing the final MUX adds 1
UI.
Reversing all three preserves (D_0,D_1,D_2,D_3,),
with 3 UI additional latency
The retimer between the final stage of the MUX and
the output driver is used to reduce the data jitter due
to the bandwidth limitation of the selection circuit in the 2 : 1 MUX
cell and duty cycle distortion of the half-rate clock driving that
stage
Synchronized divider
M. A. Kossel et al., "8.3 An 8b DAC-Based SST TX Using Metal
Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in
7nm CMOS," 2021 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2021, pp. 130-132 [https://sci-hub.ru/10.1109/ISSCC42613.2021.9365784]
Michael Perrott August 12, 2008, Short Course On Phase-Locked Loops
and Their Applications Day 2, PM Lecture Basic Building Blocks (Part II)
High Speed Frequency Dividers, Phase Detectors, Charge Pumps, and Loop
Filter Design [https://cppsim.org/PLL_Lectures/day2_pm.pdf]
The lower speed sub-rate clocks are then obtained using a
synchronous divider based on conventional master-slave
flip-flops
The preceding synchronous divider is equivalent to the synchronous
implementation described below
Each stage's toggle decision is computed from the states of
all previous stages, but its timing comes only from the common
input clock
SST Driver
sharing termination
in SST transmitter
Sharing termination keep a constant current through leg, which
improve TX speed in this way. On the other hand, the sharing termination
facilitate drain/source sharing technique in layout.
pull-up and
pull-down resistor
Original stacked structure
Pro's:
smaller static current when both pull up and pull down path is
on
Con's:
slowly switching due to parasitic capacitance behind pull-up and
pull-down resistor
with single shared linearization resistor
Pro's:
The parasitic capacitance behind the resistor still exists but is
now always driven high or low actively
Con's:
more static current
VM
Driver Equalization - differential ended termination
\[
V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1}
\]
where \(D_n \in \{-1, 1\}\)
\[
V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2}
\] With \(R_u=(L+M+N)R_T\)
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\
V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N}
\end{align}\] So \[
V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N}
\] which is same with differential ended termination
Equation-2
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \\
V_{\text{rxm}} &= 0
\end{align}\] So \[
V_{M}= \frac{1}{2}
\] which is same with differential ended termination
G. Steffan et al., "6.4 A 64Gb/s PAM-4 transmitter with
4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI," 2017
IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2017, pp. 116-117 [https://sci-hub.ru/10.1109/ISSCC.2017.7870288]
Active Peaking CMOS
Pre-Driver
C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX
in 14nm CMOS," 2018 IEEE International Solid-State Circuits
Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 104-106 [https://sci-hub.ru/10.1109/ISSCC.2018.8310205]
HungWen Lu, ChauChin Su and Chien-Nan Liu, "A scalable digitalized
buffer for gigabit I/O," 2008 IEEE Custom Integrated Circuits
Conference, San Jose, CA, USA, 2008, pp. 241-244 [https://sci-hub.ru/10.1109/CICC.2008.4672068]
Single-Ended-to-Differential
(S2D)
T. Dickson et al., "C3.2 A 72GS/s, 8-bit DAC-based Wireline
Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links," 2022 IEEE
Symposium on VLSI Technology and Circuits (VLSI Technology and
Circuits), Honolulu, HI, USA, 2022, pp. 28-29 [https://sci-hub.ru/10.1109/VLSITechnologyandCir46769.2022.9830421]
Due to circuit limitation, circuit cannot have arbitrarily large
voltage on the output, i.e. a limited maximum swing. In order
to create the high frequency shape, the best we can do is lower DC
gain (low frequency gain < 1)
FIR is not increasing the amplitude on the edges
FIR is reducing the inner eye diagram
The maximum swing stays the same, \(\sum_i
|c_i|=1\)
Basic FeedForward
Equalization Theory
Pre-cursor FFE can compensate phase distortion through the
channel
Which can be simpified as \[\begin{align}
V_{\text{rx}} &= \frac{1}{2}(V_p - V_m) \\
&= \frac{1}{2}(\frac{2}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-1) \\
&=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2}
\end{align}\]
The above eqations demonstrate that the output \(V_{\text{rx}}\) is the linear sum of
MSB and LSB; LSB and
MSB have relative weight, i.e. 1 for LSB and
2 for MSB.
Assume pre cusor has \(L\) legs,
main cursor \(M\) legs and post cursor
\(N\) legs, which is same with the
convention in "Voltage-Mode Driver Equalization"
The number of legs connected with supply can expressed as \[
n_{up} = (1-d_{n+1})L + d_{n}M + (1-d_{n-1})N
\] Where \(d_n \in \{0, 1\}\),
or \[
n_{up} = \frac{1}{2}(-D_{n+1}+1)L + \frac{1}{2}(D_{n}+1)M +
\frac{1}{2}(-D_{n-1}+1)N
\] Where \(D_n \in \{-1,
+1\}\)
Then the number of legs connected with ground is \[
n_{dn}=L+M+N-n_{up}
\] where \(n_{up}+n_{dn}=L+M+N\)
Voltage resistor divider \[\begin{align}
V_o &=
\frac{\frac{R_{U}}{n_{dn}}}{\frac{R_U}{n_{dn}}+\frac{R_U}{n_{up}}} \\
&= \frac{1}{2}- \frac{1}{2}D_{n+1}\frac{L}{L+M+N}+
\frac{1}{2}D_{n}\frac{M}{L+M+N}-\frac{1}{2}D_{n-1}\frac{N}{L+M+N} \\
&= \frac{1}{2}-\frac{1}{2}D_{n+1}\cdot l+ \frac{1}{2}D_{n}\cdot
m-\frac{1}{2}D_{n-1}\cdot n
\end{align}\]
where \(l+m+n=1\)
\(V_{\text{MSB}}\) and \(V_{\text{LSB}}\) can be obtained
\[\begin{align}
V_{\text{MSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \\
V_{\text{LSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n
\end{align}\]
Substitute the above equation into \(V_{\text{rx}}\), we obtain the relationship
between driver legs and FFE coefficients
After scaling, we obtain \[
V_{\text{rx}} = -l\cdot(2 \cdot
D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ m\cdot(2\cdot
D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) - n \cdot(2\cdot
D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1})
\] Where \(C_{-1} = l\), \(C_0 = m\) and \(C_{1}=n\), which is same with that of
NRZ
Hsinho Wu, Intel. DesignCon 2021: SNDR Analysis & Its Impacts on
Link Performance
Christiaan Bil (Intel), DesignCon 2026. An Experimental Study of PCIe
Transmitter Equalization Preset Measurement Methods for 64 and 128 GT/s
PAM4 Signaling
PCIe Gen6 Channel and Reference Package S4P Models for Rx Stressed
Eye Calibration
Above curve demonstrate that only zero is not enough to compensate
channel+pkg loss (>20 dB/decade), peaking or
Complex-Conjugate Poles is necessary
S. Shahramian et al., "30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline
Receiver Employing Enhanced Pattern Utilization CDR and Genetic
Adaptation Algorithms in 7nm CMOS," 2019 IEEE International
Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA,
2019 [pdf]
P. A. Francese et al., "10.6 continuous-time linear
equalization with programmable active-peaking transistor arrays in a
14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver," 2015
IEEE International Solid-State Circuits Conference - (ISSCC) Digest of
Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.se/10.1109/ISSCC.2015.7062988]
Z. Li, M. Tang, T. Fan and Q. Pan, "A 56-Gb/s PAM4 Receiver Analog
Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 68, no. 9, pp. 3058-3062, Sept. 2021 [slides]
[paper]
In the active copper cable (ACC) application, it is necessary to give
different equalizations at the same frequency according to different
cable lengths, Therefore, the AFE with fixed peaking
frequency and constant bandwidth
is desirable for these applications
Low-Frequency CTLE (LF-CTLE)
S. Parikh et al., "A 32Gb/s wireline receiver with a
low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS," 2013 IEEE
International Solid-State Circuits Conference Digest of Technical
Papers, San Francisco, CA, USA, 2013 [https://sci-hub.se/10.1109/ISSCC.2013.6487622]
T. Shibasaki et al., "A 56-Gb/s receiver front-end with a
CTLE and 1-tap DFE in 20-nm CMOS," 2014 Symposium on VLSI Circuits
Digest of Technical Papers, Honolulu, HI, USA, 2014, pp. 1-2
trade-offs between noise amplification and signal
equalization
Gm-TIA
H. Kimura et al., "A 28 Gb/s 560 mW Multi-Standard SerDes
With Single-Stage Analog Front-End and 14-Tap Decision Feedback
Equalizer in 28 nm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 49, no. 12, pp. 3091-3103, Dec. 2014 [https://ieeexplore.ieee.org/ielx7/4/6963535/06894632.pdf]
Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB
IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International
Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]
Z. Li, M. Tang, T. Fan and Q. Pan, "A 56-Gb/s PAM4 Receiver Analog
Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 68, no. 9, pp. 3058-3062, Sept. 2021 [slides]
[paper]
K. Kwon et al., "A 212.5Gb/s Pam-4 Receiver With Mutual
Inductive Coupled Gm-Tia in 4nm Finfet," 2025 Symposium on VLSI
Technology and Circuits (VLSI Technology and Circuits), Kyoto,
Japan, 2025
Bae, W. (2019). CMOS Inverter as Analog Circuit: An Overview.
Journal of Low Power Electronics and Applications. [pdf]
CTLE, with Gm + TIA structure
Chongyun ZHANG, 2025, "Energy-Efficient CMOS Optical Receiver for
Short-Reach Data Center Application,". [slides,
paper]
Cherry-Hooper Amplifier
Resonator-Based CTLE
Passive series peaking
D. Pfaff et al., "7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss
Transceiver in 3nm FinFET CMOS," 2024 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp.
128-130, doi: 10.1109/ISSCC49657.2024.10454537.
At DC \[
i_f = g_{md1}v_f \quad i_f = (v_f - v_o)/R_f \qquad \Longrightarrow
\qquad \frac{v_o}{v_i} = -\frac{g_{m1}}{g_{md1}} + g_{m1}R_f
\] since \(R_f=0\)\[
A_{DC} = -\frac{g_{m1}}{g_{md1}}
\]
That is \[
A_{DC}=-g_{m1}R_s\qquad\qquad A_{HF}=jg_{m1}R_s\cdot Q \qquad\qquad
\frac{A_{HF}}{A_{DC}} = Q
\]
where \(A_{HF}\) is the gain at
resonance
Q-Shaping (LC-tuned
Amplifier)
Y. Krupnik et al., "112 Gb/s PAM4 ADC Based SERDES Receiver for
Long-Reach Channels in 10nm Process," 2019 Symposium on VLSI Circuits,
Kyoto, Japan, 2019, pp. C266-C267, [https://sci-hub.jp/10.23919/VLSIC.2019.8778136]
—, "112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE
for Long-Reach Channels," in IEEE Journal of Solid-State
Circuits, vol. 55, no. 4, pp. 1077-1085, April 2020, [https://sci-hub.jp/10.1109/JSSC.2019.2959511]
Y. Segal et al., "A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver
with 31dB Loss Compensation," 2022 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp.
114-116, [https://sci-hub.jp/10.1109/ISSCC42614.2022.9731794]
A. Khairi et al., "A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based
SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach
Channels," in IEEE Journal of Solid-State Circuits, vol. 58,
no. 1, pp. 8-18, Jan. 2023, doi: 10.1109/JSSC.2022.3211475
D. Pfaff et al., "A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss
Transceiver in 3-nm FinFET CMOS," in IEEE Journal of Solid-State
Circuits, vol. 60, no. 1, pp. 9-22, Jan. 2025, doi:
10.1109/JSSC.2024.3466092
At resonant frequency \[
\boxed{|A_v|=
\frac{g_m}
{1+\left(\dfrac{g_mR_D}{1+j\omega R_DC_D}\right)}
Q_{\mathrm{ind}}\omega L,
\qquad
\omega=\frac{1}{2\pi\sqrt{L_C L_L}}}
\] where \(Q_{\mathrm{ind}}=\frac{\omega L}{R_L}, \qquad
R_p=Q_{\mathrm{ind}}^{\,2}R_L=Q_{\mathrm{ind}}\omega L\)
Q-Shaping w/ Parallel RLC
H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with
an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm
FinFET," 2025 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2025, pp. 142-144, doi:
10.1109/ISSCC49661.2025.10904638.
With Zero-Forcing, inverse of \(h_0 \sim h_1\) only
The Summer response is also treated as an
impulse-response tap sequence
when the starting sequence is the channel’s pulse
response, convolving it with the equalizer’s impulse-response
taps gives the equalized pulse-response taps:
If CTLE_HF and Summer are both represented by their block impulse
responses, their convolution gives the combined impulse
response. Including the transmitted pulse gives the pulse
response.
shunt peaking
\(\color{red}m=\frac{R^2C}{L}\) is
the ratio of the \(R/L\) zero frequency
to the original RC pole frequency \(1/RC\), and therefore measures how
aggressively the zero compensates the intrinsic RC roll-off.
The negative inductor \(-M\) can be
seen as capacitor \[
-j\omega M = \frac{1}{j}\omega M = \frac{1}{j\omega \frac{1}{\omega^2
M}}
\] That is \(C_{-M} = \frac{1}{\omega^2
M} \approx 10 \times C_E\)
T-coil w/ inverted mutual
coupling
J. Kim, J. -K. Kim, B. -J. Lee and D. -K. Jeong, "Design Optimization
of On-Chip Inductive Peaking Structures for 0.13- μm CMOS 40-Gb/s
Transmitter Circuits," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 56, no. 12, pp. 2544-2555, Dec. 2009 [https://sci-hub.st/10.1109/TCSI.2009.2023772]
TODO 📅
Triple Resonance
TODO 📅
series resonance \(\omega_\text{res}\)
Assuming, \(I_\text{in}=\cos\omega_r
t\) and \(V_\text{out}=g\cos(\omega_r t
+\theta)\)
with \(I_\text{in} =
C_L\frac{\mathrm{d}V_\text{out}}{\mathrm{d}t}\), yield \(g=\sqrt{\frac{L}{C}}\) and \(\theta=- \frac{\pi}{2}\), i.e. \(V_\text{out} = \sqrt{\frac{L}{C}}\cos(\omega_r t -
\frac{\pi}{2})\)
where \[
K =
\frac{R_L||\frac{1}{g_{\text{m}_{\text{dio}}}}||\frac{1}{g_{\text{m}_{\text{tot}}}}}{R_L||g_\text{ds\_tot}}
\]
And \(A(s)\) can be expressed as
\[
A(s) =
\frac{\frac{s}{\omega_z}+1}{\frac{s^2}{\omega_n^2}+2\frac{\zeta}{\omega_n}s+1}
\] It magnitude in dB \[
A_\text{dB} =
10\log\frac{1+(\omega/\omega_z)^2}{1+(\omega/\omega_n)^4+2\omega^2(2\zeta^2-1)/\omega_n^2}
\] Substitute \(\omega_n\) with
Eq (2), followed is obtained \[
A_\text{dB} = 10\log{\frac{\alpha^2(\omega_z^4 +
\omega_z^2\omega^2)}{\alpha^2\omega_z^4+\omega^4+2\alpha\omega_z^2(2\zeta^2-1)\omega^2}}
\] peaking frequency \[
\omega_\text{peak} = \omega_z\cdot \sqrt{\sqrt{(\alpha+1)^2 - 4\alpha
\zeta^2}-1}
\] If \(\zeta=1\)\[
\omega_{A_\text{dB = 0dB} } = \sqrt{1-2/\alpha}\cdot \omega_{p0} \qquad
\omega_\text{peak} = \omega_z\sqrt{\alpha-2} \qquad
A_\text{dB,peak} = 10\log\frac{\alpha^2}{4(\alpha-1)}
\]
Negative Capacitance Circuit
Negative Miller Capacitance
S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery
Techniques for 10-Gb/s CMOS Serial-Link Receivers," in IEEE Journal
of Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011 [pdf]
\[
C_{d1} = C_{dd1} + (1+\frac{1}{|A_{gd}|})C_{gd1}
\] where \(A_{gd}\lt 0\)
For differential mode input, effective
input capacitance\[
C_{in} = C_{gs} +(1+A_{dm}) C_{gd}+\color{red}(1-A_{dm})C_n
\] and effective output capacitance\[
C_{out} = C_{dd} + (1+\frac{1}{A_{dm}})C_{gd}+\color{red}
(1-\frac{1}{A_{dm}})C_n
\] That is \(C_n\) deteriorate
the effective output capacitance
For common mode input, effective input
capacitance\[
C_{in} = C_{gs} + (1+A_{cm}) C_{gd}+ \color{red}(1+A_{cm})C_n
\] and effective output capacitance\[
C_{d1} = C_{dd} + (1+\frac{1}{A_{cm}})C_{gd}+\color{red}
(1+\frac{1}{A_{cm}})C_n
\] i.e., \(C_n\) deteriorate
both effective input capacitance and effective output capacitance,
unfortunately
effective input capacitance \(\Pi\)
model, which is appropriate for both differential input and common mode
input
Suppose \(C_n=C_{gd}\), effective
differential input capacitance is same with effective
common-mode input capacitance (\(C_n=\frac{A_{dm}-A_{cm}}{A_{dm}+A_{cm}}C_{gd}\))
If \(C_{gd}\) is considered, and
apply miller effect. half equivalent circuit is shown as below
dual-diode based ESD
protection
??? which diodes are used in right topology — both pdiode and ndiode
are used
reference
T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M.
Mansuri, "Modern Wireline Transceivers," in IEEE Journal of
Solid-State Circuits, vol. 61, no. 2, pp. 395-422, Feb. 2026 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=11311714]
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline
Receivers"
Byungsub Kim, ISSCC 2022, "T11: Basics of Equalization Techniques:
Channels, Equalization, and Circuits"
Gain Kim, 2023. Equalization, Architecture, and Circuit Design for
High-Speed Serial Link Receiver [www.theise.org/...]
Nhat Nguyen and Masum Hossain, ISSCC 2021 Forum F6.7:
112Gb/s-and-Beyond Long-Reach and Short-Reach Electrical
Interfaces
Jihwan Kim, Intel, ISSCC 2023 Forum F1.5: Circuit Designs for
200+Gb/s Electrical Transceivers
Ariel Cohen, Intel, ISSCC 2024 Forum F6.3: Beyond 200Gbps
Electrical transceivers – Circuit Architecture, Design Implementation
and Silicon Results
Heng Zhang, Broadcom, ISSCC 2025 Forum F4.2: High-speed ADCs for
100Gbps+ Wireline Transceivers
E-Hung Chen, MTK, ISSCC 2026 Forum F2.3: State-of-the-Art 200+
Gb/s Electrical and Optical Interconnects
J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm
CMOS," 2018 IEEE International Solid-State Circuits Conference -
(ISSCC), San Francisco, CA, USA, 2018 [paper]
S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension
Techniques for CMOS Amplifiers," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006 [pdf]
S. S. Mohan, M. D. M. Hershenson, S. P. Boyd and T. H. Lee,
"Bandwidth extension in CMOS with optimized on-chip inductors," in IEEE
Journal of Solid-State Circuits, vol. 35, no. 3, pp. 346-355, March 2000
[http://smirc.stanford.edu/papers/JSSC00MAR-mohan.pdf]
J. Paramesh and D. J. Allstot, "Analysis of the Bridged T-Coil
Circuit Using the Extra-Element Theorem," in IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 53, no. 12, pp. 1408-1412,
Dec. 2006 [https://sci-hub.st/10.1109/TCSII.2006.885971]
S. C. D. Roy, "Comments on "Analysis of the Bridged T-coil Circuit
Using the Extra-Element Theorem," in IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 54, no. 8, pp. 673-674, Aug. 2007 [https://sci-hub.st/10.1109/TCSII.2007.899834]
Deog-Kyoon Jeong. Topics in IC Design: T-Coil [pdf]
P. Heydari, "Neutralization Techniques for High-Frequency Amplifiers:
An Overview," in IEEE Solid-State Circuits Magazine, vol. 9, no. 4, pp.
82-89, Fall 2017 [https://sci-hub.ru/10.1109/MSSC.2017.2745858]
—, "Evolution of Broadband Amplifier Design: From Single-Stage to
Distributed Topology," in IEEE Microwave Magazine, vol. 24, no. 9, pp.
18-29, Sept. 2023
Cowan G. Mixed-Signal CMOS for Wireline Communication:
Transistor-Level and System-Level Design Considerations. Cambridge
University Press; 2024
Starič, Peter and Erik Margan. Wideband amplifiers. (2006)
[pdf]
Walling, Jeffrey & Shekhar, Sudip & Allstot, David. (2008).
Wideband CMOS Amplifier Design: Time-Domain Considerations. Circuits and
Systems I: Regular Papers, IEEE Transactions on. 55. 1781 - 1793. [pdf]
A. A. Abidi, "The T-Coil Circuit Demystified," in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 72, no. 9, pp.
4469-4480, Sept. 2025
S. Lin, D. Huang and S. Wong, "Pi Coil: A New Element for Bandwidth
Extension," in IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 56, no. 6, pp. 454-458, June 2009
M. Kossel et al., "A T-Coil-Enhanced 8.5 Gb/s High-Swing SST
Transmitter in 65 nm Bulk CMOS With <−16 dB Return Loss Over 10 GHz
Bandwidth," in IEEE Journal of Solid-State Circuits, vol. 43,
no. 12, pp. 2905-2920, Dec. 2008 [https://web.mit.edu/magic/Public/papers/04684644.pdf]
S. Galal and B. Razavi, "Broadband ESD protection circuits in CMOS
technology," in IEEE Journal of Solid-State Circuits, vol. 38, no. 12,
pp. 2334-2340, Dec. 2003, [https://sci-hub.jp/10.1109/JSSC.2003.818568]
M. Ker and Y. Hsiao, "On-Chip ESD Protection Strategies for RF
Circuits in CMOS Technology," 2006 8th International Conference on
Solid-State and Integrated Circuit Technology Proceedings, 2006, pp.
1680-1683 [https://sci-hub.jp/10.1109/ICSICT.2006.306371]
M. Ker, C. Lin and Y. Hsiao, "Overview on ESD Protection Designs of
Low-Parasitic Capacitance for RF ICs in CMOS Technologies," in IEEE
Transactions on Device and Materials Reliability, vol. 11, no. 2, pp.
207-218, June 2011 [https://sci-hub.jp/10.1109/TDMR.2011.2106129]
Minsoo Choi et al., "An Approximate Closed-Form Channel Model for
Diverse Interconnect Applications," IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct. 2014.
[https://sci-hub.jp/10.1109/TCSI.2014.2327275]
A resonant circuit refers to an electrical
circuit using circuit elements such as an inductor (L) and a capacitor
(C) to cause resonance at a specific frequency.
There are two types of resonant circuits:
series resonant circuits
parallel resonant circuits
In a series resonant circuit, the impedance of the
circuit reaches its minimum value at resonance, whereas
in a parallel resonant circuit, the impedance reaches
its maximum value
antiresonance
Resonant Frequency
\(\zeta \lt 1\):
Complex-Conjugate Poles, but not resonant
peak
Prof. M. Green / U.C. Irvine EECS 270C / Winter 2016 Week5 [pdf]
with \(L' = \frac{L}{1 -
CR_s^2/L}\)
resonant frequency in right equivalent circuit \[
\omega_r^2 = \frac{1}{L'C} = \frac{1}{LC} -
\left(\frac{R_s}{L}\right)^2
\] which shows that the equivalent circuit preserves the resonant
frequency of the original network.
assuming \(i(t) = I_p\cos\omega_0
t\), where \(\omega_0
=1/\sqrt{LC}\) , suppose all current flow into \(R\)\[
V(t) = I_pR\cdot \cos\omega_0 t
\]\(I_C\), the current flow
through \(C\)\[
\color{red}I_C(t)=C\frac{\mathrm{d}V(t)}{\mathrm{d}t}=-C\omega_0\cdot
I_pR\cdot \sin\omega_0 t
\] Then, we have voltage between \(L\), given \(I_L
= -I_C\)\[
V_L(t) = L\frac{\mathrm{d}I_L(t)}{\mathrm{d}t} = LC\omega_0^2\cdot
I_pR\cdot \cos\omega_0 t = I_pR\cdot \cos\omega_0 t
\]
Series resonance
assuming \(V(t)=V_s\cos\omega_0t\),
where \(\omega_0 =1/\sqrt{LC}\) ,
suppose all current flow into \(V_C+V_L=0\)\[
V_R(t) = V(t) = V_s\cos\omega_0t
\] then \[
I_s(t) = \frac{V_s}{R}\cos\omega_0 t
\]\(V_L(t)\) is obtained \[
V_L(t) = L\frac{\mathrm{d}I_s(t)}{\mathrm{d}t} = -L\omega_0\cdot
\frac{V_s}{R}\sin\omega_0 t
\] Then \[
V_C(t) = V(t) - (V_L(t) + V_R(t)) = -V_L(t)
\] Therefore, \(I_C\) current
flow through \(C\)\[
I_C(t) = C\frac{\mathrm{d}V_C(t)}{\mathrm{d}t}= LC\omega_0^2\cdot
\frac{V_s}{R}\cos\omega_0 t= \frac{V_s}{R}\cos\omega_0 t
\] voltage potential between \(L\) and \(C\)\[
\color{red}V_m(t) = V_R(t) + V_L(t) = V_s\cos\omega_0t -L\omega_0\cdot
\frac{V_s}{R}\sin\omega_0 t = V_s\sqrt{1+L/R^2C}\cos(\omega_0t+\phi)
\]
\[
f_\text{SRF} = \frac{1}{2\pi \sqrt{LC}}
\] The SRF of an inductor is the frequency at which the parasitic
capacitance of the inductor resonates with the ideal inductance of the
inductor, resulting in an extremely high impedance. The inductance only
acts like an inductor below its SRF
For choking applications, chose an inductor
whose SRF is at or near the frequency to be attenuated
For other applications, the SRF should be at least
10 times higher than the operating frequency
it is more important to have a relatively flat inductance
curve (constant inductance vs. frequency) near the required
frequency
RLC inspection
For analyzing RLC circuits, Log-Log is indeed the best
choice.
J. Nako, G. Tsirimokou, C. Psychalinos and A. S. Elwakil,
"Approximation of First–Order Complex Resonators in the
Frequency–Domain," in IEEE Access, vol. 13, pp. 54494-54503,
2025 [pdf]
\[\begin{align}
V_o(t) &= m \cdot \sin(\omega t + \frac{\pi}{4}) + p\cdot
\sin(\omega t) = \frac{\sqrt{2}}{2}m\cdot \cos(\omega t) + \left(
\frac{\sqrt{2}}{2}m + p\right)\cdot \sin(\omega t) \\
&= \sqrt{m^2 + p^2 +\sqrt{2}pm}\cdot \sin(\omega t + \phi)
\end{align}\]
\[
H_1 - \left[H_1(1-H_3) + H_2H_3\right] = (H_1-H_2)H_3
\]
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