image-20250703212349339

speculative DFE is also known as loop unrolled DFE, which solve the critical timing on first tap


image-20250726092747147

VGA/attenuator: ensure a constant swing at the slicer input regardless of the channel variation


Inductive Peaking

TODO ๐Ÿ“…

series peaking: capacitive splitting - split the load capacitance between the amplifier drain capacitance and the next stage gate capacitance

S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension Techniques for CMOS Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006 [https://people.engr.tamu.edu/spalermo/ecen689_oi/2006_passive_bw_extension_techniques_shekhar_jssc.pdf]

CTLE Linearity

TODO ๐Ÿ“… image-20250726180642570

Front-End Noise

https://people.engr.tamu.edu/spalermo/ecen689/lecture6_ee720_rx_circuits.pdf

image-20250726180326659

image-20250726181859362

DFE Error Propagation

TODO ๐Ÿ“…

image-20250609201647012

Geoff Zhang. Preliminary Studies on DFE Error Propagation, Precoding, and their Impact on KP4 FEC Performance for PAM4 Signaling Systems [https://www.ieee802.org/3/ck/public/18_09/zhang_3ck_01a_0918.pdf]

CTLE transfer function

image-20250609201257138

Circuit Insights @ ISSCC2025: Circuits for Wireline Communications - Kevin Zheng [https://youtu.be/8NZl81Dj45M?si=J11oGnXnkJYPUi2n&t=1045]

DFE architecture

image-20250609201522455

image-20250607235201147

Extensive work on DFEs has produced a multitude of architectures, which can be broadly categorized as "direct"" or "unrolled" (speculative) DFEs with "full-rate" or "half-rate" clocking

image-20250608000306928

image-20250608000338808

image-20250608000357010

S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for 20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]

S. Ibrahim and B. Razavi, Low-Power DFE Design [https://picture.iczhiku.com/resource/eetop/wykflwIuIQDzYNcB.PDF]

PAM4 DFE

image-20250525202236767

image-20250525210606180

image-20250525221556845

image-20250525221432513

image-20250525221148218

K. -C. Chen, W. W. -T. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 750-762, March 2021 [https://www.mics.caltech.edu/wp-content/uploads/2021/02/JSSC-2020-Xavier-PAM4-Receiver.pdf]

Hongtao Zhang, DesignCon 2016. PAM4 Signaling for 56G Serial Link Applications โˆ’ A Tutorial [https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

reference

Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025

Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes [https://www.youtube.com/live/wHNOlxHFTzY]

image-20250607092632549

1UI Data Staggering

TODO ๐Ÿ“…

1UI Pulse Generator

duty correction & delay adjustment

TODO ๐Ÿ“…

DAC Driver SNDR

TODO ๐Ÿ“…

Eye Linearity vs. RLM (Relative Level Mismatch)

TODO ๐Ÿ“…

Chaowaroj (Max) Wanotayaroj. Introduction to PAM4 [https://indico.cern.ch/event/979659/contributions/4127016/attachments/2159338/3642883/PAM4Eval%20-%20Dec2020%20Seminar.pdf]

CML vs. SST based driver

image-20240825194548697

Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

image-20250607090928137

image-20250607091140352

the resistance of MOS is not highly controlled -> \(R_T + Z_N\)

image-20250607091858740

Peak power constraint of TX FIR

image-20250514215647905

Due to circuit limitation, circuit cannot have arbitrarily large voltage on the output, i.e. a limited maximum swing. In order to create the high frequency shape, the best we can do is lower DC gain (low frequency gain < 1)

  • FIR is not increasing the amplitude on the edges
  • FIR is reducing the inner eye diagram

The maximum swing stays the same, \(\sum_i |c_i|=1\)

Circuit Insights @ ISSCC2025: Circuits for Wireline Communications - Kevin Zheng [https://youtu.be/8NZl81Dj45M?si=2a8FdfGNP6yBgIW8&t=829]

SST Driver

sharing termination in SST transmitter

tx_leg.drawio

Sharing termination keep a constant current through leg, which improve TX speed in this way. On the other hand, the sharing termination facilitate drain/source sharing technique in layout.

pull-up and pull-down resistor

sst-evolution

Original stacked structure

Pro's:

โ€‹ smaller static current when both pull up and pull down path is on

Con's:

โ€‹ slowly switching due to parasitic capacitance behind pull-up and pull-down resistor

with single shared linearization resistor

Pro's:

โ€‹ The parasitic capacitance behind the resistor still exists but is now always driven high or low actively

Con's:

โ€‹ more static current

VM Driver Equalization - differential ended termination

\[ V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1} \]

where \(D_n \in \{-1, 1\}\)

vdrv.drawio \[ V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \] With \(R_u=(L+M+N)R_T\)

Normalize above equation, obtain \[ V_{\text{rx,norm}} = \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \]

\(D_{n-1}\) \(D_{n}\) \(D_{n+1}\)
\(C_{-1}\) 1 -1 -1
\(C_0\) -1 1 -1
\(C_{+1}\) -1 -1 1

Where precursor \(R_L = L\times R_T\), main cursor \(R_M = M\times R_T\) and post cursor \(R_N = N\times R_T\)

image-20220709151054840

Equation-1

\(D_{n-1}D_nD_{n+1}=1,-1,-1\)

pre.drawio

\[\begin{align} R_1 &= R_N \\ &= \frac{R_u}{N} \\ R_2 &= R_L\parallel R_M \\ &= \frac{R_u}{L+M} \end{align}\]

We obtain \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \]

Equation-2

\(D_{n-1}D_nD_{n+1}=-1,1,-1\)

main.drawio

with \(R_1=R_T\) and \(R_2=+\infty\), we obtain \[ V_M = \frac{1}{2} \]

Equation-3

\(D_{n-1}D_nD_{n+1}=-1,-1,1\)

\[\begin{align} R_1 &= R_L \\ &= \frac{R_u}{L} \\ R_2 &= R_N\parallel R_M \\ &= \frac{R_u}{N+M} \end{align}\]

We obtain \[ V_N = \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

We define \[\begin{align} l &= \frac{L}{L+M+N} \\ m &= \frac{M}{L+M+N} \\ n &= \frac{N}{L+M+N} \end{align}\]

where \(l+m+n=1\)

Due to Eq1 ~ Eq3 \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = \frac{1}{2}(n-l-m) \\ -C_{-1}+C_0-C_1 & = \frac{1}{2} \\ -C_{-1}-C_0+C_1 & = \frac{1}{2}(l-n-m) \end{array} \right. \] After scaling, we get \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = -l-m+n \\ -C_{-1}+C_0-C_1 & = l+m+n \\ -C_{-1}-C_0+C_1 & = l-m-n \end{array} \right. \] Then, the relationship between FIR coefficients and legs is clear, i.e. \[\begin{align} C_{-1} &= -\frac{L}{L+M+N} \\ C_{0} &= \frac{M}{L+M+N} \\ C_{1} &= -\frac{N}{L+M+N} \end{align}\]

For example, \(C_{-1}=-0.1\), \(C_0=0.7\) and \(C_1=-0.2\) \[ H(z) = -0.1+0.7z^{-1}-0.2z^{-2} \] image-20220709185832444

1
2
3
4
5
6
7
w = [-0.1, 0.7, -0.2];
Fs = 32e9;
[mag, w] = freqz(w, 1, [], Fs);
plot(w/1e9, abs(mag));
xlabel('Freq(GHz)');
ylabel('mag');
grid on;

VM Driver Equalization - single ended termination

Equation-1

pre_se.drawio

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\ V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N} \end{align}\] So \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \] which is same with differential ended termination

Equation-2

main_se.drawio

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \\ V_{\text{rxm}} &= 0 \end{align}\] So \[ V_{M}= \frac{1}{2} \] which is same with differential ended termination

Equation-3

\[ V_{N}= \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

Same with differential ended termination driver.

Basic Feed Forward Equalization Theory

image-20220709111229772

image-20220709112543338

image-20220709125046329

Pre-cursor FFE can compensate phase distortion through the channel

image-20220709130050057

Single-ended termination

Differential termination

TX Serializer

mux timing

mux2-1.drawio

divider latch timing

div2-latch.drawio

Two latches

two-latch.drawio

PAM4 TX

image-20220717010007963

Here, \(d_{\text{LSB}} \in \{-1, 1\}\), \(d_{\text{MSB}} \in \{-2, 2\}\) and \(d' \in \{ -3, -1, 1, 3 \}\)

Implementation-1 could potentially experience performance degradation due to

  1. Clock skew, \(\Delta t\), could make the eye misaligned horizontally
  2. Gain mismatch, \(\Delta G\), could cause eye nonlinearity
  3. Bandwidth mismatch, \(\Delta f_{\text{BW}}\), could make the eye misaligned vertically

image-20220717011129124

Typically, a 3-tap FIR (pre + main + post) TX de-emphasis is used

3-tap FIR results in \(4^3 = 64\) possible distinct signal levels

msb_lsb.drawio

\[\begin{align} R_U^M \parallel R_D^M &= \frac{3R_T}{2}\\ R_U^L \parallel R_D^L &= 3R_T \end{align}\]

Thevenin Equivalent Circuit is thevenin_1.drawio

Which can be simpified as thevenin_2.drawio \[\begin{align} V_{\text{rx}} &= \frac{1}{2}(V_p - V_m) \\ &= \frac{1}{2}(\frac{2}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-1) \\ &=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2} \end{align}\]

The above eqations demonstrate that the output \(V_{\text{rx}}\) is the linear sum of MSB and LSB; LSB and MSB have relative weight, i.e. 1 for LSB and 2 for MSB.

Assume pre cusor has \(L\) legs, main cursor \(M\) legs and post cursor \(N\) legs, which is same with the convention in "Voltage-Mode Driver Equalization"

The number of legs connected with supply can expressed as \[ n_{up} = (1-d_{n+1})L + d_{n}M + (1-d_{n-1})N \] Where \(d_n \in \{0, 1\}\), or \[ n_{up} = \frac{1}{2}(-D_{n+1}+1)L + \frac{1}{2}(D_{n}+1)M + \frac{1}{2}(-D_{n-1}+1)N \] Where \(D_n \in \{-1, +1\}\)

Then the number of legs connected with ground is \[ n_{dn}=L+M+N-n_{up} \] where \(n_{up}+n_{dn}=L+M+N\)

Voltage resistor divider \[\begin{align} V_o &= \frac{\frac{R_{U}}{n_{dn}}}{\frac{R_U}{n_{dn}}+\frac{R_U}{n_{up}}} \\ &= \frac{1}{2}- \frac{1}{2}D_{n+1}\frac{L}{L+M+N}+ \frac{1}{2}D_{n}\frac{M}{L+M+N}-\frac{1}{2}D_{n-1}\frac{N}{L+M+N} \\ &= \frac{1}{2}-\frac{1}{2}D_{n+1}\cdot l+ \frac{1}{2}D_{n}\cdot m-\frac{1}{2}D_{n-1}\cdot n \end{align}\]

where \(l+m+n=1\)

\(V_{\text{MSB}}\) and \(V_{\text{LSB}}\) can be obtained

\[\begin{align} V_{\text{MSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot m-\frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \\ V_{\text{LSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot m-\frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n \end{align}\]

Substitute the above equation into \(V_{\text{rx}}\), we obtain the relationship between driver legs and FFE coefficients

\[\begin{align} V_{\text{rx}} &=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2} \\ &= \frac{1}{3} \left\{ 2\left( \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot m- \frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \right) + \left( \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot m- \frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n \right) \right\}-\frac{1}{2} \\ &= \left(-\frac{l}{6} \cdot 2 \cdot D^{\text{MSB}}_{n+1}+ \frac{m}{6} \cdot 2 \cdot D^{\text{MSB}}_{n}- \frac{n}{6} \cdot 2 \cdot D^{\text{MSB}}_{n-1}\right) + \left(-\frac{l}{6} \cdot D^{\text{LSB}}_{n+1}+ \frac{m}{6} \cdot D^{\text{LSB}}_{n}- \frac{n}{6} \cdot D^{\text{LSB}}_{n-1}\right) \\ &= -\frac{l}{6}(2 \cdot D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ \frac{m}{6}(2\cdot D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) -\frac{n}{6}(2\cdot D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1}) \end{align}\]

After scaling, we obtain \[ V_{\text{rx}} = -l\cdot(2 \cdot D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ m\cdot(2\cdot D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) - n \cdot(2\cdot D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1}) \] Where \(C_{-1} = l\), \(C_0 = m\) and \(C_{1}=n\), which is same with that of NRZ

Test Challenges

PAM4 Transmitter Test Challenges [https://harrisburg.psu.edu/files/pdf/16861/2019/05/06/tektronix_penn_state_si_april_12_2019.pdf]

PAM4 Signaling in High Speed Serial Technology: Test, Analysis, and Debug [https://download.tek.com/document/55W_60273_1_HR_Letter.pdf]

TODO ๐Ÿ“…

reference

Noman Hai, Synopsys. CICC 2025 Circuit Insights: Basics of Wireline Transmitter Circuits [https://youtu.be/oofViBGlrjM?si=WZnOqtDVG3iDnBHI]

โ€”, Synopsys. Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

โ€”, Synopsys. CMOS Circuit Techniques for Wireline Transmitters [https://www.synopsys.com/webinars/wireline-transmitters-part-1.html]

Jihwan Kim, CICC 2022, ES4-4: Transmitter Design for High-speed Serial Data Communications

โ€”, ISSCC2019 F5: Design Techniques for a 112Gbs PAM-4 Transmitter

Friedel Gerfers, ISSCC2021 T6: Basics of DAC-based Wireline Transmitters [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T6.pdf]

Tod Dickson, IBM. High-Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Interconnects [https://www.youtube.com/watch?v=g1pcZabsRNc]

B. Razavi, "Design Techniques for High-Speed Wireline Transmitters," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 53-66, 2021, [https://www.seas.ucla.edu/brweb/papers/Journals/BROJSSCSep21.pdf]


Yvain Thonnart, CEA-LIST. ISSCC2021 T8: On-Chip Interconnects: Basic Concepts, Designs and Future Opportunities [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T8.pdf]

Mozhgan Mansuri. ISSCC2021 SC3: Clocking, Clock Distribution, and Clock Management in Wireline/Wireless Subsystems [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC3.pdf]

Sam Palermo. High-Performance SERDES Design" Online Course (2025): Current-Mode DAC TX [https://youtu.be/A2VsvCPDWxk?si=14J7JC_bnejAlHGW]

PCIeยฎ 6.0 Specification: The Interconnect for I/O Needs of the Future PCI-SIGยฎ Educational Webinar Series, [https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf]

J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012, doi: 10.1109/JSSC.2012.2216414.

C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 104-106, doi: 10.1109/ISSCC.2018.8310205.

E. Chong et al., "A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 523-526, doi: 10.1109/ESSCIRC53450.2021.9567801.

Wang, Z., Choi, M., Lee, K., Park, K., Liu, Z., Biswas, A., Han, J., Du, S., & Alon, E. (2022). An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE Journal of Solid-State Circuits, 57(1), 21-31. https://doi.org/10.1109/JSSC.2021.3109562

J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 102-104, doi: 10.1109/ISSCC.2018.8310204.

Gm-TIA CTLE

CTLE, with Gm + TIA structure

image-20250904202636824

Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]

Z. Li, M. Tang, T. Fan and Q. Pan, "A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3058-3062, Sept. 2021 [slides] [paper]

K. Kwon et al., "A 212.5Gb/s Pam-4 Receiver With Mutual Inductive Coupled Gm-Tia in 4nm Finfet," 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025

RX Equalization Noise Enhancement

Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall and H. L. Heck, John Wiley & Sons, 2009

image-20250904234845006

image-20250904235434247

Assuming \(\mathrm{SNR}(f) = \frac{S_x(f)}{S_n(f)}\)

input network

image-20250706110415914


image-20250611075951974

1
2
3
4
5
>> 10e6/2/pi/400/50

ans =

79.5775

image-20250611080033319

charging parasitic from CTLE is signal processing, bypassing the capacitor is not feasible

image-20250611080134737

image-20250611080647262

image-20250611080709544

Asymmetric T-Coil

TODO ๐Ÿ“…

Deog-Kyoon Jeong. Topics in IC Design: T-Coil [pdf]

Razavi, Behzad, "The bridged T-coil [a circuit for all seasons]." IEEE Solid-State Circuits Magazine 7.4 (2015): 9-13. [https://www.seas.ucla.edu/brweb/papers/Journals/BRFall15TCoil.pdf]

reference

J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS," 2018 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018 [https://2024.sci-hub.se/6715/9a3d5a4825e551544403f87f0b9f6a89/10.1109@ISSCC.2018.8310204.pdf] [slides]

Miguel Gandara. CICC2025 Circuits Insights: Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]

PFD/CP Modelling

image-20250807225013850

pfdcp-lmdl.drawio


image-20250807230740496

Deog-Kyoon Jeong. Topics in IC Design 2.1 Introduction to Phase-Locked Loop [pdf]

Charge Pump Noise

Cyclostationary Noise (Modulated Noise) [https://raytroop.github.io/2024/04/27/noise/#cyclostationary-noise-modulated-noise]

image-20250726174414209


Saurabh Saxena,Phase Locked Loops: Noise Simulations for CP-PLL Blocks [https://youtu.be/Q1libz-XqRw]

image-20250726183455160


image-20240928013058435

Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]

M.H. Perrott, M.D. Trott, C.G. Sodini, "A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis", JSSC, vol 38, no 8, pp 1028-1038, Aug 2002. [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]

charge pump with amplifier

image-20241002211524347

Young, I.A., Greason, J.K., Wong, K.L.: A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors. IEEE Journal of Solid-State Circuits 27(11), 1599โ€“ 1607 (1992) [https://people.engr.tamu.edu/spalermo/ecen620/pll_intel_young_jssc_1992.pdf]

Johnson, M., Hudson, E.: A variable delay line PLL for CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits 23(10), 1218โ€“1223 (1988) [https://sci-hub.se/10.1109/4.5947]

Sam Palermo, Lecture 5: Charge Pump Circuits, ECEN620: Network Theory Broadband Circuit Design Fall 2024 [https://people.engr.tamu.edu/spalermo/ecen620/lecture05_ee620_charge_pumps.pdf]

Non-ideal Effects in Charge Pump

The periodic signal on VCTRL modulates the VCO, giving rise to deterministic jitter


  • Timing Offsets Between Up and Dn Pulses
  • Mismatch Between Charge-Pump Current Sources
  • Incomplete Settling of Charge-Pump Currents
  • Finite Output Resistance of the Charge Pump

Up/Dn Timing Offset

image-20241222171705612

If Dn pulse arrives \(\Delta T\) after the Up pulse, the steady-state VCTRL will be slightly lower than it would be without the \(\Delta T\) mismatch so as to return the VCO's phase to match the reference clocks.

Vice versa, if If Up pulse arrives \(\Delta T\) after the Dn pulse, the steady-state VCTRL will be slightly higher than without \(\Delta T\) mismatch

Current Sources Mismatch

image-20241222174620713

image-20241222174718564

Incomplete Settling

TODO ๐Ÿ“…

W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]

Cowan G. Mixed-Signal CMOS for Wireline Communication: Transistor-Level and System-Level Design Considerations. Cambridge University Press; 2024

2nd loop filter

PI (proportional - integral) Loop Filter

image-20240907123938255

image-20240907124029346

image-20240907124018476

PFD Deadzone

Dead zone induced by incomplete settling of charge-pump currents

This situation can be avoided by adding additional delay to the AND gate in the PFD

image-20241222190011244

Sam Palermo, "Lecture 4: Phase Detector Circuit" [https://people.engr.tamu.edu/spalermo/ecen620/lecture04_ee620_phase_detectors.pdf]

LPF leakage

image-20241222192007824

For the sake of simplicity, \(V_{ctr}\) looks like a rectangular pulse with an amplitude of \(I_{CP}R_1\) and a duty ratio of (\(I_{leak}/I_{CP}\)), whose first coefficient of Fourier series is

image-20241222200514941

where \(I_\text{leak} \ll I_{CP}\) is assumed

Then, the peak frequency deviation \(\Delta f\) \[ \Delta f = a_1 \cdot K_v = 2I_\text{leak}R_1 K_v \] using narrowband FM approximation, we have \[ P_\text{spur} = 20\log\left(\frac{\Delta f}{2f_\text{ref}}\right) = 20\log\left(\frac{I_\text{leak}R_1 K_v}{f_\text{ref}}\right) \]

W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]

โ€”. Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons


image-20241222200158107

[https://lpsa.swarthmore.edu/Fourier/Series/ExFS.html]

reference

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007.

Saurabh Saxena. Noise Simulations for CP-PLL Blocks [https://youtu.be/Q1libz-XqRw]

โ€”, IIT Madras. CICC2022 Clocking for Serial Links - Frequency and Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery

Helene Thibieroz, Customer Support CIC. Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=3056e59ea76165373f90152f915a829d25dabebc]


Chembiyan T. Chargepump PLL Basics- From A Control Theoretic Viewpoint [linkedin]

โ€”. Challenges in Chargepump PLL Design- A Qualitative Approach [linkedin]

โ€”. A Unified Approach to Low Noise Loop Design in Chargepump PLLs [linkedin]


Xiang Gao Credo Semiconductor. ISSCC2018 T1: Low-Jitter PLLs for Wireless Transceivers [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T1/T1Visuals.pdf]

Hunting Jitter

Hunting jitter is often referred to as dithering jitter, the periodic time error between data clock and input data, which exhibits a limit-cycle behavior

image-20250819202727871

image-20250819203806711

image-20250819210031102

BB PD

Youngdon Choi, Deog-Kyoon Jeong and W. Kim, "Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 775-783, Nov. 2003 [https://sci-hub.st/10.1109/TCSII.2003.819070]

John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and Data Recovery [slides transcript]

Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems. [pdf]

โ€”, Clock and Data Recovery for Serial Data Communications, focusing on bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]

It's ternary, because early, late and no transition

notice the transition density = 1 in digital PLL

Linearization

The effective PD gain is a function of the input jitter pdf, it enables one to anticipate the effects of input jitter on loop characteristics

BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),

BB only produces output for a transition and this de-rates the gain. Transition density = 0.5 for random data

\[ K_{BB} = \frac{1}{2}\frac {\partial \mu}{\partial \phi} \]

where \(\mu = (1)\times \mathrm{P}(\text{late}|\phi) + (-1)\times \mathrm{P}(\text{early}|\phi)\)

bb-PDF.drawio

Both jitter and amplitude noise distribution are same, just scaled by slope

Self-Noise Term

One price we pay for BB PD versus linear PD is the self-noise term. For small phase errors BB output noise is the full magnitude of the sliced data

The PD output should be almost 0 for small phase errors. i.e. ideal PD output noise should be 0

\[ \sigma_{BB}^2 = 1^2 \cdot \mathrm{P}(\text{trans}) + 0^2\cdot (1-\mathrm{P}(\text{trans})) = 0.5 \]

image-20241127215947017

Input referred jitter from BB PD is proportional to incoming jitter

image-20241127220933103

gain simulation

L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S. Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]

T. -K. Kuan and S. -I. Liu, "A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques," in IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 821-831, April 2016 [https://sci-hub.st/10.1109/JSSC.2016.2519391]

image-20250902215541227

image-20250913192552933

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import matplotlib.pyplot as plt
import numpy as np

N = 2**10
sigma = 0.1
dt = np.random.normal(sigma,size=N)
et = np.sign(dt)

# Eq-(2)
coef_form = np.mean(np.abs(dt)) / np.mean(np.power(dt, 2))
print(f'coef_form: {coef_form}')

# Eq-(9)
coef_gauss = (2/np.pi)**0.5/sigma
print(f'coef_gauss: {coef_gauss}')

# polyfit
coef_fit = np.polyfit(dt, et, 1)
print(f'coef_fit: {coef_fit}')

x = np.linspace(-3.5, 3.5, 1000)
y = coef_fit[0]*x + coef_fit[1]

plt.figure(figsize=(12,6))
plt.plot(dt, et, 'o')
plt.plot(x, y, linewidth=2, linestyle='--')

# Calculate histogram counts and bin edges
counts, bin_edges = np.histogram(dt, bins=100)
# Find the maximum count
max_count = counts.max()
# Create weights to normalize the maximum height to 1
weights = np.ones_like(dt) / max_count
plt.hist(dt, bins=100, weights=weights)

plt.xlabel(r'$\Delta t$')
plt.grid(True)
plt.legend([r'$\Delta t \sim \varepsilon $', r'$x_{fit} \sim y_{fit}$', r'$ \text{hist}_{\Delta t}$'])
plt.show()


# coef_form: 0.7910794009505085
# coef_gauss: 7.978845608028654
# coef_fit: [0.79013999 0.0204332 ]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016). Understanding Delta-Sigma Data Converters. 2nd ed. Wiley. - 2.2.1 Quantizer Modeling

image-20250902212931083 \[ \frac{d\sigma_e^2}{dk} =0\space\space\Rightarrow\space\space k=\frac{\left\langle v,y\right\rangle}{\left\langle y,y \right\rangle} \]

image-20250902231449843

DCO Quantization Noise

TODO ๐Ÿ“…

TDC Quantization Noise

TODO ๐Ÿ“…

image-20250601122145164

CDR Loop Latency

Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery Circuits"

CC Chen. Why A Low Loop Latency in A CDR Design? [https://youtu.be/io9WZbhlahU]

โ€”. Why Understanding and Optimizing Loop Latency for A CDR Design? [https://youtu.be/Jyy18865jv8]

image-20250706173343946


image-20250706121529451


image-20241102235118149

image-20241102235145417

loop latency is represented as \(e^{-sD}\) in linear model


image-20241102235736432

image-20241103000223470

image-20241103000653906

Sensitivity to Loop Latency

image-20241103142137640


image-20241103142656134

image-20241103142531277

image-20241103142938907

Optimizing Loop Latency

TODO ๐Ÿ“…

CC Chen. Circuit Image: Why Understanding and Optimizing Loop Latency for A CDR Design? [https://youtu.be/Jyy18865jv8?si=uY2HUV8mERLterwH]

DT & CT Spectral Density

image-20250512230604969


[Sampling of WSS process of Systems, Modulation and Noise]

image-20250512233058520

That is \[ P_{x_s x_s} (f)= \frac{1}{T_s}P_{xx}(f) \] In going from discrete time to continuous time, we must add a scale factor \(1/T\), the sample period


image-20250513211531981

reference

Sam Palermo, ECEN620 2024 Lecture 9: Digital PLLs [https://people.engr.tamu.edu/spalermo/ecen620/lecture09_ee620_digital_PLLs.pdf]

Topics in IC(Wireline Transceiver Design) [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

Michael H. Perrott, ISSCC 2008 Tutorial on Digital Phase-Locked Loops [https://www.nishanchettri.com/isscc-slides/2008%20ISSCC/Tutorials/T05_Pres.pdf]

โ€”, CICC 2009 Tutorial on Digital Phase-Locked Loops [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

Robert Bogdan Staszewski, CICC 2020: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis [link]

Akihide Sai, ISSCC 2023 T5: All-digital PLLs From Fundamental Concepts to Future Trends [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T5.pdf]

Mike Shuo-Wei Chen, CICC 2020 ES2-3: Low-Spur PLL Architectures and Techniques [https://youtu.be/sgPDchYhN-4?si=FAy8N3SuX6vVpYhl]

S. Levantino, "Digital phase-locked loops," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018 [slides]

Saurabh Saxena, IIT Madras. Phase-Locked Loops: Noise Analysis in Digital PLL [https://youtu.be/mddtxcqfiKU?si=yD15KM9WBkT6c68P]


Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 7, pp. 3030-3036, July 2022


Neil Robertson. Digital PLL's -- Part 1 [https://www.dsprelated.com/showarticle/967.php]

Neil Robertson. Digital PLL's -- Part 2 [https://www.dsprelated.com/showarticle/973.php]

Neil Robertson. Digital PLL's -- Part 3 [https://www.dsprelated.com/showarticle/1177.php]

Daniel Boschen. GRCon24 - Quick Start on Control Loops with Python Workshop [video, slides]


L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S. Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]

M. Zanuso, D. Tasca, S. Levantino, A. Donadel, C. Samori and A. L. Lacaita, "Noise Analysis and Minimization in Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 11, pp. 835-839, Nov. 2009 [https://sci-hub.st/10.1109/TCSII.2009.2032470]

N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3663-3675, Dec. 2008 [https://sci-hub.st/10.1109/TCSI.2008.925948]

โ€”, "Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 11, pp. 1195-1199, Nov. 2006 [https://sci-hub.st/10.1109/TCSII.2006.883197]

โ€”, "A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005 [https://sci-hub.se/10.1109/TCSI.2004.840089]

โ€”, "Theory and Implementation of Digital Bang-Bang Frequency Synthesizers for High Speed Serial Data Communications", PhD Dissertation, RWTH Aachen University, Aachen, North Rhine-Westphalia, Germany, 2007 [pdf]

Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems. [paper,slides]


hunting jitter

S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim and D. -K. Jeong, "An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bangโ€“Bang Phase-Frequency Detection," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 9, pp. 836-840, Sept. 2015 [https://sci-hub.st/10.1109/TCSII.2015.2435691] [phd thesis]

Deog-Kyoon Jeong. Topics in IC (Wireline Transceiver Design). Lec 3 - All-Digital PLL [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

โ€”. Topics in IC (Wireline Transceiver Design). Lec 6 - Clock and Data Recovery [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

Lee Hae-Chang.: โ€˜An estimation approach to clock and data recoveryโ€™, PhD Thesis, Stanford University, November 2006 [pdf]

J. Kim, Design of CMOS Adaptive-Supply Serial Links, Ph.D. Thesis, Stanford University, December 2002. [pdf]

High-speed Serial Interface 2013. Lect. 16 โ€“ Clock and Data Recovery 3 [http://tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect16_CDR-3.pdf]

CC Chen. Why Hunting Jitter Happens in CDR: The Role of Input Jitter and Latency? [https://youtu.be/hPDielPsFgY]

Switched Capacitor Circuits

image-20250607160642574

image-20250607171740269

Clock Feedthrough

aka. LO leakage

TODO ๐Ÿ“…

Integrator

TODO ๐Ÿ“…

[https://www.eecg.utoronto.ca/~johns/ece1371/slides/10_switched_capacitor.pdf]

[https://www.seas.ucla.edu/brweb/papers/Journals/BRWinter17SwCap.pdf]

[https://class.ece.iastate.edu/ee508/lectures/EE%20508%20Lect%2029%20Fall%202016.pdf]

reference

R. S. Ashwin Kumar, Analog circuits for signal processing [https://home.iitk.ac.in/~ashwinrs/2022_EE698W.html]

R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. Wiley-Interscience, 1986 [pdf]

Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]

Boris Murmann. EE315A VLSI Signal Conditioning Circuits


Negar Reiskarimian. CICC 2025 Insight: Switched Capacitor Circuits [https://youtu.be/SL3-9ZMwdJQ]

Temperature compensation for VCO

Temperature compensation for the VCO oscillation frequency is a critical issue

TODO ๐Ÿ“…

Leeson Model

M.H. Perrott [https://www.cppsim.com/PLL_Lectures/day2_am.pdf]

โ€”. [https://ocw.mit.edu/courses/6-976-high-speed-communication-circuits-and-systems-spring-2003/ceb3d539691d5393a29af71ae98afb62_lec12.pdf]

Leeson's model is outcome of linearized VCO noise analysis

image-20250920125120068

image-20250920170108939

\[ Q = R_p\omega_0 C_p = \frac{R_p}{\omega_0 L} \]

where \(\omega_0 = \frac{1}{\sqrt{L_pC_p}}\)

image-20250920170331118

[https://stanford.edu/class/ee133/handouts/lecturenotes/lecture5_tank.pdf]

image-20250920171147163

image-20250920171411886

LTV Models

image-20250629065454831

image-20250629073305626

PPV (Perturbation Projection Vector)

A. Demir and J. Roychowdhury, "A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 188-197, Feb. 2003 [https://sci-hub.se/10.1109/TCAD.2002.806599]

Helene Thibieroz, Customer Support CIC. Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=3056e59ea76165373f90152f915a829d25dabebc]

Aditya Varma Muppala. Perturbation Projection Vector (PPV) Theory | Oscillators 11 | MMIC 16 [youtu.be, notes]

image-20250920101142887

Limit Cycles

[https://adityamuppala.github.io/assets/Notes_YouTube/MMIC_Limit_Cycles.pdf]

Nonlinear Dynamics

image-20250622202023590

image-20250920101927173

ISF model

image-20251008184336891

image-20251008184349072

C. Livanelioglu, L. He, J. Gong, S. Arjmandpour, G. Atzeni and T. Jang, "19.10 A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving โˆ’255.2dB FoMJ Including the XO Power and Noise," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025

image-20251008185243498

image-20251008185406867


image-20250626210829173

[https://adityamuppala.github.io/assets/Notes_YouTube/Oscillators_ISF_model.pdf]

image-20250629080430980

Periodic ISF: Noise Folding

image-20250629080632902

When performing the phase noise computation integral, there will be a negligible contribution from all terms, other than \(n=m\)

image-20250629083344136

image-20250629083453955

Given \(i(t) = I_m \cos[(m\omega_0 +\Delta \omega)t]\),

\[\begin{align} \phi(t) &= \frac{1}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t I_m\cos((m\omega_0 +\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t I_m\cos((m\omega_0 +\Delta \omega)\tau)\cos(n\omega_0\tau)d\tau\right] \\ &= \frac{I_m}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t \cos((m\omega_0 +\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t \frac{\cos((m\omega_0 + \Delta \omega+ n\omega_0)\tau)+ \cos((m\omega_0+\Delta \omega - n\omega_0)\tau)}{2}d\tau\right] \end{align}\]

If \(m=0\) \[ \phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \] If \(m\neq 0\) and \(m=n\) \[ \phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \]

\(m\omega_0 +\Delta \omega \ge 0\)

image-20250629105156403

image-20250629100444702

A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," in IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998

image-20250629102112814


Corrections to "A General Theory of Phase Noise in Electrical Oscillators"

A. Hajimiri and T. H. Lee, "Corrections to "A General Theory of Phase Noise in Electrical Oscillators"," in IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp. 928-928, June 1998 [https://sci-hub.se/10.1109/4.678662]

Ali Hajimiri. Phase Noise in Oscillators [http://www-smirc.stanford.edu/papers/Orals98s-ali.pdf]

L. Lu, Z. Tang, P. Andreani, A. Mazzanti and A. Hajimiri, "Comments on โ€œComments on โ€œA General Theory of Phase Noise in Electrical Oscillatorsโ€โ€," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2170-2170, Sept. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005028]

image-20250629104527666

image-20250629081831223

Given \(i(t) = I_m \cos[(m\omega_0 - \Delta \omega)t]\) and \(m \ge 1\)

\[\begin{align} \phi(t) &= \frac{1}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t I_m\cos((m\omega_0 -\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t I_m\cos((m\omega_0 -\Delta \omega)\tau)\cos(n\omega_0\tau)d\tau\right] \\ &= \frac{I_m}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t \cos((m\omega_0 -\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t \frac{\cos((m\omega_0 - \Delta \omega+ n\omega_0)\tau)+ \cos((m\omega_0-\Delta \omega - n\omega_0)\tau)}{2}d\tau\right] \end{align}\]

If \(m\ge 1\) and \(m=n\) \[ \phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \] That is

\(m = 0\) \(m\gt 0\) & \(m\omega_0+\Delta \omega\) \(m\gt 0\) & \(m\omega_0-\Delta \omega\)
\(\phi(t)\) \(\frac{I_0C_0}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t)\) \(\frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t)\) \(\frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t)\)
\(P_{SBC}(\Delta \omega)\) \(10\log(\frac{I_0^2C_0^2}{16q_\text{max}^2\Delta \omega^2})\) \(10\log(\frac{I_m^2C_m^2}{16q_\text{max}^2\Delta \omega^2})\) \(10\log(\frac{I_m^2C_m^2}{16q_\text{max}^2\Delta \omega^2})\)

\[\begin{align} \mathcal{L}\{\Delta \omega\} &= 10\log\left(\frac{I_0^2C_0^2}{16q_\text{max}^2\Delta \omega^2} + 2\frac{I_m^2C_m^2}{16q_\text{max}^2\Delta \omega^2}\right) \\ &= 10\log\left(\frac{\overline{i_n^2/\Delta f}\cdot \frac{C_0^2}{2} }{4q_\text{max}^2\Delta \omega^2} + \frac{\overline{i_n^2/\Delta f}\cdot\sum_{m=1}^\infty C_m^2 }{4q_\text{max}^2\Delta \omega^2}\right) \\ &= 10\log \frac{\overline{i_n^2/\Delta f}(C_0^2/2+\sum_{m=1}^\infty C_m^2)}{4q_\text{max}^2\Delta \omega^2} \\ &= 10\log \frac{\overline{i_n^2/\Delta f}\cdot \Gamma_\text{rms}^2}{2q_\text{max}^2\Delta \omega^2} \end{align}\]

ISF & \(1/f\)-noise up-conversion

TODO ๐Ÿ“…

image-20250626211817628

ISF Simulation

image-20241113232703941

PSS + PXF Method

Yizhe Hu, "A Simulation Technique of Impulse Sensitivity Function (ISF) Based on Periodic Transfer Function (PXF)" [https://bbs.eetop.cn/thread-869343-1-1.html]

TODO ๐Ÿ“…

Transient Method

David Dolt. ECEN 620 Network Theory - Broadband Circuit Design: "VCO ISF Simulation" [https://people.engr.tamu.edu/spalermo/ecen620/ISF_SIM.pdf]

image-20241016211020230

image-20241016211101204

image-20241016211115630

To compare the ring oscillator and VCO the total injected charge to both should be the same

Injection Locking

TODO ๐Ÿ“…


"Topics in IC (Wireline Transceiver Design): Lec 4 - Injection Locked Oscillators" [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%204%20-%20Injection%20Locked%20Oscillators.pdf]

Cowan, Glenn. (2024). Mixed-Signal CMOS for Wireline Communication: Transistor-Level and System-Level Design Considerations

Mozhgan Mansuri. ISSCC2021 SC3: Clocking, Clock Distribution, and Clock Management in Wireline/Wireless Subsystems [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC3.pdf]

Aditya Varma Muppala. Oscillator Theory - Injection Locking [note, video1, video2]

Min-Seong Choo. Review of Injection-Locked Oscillators [https://journal.theise.org/jse/wp-content/uploads/sites/2/2020/09/JSE-2020-0001.pdf]

Capacitor simulation

VCO varactor

Two methods: 1. pss + pac; 2. pss+psp

PSS + PAC

image-20220510192206354

pss time domain

image-20220510192351590

using the 0-harmonic

image-20220510192447040

PSS + PSP

image-20220510192753324

using Y11 of psp

image-20220510192639080

comparison

image-20220510193036717

which are same

inverter input

R-C, series equivalent circuit

invCap

inverter output

R-C, parallel equivalent circuit


AC simulation

image-20250628112910588

@vi = 0

image-20250628104042741

sweep vi from 0 to 800mV (vdd)

image-20250628105510374


SP simulation

image-20250628112857124

image-20250628112620876

EEStream. Cadence - How to find device capacitance - DC simulation, SP simulation and Large-signal SP simulation [https://www.youtube.com/watch?v=M3zP6eJnONk]

image-20250628114414562

reference

Jiล™รญ Lebl. Notes on Diffy Qs: Differential Equations for Engineers [link]

Matt Charnley. Differential Equations: An Introduction for Engineers [link]

ร…strรถm, K.J. & Murray, Richard. (2021). Feedback Systems: An Introduction for Scientists and Engineers Second Edition [https://www.cds.caltech.edu/~murray/books/AM08/pdf/fbs-public_24Jul2020.pdf]

Strogatz, S.H. (2015). Nonlinear Dynamics and Chaos: With Applications to Physics, Biology, Chemistry, and Engineering (2nd ed.). CRC Press [https://www.biodyn.ro/course/literatura/Nonlinear_Dynamics_and_Chaos_2018_Steven_H._Strogatz.pdf]

Cadence Blog, "Resonant Frequency vs. Natural Frequency in Oscillator Circuits" [link]


Aditya Varma Muppala. Oscillators [https://youtube.com/playlist?list=PL9Trid0A4Da2fOmYTEjhAnUkGPxyiH7H6&si=ILxn8hfkMYjXW5f4]

P.E. Allen - 2003. ECE 6440 - Frequency Synthesizers: Lecture 160 โ€“ Phase Noise - II [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L160-PhNoII(2UP).pdf]

Y. Hu, T. Siriburanon and R. B. Staszewski, "Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019 [https://sci-hub.se/10.1109/TCSII.2019.2896483]

S. Levantino, P. Maffezzoni, F. Pepe, A. Bonfanti, C. Samori and A. L. Lacaita, "Efficient Calculation of the Impulse Sensitivity Function in Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 10, pp. 628-632, Oct. 2012 [https://sci-hub.se/10.1109/TCSII.2012.2208679]

S. Levantino and P. Maffezzoni, "Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 10, pp. 1499-1507, Oct. 2012 [https://sci-hub.se/10.1109/TCAD.2012.2194493]

Thomas H. Lee. Linearity, Time-Variation, Phase Modulation and Oscillator Phase Noise [https://class.ece.iastate.edu/djchen/ee507/PhaseNoiseTutorialLee.pdf]

Y. Hu, T. Siriburanon and R. B. Staszewski, "Oscillator Flicker Phase Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468]

Jaeha Kim. Lecture 8. Special Topics: Design Trade -Offs in LC -Tuned Oscillators [https://ocw.snu.ac.kr/sites/default/files/NOTE/7033.pdf]

A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in oscillators: a unifying theory and numerical methods for characterization," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674, May 2000 [https://sci-hub.se/10.1109/81.847872]


A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC Oscillator," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 45-59, 2025 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10818782]

Akihide Sai, Toshiba. ISSCC 2023 T5: All-digital PLLs From Fundamental Concepts to Future Trends [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T5.pdf]


Pietro Andreani. ISSCC 2011 T1: Integrated LC oscillators [slides,transcript]

โ€”. ISSCC 2017 F2: Integrated Harmonic Oscillators

โ€”. SSCS Distinguished Lecture: RF Harmonic Oscillators Integrated in Silicon Technologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto.pdf]

โ€”. ESSCIRC 2019 Tutorials: RF Harmonic Oscillators Integrated in Silicon Technologies [https://youtu.be/k1I9nP9eEHE?si=fns9mf3aHjMJobPH]

โ€”. "Harmonic Oscillators in CMOSโ€”A Tutorial Overview," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021 [pdf]

C. Samori, "Tutorial: Understanding Phase Noise in LC VCOs," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016

โ€”, "Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits," in IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 81-91, Fall 2016 [https://sci-hub.se/10.1109/MSSC.2016.2573979]

โ€”, Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-VCO-short.pdf]

Jun Yin. ISSCC 2025 T10: mm-Wave Oscillator Design

TODO ๐Ÿ“…

ADC Calibration

Ahmed Ali, ISSCC 2021 T5: Calibration Techniques in ADCs [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T5.pdf]

Jiang, Xicheng, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015.

Offset Calibration

long-term average of all 32 sub-ADC samples = 0

Gain Calibration

long-term average of absolute values of all 32 sub-ADC samples should be equal

Background vs. foreground

TODO ๐Ÿ“…

Linear phase

image-20241213232002042


image-20241213233748837

image-20241213233917966

[https://web.ece.ucsb.edu/~yoga/courses/DSP/P10_Linear_phase_FIR.pdf]

Digital DC Offset Correction

image-20241229122711845 \[ X- Y\cdot \beta z^{-1}\cdot \frac{1}{1-z^{-1}} = Y \] therefore \[ \frac{Y}{X} = \frac{1-z^{-1}}{1-(1-\beta)z^{-1}} \]

VDD Droop Mitigation

image-20250105134745277

speed of voltage monitor does matter

reference

Chadi Jabbour, ed, Digitally Enhanced Mixed Signal Systems. IET 2019

Jiang X, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge University Press; 2015.

Ping-Hsuan Hsieh. SSCS Events: Digitally-Enhanced Clock Generation and Distribution; 20 August 2025.

ISSCC 2024 FORUM 3: Digitally Enhanced Analog Circuits: Trends & State-of-the-art Designs

Albert Jerng. ISSCC2012 T7: Digital Calibration for RF Transceivers [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T7.pdf]

Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in ADCs [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T5.pdf]

Salvatore Levantino. ISSCC2024 T5: Calibration Techniques in PLLs [https://www.nishanchettri.com/isscc-slides/2024%20ISSCC/TUTORIALS/T5.pdf]


B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and Applications (2nd ed.). John Wiley & Sons, Inc.

Simon O. Haykin (2014), "Adaptive Filter Theory" Prentice-Hall, Inc. 5rd edition

Diniz, P. S. R. (2020). Adaptive Filtering: Algorithms and Practical Implementation (5th ed.). Springer

Sen M. Kuo. Real-Time Digital Signal Processing: Fundamentals, Implementations and Applications, 3rd Edition. John Wiley & Sons 2013

Stankovic, Ljubisa. (2015). Digital Signal Processing with Selected Topics.


A. Chan Carusone and D. A. Johns, "Analog Filter Adaptation Using a Dithered Linear Search Algorithm," IEEE Int. Symp. Circuits and Syst., May 2002. [PDF], [Slides]

โ€”, Ph. D. Thesis, "Digital Algorithms for Analog Adaptive Filters", Feb. 2002. [http://www.eecg.utoronto.ca/~tcc/thesis.pdf]

โ€”, "Analog Adaptive Filters," tutorial at the IEEE Int. Symp. Circuits and Syst., Bangkok, Thailand, May 2003. [http://www.eecg.utoronto.ca/~tcc/iscas03_tutorial.pdf]

โ€”, 2022 Optimization Tools for Future Wireline Transceivers [https://www.ieeetoronto.ca/wp-content/uploads/2022/12/UofT-Future-of-Wireline-Workshop-2022.pdf]

David Johns, "Integrated Circuits for Digital Communications" [https://www.eecg.toronto.edu/~johns/nobots/courses/ece1392/slides.pdf]

Tai-Haur Kuo "Advanced Analog IC Design for Communications" [http://msic.ee.ncku.edu.tw/course/AdvancedAnalogICDesign/AdvancedAnalogICDesign.html]

Chadi Jabbour, Telecom Paristech. ISCAS 2019 T12: Digitally Enhanced Mixed Signal Systems [https://www.youtube.com/watch?v=rACuCSDm5jQ]

Time domain modeling

While many different analysis methods exist, including frequency and statistical analysis, time domain results remain the final sign-off

image-20250824223103058

image-20250807000316790

serdespy

Richard Barrie. serdespy โ€” A python library for system-level SerDes modelling and simulation [https://github.com/richard259/serdespy]

JLSD

Kevin Zheng. JLSD โ€” Julia SerDes [https://github.com/kevjzheng/JLSD]


Kronecker product to create oversampled waveform

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function gen_wvfm(bits; tui, osr)
#helper function used to generate oversampled waveform

Vbits = kron(bits, ones(osr)) #Kronecker product to create oversampled waveform
dt = tui/osr
tt = 0:dt:(length(Vbits)-1)*dt

return tt, Vbits
end

normalized to the time step \[ \frac{\alpha}{s+\alpha} \overset{\mathcal{L}^{-1}}{\longrightarrow} \alpha\cdot e^{-\alpha t} \]

The integral of impulse response of low pass RC filter \(\int_{0}^{+\infty} \alpha\cdot e^{-\alpha t}dt = 1\) โ€” sum(ir*dt)

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function gen_ir_rc(dt,bw,t_len)
#helper function that directly calculates a first order RC response, normalized to the time step
tt = [0:dt:t_len-dt;]

#checkout the intuitive symbols!
ฯ‰ = (2*ฯ€*bw)
ir = ฯ‰*exp.(-tt*ฯ‰)
ir .= ir/sum(ir*dt)

return ir
end
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using Plots
using LaTeXStrings

tui = 1/10e9;
tlen_ir = 20*tui;


osr_list = [4, 8, 16, 32, 64, 128, 256, 512, 1024];
bw_ir = 8e9;

ฯ‰ = (2*ฯ€*bw_ir);

ir_dt_sum_list = [];

for osr_cur in osr_list
dt = tui/osr_cur; # Simulation time step
tt = [0:dt:tlen_ir-dt;]
ir = ฯ‰*exp.(-tt*ฯ‰);
ir_dt_sum = sum(ir*dt);
push!(ir_dt_sum_list, ir_dt_sum)
end

println(ir_dt_sum_list)
# Any[1.756575097878581, 1.3468434968519964, 1.1652908056870317, 1.0805951388547221, 1.0397838972257087, 1.0197634612560418, 1.0098496044545267, 1.0049167704129547, 1.0024563772359665]

p = plot(osr_list, ir_dt_sum_list, label = "OSR")
gui(p)

image-20251008131325508


Elastic Buffer

the elastic buffer approach would be the most general for modeling say frequency offsets between TX and RX (will be addressed in future development)

An_example_of_elastic_buffer


generate PAM symbols

here Big Endian

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#generate PAM symbols
fill!(So, zero(Float64)) #reset So to all 0
for n = 1:bits_per_sym
@. So = So + 2^(bits_per_sym-n)*So_bits[n:bits_per_sym:end]
end
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function int2bits(num, nbit)
return [Bool((num>>k)%2) for k in nbit-1:-1:0]
end


Si_bits .= vec(stack(int2bits.(Si, bits_per_sym)))

Detailed Transmitter

tx blk diagram

DaVE

DaVE โ€” tools regarding on analog modeling, validation, and generation, [https://github.com/StanfordVLSI/DaVE]

Statistical Eye

Sanders, Anthony, Michael Resso and John D'Ambrosia. โ€œChannel Compliance Testing Utilizing Novel Statistical Eye Methodology.โ€ (2004).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

HSPICEยฎ User Guide: Signal Integrity Modeling and Analysis, Version Q-2020.03, March 2020

IA Title: Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]

J. Park and D. Kim, "Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review," in IEEE Access, vol. 12, pp. 22880-22891, 2024 [pdf]

StatOpt

Savo Bajic, ECE1392, Integrated Circuits for Digital Communications: StatOpt in Python [https://savobajic.ca/projects/academic/statopt] [https://www.eecg.utoronto.ca/~ali/statopt/main.html]

Analog Signals Representation

Ben Yochret Sabrine, 2020, "BEHAVIORAL MODELING WITH SYSTEMVERILOG FOR MIXED-SIGNAL VALIDATION" [https://di.uqo.ca/id/eprint/1224/1/Ben-Yochret_Sabrine_2020_memoire.pdf]

image-20250913234701819


image-20250914115332274

PRBS Generator & Checker

PRBS Generator

image-20251008232419923

[https://opencpi.gitlab.io/releases/latest/rst/comp_sdr/components/generator/prbs_generator_b.comp/prbs_generator_b-index.html]

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# Julia

function bist_prbs_gen(;poly, inv, Nsym, seed)
seq = Vector{Bool}(undef,Nsym)
for n = 1:Nsym
seq[n] = inv
for p in poly
seq[n] โŠป= seed[p]
end
seed .= [seq[n]; seed[1:end-1]]
end
return seq, seed
end
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%% Matlab

function [seq, seed] = bist_prbs_gen(poly,inv, Nsym, seed)
seq = zeros(1,Nsym);
for n = 1:Nsym
seq(n) = inv;
for p = poly
seq(n) = xor(seq(n), seed(p));
end
seed = [seq(n), seed(1:end-1)];
end
end

image-20251003110528405

[https://github.com/kevjzheng/JLSD/blob/main/Pluto%20Notebooks/pdf/JLSD_pt1_background.pdf]

PRBS Checker

previous bit determine current bit

bert.drawio

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function ber_check_prbs(rcvd_bits; poly, inv, seed, lock_status, lock_cnt, lock_threshold, ber_err_cnt, ber_tot_cnt)

nbits_rcvd = lastindex(rcvd_bits)

if lock_status #if prbs already locked, use prbs_gen for reference bits
ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv,
Nsym=nbits_rcvd, seed=seed)
ber_err_cnt += sum(rcvd_bits .โŠป ref_bits)
ber_tot_cnt += nbits_rcvd

else # if not locked yet, use received bits as seed
for n = 1:nbits_rcvd
brcv = rcvd_bits[n]
btst = inv
for p in poly
btst โŠป= seed[p]
end
seed .= [brcv; seed[1:end-1]]

#need consecutive non-error for lock. reset when error happens
lock_cnt = (btst == brcv) ? lock_cnt+1 : 0

if lock_cnt == lock_threshold
lock_status = true
println("prbs locked")
#run prbs till end
ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv,
Nsym=nbits_rcvd-n, seed=seed)
ber_err_cnt += sum(rcvd_bits[n+1:end] .โŠป ref_bits)
ber_tot_cnt += nbits_rcvd - n

break
end
end
end

return seed, lock_status, lock_cnt, ber_err_cnt, ber_tot_cnt
end

Reference

MATLABยฎ and Simulinkยฎ RF and Mixed Signal [https://www.mathworks.com/help/overview/rf-and-mixed-signal.html]


Lim, Byong Chan, M. Horowitz, "Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1, pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]

โ€”, Ph.D. Dissertation 2012. "Model validation of mixed-signal systems" [https://stacks.stanford.edu/file/druid:xq068rv3398/bclim-thesis-submission-augmented.pdf]

โ€”, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog Design: Enabling Mixed-Signal System Validation," in IEEE Design & Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

โ€” , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim, Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

S. Liao and M. Horowitz, "A Verilog piecewise-linear analog behavior model for mixed-signal validation," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013 [https://sci-hub.se/10.1109/CICC.2013.6658461]

โ€”, M. Horowitz, "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2229-2235, Aug. 2014 [https://sci-hub.se/10.1109/TCSI.2014.2332265]

โ€”,Ph.D. Dissertation 2012. Verilog Piecewise Linear Behavioral Modeling For Mixed-Signal Validation [https://stacks.stanford.edu/file/druid:pb381vh2919/Thesis_submission-augmented.pdf]

Ji-Eun Jang et al. โ€œTrue event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver exampleโ€. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. 2012 [https://sci-hub.se/10.1109/CICC.2012.6330558]

โ€”, Si-Jung Yang, and Jaeha Kim. โ€œEvent-driven simulation of Volterra series models in SystemVerilogโ€. In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference. 2013 [https://sci-hub.se/10.1109/CICC.2013.6658460]

โ€”, Ph.D. Dissertation 2015. Event-Driven Simulation Methodology for Analog/Mixed-Signal Systems [file:///home/anon/Downloads/000000028723.pdf]


"Creating Analog Behavioral Models VERILOG-AMS ANALOG MODELING" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/CDN_Creating_Analog_Behavioral_Models.pdf]

Rainer Findenig, Infineon Technologies. "Behavioral Modeling for SoC Simulation Bridging Analog and Firmware Demands" [https://www.coseda-tech.com/files/Files/Dokumente/Behavioral_Modeling_for_SoC_Simulation_COSEDA_UGM_2018.pdf]


CC Chen. Why Efficient SPICE Simulation Techniques for BB CDR Verification? [https://youtu.be/Z54MV9nuGUI]


T. Wen and T. Kwasniewski, "Phase Noise Simulation and Modeling of ADPLL by SystemVerilog," 2008 IEEE International Behavioral Modeling and Simulation Workshop, San Jose, CA, USA, 2008 [slides, paper]


Jaeha Kim,Scientific Analog. UCIe PHY Modeling and Simulation with XMODEL [pdf]

bandwidth - Rules of Thumb

NRZ Bandwidth

Maxim Integrated,NRZ Bandwidth - HF Cutoff vs. SNR [https://pdfserv.maximintegrated.com/en/an/AN870.pdf]

image-20240607221359970

\(0.35/T_r\)

image-20250930165629384


32 to 56 Gbps Serial Link Analysis and Optimization Methods for Pathological Channels [https://docs.keysight.com/eesofapps/files/678068240/678068273/1/1629077956000/tutorial-32-to-56-gbps-serial-link-analysis-optimization-methods-pathological-channels.pdf]

image-20250930165251231

Rise Time Sine Wave \[\begin{align} \sin 2\pi f t_{20} &= -1+2\times 0.2 = -0.6 \\ \sin 2\pi f t_{80} &= -1+2\times 0.8 = 0.6 \end{align}\] \[ f = \frac{\arcsin(0.6) - \arcsin(-0.6)}{2\pi (t_{80} - t_{20})} = \frac{0.2}{T_r} \]

Step Response RC Tank

\[\begin{align} 0.8 &= 1- e^{-\frac{t_{80}}{\tau_{RC}}} \to t_{80} = -\ln0.2 \cdot \tau_{RC} \\ 0.2 &= 1- e^{-\frac{t_{80}}{\tau_{RC}}} \to t_{20} = -\ln0.8 \cdot \tau_{RC} \end{align}\]

Then rise time of 20% to 80% is \[ T_{r} = \tau_{RC}\cdot \ln\frac{0.8}{0.2} = 1.3863 \cdot \tau_{RC} \] we have \[ f_{3dB} = \frac{1}{2\pi}\frac{1}{\tau_{RC}} = \frac{1}{2\pi}\frac{ 1.3863}{T_r} = \frac{0.22}{T_r} \]

\(0.5/T_r\)

TODO ๐Ÿ“…

CMI & DMI

Ahmed Sada Staff Silicon Validation Engineer, Synopsys. Don't Be Intimidated: Manual Calibration for Stressed Eye Testing

Patrick Kennedy, Impact of Noise Coupler on 128 GT/s Rx Calibration and DUT Testing

Anritsu White paper: PCIeยฎ 6.0: Testing for a New Generation [link]

sinusoidal differential mode interference (DMI), and common mode interference (CMI)

image-20250904225444111

image-20250904223855075


image-20250904204007383

Single-Ended & Differential Signaling

[https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/handouts/markChapt.pdf]

image-20250817110423246

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[https://www.allaboutcircuits.com/technical-articles/the-why-and-how-of-differential-signaling/]

image-20250817110059363

Since we have (ideally) no return current, the ground reference becomes less important. The ground potential can even be different at the sender and receiver or moving around within a certain acceptable range. However, you need to be careful because DC-coupled differential signaling (such as USB, RS-485, CAN) generally requires a shared ground potential to ensure that the signals stay within the interface's maximum and minimum allowable common-mode voltage.

Coupling noise & Crosstalk

High-speed Serial Interface Lect. 9 โ€“ Noise [http://tera.yonsei.ac.kr/class/2017_2_2/lecture/Lect%209%20Noise.pdf]

TODO ๐Ÿ“…

Clocking Structures

Synchronous, Mesochronous, Plesiochronous

image-20250815221238051

Cascaded PLLs

Chembiyan T, A General Theory of Cascaded PLL Design [link]

Nicola Da Dalt, ISSCC 2012 T5: JITTER basic and advanced concepts, statistics and applications [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T5.pdf]

โ€”. ESSCIRC 2019 Tutorials: Jitter in Wireline and Data Converter Applications [https://youtu.be/aapkfCeHTrQ]

To understand the impact of the clock jitter on the performance of a wireline system, the transfer functions of the PLL in the transmitter side and the CDR loop in the receiver should be taken into consideration

image-20250524111908032

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the minimum jitter occurs at the point where the transmit PLL UGB is minimum and the CDR UGB is maximized

  • the net rms jitter that impacts the performance of a wireline transceiver is much lower than the rms jitter of the transmit PLL
  • the jitter requirements of the transmit PLL on the wireline system is much more relaxed compared to the wireless transceiver

Low-Latency PCIe

TODO ๐Ÿ“…

AC-coupling vs DC-coupling

TODO ๐Ÿ“…

Nonlinear & Intermodulations

S. Stegemann, W. Mathis. MOS-AK 2012: Interference and Distortion Analysis for Nonlinear Analog Circuits [https://www.mos-ak.org/dresden_2012/publications/T8_Stegemann_MOS-AK_Desden_12.pdf]

Ali Sheikholeslami. A-SSCC 2024 insight: Noise and Distortion, [https://youtu.be/bvsJgHJ19jI?si=1CKDJvTy5EQdPLB4]

B. Razavi, "Design considerations for direct-conversion receivers," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]

image-20250924003304052

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Even-Order Distortion

Odd-order distortion: symmetry

Even-Order Distortion: non-symmetry (Effect of Mismatch)

image-20250613235048524


[http://cc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter_09_Nonlinearity%20and%20Mismatch.pdf]

image-20250613235212237

PAM4

image-20250607083851955

image-20240808205451067

image-20240808205635598

Eye-Diagram and Bit-Error-Ratio (BER)

image-20250607082220455

image-20250607082510464

Noman Hai, Synopsys. CICC 2025 Circuit Insights: Basics of Wireline Transmitter Circuits [https://youtu.be/oofViBGlrjM?si=WZnOqtDVG3iDnBHI]

JTOL btw DSP-based vs Analog PAM4 RX

image-20250525110540570

CC Chen, Why Analog PAM4 Receiver? [https://youtu.be/J2ojSMYiuBs?si=7y41W91ciIw_hme2]

challenges in DSP-based SerDes

image-20250524224829419

Parallel implementation

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Loop-Unrolling DFE

image-20250525105017605

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Corresponding to the three distinct voltage thresholds in the PAM4 systems, it would need 12 slicers, 3 multiplexers, and one thermometer-to-binary decoder in each deserialized data path, even if only one tap of the DFE is unrolled

Look-Ahead Multiplexing DFE

image-20250525151918214

The look-ahead multiplexing technique brings the key benefit that the timing constraint can be significantly relaxed, as the iteration bound is doubled at the expense of extra hardware

image-20250525192228275

Synopsys Italia, Tech Talk: Introduction to DSP-based SerDes [https://youtu.be/puEP0DlVZGI?si=lFiu1Kl4AKsg3O9f]

Chen, Kuan-Chang (2022) Energy-Efficient Receiver Design for High-Speed Interconnects. Dissertation (Ph.D.), California Institute of Technology. [https://thesis.library.caltech.edu/14318/9/chen_kuan-chang_2022_thesis_final.pdf]

Trellis Coding

TODO ๐Ÿ“…

Convolutional Code

TODO ๐Ÿ“…

Forward Error Correction (FEC)

It is called "forward" error correction because it can correct errors even in the common situations where there is no backward channel

image-20250527212624165

Keysight Technologies. Tutorial โ€“ Why Use Forward Error Correction (FEC) [https://youtu.be/56nF4c61KR0?si=jYJSH50q9M3pIvQt]

Paul McLellan, What the FEC is Forward Error Correction? [https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/fec]

Baseline Wander

TODO ๐Ÿ“…

Pete Anslow, Ciena. Baseline wander with FEC [https://www.ieee802.org/3/bs/public/17_05/anslow_3bs_03_0517.pdf]

Vladimir Dmitriev-Zdorov. Baseline Wander, its Time Domain and Statistical Analysis [https://ibis.org/summits/feb19/dmitriev-zdorov.pdf]

Pavel Zivny, Tektronix. Baseline Wander: Systematic Approach to Rapid Simulation and Measurement [pdf]

Update on Performance Studies of 100 Gigabit Ethernet Enabled by Advanced Modulation Formats [https://www.ieee802.org/3/bm/public/sep12/wei_01_0912_optx.pdf]

Sampling Front-End (SFE) Pulse Response

image-20250107234500537

sweep the setup time between ideal pulse input and clock, sample the output of SFE at falling edge

ISI & DDJ filtering

image-20250104183820308

Modulation and SNR

Data and noise mutually uncorrelated

\[ x_{RX,n}[p] = d[p]h_{RX}[0] +\sum \text{ISI} + n[p] \]

image-20250101105936807

image-20250101110902006

"ISI cancellation" based equalization is conceptually more straightforward but suffers from SNR penalty or error propagation

Jitter Amplification by Passive Channels

image-20250103215417021

Enhancing Resolution with a \(\Delta \Sigma\) Modulator

Sub-Resolution Time Averaging

image-20241103160332995

\(\Delta \Sigma\) modulator effectively dithers the LSB bit between zero and one, such that you can get the effective resolution of a much higher resolution DAC in the number of bits

Decimation

how they affect sampling phase

image-20241020140430663

DLF's input bit-width can be reduced by decimating BBPD's output. Decimation is typically performed by realizing either majority voting (MV) or boxcar filtering.

Note that deserialization is inherent to both MV and boxcar filtering

image-20241019225016868

  • Decimation is commonly employed to alleviate the high-speed requirement. However, decimation increases loop-latency which causes excessive dither jitter.
  • Decimation is basically, widen the data and slowing it down
  • Decimating by \(L\) means frequency register only added once every \(L\) UI, thus integral path gain reduced by \(L\) in linear model
  • proportional path gain is unchanged

intg_path_decim.drawio

CDR Linear Model

image-20220504101924272

condition:

Linear model of the CDR is used in a frequency lock condition and is approaching to achieve phase lock

Using this model, the power spectral density (PSD) of jitter in the recovered clock \(S_{out}(f)\) is \[ S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f) \] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they come from independent sources.

Jitter Transfer Function (JTF)

\[ H_T(s) = \frac{\varphi_{out}(s)}{\varphi_{in}(s)}|_{\varphi_{vco}=0}=\frac{K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}}{s^2+K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}} \]

Using below notation \[\begin{align} \omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\ \xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2} \end{align}\]

We can rewrite transfer function as follows \[ H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2} \]

The jitter transfer represents a low-pass filter whose magnitude is around 1 (0 dB) for low jitter frequencies and drops at 20 dB/decade for frequencies above \(\omega_n\)

image-20220504104202197

  • the recovered clock track the low-frequency jitter of the input data
  • the recovered clock DONT track the high-frequency jitter of the input data

The recovered clock does not suffer from high-frequency jitter even though the input signal may contain high-frequency jitter, which will limit the CDR tolerance to high-frequency jitter.

Jitter Peaking in Jitter Transfer Function

The peak, slightly larger than 1 (0dB) implies that jitter will be amplified at some frequencies in the CDR, producing a jitter amplitude in the recovered clock, and thus also in the recovered data, that is slightly larger than the jitter amplitude in the input data.

This is certainly undesirable, especially in applications such as repeaters.

image-20220504110722442

Jitter Generation

If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the recovered clock comes directly from the VCO jitter. The transfer function that relates the VCO jitter to the recovered clock jitter is known as jitter generation. \[ H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi \omega_n s+\omega_n^2} \] Jitter generation is high-pass filter with two zeros, at zero frequency, and two poles identical to those of the jitter transfer function

image-20220504110737718

Jitter Tolerance (JTOL)

To quantify jitter tolerance, we often apply a sinusoidal jitter of a fixed frequency to the CDR input data and observe the BER of the CDR

The jitter tolerance curve DONT capture a CDR's true tolerance to random jitter. Because we are applying "sinusoidal" jitter, which is deterministic signal.

We can deal only with the jitter's amplitude and frequency instead of the PSD of the jitter thanks to deterministic sinusoidal jitter signal. \[ JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad \text{for a fixed BER} \] Where the subscript \(\text{pp-max}\) indicates the maximum peak-to-peak amplitude. We can further expand this equation as follows \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot |\varphi_e(f)|_\text{pp-max} \] image-20250627204121289

Relative jitter, \(\varphi_e\) must be less than 1UIpp for error-free operation

In an ideal CDR, the maximum peak-to-peak amplitude of \(|\varphi_e(f)|\) is 1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)

Accordingly, jitter tolerance can be expressed in terms of the number of UIs as \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad \text{[UI]} \] Given the linear CDR model, we can write \[ JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad \text{[UI]} \] Expand \(H_{LF}(f)\) for the CDR, we can write \[ JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) - \left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]} \] At frequencies far below and above the natural frequency, the jitter tolerance can be approximated by the following \[ JTOL(f) = \left\{ \begin{array}{cl} \left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\ 1 & : \ f\gg f_n \end{array} \right. \]

the jitter tolerance at very high jitter frequencies is limited to 1UIpp

image-20250627212710868

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clc;
clear all;

f_fn = logspace(-1, 2, 60);
for xi = [2, 1, 0.5, 0.2]
jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2);
loglog(f_fn, jtol,LineWidth=2)
disp(["min(JTpp)=", min(jtol),"@\xi=",xi])
hold on
end
grid on;
xlabel("f/f_n")
ylabel('JT_{pp}')
legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')

CC Chen, Circuit Images: Why JTOL in a CDR? [https://youtu.be/kZExm9wy0G8?si=5ULT0t_oHNkp7c2v]

โ€”. Why Pseudo-JTOL in a CDR Design or Verification? [https://youtu.be/DZyzLhk59aY?si=xMcN2Xo3hnCeL3RX]

image-20250627202659095

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OJTF

Concepts of JTF and OJTF

Simplified Block Diagram of a Clock-Recovery PLL pll_block_diagram

Jitter Transfer Function (JTF)

  • Input Signal Versus Recovered Clock
  • JTF, by jitter frequency, compares how much input signal jitter is transferred to the output of a clock-recovery's PLL (recovered clock)
    • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter that is faithfully transferred (closed-loop gain) to the clock recovery PLL's output signal. JTF in this situation is approximately 1.
    • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in decreasing jitter (open-loop gain) on the clock recovery PLL's output, because the jitter is filtered out and no longer reaches the PLL's VCO

Observed Jitter Transfer Function

  • Input Signal Versus Sampled Signal
  • OJTF compares how much input signal jitter is transferred to the output of a receiver's decision making circuit as effected by a clock recovery's PLL. As the recovered clock is the reference for detecting the input signal
    • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter on the recovered clock which reduces the amount of jitter that can be detected. The input signal and clock signal are closer in phase
    • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in reduced jitter on the recovered clock which increases the amount of jitter that can be detected. The input signal and clock signal are more out of phase. Jitter that is on both the input and clock signals can not detected or is reduced

JTF and OJTF for 1st Order PLLs

jsa_1st_order_graph

neuhelium-jtf-ojtf

The observed jitter is a complement to the PLL jitter transfer response OJTF=1-JTF (Phase matters!)

OTJF gives the amount of jitter which is tracked and therefore not observed at the output of the CDR as a function of the jitter rate applied to the input.

A-jtf-ojtf

Jitter Measurement

\[ J_{\text{measured}} = JTF_{\text{DUT}} \cdot OJTF_{\text{instrument}} \]

The combination of the OJTF of a jitter measurement device and the JTF of the clock generator under test gives the measured jitter as a function of frequency.

image-20220716094732273

For example, a clock generator with a type 1, 1st order PLL measured with a jitter measurement device employing a golden PLL is \[ J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2} \]

Accurate measurement of the clock JTF requires that the OJTF cutoff of the jitter measurement be significantly below that of the clock JTF and that the measurement is compensated for the instrument's OJTF.

The overall response is a band pass filter because the clock JTF is low pass and the jitter measurement device OJTF is high pass.

The compensation for the instrument OJTF is performed by measuring the jitter of the reference clock at each jitter rate being tested and comparing the reference jitter with the jitter measured at the output of the DUT.

jtf-ojtf

The lower the cutoff frequency of the jitter measurement device the better the accuracy of the measurement will be.

The cutoff frequency is limited by several factors including the phase noise of the DUT and measurement time.

Digital Sampling Oscilloscope

How to analyze jitter:

  • TIE (Time Interval Error) track
  • histogram
  • FFT

TIE track provides a direct view of how the phase of the clock evolves over time.

histogram provides valuable information about the long term variations in the timing.

FFT allows jitter at specific rates to be measured down to the femto-second range.

Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop bandwidth minimizes the response error

reference

Dalt, Nicola Da and Ali Sheikholeslami. โ€œUnderstanding Jitter and Phase Noise: A Circuits and Systems Perspective.โ€ (2018).

neuhelium, ๆŠ–ๅŠจใ€็œผๅ›พๅ’Œ้ซ˜้€Ÿๆ•ฐๅญ—้“พ่ทฏๅˆ†ๆžๅŸบ็ก€ URL: http://www.neuhelium.com/ueditor/net/upload/file/20200826/DSOS254A/03.pdf

Keysight JTF & OJTF Concepts, https://rfmw.em.keysight.com/DigitalPhotonics/flexdca/FlexPLL-UG/Content/Topics/Quick-Start/jtf-pll-theory.htm?TocPath=Quick%20Start%7C_____4

Complementary Transmitter and Receiver Jitter Test Methodlogy, URL: https://www.ieee802.org/3/bm/public/mar14/ghiasi_01_0314_optx.pdf

SerDesDesign.com CDR_BangBang_Model URL: https://www.serdesdesign.com/home/web_documents/models/CDR_BangBang_Model.pdf

M. Schnecker, Jitter Transfer Measurement in Clock Circuits, LeCroy Corporation, DesignCon 2009. URL: http://cdn.teledynelecroy.com/files/whitepapers/designcon2009_lecroy_jitter_transfer_measurement_in_clock_circuits.pdf

VCO model

TODO ๐Ÿ“…

respone to vctrl focus on phase

[https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va]

ADC Spec

TODO ๐Ÿ“…

ENOB - Not sufficient & not accurate enough

  • Based on SNDR
  • Assume unbounded Gaussian distribution

quantization noise is ~ bounded uniform distribution

Using unbounded Gaussian -> pessimistic BER prediction

AFE Nonlinearity

"total harmonic distortion" (THD) in AFE

Relative to NRZ-based systems, PAM4 transceivers require more stringent circuit linearity, equalizers which can implement multi-level inter-symbol interference (ISI) cancellation, and improved sensitivity

image-20240923204055369

Because if it compresses, it turns out you have to use a much more complicated feedback filter. As long as it behaves linearly, the feedback filter itself can remain a linear FIR

image-20240923211841053

Linearity can actually be a critical constraint in these signal paths, and you really want to stay as linear as you can all the way up until the point where you've canceled all of the ISI

image-20240923222650556

A. Roshan-Zamir, O. Elhadidy, H. -W. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sept. 2017 [https://people.engr.tamu.edu/spalermo/ecen689/2017_reconfigurable_16_32Gbps_NRZ_PAM4_SERDES_roshanzamir_jssc.pdf]

Hongtao Zhang, designcon2016. "PAM4 Signaling for 56G Serial Link Applications โˆ’ A Tutorial"[https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers"

BER with Quantization Noise

image-20240804110522955

\[ \text{Var}(X) = E[X^2] - E[X]^2 \]

image-20240804110235178

Impulse Response or Pulse Response

image-20240807221637401

image-20240807224407213image-20240807224505987

TX FFE

TX FFE suffers from the peak power constraint, which in effect attenuates the average power of the outgoing signal - the low-frequency signal content has been attenuated down to the high-frequency level

image-20240727225120002

[https://www.signalintegrityjournal.com/articles/1228-feedforward-equalizer-location-study-for-high-speed-serial-systems]

S. Palermo, "CMOS Nanoelectronics Analog and RF VLSI Circuits," Chapter 9: High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems, McGraw-Hill, 2011.

Eye-Opening Monitor (EOM)

An architecture that evaluates the received signal quality

data slicers, phase slicers, error slicers, scope slicers

image-20240922143125270

image-20240922144605196

Analui, Behnam & Rylyakov, Alexander & Rylov, Sergey & Meghelli, Mounir & Hajimiri, Ali. (2006). A 10-Gb/s two-dimensional eye-opening monitor in 0.13-??m standard CMOS. Solid-State Circuits, IEEE Journal of. 40. 2689 - 2699, [https://chic.caltech.edu/wp-content/uploads/2013/05/B-Analui_JSSC_10-Gbs_05.pdf]

reference

G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link Foundations Standards, Link Budgets & Models," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95 [https://youtu.be/OABG3u2H2J4?si=CxryBSGbxrUpZNBT] [https://picture.iczhiku.com/resource/ieee/SHKhwYfGotkIymBx.pdf]

Paul Muller Yusuf Leblebici ร‰cole Polytechnique Fรฉdรฉrale de Lausanne (EPFL). Pattern generator model for jitter-tolerance simulation; VHDL-AMS models

Anritsu Company, "Measuring Channel Operating Margin," 2016. [https://dl.cdn-anritsu.com/en-us/test-measurement/files/Technical-Notes/White-Paper/11410-00989A.pdf]

Kiran Gunnam, Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part I: Modeling," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 97-109, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10608184]

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part II: Optimization and Performance Assessment," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]

G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10184121]

loop dynamic

Hanumolu, Pavan Kumar. 2006. Design Techniques for Clocking High Performance Signaling Systems. : Oregon State University. https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]

Hae-Chang Lee, "An Estimation Approach To Clock And Data Recovery" [https://www-vlsi.stanford.edu/people/alum/pdf/0611_HaechangLee_Phase_Estimation.pdf]

R. Walker, โ€œDesigning Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,โ€ in Phase-Locking in High-Performance Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]

J. Kim, Design of CMOS Adaptive-Supply Serial Links, Ph.D. Thesis, Stanford University, December 2002. [https://www-vlsi.stanford.edu/people/alum/pdf/0212_Kim_______Design_Of_CMOS_AdaptiveSu.pdf]

P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps Digital Clock and Data Recovery Circuit," IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]

Da Dalt N. A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers. 2005;52(1):21โ€“31. [https://sci-hub.se/10.1109/TCSI.2004.840089]

Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop gain tracking all-digital PLL using autocorrelation of bangโ€“bang phase frequency detection. IEEE Transactions on Circuits and Systems II: Express Briefs. 2015;62(9):836โ€“840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]


ditheringjitter.drawio

image-20240925213924764

CDR Loop Latency

Denoting the CDR loop latency by \(\Delta T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The resulting right-half-plane zero, \(f_z\) degrades the phase margin and must remain about one decade beyond the BW \[ f_z\simeq \frac{1}{2\pi \Delta T} \]

This assumption is true in practice since the bandwidth of the CDR (few mega Hertz) is much smaller than the data rate (multi giga bits/second).

Fernando , Marvell Italy."Considerations for CDR Bandwidth Proposal" [https://www.ieee802.org/3/bs/public/16_03/debernardinis_3bs_01_0316.pdf]

Loop Bandwidth

The closed-loop โˆ’3-dB bandwidth is sometimes called the โ€œloop bandwidthโ€

Continuous-Time Approximation Limitations

A rule of thumb often used to ensure slow changes in the loop is to select the loop bandwidth approximately equal to one-tenth of the input frequency.

image-20240806230158367

image-20240928095850580

Gardner, F.M. (1980). Charge-Pump Phase-Lock Loops. IEEE Trans. Commun., 28, 1849-1858.

Homayoun, Aliakbar and Behzad Razavi. โ€œOn the Stability of Charge-Pump Phase-Locked Loops.โ€ IEEE Transactions on Circuits and Systems I: Regular Papers 63 (2016): 741-750.

N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021

Deog-Kyoon Jeong, Topics in IC Design - 2.1 Introduction to Phase-Locked Loop [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%202%20-%20Charge-Pump%20PLL%2C%20Freuqency%20Synthesizers%2C%20and%20SSCG.pdf]

Limit Cycle Oscillation

limit cycles imply self-sustained oscillators due nonlinear nature

Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]

Digital CDR Category

image-20241024221619909

  • DCO part is analogous so that it cannot be perfectly modeled
  • Digital-to-phase converter is well-defined phase output, thus, very good to model real situation

Z-domain modeling

image-20241027001226490

The difference equation is \[ \phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi \] z-transform is \[ \frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}} \]

where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)

\(\Delta \Sigma\)-dithering in DCO

Quantization noise

image-20241019200102827

Here, \(\alpha_T\) is data transition density

BBPD quantization noise

DAC quantization noise

M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]

Time to Digital Converter (TDC)

Digital to Phase Converter (DPC)

IIR low pass filter

image-20241024232055792

simple approximation: \[ z = 1 + sT \] bilinear-z transform \[ z =\frac{}{} \]

image-20241024232111368

FAQ

PLL vs. CDR

PLL CDR
Clock edge periodic Data edge random
Phase & Frequency detecting possible Phase detecting possible ,
Frequency detecting impossible

PLL or FD(Frequency Detector) for frequency detecting in CDR

reference

J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]

P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and Circuits" [slides]

Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery Circuits"

Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]

M. Perrott. 6.976 High Speed Communication Circuits and Systems (lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT OpenCourseWare, [lec21.pdf]

Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental Concepts To Future Trends" [T5.pdf]

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

โ€”, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

Fernando De Bernardinis, eSilicon. "Introduction to DSP Based Serial Links" [https://www.corsi.univr.it/documenti/OccorrenzaIns/matdid/matdid835215.pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]


H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10630516]

Marinaci, Stefano. "Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate" [https://cds.cern.ch/record/2870334/files/CERN-THESIS-2023-147.pdf]

P. Palestri et al., "Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25ฮผm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol. 41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]

M.H. Perrott. CICC 2009 "Tutorial on Digital Phase-Locked Loops" [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

โ€”, Short Course On Phase-Locked Loops and Their Applications Day 4, PM Lecture "Examples of Leveraging Digital Techniques in PLLs" [https://www.cppsim.com/PLL_Lectures/day4_pm.pdf]

โ€”, Short Course On Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA "Digital Frequency Synthesizers" [https://www.cppsim.com/PLL_Lectures/digital_pll.pdf]

Gain Kim, "Equalization, Architecture, and Circuit Design for High-Speed Serial Link Receiver" [pdf]


Deog-Kyoon Jeong Topics in IC(Wireline Transceiver Design) - 3.1. Introduction to All Digital PLL [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

โ€”, Topics in IC(Wireline Transceiver Design) - 6.1 Introduction to Clock and Data Recovery [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

High-speed Serial Interface Lect. 16 โ€“ Clock and Data Recovery 3 [http://tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect16_CDR-3.pdf]

Shiva Kiran. Phd thesis 2018. Modeling and Design of Architectures for High-Speed ADC-Based Serial Links [https://hdl.handle.net/1969.1/192031]

โ€”, et al., "Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 3, pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]

K. Zheng, "System-Driven Circuit Design for ADC-Based Wireline Data Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]

S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo, "Statistical modeling of metastability in ADC-based serial I/O receivers," 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems [pdf]

John M. Cioffi. "Decoding Methods" [https://cioffi-group.stanford.edu/doc/book/chap7.pdf]

โ€”. "Equalization" [https://cioffi-group.stanford.edu/doc/book/chap3.pdf]

Iain. [https://youtu.be/rnjy4_gXLAg?si=PC3aowaon-e_mhXX]

โ€”. [https://youtu.be/IJE94FhyygM?si=BMMQ-GmirBWNf4ep]

Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes [https://www.youtube.com/live/wHNOlxHFTzY?si=179HZozbtW59H8Lm]

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