we can get \(V_{i,n}^2 =
\frac{V_{i,sig}^2}{\text{SNR}}\), which is constant also
That is \[
V_{i,n}^2 = \frac{V_{i,sig}^2}{V_{o,sig}^2}V_{o,n}^2 =
\frac{V_{o,n}^2}{A_v^2}
\] where \(V_{i,sig}\) is
constant signal is applied to input of comparator
Transient Noise Method
Noise Fmax sets the bandwidth of the random noise
sources that are injected at each time point in the transient
analysis
We can identify the RMS noise value easily by looking at 15.9% or
84.1% of CDF (\(1\sigma\)), the
input-referred noise in the RMS is 0.9mV
Thus, if \(V_S\) is chosen so as to
reduce the probability of zeros to 16%, then \(V_S = 1\sigma\), which is also the total
root-mean square (rms) noise referred to the input.
Comparison of two methods
It seems that \(\sigma_\text{pnoise} =
\sqrt{2}\sigma_\text{trannoise}\), the factor \(\sqrt{2}\) is implicitly in formula in ADC
Rak of Cadence
E. Gillen, G. Panchanan, B. Lawton and D. O'Hare, "Comparison of
transient and PNOISE simulation techniques for the design of a dynamic
comparator," 2022 33rd Irish Signals and Systems Conference (ISSC),
Cork, Ireland, 2022, pp. 1-5
J. Conrad, J. Kauffman, S. Wilhelmstatter, R. Asthana, V. Belagiannis
and M. Ortmanns, "Confidence Estimation and Boosting for
Dynamic-Comparator Transient-Noise Analysis," 2024 22nd IEEE
Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada,
2024, pp. 1-5
If the input referred offset follows a normal distribution than it is sufficient to apply a single offset voltage to calculate the offset voltage. See details in Razavi, B., The StrongARM Latch [A Circuit for All Seasons], IEEE Solid-State Circuits Magazine, Volume:7, Issue: 2, Spring 2015
Omran, Hesham. (2019). Fast and accurate technique for comparator
offset voltage simulation. Microelectronics Journal. 89.
10.1016/j.mejo.2019.05.004.
Kickback noise trades with the dimensions of the input
transistors and hence with the offset voltage
affects the comparator's own decision
corrupts the input voltage while it is sensed by other circuits
Tetsuya Iizuka,VLSI2021_Workshop3 "Nyquist A/D Converter Design in
Four Days"
Figueiredo, Pedro & Vital, João. (2006). Kickback noise reduction
techniques for CMOS latched comparators. Circuits and Systems II:
Express Briefs, IEEE Transactions on. 53. 541 - 545.
10.1109/TCSII.2006.875308. [https://sci-hub.se/10.1109/TCSII.2006.875308]
P. M. Figueiredo and J. C. Vital, "Low kickback noise techniques for
CMOS latched comparators," 2004 IEEE International Symposium on Circuits
and Systems (ISCAS), Vancouver, BC, Canada, 2004, pp. I-537 [https://sci-hub.se/10.1109/ISCAS.2004.1328250]
If the comparator can not generate a well-defined logical output in
half of the clock period, we say the circuit is
"metastable"
Math Background
Relating \(\Phi\) and erf
Error Function (Erf) of the
standard Normal distribution \[
\text{Erf}(x) = \frac{2}{\sqrt{\pi}}\int_0^x e^{-t^2} \mathrm{d}t.
\]Cumulative Distribution Function
(CDF) of the standard Normal distribution \[
\Phi(x) = \frac{1}{\sqrt{2\pi}}\int_{-\infty}^x e^{-z^2/2} \mathrm{d}z.
\]
P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise
Analysis of Regenerative Comparators for Reconfigurable ADC
Architectures," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008 [https://picture.iczhiku.com/resource/eetop/SYirpPPPaAQzsNXn.pdf]
J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity
function analysis of periodic circuits," 2008 IEEE/ACM International
Conference on Computer-Aided Design, 2008, pp. 386-391, doi:
10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]
Y. Luo, A. Jain, J. Wagner and M. Ortmanns, "Input Referred
Comparator Noise in SAR ADCs," in IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 66, no. 5, pp. 718-722, May 2019. [https://sci-hub.se/10.1109/TCSII.2019.2909429]
X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating
Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55,
no. 4, pp. 1011-1022, April 2020 [https://sci-hub.se/10.1109/JSSC.2019.2960485]
C. Mangelsdorf, "Metastability: Deeply misunderstood [Shop Talk: What
You Didn’t Learn in School]," in IEEE Solid-State Circuits Magazine,
vol. 16, no. 2, pp. 8-15, Spring 2024
where \(H(j\omega)\), \(H(e^{j\hat{\omega}})\) is frequency
response of continuous-time systems and
discrete-time systems, which is the function of \(\omega\) and \(\hat{\omega}\)\[\begin{align}
H(j\omega) &= \int_{-\infty}^{+\infty}h(t)e^{-j\omega t}dt \\ \\
H(e^{j\hat{\omega}}) &=
\sum_{n=-\infty}^{+\infty}h[n]e^{-j\hat{\omega} n}
\end{align}\]
The frequency response of discrete-time LTI systems
is always a periodic function of the frequency variable
\(\hat{\omega}\) with period \(2\pi\)
Sampling Theorem
time-sampling theorem: applies to bandlimited
signals
spectral sampling theorem: applies to
timelimited signals
Aliasing
The frequencies \(f_{\text{sig}}\)
and \(Nf_s \pm f_{\text{sig}}\) (\(N\) integer), are
indistinguishable in the discrete time
domain.
Given below sequence \[
X[n] =A e^{j\omega T_s n}
\]
\[\begin{align}
A e^{j(\omega_s + \Delta \omega) T_s n} &= A e^{j(k\omega_s + \Delta
\omega) T_s n} \\
A e^{j(\omega_s - \Delta \omega) T_s n} &= A e^{j(k\omega_s - \Delta
\omega) T_s n}
\end{align}\]
CTFS & CTFT
Fourier transform of a periodic signal with Fourier series
coefficients \(\{a_k\}\) can be
interpreted as a train of impulses occurring at the
harmonically related frequencies and for which the area of the impulse
at the \(k\)th harmonic frequency \(k\omega_0\) is \(2\pi\) times the \(k\)th Fourier series coefficient \(a_k\)
inverse CTFT & inverse DTFT
time domain
frequency domain
inverse CTFT
\(\delta(t)\)
\(\int_{\infty}d\omega\)
inverse DTFT
\(\delta[n]\)
\(\int_{2\pi}d\hat{\omega}\)
inverse CTFT shall integral from \(-\infty\) to \(+\infty\) to obtain \(\delta(t)\) in time domain, e.g., \(x_s(t)\) impulse train
spectral sampling
spectral sampling by \(\omega_0\),
and \(\frac{2\pi}{\omega_0} \gt \tau\)\[
X_{n\omega_0}(\omega) =
\sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega - n\omega_0)
\] Periodic repetition of \(x(t)\) is \[
x_{n\omega_0}(t) = \frac{1}{\omega_0}\sum_{n=-\infty}^{\infty}x(t
-n\frac{2\pi}{\omega_0})=\frac{T_0}{2\pi}\sum_{n=-\infty}^{\infty}x(t
-nT_0)
\]
Then, if \(x_{T_0} (t)\), a periodic
signal formed by repeating \(x(t)\)
every \(T_0\) seconds (\(T_0 \gt \tau\)), its CTFT is \[
X_{T_0}(\omega) = \frac{2\pi}{T_0} \cdot X_{n\omega_0}(\omega) =
\frac{2\pi}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega -
n\omega_0)
\] Then \(x_{T_0} (t)\) can be
expressed with inverse CTFT as \[\begin{align}
x_{T_0} (t) &=
\frac{1}{2\pi}\int_{-\infty}^{\infty}X_{T_0}(\omega)e^{j\omega t}d\omega
\\
&= \frac{1}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)e^{jn\omega_0
t} =\sum_{n=-\infty}^{\infty}\frac{1}{T_0}X(n\omega_0)e^{jn\omega_0 t}
\end{align}\]
i.e. the coefficients of the Fourier series for \(x_{T_0} (t)\) is \(D_n =\frac{1}{T_0}X(n\omega_0)\)
alternative method by direct Fourier series
Why DFT ?
We can use DFT to compute DTFT samples and CTFT samples
\[
\overline{x}(t) = \sum_{n=0}^{N_0-1}x(nT)\delta(t-nT)
\] applying the Fourier transform yieds \[
\overline{X}(\omega) = \sum_{n=0}^{N_0-1}x[n]e^{-jn\omega T}
\] But \(\overline{X}(\omega)\),
the Fourier transform of \(\overline{x}(t)\) is \(X(\omega)/T\), assuming negligible
aliasing. Hence, \[
X(\omega) = T\overline{X}(\omega) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn\omega
T}
\] and \[
X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\omega_0 T}
\] with \(\hat{\omega}_0 = \omega_0
T\)\[
X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\hat{\omega}_0}
\]i.e. the relationship between CTFT and DFT is \(X(k\omega_0) = T\cdot X[k]\), DFT is a tool
for computing the samples of CTFT
C/D
Sampling with a periodic impulse train, followed by conversion to a
discrete-time sequence
The periodic impulse train is \[
s(t) = \sum_{n=-\infty}^{\infty}\delta(t-nT)
\]\(x_s(t)\) can be expressed
as \[
x_s(t) = \sum_{n=-\infty}^{\infty}x_c(nT)\delta(t-nT)
\] i.e., the size (area) of the impulse at sample time
\(nT\) is equal to the value of the
continuous-time signal at that time.
\(x_s(t)\) is, in a sense, a
continuous-time signal (specifically, an impulse train)
samples of \(x_c(t)\) are represented by
finite numbers in \(x[n]\)
rather than as the areas of impulses, as with \(x_s(t)\)
Frequency-Domain
Representation of Sampling
The relationship between the Fourier transforms of the input and the
output of the impulse train modulator \[
X_s(j\omega) = \frac{1}{T}\sum_{k=-\infty}^{\infty}X_c(j(\omega
-k\omega_s))
\] where \(\omega_s\) is the
sampling frequency in radians/s
\(X(e^{j\hat{\omega}})\), the
discrete-time Fourier transform (DTFT) of the sequence \(x[n]\), in terms of \(X_s(j\omega)\) and \(X_c(j\omega)\)
\[\begin{align}
x_r[n] &= \frac{1}{2\pi} \int_{\infty}X_c(\omega) e^{j\omega T
n}d\omega \\
&= \frac{1}{2\pi} \int_{\infty} \pi[\delta(\omega - \omega_0) +
\delta(\omega + \omega_0)]e^{j\omega T n}d\omega \\
&= \frac{1}{2}(e^{j\omega_0 T n}+e^{-j\omega_0 T n}) \\
&= \cos(\hat{\omega}_0 n)
\end{align}\]
where \(\hat{\omega}_0 = \omega_0
T\)
D/C
zero padding
This option increases \(N_0\), the
number of samples of \(x(t)\), by
adding dummy samples of 0 value. This addition of dummy samples is known
as zero padding.
We should keep in mind that even if the fence were transparent, we
would see a reality distorted by aliasing.
Zero padding only allows us to look at more samples of that imperfect
reality
Gotcha
A remarkable fact of linear systems is that the complex
exponentials are eigenfunctions of a linear
system, as the system output to these inputs equals the input multiplied
by a constant factor.
Both amplitude and phase may change
but the frequency does not change
For an input \(x(t)\), we can
determine the output through the use of the convolution integral, so
that with \(x(t) = e^{st}\)\[\begin{align}
y(t) &= \int_{-\infty}^{+\infty}h(\tau)x(t-\tau)d\tau \\
&= \int_{-\infty}^{+\infty} h(\tau) e^{s(t-\tau)}d\tau \\
&= e^{st}\int_{-\infty}^{+\infty} h(\tau) e^{-s\tau}d\tau \\
&= e^{st}H(s)
\end{align}\]
Take the input signal to be a complex exponential of the form \(x(t)=Ae^{j\phi}e^{j\omega t}\)
The real cosine signal is actually composed of two
complex exponential signals: one with positive
frequency and the other with negative \[
cos(\omega t + \phi) = \frac{e^{j(\omega t + \phi)} + e^{-j(\omega t +
\phi)}}{2}
\]
The sinusoidal response is the sum of the complex-exponential
response at the positive frequency \(\omega\) and the response at the
corresponding negative frequency \(-\omega\) because of LTI systems's
superposition property
input: \[\begin{align}
x(t) &= A cos(\omega t + \phi) \\
&= \frac{1}{2}Ae^{\phi}e^{\omega t} +
\frac{1}{2}Ae^{-\phi}e^{-\omega t}
\end{align}\]
It divides the process into several comparison stages, the number of
which is proportional to the number of bits
Due to the pipeline structure of both analog and digital signal path,
inter-stage residue amplification is needed which
consumes considerable power and limits high speed operation
It also divides a full conversion into several comparison stages in a
way similar to the pipeline ADC, except the algorithm is
executed sequentially rather than in parallel
as in the pipeline case.
However, the sequential operation of the SA algorithm has
traditionally been a limitation in achieving high-speed
operation
a clock running at least \((N + 1) \cdot
F_s\) is required for an \(N\)-bit converter with conversion rate of
\(F_s\)
every clock cycle has to tolerate the worst case comparison
time
every clock cycle requires margin for the clock jitter
The power and speed limitations of a synchronous SA design comes
largely from the high-speed internal clock
For overlapped search ranges, a less than radix-2
(sub-binary) search is needed. Essentially, a sub-binary
search takes more than \(N\) steps to convert an
analog input into a \(N\)-bit digital output
Krämer, M. et al. (2015) High-resolution SAR A/D converters with
loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].
Asynchronous processing
a global clock running at the sample rate is still used for an
uniform sampling
The concept of asynchronous processing is to trigger the internal
comparison from MSB to LSB like dominoes.
The maximum resolving time reduction between synchronous and
asynchronous case is two fold
reference
S. -W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW
Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006
Pieter Harpe, ISSCC 2016 Tutorial: "Basics of SAR ADCs Circuits &
Architectures"
C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit
50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in
IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp.
731-740, April 2010 [https://sci-hub.se/10.1109/JSSC.2010.2042254]
Single-Pole Filter and Complex Conjugate Pole pair in Event-Driven
PWL model
Real number modeling of analog circuits in hardware
description languages (HDLs) has become more common as a part of
mixed-signal SoC validation. Piecewise linear (PWL)
waveform approximation represent analog signals and dynamically
schedule the events for approximating the signal waveform to
PWL segments with a well controlled error bound.
Definition of a piecewise liner (PWL) waveform using struct in
Systemverilog
1 2 3 4 5
typedefstruct { real y; // signal offset real slope; // signal slope real t0; // time offset } pwl; // pwl datatype
When to update piecewise
model
model parameter update once new input come in
error is greater than user-define tolerance \(e_{tol}\), trigger by \(\Delta T\)
Dynamic Time Step Control
When approximating a function \(y(t)\) to a piecewise linear
segment for the interval \(t_0 \le
t_0 + \Delta t\), the approximation error \(err\) is bounded by \[
\left| err \right| \le \frac{1}{8}\cdot \Delta t^2 \cdot \max(\left|
\ddot{y(t)} \right|)
\] Using Rolle's theorem for the interval \(t_0 \le t_0 + \Delta t\), the needed time
step \(\Delta t\) is givend by \[
\Delta t(t=t_0) = \sqrt{\frac{8\cdot e_{tol}}{\max(\left| \ddot{y(t)}
\right|)}}
\]
Single-Pole Filter Model
The ramp input \(X(s)\), the single pole system Laplace
s-domain \(H(s)\) and the output
response \(Y(s)\), \[\begin{align}
X(s) &= \frac{a}{s} +\frac{b}{s^2} \\
H(s) &= \frac{Y(s)}{X(s)} = \frac{1}{1+\frac{s}{\omega_{1}}} \\
Y(s) &= X(s) \cdot H(s)
\end{align}\]
Time domain of ramp input shown as below \[
x(t) = a +b \cdot t
\]
The output transfer function \[\begin{align}
Y(s) &= X(s) \cdot H(s) \\
&= \frac{\omega_1}{\omega_1+s}\cdot X
\end{align}\]
step-1 transfer function in Laplace s-domain, which
don't initial conditon and is only steady response.
step-2 differential equation
step-3 Laplace transform of \(Y(s)\), (the initial conditon of input
\(X(s)\) is zero, that of \(Y(s)\) is explicit)
step-4 inverse Laplace transform, with the help of Laplace transform
table or matlab syms and ilaplace function
\(y(t)\) has a continuous second
derivative \(\ddot{y(t)}\)\[
\ddot{y(t)} =(-a+\frac{b}{\omega_1}+y_0)\cdot \omega_1^2\cdot
e^{-\omega_1t}
\] It's obvious \(\left| \ddot{y(t)}
\right|\) is a decaying function and thus the maximum value is
\(\left| \ddot{y(t_0)} \right|\) for
the interval \(t_0 \le t_0 + \Delta
t\). The time step \(\Delta t\)
for the error tolerance \(e_{tol}\):
\[
\Delta t(t=t_0) = \sqrt{\frac{8\cdot e_{tol}}{\left| \ddot{y(t_0)}
\right|}}
\]
where \(\omega_p\) and \(r\) are complex numbers, \(r=r_r+jr_i\), \(\omega_p=\omega_{pr}+j\omega_{pi}\)
Follow the procedure as above single pole \[
\frac{Y(s)}{X(s)} = \frac{s\cdot r_{cs}+e}{s^2+s\cdot \omega_{p\_cs}+f}
\] where \(r_{cs}=r+r^*\), \(\omega_{p\_cs}=\omega_p+\omega_p^*\) and
\(e=r\omega_p^*+r^*\omega_p\), \(f=\omega_p\omega_p^*\) implies \[
s^2Y(s)+s\omega_{p\_cs}Y(s)+fY(s)=(s\cdot r_{cs}+e)X(s)
\] or a differential equation \[
\frac{d^2y(t)}{dt^2}+\omega_{p\_cs}\frac{dy(t)}{dt}+fy(t)=r_{cs}\frac{dx(t)}{dt}+e\cdot
x(t)
\] Taking Laplace transform with initial conditions \(y_0\), \(\dot{y_0}\) and \(x_0=0\), \[
s^2-sy_0-\dot{y_0}+\omega_{p\_cs}(sY(s)-y_0)+f\cdot y(t) = r_{cs}\cdot
(sX(s)-0)+e\cdot X(s)
\] Solving for \(Y(s)\)\[
Y(s)=\frac{s\cdot
y_0+\dot{y_0}+\omega_{p\_cs}y_0}{s^2+s\cdot{\omega_{p\_cs}}+f}+\frac{s\cdot{r_{cs}}+e}{s^2+s\cdot{\omega_{p\_cs}}+f}X(s)
\] With an ramp input, height \(a\), slope \(b\), i.e. \(X(s)=\frac{a}{s}+\frac{b}{s^2}\)\[
Y(s)=\frac{s\cdot
y_0+\dot{y_0}+\omega_{p\_cs}y_0}{s^2+s\cdot{\omega_{p\_cs}}+f}+\frac{s\cdot{r_{cs}}+e}{s^2+s\cdot{\omega_{p\_cs}}+f}(\frac{a}{s}+\frac{b}{s^2})
\] After inverse Laplace transform, we can get total response
\[
y(t)=e^{-\omega_{pr}t}\cdot \left[ y_0\cdot
\cos(\omega_{pi}t)+\frac{\dot{y_0}+y_0\omega_{pr}}{\omega_{pi}}\sin(\omega_{pi}t)+D\cdot
\cos(\omega_{pi}t)+\frac{C-D\cdot{\omega_{pr}}}{\omega_{pi}}\sin(\omega_{pi}t)
\right]+B+A\cdot{t}
\] where \[\begin{align}
A &= \frac{e\cdot{b}}{f} \\
B &= \frac{r_{cs}\cdot{b}+a\cdot{e}-A\cdot{\omega_{p\_{cs}}}}{f} \\
C &= a\cdot{r_{cs}}-A-B\cdot{\omega_{p\_cs}} \\
D &= -B
\end{align}\]
As a double check, note that at \(t=0\), \[
y(0)=\left[ y_0 + D \right]+B=y_0
\]
To derive derivative, we first assume \[
y_0\cdot
\cos(\omega_{pi}t)+\frac{\dot{y_0}+y_0\omega_{pr}}{\omega_{pi}}\sin(\omega_{pi}t)+D\cdot
\cos(\omega_{pi}t)+\frac{C-D\cdot{\omega_{pr}}}{\omega_{pi}}\sin(\omega_{pi}t)
= \alpha \cdot{\cos(\omega_{pi}t+\phi)}
\] The above equation implies \[\begin{align}
y_0+D &= \alpha\cdot{\cos(\phi)} \\
\frac{\dot{y_0}+y_0\omega_{pr}}{\omega_{pi}}+\frac{C-D\cdot{\omega_{pr}}}{\omega_{pi}}
&= -\alpha\cdot{\sin(\phi)}
\end{align}\] Then \[
\alpha^2=(y_0+D)^2+\left(\frac{\dot{y_0}+y_0\omega_{pr}}{\omega_{pi}}+\frac{C-D\cdot{\omega_{pr}}}{\omega_{pi}}
\right)^2
\] And \(\alpha\) can be used to
estimate time step size. The total response is \[
y(t)=e^{-\omega_{pr}t}\cdot \alpha
\cdot{\cos(\omega_{pi}t+\phi)}+B+A\cdot{t}
\] It's second derivative is \[
\ddot{y(t)} = \alpha\left[
(\omega_{pr}^2-\omega_{pi}^2)e^{-\omega_{pr}t}\cos(\omega_{pi}t+\phi)+2\cdot
\omega_{pr}\omega_{pi}e^{-\omega_{pr}t}\sin(\omega_{pi}t+\phi) \right]
\] Absolute value \[
\left| \ddot{y(t)} \right| = \left| \alpha \right| \left|
(\omega_{pr}^2-\omega_{pi}^2)e^{-\omega_{pr}t}\cos(\omega_{pi}t+\phi)+2\cdot
\omega_{pr}\omega_{pi}e^{-\omega_{pr}t}\sin(\omega_{pi}t+\phi) \right|
\] Define new function \(g_0(t)\)\[
g_0(t) = \left| \alpha \right| \left|
(\omega_{pr}^2-\omega_{pi}^2)e^{-\omega_{pr}t}\cos(\omega_{pi}t+\phi)
\right|+2\cdot |\alpha| \left|
\omega_{pr}\omega_{pi}e^{-\omega_{pr}t}\sin(\omega_{pi}t+\phi) \right|
\] another new funtion \(g_1(t)\), by equating \(\sin(\omega_{pi}t+\phi)\) and \(\cos(\omega_{pi}t+\phi)\) to one \[
g_1(t) = \left| \alpha \right| \left|
(\omega_{pr}^2-\omega_{pi}^2)e^{-\omega_{pr}t} \right|+2\cdot |\alpha|
\left| \omega_{pr}\omega_{pi}e^{-\omega_{pr}t} \right|
\]
By triangular inequality, \(g_0(t)\)
is the upper bound of \(\left| \ddot{y(t)}
\right|\), and \(g_1(t)\) is the
upper bound of \(g_0(t)\)
Because \(g_1(t)\) is a decaying
exponential function, Therefore, a conservative time step can be
obtained, for inteval \(t_0 \le t_0 + \Delta
t\), \[
\Delta t(t=t_0) = \sqrt{\frac{8\cdot e_{tol}}{\left| g_1(t_0) \right|}}
\]
My colleague, Zhang Wenpian help me a lot in understanding this
modeling method. Lots of content here are copied from Zhang's note.
Reference
B. C. Lim and M. Horowitz, "Error Control and Limit Cycle Elimination
in Event-Driven Piecewise Linear Analog Functional Models," in IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1,
pp. 23-33, Jan. 2016, doi: 10.1109/TCSI.2015.2512699.
S. Liao and M. Horowitz, "A Verilog piecewise-linear analog behavior
model for mixed-signal validation," Proceedings of the IEEE 2013 Custom
Integrated Circuits Conference, 2013, pp. 1-5, doi:
10.1109/CICC.2013.6658461.
DaVE - tools regarding on analog modeling,validation, and generation,
https://github.com/StanfordVLSI/DaVE](https://github.com/StanfordVLSI/DaVE)
B. C. Lim, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital
Analog Design: Enabling Mixed-Signal System Validation," in IEEE
Design & Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
The difference between the lowest and highest levels is
called the full-scale (FS) of the quantizer
Bootstrapped Switch
A. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to
Digital Converter," IEEE J. Solid-State Circuits, pp. 599, May 1999 [https://sci-hub.se/10.1109/4.760369]
Dessouky and Kaiser, "Input switch configuration suitable for
rail-to-rail operation of switched opamp circuits," Electronics Letters,
Jan. 1999. [https://sci-hub.se/10.1049/EL:19990028]
Quantization noise is less with higher resolution as the input range
is divided into a greater number of smaller ranges
This error can be considered a quantization noise with
RMS
ENOB & SQNR
The quantization noise power \(P_Q\)
for a uniform quantizer with step size \(\Delta\) is given by \[
P_Q = \frac{\Delta ^2}{12}
\] For a full-scale sinusoidal input signal with an amplitude
equal to \(V_{FS}/2\), the input signal
is given by \(x(t) =
\frac{V_{FS}}{2}\sin(\omega t)\)
Then input signal power \(P_s\) is
\[
P_s = \frac{V_{FS}^2}{8}
\] Therefore, the signal-to-quantization noise ratio
(SQNR) is given by \[
\text{SQNR} = \frac{P_s}{P_Q} =
\frac{V_{FS}^2/8}{\Delta^2/12}=\frac{V_{FS}^2/8}{V_{FS}^2/(12\times
2^{2N})} = \frac{3\times 2^{2N}}{2}
\] where \(N\) is the number of
quantization bits
When represented in dBs \[
\text{SQNR(dB)} = 10\log(\frac{P_s}{P_Q}) = 10\log(\frac{3\times
2^{2N}}{2})= 20N\log(2) + 10\log(\frac{3}{2})= 6.02N + 1.76
\]
Quantization is NOT Noise
ADC INL Testing
ADC DNL Testing
DAC DNL Testing
One difference between ADC and DAC is that DAC DNL can be less than
-1 LSB
In a DAC, DNL < -1LSB implies
non-monotinicity
Bottom plate sampling
Sample signal at the "grounded" side of the capacitor to
achieve signal independent sampling
P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE
International Solid-State Circuits Conference - Digest of Technical
Papers, San Francisco, CA, USA, 2008, pp. 544-634
B. Sedighi, A. T. Huynh and E. Skafidas, "A CMOS track-and-hold
circuit with beyond 30 GHz input bandwidth," 2012 19th IEEE
International Conference on Electronics, Circuits, and Systems (ICECS
2012), Seville, Spain, 2012, pp. 113-116
The charge redistribution capacitor network is used to
sample the input signal and serves as a digital-to-analog converter
(DAC) for creating and subtracting reference voltages
That make sense, charge redistribution consume
energy
Comparator input cap effect
\[
-V_{in}\cdot 2^N C = V_c (2^N C + C_p)
\] Then \(V_c = -\frac{2^N C}{2^N C +
C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude
by the factor
During conversion \[\begin{align}
V_c &= -\frac{2^N C}{2^N C + C_p}V_{in} +V_{ref}\sum_{n=0}^{N-1}
\frac{b_n\cdot2^n C}{2^N C + C_p} \\
&= \frac{2^N C}{2^N C + C_p}\left(-V_{in} +
V_{ref}\sum_{n=0}^{N-1}\frac{b_n }{2^{N-n}} \right)
\end{align}\]
That is, it does not change the sign
Comparator offset effect
Summing Interleaved Alias
The sampling function - impulse train is \[
s(t) = \sum_{n=-\infty}^{\infty}\left[ \delta(t-n4T_s) +
\delta(t-n4T_s-T_s) + \delta(t-n4T_s-2T_s) + \delta(t-n4T_s-3T_s)\right]
\]
By square-law, the Eq \(g_m = \sqrt{2\mu
C_{ox}\frac{W}{L}I_D}\), it is possible to obtain a
higer transconductance by increasing \(W\) while maintaining \(I_D\) constant. However, if \(W\) increases while \(I_D\) remains constant, then \(V_{GS} \to V_{TH}\) and device enters the
subthreshold region. \[
I_D = I_0\exp \frac{V_{GS}}{\xi V_T}
\]
where \(I_0\) is proportional to
\(W/L\), \(\xi \gt 1\) is a nonideality factor, and
\(V_T = kT/q\)
As a result, the transconductance in subthreshold region is \[
g_m = \frac{I_D}{\xi V_T}
\]
which is \(g_m \propto I_D\)
PTAT with subthreshold MOS
MOS working in the weak inversion region
("subthreshold conduction") have the similar
characteristics to BJTs and diodes, since the effect of diffusion
current becomes more significant than that of drift current
Hongprasit, Saweth, Worawat Sa-ngiamvibool and Apinan Aurasopon.
"Design of Bandgap Core and Startup Circuits for All CMOS Bandgap
Voltage Reference." Przegląd Elektrotechniczny (2012):
277-280.
VBE
temperature coefficient of \(V_{BE}\) itself depends on the
temperature,
temperature coefficient of the \(V_{BE}\) at a given temperature T depends
on the magnitude of \(V_{BE}\)
itself
\(\frac{kT}{q}\) is approximately
26mV, at room temperature 300K
In advanced node, N4P, \(V_{BE}\) is
about -1.45mV/K
constant-gm
aka. Beta-multiplier reference
\(I_\text{out}\) is
PTAT in case temperature coefficient of \(R_s\) is less than that of \(\mu_n\)
Body effect of M2
Boris Murmann, Systematic Design of Analog Circuits Using
Pre-Computed Lookup Tables
S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias
Circuits," in IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022
S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog
Integrated Circuits", IEEE International Symposium on Circuits and
Systems, ISCAS 2004, Vancouver , May 2004
Why MOS in saturation ?
\(g_m\), \(g_\text{ds}\) at fixed \(V_\text{GS}\)
\(g_{ds}\) is constant in saturation
region
in triode region \[
g_{ds} = \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS})
\]
Interestingly, \(g_m\) in the
saturation region is equal to the inverse of \(R_\text{on}\) in the deep triode
region.
\(g_m\), \(g_\text{ds}\) at fixed \(I_d\), \(V_G\)
In triode region\[
I_D =
\frac{1}{2}\mu_nC_{ox}\frac{W}{L}[2(V_{GS}-V_{TH})V_{DS}-V_{DS}^2]
\] where \(I_D\) and \(V_G\) is fixed
Then \(V_S\) can be expressed with
\(V_D\), that is \[
V_S = V_{GT} - \sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}
\] where \(V_{GT}=V_G-V_{TH}\),
\(V_{dsat}\) is \(V_{DS}\) saturation voltage \[
g_m =
\mu_nC_{ox}\frac{W}{L}\left(V_D-V_{GT}+\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}\right)
\] Then \[
\frac{\partial g_m}{\partial V_D} \propto 1 -
\frac{V_{GT}-V_D}{\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}} \gt 0
\]
We get \(I_{\Delta_{V_{TH}}}\simeq
1.71\%\) and \(I_{\Delta_{WL}} \simeq
1.73\%\)
Biasing
current source and global variation Monte Carlo
iwl: biased by mirror
iwl_ideal: biased by vdc source, whose
value is typical corner
For local variation, constant voltage bias
(vb_const in schematic) help reduce variation from \(\sqrt{2}\Delta V_{th}\) to \(\Delta V_{th}\)
For global variation, all device have same
variation, mirror help reduce variation by sharing same \(V_{gs}\)
global variation + local variation (All MC)
local variation (Mismatch MC)
global variation (Process MC)
We had better bias mos gate with mirror rather than the vdc
source while simulating sub-block.
This is real situation due to current source are always biased by
mirror and vdc biasing don't give the right result in global
variation Monte Carlo simulation (542.8n is too pessimistic,
13.07p is right result)
For any given constant values of u and v, the
constant values of variables that solve the the feed back relationship
are called the operating points, or equilibrium
points.
Operating points can be either stable or
unstable.
An operating point is unstable if any or some small perturbation near
it causes divergence away from that operating point.
If the loop gain evaluated at an operating point is less than
one, that operating point is stable.
This is a sufficient condition
With \(m_{1\to 2} = 1\)\[
\text{Loop Gain} \simeq \frac{V_{BN}-V_{T2}}{V_{BN}-V_{T2} + V_R}
\tag{LG\_0}
\] Assuming all MOS in strong inv operation, \(I\), \(V_{BN}\) and \(V_R\) is obtain \[\begin{align}
I &= \frac{2\beta _1 + 2\beta _2 - 4\sqrt{\beta _1 \beta
_2}}{R^2\beta _1 \beta _2} \\
V_{BN} &= V_{T2} + \frac{2}{R\beta _2}(1- \sqrt{\frac{\beta
_2}{\beta _1}}) \\
IR &= \frac{2}{R}\left( \frac{1}{\sqrt{\beta_2}}
- \frac{1}{\sqrt{\beta_1}} \right)
\end{align}\]
Substitute \(V_{BN}\) and \(V_R\) of \((LG\_0)\)\[\begin{align}
\text{Loop Gain} & \simeq
\frac{1-\sqrt{\frac{\beta_2}{\beta_1}}}{\frac{\beta_2}{\beta_1} -
3\sqrt{\frac{\beta_2}{\beta_1}}+2} \\
&= \frac{1}{2-\sqrt{\frac{\beta_2}{\beta_1}}} \tag{LG\_1}
\end{align}\]
then \[
\Delta I_1 = \frac{1}{2}(V_{a1} - V_{b1})(g_{m,a1}+g_{m,b1})
\] That is, \(g_{m,a1}+g_{m,b1} = \mu
C_{OX}\frac{W}{L}(V_{a1}+V_{b1} - 2V_{TH})\)
To minimize the difference between \(\Delta
I_1\) and \(\Delta I_0\), the
drift of both differential and common mode between \(V_a\) and \(V_b\) shall be alleviated
reference
B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog
Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3,
pp. 6-16, Summer 2021, doi: 10.1109/MSSC.2021.3088963
The Fourier transform of \(s(t)=x(t)x(t)\), and we know \[\begin{align}
S(j2n\omega_0) &= \frac{1}{2\pi}\int X(j(2n\omega_0
-\omega))X(j\omega) d\omega\\
&= \frac{1}{2\pi}\int X(j(\omega-2n\omega_0))X(j\omega) d\omega
\end{align}\]
spurs are carrier or clock frequency spectral
imperfections measured in the frequency domain just like phase noise.
However, unlike phase noise they are discrete frequency
components.
Spurs are deterministic.
Spur power is independent of bandwidth.
Spurs contribute bounded peak jitter in the time domain.
Sources of Spurs
External (coupling from other noisy block) Supply, substrate, bond
wires, etc.
Internal (int-N/fractional-N operation)
Frac spur: Fractional divider (multi-modulus and
frequency accumulation)
alias bk hiSetBindKey when ( isCallable('schGetEnv') bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")") bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")") bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")") bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()") bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)") ) unalias bk
leBindKeys.il
layout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
alias bk hiSetBindKey when ( isCallable('leGetEnv) bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" ) ; M1-VIA1-M2 bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" ) ; M2-VIA2-M3 bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" ) ; M3-VIA3-M4 bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" ) ; M4-VIA4-M5 ; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" ) ; all visiable bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" ) ) unalias bk
Design Variable in vpwlf
PWL File as Design Var? parameter in vpwlf cell
is convenient for sweep simulation or corner simulation, wherein there
are multiple pwl files .
The file path should be surrounded with
double-quotes to be protected from evaluation.
save option
none:
Does not save any data (currently does save one node chosen at
random)
selected:
Saves only signals specified with save statements. The default
setting.
lvlpub:
Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.
lvl:
Saves all signals up to nestlvl deep in the subcircuit hierarchy.
This option is relevant for subcircuits.
allpub:
Saves only signals that are normally useful.
all:
Saves all signals.
Signals that are "normally useful" include the shared node voltages
and currents through voltage sources and iprobes, and exclude the
internal nodes on devices (the internal collector, base, emitter on a
BJT, the internal drain, source on a FET, and so on). It also excludes
currents through inductors, controlled sources, transmission lines,
transformers, etc.
If you use lvl or all instead of
lvlpub or allpub, you will also get
internal node voltages and currents through other components that happen
to compute current.
Thus, using *pub excludes internal nodes on devices
(the internal collector, base, emitter on a BJT, the internal drain and
source on a FET, etc). It also excludes the currents through inductors,
controlled sources, transmission lines, transformers, etc.
nestlvl
This variable is used to save groups of signals as results and when
signals are saved in subcircuits. The nestlvl parameter also specifies
how many levels deep into the subcircuit hierarchy you want to save
signals.
virtuoso "dlopen failed
to open 'libdl.so'"
1
$ sudo yum install glibc-devel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST. Dependencies resolved. ========================================================================================================================================= Package Architecture Version Repository Size ========================================================================================================================================= Installing: glibc-devel x86_64 2.28-189.5.el8_6 baseos 78 k Installing dependencies: glibc-headers x86_64 2.28-189.5.el8_6 baseos 482 k kernel-headers x86_64 4.18.0-372.26.1.el8_6 baseos 9.4 M libxcrypt-devel x86_64 4.1.1-6.el8 baseos 24 k
* DSPF files to use with Corner Definitions * This is an example file showing how to define different dspf files for different corners * using model files for individual components as the * building blocks. simulator lang=spectre library dspf_files_corners
section rcworst_25 dspf_include "DSPF_RC_WORSE25.spf" end section rcworst_25
section rcworst_125 dspf_include "DSPF_RC_WORSE125.spf" end section rcworst_125
endlibrary dspf_files_corners
Add the file created above ‘myDSPF_File.scs’ in
‘Add/Edit Model Files’ of Corners setup form
split pins in dspf_emir
dspf extract using starrc
multiple label and rectangle in vssa net
general dspf
SHORT_PINS: YES
other pin are short together
dspf for emir analysis
It seems that dspf_emir don't contain the
rectangle pin information.
only label is necessary
setup
spectre result
netlist type
dspf option
emir analysis
dspf
/
disable
✓
dspf_emir
/
disable
✗
dspf_emir
=shortPins=”yes”
disable
✓
dspf_emir
=shortPins=”no”
disable
✗
dspf_emir
/
enable
✓
dspf_emir
=shortPins=”yes”
enable
✓
dspf_emir
=shortPins=”no”
enable
✓
shortPins=”yes” is preferred default option for
dspf_emir, which has split pins
DSPF Syntax
::=*|P ?
describes pins in the net. Multiple pin descriptions can be listed in
one line.
::=( {}?)
represents the name of the pin. represents the type
of the pin. It can be any of the following: I (Input), O (Output),
B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
represents the capacitance value associated with the pin.
is optional. It represents the location of the pin. Multiple pin
locations are allowed
split pins
1 2 3 4 5
*|P (avss_1 O 0 207.7555 59.9170) *|P (avss_10 O 0 181.1610 151.1130) *|P (avss_11 O 0 186.6330 151.1130) *|P (avss_12 O 0 192.1050 151.1130) *|P (avss_13 O 0 197.5770 151.1130)
StarRC User Guide and Command Reference Version O-2018.06, June
2018
DSPF Options
Case Sensitivity
netlist format
default option
Spectre netlist
case sensitive
dspf format
case insensitive
For a dspf format, it will be treated as a spice
netlist format, which is by default case insensitive
Pay attention to VerilogIn block, which may contain upper
case / lower case net name, e.g NET1 and net1.
The extracted DSPF using extraction tool also contain NET1 and net1,
which shall not be shorted together.
Port Order
If you use .dspf_include, the following rules apply:
The subcircuit description is taken from the DSPF file even if the
same subcircuit description is available in the schematic netlist.
Depending on the port_order option, the port order of
the subcircuit definition is taken from the pre-layout schematic netlist
or from the DSPF file subcircuit definition, as shown below.
port_order=sch – (Default). The port order is taken
from schematic subcircuit definition. The same port number and names are
required. If the schematic subcircuit definition is not available, a
warning is issued in the log file, and DSPF port order is used.
port_order=spf – The port order is taken from the DSPF
subcircuit definition.
SPICE_SUBCKT_FILE of StarRC
The StarRC tool reads the files specified by the
SPICE_SUBCKT_FILE command to obtain port ordering
information. The files control the port ordering of the top
cell as well. The port order and the port list members read from the
.subckt for a skip cell are preserved in the output
netlist.
The file usually is the cdl netlist of extracted cell, this
way, port order is not problem
CDF termOrder
DSPF same order
DSPF
input.scs
different order
manual change DSPF's pin order shown as below
port_order=sch
dspf port is mapping to schematic by name, and the
simulation result is right
port_order=spf
dspf pin order is retained, and no mapping between
spectre netlist and dspf.
The simulation result is wrong
bus_delim="_ <>"
The way this works is that the first part of bus_delim is
the "schematic" delimiter (i.e. what's in the spectre netlist), and the
other part is the DSPF delimiter
Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit
Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1
StarRC™ User Guide and Command Reference Version O-2018.06, June
2018
Virtual Connectivity
Normally, if the layout connectivity extractor finds disjoint,
unconnected geometries with the same net name text attached, the
extractor will view this as an open circuit.
Virtual connection results in the extraction of a single net from
two or more disjoint physical nets when the physical net segments share
the same name.
Virtual connectivity is triggered by the rule file VIRTUAL
CONNECT COLON and VIRTUAL CONNECT NAME
specification statements.
Virtual connectivity can also be specified through the Calibre
Interactive GUI.
VIRTUAL CONNECT COLON
Virtual Connect Colon is used to virtually connect
nets that share a common prefix before a colon, like
VDD:1, VDD:2, and so forth.
If you specify YES, then the connectivity extractor first
strips off all characters from the first colon to the end of
the label names.
Next, the extractor forms a virtual connection between any two labels
that have the same name and that originally contained a
colon.
Colons can appear anywhere in the name with the exception that a
colon at the beginning of a name is treated as a regular character (that
is, it has no special effect).
up to the first colon character encountered
The colon is discarded in the extracted net
name
VIRTUAL CONNECT NAME
Virtual Connect Name virtually connects nets that
share the same name
Each name is a net name and can be optionally enclosed in quotes.
The connectivity extractor forms a virtual connection between any two
labels having the same name such that the label name appears in a
Virtual Connect Name specification statement in the
rule file.
VIRTUAL CONNECT NAME ? == Connect all nets by name
Note that if Virtual Connect Colon YES is also
specified, then Virtual Connect Name operates on names
after all colon suffixes have been stripped off.
Calibre Verification User’s Manual Software Version 2019.3 Document
Revision 7
Calibre Runsets
Calibre Interactive stores a list of your most recently opened
runsets in your home directory as .cgidrcdb or
.cgilvsdb for Calibre Interactive DRC or LVS,
respectively.
When invoked, the Calibre DRC and LVS windows automatically load the
runset used when the last session was closed.
Runsets are ASCII files that set up Calibre Interactive for a Calibre
run. They contain only information that differs from the default
configuration of Calibre Interactive. There is a one-to-one
correspondence between entry lines in the runset file and fields and
button items in the Calibre Interactive user interface. Here is as
example of a DRC runset:
The runset filename opened at startup (if no runset is specified on
the command line) can also be specified by setting the
MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC,
and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable
for LVS. If these environment variables are set, they take precedence
over all other runset opening behavior options.
On the transient options form, there's a field called "infotimes" -
specify the times at which you want it to output the dc operating point
data. You can then annotate the "transient operating points" from any of
these times after the simulation, or access them via the results
browser.
Or you could get the operating point data to be continuously saved
during the transient for selected devices - if so, create a file called
(say) "save.scs" (make sure it has a ".scs" suffix), and put: save
M1:oppoint or save M*:oppoint sigtype=dev in this file, and then
reference the file via Setup->Model Libraries or as a "definition
file" on Setup->Simulation Files. With this approach you can then
find the operating point data for the selected devices in the results
browser and plot it versus time (be cautious of saving too much though
because this can generate a lot of data if you're not careful)
<divider> represents the hierarchical pathname
divider. The default hierarchical character is forward slash
(/).
*|DELIMITER <delimiter>
<delimiter> represents the delimiter character
used to concatenate an instance name and pin name to form an instance
pin name.
It is also represents the delimiter character used to concatenate a
net name and subnode number to form a subnode name. The default
character is colon (:)
*|BUSBIT <left_busbit_char><right_busbit_char>
<left_busbit_char> and
<right_busbit_char> are used at the end of an
identifier of an array to select a single object of the array.
Objects which may be indexed include nets, primary pins, and
instance pins
*|NET <netName> <netCap>
<netName> represents the name of a net. It can be
a user-provided net name, the name of the driving pin, or the name of
the driving instance pin.
<netCap> represents the total
capacitance value in farads associated with the net. This may be
comprised of capacitances to ground and capacitances to nearby
wires.
*|P <pinName> <pinType> <pinCap> {<coord>}
<pinName> represents the name of the pin.
<pinType> represents the type of the pin. It can
be any of the following: I (Input), O (Output), B (Bidirectional), X
(don’t care), S (Switch), and J (Jumper).
<pinCap> represents the capacitance value
associated with the pin.
<coord> is optional. It represents the location
of the pin. Multiple pin locations are allowed.
*|S <subNodeName> {<coord>}
subnodes in the net
<subNodeName> represents the name of the subnode.
A subnode name is obtained by concatenating the net name and a subnode
number using the delimiter specified in the DELIMITER statement. The
default delimiter is colon (:).
<instPinName> represents the name of the instance
pin. An instance pin name is obtained by concatenating the
<instName> and the <pinName> with
a delimiting character which is specified by the DELIMITER
statement
<instName> represents the name of the
instance
*|DeviceFingerDelim "@"
MOS finger delimiter
For example, M8's finger is 4, then split into 4 Devices
in DSPF
MM8, MM8@2, MM8@3,
MM8@4
its drain terminal will be
MM8:d, MM8@2:d, MM8@3:d,
MM8@4:d
DSPF Syntax
DSPF has two sections:
a net section
The net section consists of a series of net description blocks. Each
net description block corresponds to a net in the physical design. A net
description block begins with a net statement followed by pins, instance
pins, subnodes, and parasitic resistor/capacitor
(R/C) components that characterize the
electrical behavior of the net.
an instance section
The instance section consists of a series of SPICE instance
statements. SPICE instance statements begin with an
X.
Each file consists of hierarchical cells and interconnects only.
The DSPF format is as generic and as much like SPICE as possible.
While native SPICE statements describe the R/C sections, some non-native
SPICE statements complete the net descriptions. These non-native SPICE
statements start with the notation "*|" to differentiate them from
native SPICE statements. For native SPICE statements, a continuation
line begins with the conventional "+" sign in the first column.
The native SPICE statements used by the DSPF format are listed
below:
.SUBCKT represents a subcircuit statement.
.ENDS represents the end of a subcircuit
statement.
R represents a resistor element.
C represents a capacitor element.
E represents a voltage-controlled voltage sources
element.
X represents an instance of a cell;
* represents a comment line unless it is
*| or *+.
.END is an optional statement that represents the end
of a simulation session
spectre netlist
hier_delimiter="."
Used to set hierarchical delimiter. Length of
hier_delimiter should not be longer than 1, except the
leader escape character
This option maps the bus delimiter between schematic netlist and
parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus
delimiter in the schematic netlist, and optionally the bus delimiter in
the parasitic file. By default, the bus delimiter of the parasitic file
is taken from the parasitic file header (i.e. |BUSBIT [],
|BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not
defined in the parasitic file header, you need to specify it by using
the spfbusdelim option in schematic netlist.
Exampel
spfbusdelim=<> - A<1> in the schematic netlist is mapped
to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is
"_".
spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1]
in the DSPF file (the bus delimiter in DSPF header will be
ignored).
How to Save Net voltage in
DSPF
!!! follow the name of net section in DSPF - prepend to top-level
devices in the schematic with X
Assume node n1...n4 are named as below in DSPF file (prefix
X)
n1
XXosc/zip:1
n2
XXosc/zip:2
n3
XXosc/zip:3
n4
XXosc/zip:4
To save these nodes, you can add follow code in Definition
Files
saveopt.scs
1 2 3 4
save Xwrapper.Xvco.XXosc\/zip\:1 save Xwrapper.Xvco.XXosc\/zip\:2 save Xwrapper.Xvco.XXosc\/zip\:3 save Xwrapper.Xvco.XXosc\/zip\:4
Escape character \ is used for hierarchical pathname
divider / and subnode :
By the way, . is hierarchical delimiter of
Spectre
Calibre always prepend one X to instance name of
schematic in generated DSPF file
The DSPF design is flatten, the DIVIDER character
indicate the hierarchy
1
save Xwrapper.Xvco.XXosc\/zip
The above save voltage, however I'm NOT sure which node it save.
To avoid this unsure problem, the MOS terminal may be better choice
to save.
But keep in mind
OD resistance is lumped in the FEOL model
M0OD and above layer resistances are extracted by RC tool
How to Save Current in DSPF
!!! follow the name of instance section of DSPF - prepend to
top-level devices in the schematic with XX
MOS in schematic: Xsupply.M4
MOS related information in DSPF (prefix XX in instance
section):
1 2 3 4 5 6 7 8 9
... // net section *|I XXsupply/MM4:d XXsupply/MM4 d B 0.0
<instName> in
*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}
which has prefix X corresponding to schematic is
NOT the instance name in DSPF. The instance name is in
instance section and has prefix XX
!!! Only work for MOS terminal current. Fail to apply to block
pin
Thinking about voltage
and current save
MOS device always prepend with M
To save net voltage, take account of the prefix
X of top-level device
To save MOS terminal, take account of the prefix
XX of top-level device
Post-layout netlists are created by layout extraction tools - Mentor
Calibre
Differences
Between DSPF and Schematic Names
MOS Terminal Mismatch ( ‘s’ vs ‘1’)
Schematic: number '1' ,'2', '3','4'
DSPF: 'd', 'g', 's','b'
.simrc file
If DSPF files show such differences, you can set options in the
.simrc file to update the save statement in the
netlist so that the device names match with those in the DSPF
file
Additionally, dspf_include reads all the DSPF lines
starting with * (|NET, |I, *|P,*|S), while
include considers all related lines as comments.
Only verified to DSPF output of Mentor Calibre
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
; ensure that the netlist is recreated each time nlReNetlistAll=t
The net name is x1/x1:DRN. During the simulation, the following
warning is reported:
Warning from spectre during initial setup.
1 2
WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name. WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.
How can I save this net for plotting and measurements?
Solution
The colon (:) in the save statement specifies terminal
current. So, the save statement used above is for terminal
current and, hence, the warning messages are reported.
1
save xpi1.x1\/x1:DRN
You need to modify the save statement as below:
1
save xpi1.x1\/x1\:DRN
Now, run the simulation and the issue will be resolved.
DSPF r vs rcc
rcc
c
only c dspf give the lumped
capacitance
EMIR via Voltus-Fi
general terminology
DC related
Imax in T*'s DRC document is the maximum allowed
DC current, which depends on Length and Width
only
Iavg is the average value of the current, which is
the effective DC current. Therefore, Iavg
rules are identical to Imax
rules \[
I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau}
\] Similarly, Iabsavg rules are
identical to Imax rules, too \[
I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau}
\]
rms
Irms is the root-mean-square of the current through
a metal line, which depends w(in um), the drawn
width of the metal line and \(\Delta
T\), the temperature rise due to Joule heating. \[
I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2}
\]
peak current
Ipeak in T*'s DRC document is the current at which a
metal line undergoes excessive Joule heating and can begin to melt.
Ipeak is corresponding to
EM Current Analysis: max in Voltus-Fi Analysis Setup \[
I_{\text{peak}}=\max(|I(t)|)
\] The limit for the peak current is \[
I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r
} }
\] where r is the duty ratio
The relationship between Ipeak and
Ipeak_DC is merged in DRC document so that there is
only Ipeak equation in document
\(I_{\text{peak,limit}}\) depends on
\(t_D\), r, width and length
\[
r=\frac{t_D}{\tau}
\]
where \(t_D\) is equivalent duration
\[
t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}}
\] or \[
r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}}
\]
where the drawn width is 1um, r is 0.1
\[
9.37*(1-0.004)/\sqrt0.1 = 29.512
\]
acpeak/pwc
It's same with max EM Current Analysis in
Voltus-Fi
dynamicACPeak
This option affect how duty ratio r is computed in max
and acpeak/pwc EM current Analysis
When the dynamicACPeak variable is set to
true or multiPeak\[
r=\frac{T_d}{T_{\text{total}}}
\]
where \(T_{\text{total}} = \text{EMIR time
window}\)
\(T_d\) = the time duration in
microsecond of the total "On Time" period based on IPWC
Pulse-Wise Constant EM current calculation (IPWC)
where Tau is \(T_d\) in above formula
!!! It seems that t*'s PDK don't support
dynamicACPeak=true
IR drop filter layers
EM techfile (qrcTechFile) may take diffusion contact
(n_odtap, p_odtap in DSPF file) into account during IR
drop analysis. And these segment often dominate IR drop, but we as IC
designer can NOT improve them. In general, the IR drop to M1 layer is
enough and feasible.
Regular
analysis statements in emir configuration
1 2
net name=[I0.vdd I0.vss] analysis=[vmax vavg] net name=[I0.*] analysis =[imax ivavg irms]
emirreport command
Creating reports for specific nets after simulation using
emirreport
Create a new config file as shown below:
1 2 3
** test.conf** net name=[I1.VDD I1.VSS] analysis=[iavg] net name=[I1.VBIAS] analysis=[imax]
Run emirreport on the command line using the
emirdatabase (emir*.bin) and test.conf
created above in
input.emir0_bin: The first EMIR Analysis which is DC or
Transient, which depends on Analyses order
input_tran.emir0_bin: EMIR Analysis in Transient
simulation
input_dcOp.emir0_bin: EMIR Analysis in DC
simulation
For example
Two results are generated input.emir0_bin and
input_dcOp.emir0_bin and their reports respectly
Fix Electromigration
Type
wider wire
downsize drivers
decrease fanout
RJ JMAX
✓
✓
JAVG
JABSAVG
JACPEAK
JACRMS
✓
✓
✓
Iavg
The average value of the current, which is the effective DC
current
Irms
Irms rule relates to the heat or Joule-heating of metal
lines
Ipeak
The main goal of the Ipeak limits is to ensure that no thermal
breakdown could occur on single overshoot events. If the signal may not
have a high current density but if it has a very large peak current
density, then, local melting will happen and cause failures
QA
Q. Why “length” column in EM results form doesn’t show extracted
length, it shows “NA”.
A. Voltus-Fi reports the “length” column only when length rules are
present in the emDataFile.
Seeing different port currents with and without emir simulations
for same dspf included in EMIR Direct method using dspf_include.
Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the
regular spectre flow. Islands patching is only performed in EMIR
only
Setting temperature for EM analysis
By Default, Voltus-FI and VPS pick up the current density limit for
temperature at which simulation has been performed.
By the way, Design Variables - temperature will
override the temperature in Setup toolbar which is gray in ADE
Explorer
AC Peak EM analysis - Voltus-Fi
The available options within the EM current analysis section in the
EMIR Analysis Setup form are:
max / avg / avgabs / rms.
In order to enable the AC Peak based information when
loading the EM results, both max and avg should be
selected when setting up the EMIR Analysis Setup.
With this configuration, the AC Peak option becomes available and can
be used.
How to print average, rms, and peak current of device
tap in Spectre/Voltus FI EMIR analysis
The following option enables you to save the average, rms, and peak
tap currents in the emir0bin file and report it in the
input.rpt_tapi file.
1
solver report_tapi=true
Add this option in emir.conf to enable the reporting
of tap current after the Spectre EMIR simulation. The input.rpt_tapi
file will be saved in the psf/raw directory.
Note: This feature is supported in SPECTRE20.1 ISR14
and later versions.
emir.conf file
emir.conf file is generated automaticaly after configure
EM/IR Analysis in ADE, which is in netlist
directory.
Setting default path for EM rules file in APS EMIR analysis
set the following environment variable in your terminal
1
setenv EMDATAFILE < path to EM rules file>
or set in .cdsinit
1
setShellEnvVar("EMDATAFILE=<path to EM rules file>")
Print node names and length associated with parasitic resistors
in EM report file
export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME
Printing the parasitic resistor length in the EM report
1
emirutil reportLength=true
Printing nodes that are associated with the parasitic
resistor
1
emirutil reportNodeName=true
Once these are enabled, you will have the Length,
Node_1, and Node_2 columns printed in
the EM report file, as shown below:
Is it possible to run RMS IR Drop analysis using Voltus-Fi?
Typically, in a simulation, Power/Ground nets are always biased with
a constant DC source. Hence, at present, Voltus-Fi only
supports Average and Maximum (Peak) IR Drop
analysis.
For a net to have data for IR analysis(vmax/vavg), the net/node must
be connected to a DC vsource or a vsource which is constant
within the emir time window.
Can we change the time window of EM computation after the
simulation completed ?
It is not possible to modify the EM time window without re-running
the full simulation.
However you can specify several time window in the emir conf file for
instance for 2 time window [0 to 10n] and [10n 20n]
1
time window=[0 10n 10n 20n]
In that case it will create 2 emir_bin files and
then 2 different em report files according to the 2 different time
windows.
How to print segment_W values being used to compute EM limits
You can use the following option to print segment_W to
the report:
1
emirutil reportSegmentWidth=[true]
This would print a Segment_w column in the report
containing the segment width values used for computing the limit:
Pass/Fail %
Resistor
layer
Current
Width
PathLength
I limit
X1
Y1
X2
Y2
J/JMAX
Res
ViaArea
No of needed vias
width/#via
J limit
Segment_w
(mA)
(um)
(um)
(um)
(um)
(um)
(um)
(nm^2)
(um/#)
(A/um)
pass-100.0
Rj3292
Met1
9.02376e-12
0.1
42.72
1.10067
0.350
11.568
0.350
11.376
8.19843e-12
0.7382
NA
NA
0.0001
0.0110067
0.1
pathLength vs Length in EM report file
Length: parasitic resistor length, which is set by
emirutil reportLength=true
pathlength: Blech length is also known as "Short length" or "Path
length", and can be explained as : The longest and continuous
centerline path from edge to edge among the connected wire
shapes on the same metal layer.
For all resistors falling on this shape, same
pathLength is reported.
After the longest path in shape has been determined the tool applies
the same blech length to all the resistor falling on that shape.
This resistor length is NOT used in EM analysis
because EM rules consider Blech length of the resistor.
where W is the wire width and L is the Blech length.
By default the tool will sum all branches of a given
metal layer. In other words the path length that will be used
to look up the EM density limit is :
To enable EMIR in PSS, you have to enable DC and/or Tran simulation
simultaneously. Two or more binary results file should be generated and
select the file based file name or configure text file in
psf directory.
(given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)
reference
AC Peak Analysis Using IPWC Rapid Adoption Kit (RAK) Product Version:
IC6.1.8 ISR10, SPECTRE19.1 ISR5 April 2020
A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts
of electromigration awareness," 2013 18th Asia and South Pacific Design
Automation Conference (ASP-DAC), 2013, pp. 527-532, doi:
10.1109/ASPDAC.2013.6509650.
Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling
of electromigration in SRAMs.” (2014).
N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical
approach to static signal electromigration analysis," Proceedings 1998
Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998,
pp. 572-577, doi: 10.1109/DAC.1998.724536.
Blaauw, David & Oh, Chanhee & Zolotov, Vladimir &
Dasgupta, Aurobindo. (2003). Static electromigration analysis for
on-chip signal interconnects. Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on. 22. 39 - 48.
10.1109/TCAD.2002.805728.
Johnson, M., Hudson, E.: A variable delay line PLL for
CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits
23(10), 1218–1223 (1988) [https://sci-hub.se/10.1109/4.5947]
M.H. Perrott, M.D. Trott, C.G. Sodini, "A Modeling Approach for
Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward
Noise Analysis", JSSC, vol 38, no 8, pp 1028-1038, Aug 2002. [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]
why 2nd loop filter ?
PI (proportional - integral) Loop Filter
Switched Capacitor Banks
Q: why \(R_b\) ?
A: TODO 📅
Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in
RF/millimeter-wave oscillators for 5G communications." PhD diss.,
2019.
S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough
analysis of the tank quality factor in LC oscillators with switched
capacitor banks," Proceedings of 2010 IEEE International Symposium
on Circuits and Systems, Paris, France, 2010, pp. 1903-1906
SSC intuition
Due to \(f= K_{vco}V_{ctrl}\), its
derivate to \(t\) is
\[
\frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt}
\]
For chargepump PLL, \(dV_{ctrl} =
\frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[
\frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C}
\]
Injection Lock
TODO 📅
Phase Interpolator (PI)
!!! Clock Edges
And for a phase interpolator, you need those reference clocks to be
completely the opposite. Ideally they would be
triangular shaped
four input clocks given by the cyan, black, magenta, red
even-stage ring oscillator ( multipath ring oscillators)
DLL: harmonic locking, stuck locking
clock edge impact
ck1 is div2 of ck0
edge of ck0 is affected differently by ck1
edge of ck1 is affected equally by ck0
clock distribution
TODO 📅
X. Mo, J. Wu, N. Wary and T. C. Carusone, "Design Methodologies for
Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the
Solid-State Circuits Society, vol. 1, pp. 94-103, 2021
Feedback Dividers
Large values of N lowers the loop BW which is bad for jitter
Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF,
Analog and Mixed Signal Circuits and Systems. Aalborg: River
Publishers, 2017.
clock gating
PLL Type & Order
Type: # of integrators within the loop
Order: # of poles in the closed-loop
transfer function
Type \(\leq\) Order
Why Type 2 PLL ?
That is, to have a wide bandwidth, a high loop gain is required
More importantly, the type 1 PLL has the problem of a static phase
error for the change of an input frequency
Since duty-cycle error is high frequency component, the
high-pass filter suppresses the duty-cycle error propagating to the
output
The AC-coupling capacitor blocks the low-frequency component of the
input
The feedback resistor sets common mode voltage to the crossover
voltage
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
Casper B, O’Mahony F. Clocking analysis, implementation and
measurement techniques for high-speed data links: A tutorial. IEEE
Transactions on Circuits and Systems I: Regular Papers.
2009;56(1):17–39
Divider phase noise &
jitter
Multiplying the frequency of a signal by a factor of N using an
ideal frequency multiplier increases the phase noise of
the multiplied signal by \(20\log(N)\)
dB.
Similarly dividing a signal frequency by N reduces the phase noise
of the output signal by \(20\log(N)\)
dB
The sideband offset from the carrier in the frequency
multiplied/divided signal is the same as for the original signal.
The 20log(N) Rule
If the carrier frequency of a clock is divided down by a factor of
\(N\) then we expect the phase noise to
decrease by \(20\log(N)\).The primary
assumption here is a noiseless conventional digital
divider.
The \(20\log(N)\) rule only applies
to phase noise and not integrated phase noise or phase
jitter. Phase jitter should generally measure about the
same.
What About Phase Jitter?
We integrate SSB phase noise L(f) [dBc/Hz] to
obtain rms phase jitter in seconds as follows for “brick wall”
integration from f1 to f2 offset frequencies in Hz and where f0 is the
carrier or clock frequency.
Note that the rms phase jitter in seconds is inversely proportional
to f0. When frequency is divided down, the phase noise, L(f),
goes down by a factor of 20log(N). However, since the frequency goes
down by N also, the phase jitter expressed in units of time is
constant.
Therefore, phase noise curves, related by 20log(N), with the same
phase noise shape over the jitter bandwidth, are expected to
yield the same phase jitter in seconds.
A step response test is an easy way to determine the
bandwidth.
Sum a small step into the control voltage of your oscillator
(VCO or NCO), and measure the 90% to 10% fall time of the
corrected response at the output of the loop filter as shown in this
block diagram
a first order loop \[
BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}
\] Where \(BW\) is the 3 dB
bandwidth in Hz and \(𝑡\) is the
10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7
this relationship is closer to: \[
BW = \frac{0.33}{t}\space\space\space\space \text{(second order system,
damping factor = 0.7)}
\]
A sine wave with phase modulation is expressed as \[
y(t) = A_0 \sin(2\pi f_0 t + \phi _0 +\phi (t))
\] where \(\phi (t)\) is a
time-varying phase modulation function
Assuming a narrowband phase modulation (PM), that is, the
absolute amount of modulated phase is small enough
otherwise the modulation becomes frequency modulation (FM) and
its analysis becomes more complex
\[
y(t) \simeq A_0 \sin(2\pi f_0 t +\phi _0) + A_0 \phi (t)\cos(2\pi f_0 t
+ \phi _0)
\]
Because \(\cos \phi(t)\) and \(\sin \phi(t)\) are approximated to \(1\) and \(\phi
(t)\), respectively
The Fourier transform of \(y(t)\) is
\[
Y(f) = \frac{1}{2}A_0 e^{j\phi _0}\delta(f-f_0)
-\frac{1}{2}A_0e^{-j\phi_0}\delta(f+f_0)+\frac{1}{2}A_0e^{j\phi_0}\Phi(f-f_0)-\frac{1}{2}A_0e^{-j\phi_0}\Phi(f+f_0)
\]
where \(\Phi(f)\) is the Fourier
transform pair of \(\phi(t)\)
Fourier transform of \(R(\tau)\) is
\[
S_y(f) = \frac{1}{4}A_0^2 \delta (f-f_0) + \frac{1}{4}A_0\delta(f+f_0) +
\frac{1}{4}A_0^2S_\phi (f-f_0)+\frac{1}{4}A_0^2S_\phi (f+f_0)
\]
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
approximation limitation
Don't retain the same total power
Leeson's model
Leeson's equation is an empirical expression that describes
an oscillator's phase noise spectrum
Limitation:
that the PSD diverges to infinity for very low values of
the frequency offset \(f\)
Lorentzian Spectrum
We typically use the two spectra, \(S_{\phi
n}(f)\) and \(S_{out}(f)\),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal \(x(t)\) can be
expanded in Fourier series as:
Assume that the signal is subject to excess phase noise, which is
modeled by adding a time-dependent noise component \(\alpha(t)\). The noisy signal can be
written \(x(t+\alpha(t))\), the added
excess phase \(\phi(t)=
\frac{\alpha(t)}{\omega_0}\)
The autocorrelation of the noisy signal is by definition:
The autocorrelation averaged over time results in:
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal \(x(t + \alpha(t))\) can
be expressed as
It is also interesting to note how the integral in Equation 9.80
around each harmonic is equal to the power of the harmonic itself \(|X_n|^2\)
The integral \(S_x(f)\) around
harmonic is \[\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}\]
The phase noise does not affect the total power in the signal, it
only affects its distribution.
Without phase noise, \(S_v(f)\) is
a series of impulse functions at the harmonics of \(f_o\).
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
