By square-law, the Eq \(g_m = \sqrt{2\mu
C_{ox}\frac{W}{L}I_D}\), it is possible to obtain a
higer transconductance by increasing \(W\) while maintaining \(I_D\) constant. However, if \(W\) increases while \(I_D\) remains constant, then \(V_{GS} \to V_{TH}\) and device enters the
subthreshold region. \[
I_D = I_0\exp \frac{V_{GS}}{\xi V_T}
\]
where \(I_0\) is proportional to
\(W/L\), \(\xi \gt 1\) is a nonideality factor, and
\(V_T = kT/q\)
As a result, the transconductance in subthreshold region is \[
g_m = \frac{I_D}{\xi V_T}
\]
which is \(g_m \propto I_D\)
PTAT with subthreshold MOS
MOS working in the weak inversion region
("subthreshold conduction") have the similar
characteristics to BJTs and diodes, since the effect of diffusion
current becomes more significant than that of drift current
Hongprasit, Saweth, Worawat Sa-ngiamvibool and Apinan Aurasopon.
“Design of Bandgap Core and Startup Circuits for All CMOS Bandgap
Voltage Reference.” Przegląd Elektrotechniczny (2012):
277-280.
VBE
temperature coefficient of \(V_{BE}\) itself depends on the
temperature,
temperature coefficient of the \(V_{BE}\) at a given temperature T depends
on the magnitude of \(V_{BE}\)
itself
\(\frac{kT}{q}\) is approximately
26mV, at room temperature 300K
In advanced node, N4P, \(V_{BE}\) is
about -1.45mV/K
constant-gm
aka. Beta-multiplier reference
\(I_\text{out}\) is
PTAT in case temperature coefficient of \(R_s\) is less than that of \(\mu_n\)
Body effect of M2
Boris Murmann, Systematic Design of Analog Circuits Using
Pre-Computed Lookup Tables
S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias
Circuits," in IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022
S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog
Integrated Circuits", IEEE International Symposium on Circuits and
Systems, ISCAS 2004, Vancouver , May 2004
Why employ MOSFETs in
saturation?
gm, gds at fixed VGS
\(g_{ds}\) is constant in saturation
region
in triode region \[
g_{ds} = \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS})
\]
Interestingly, \(g_m\) in the
saturation region is equal to the inverse of \(R_\text{on}\) in the deep triode
region.
gm, gds at fixed Id, VG
In triode region\[
I_D =
\frac{1}{2}\mu_nC_{ox}\frac{W}{L}[2(V_{GS}-V_{TH})V_{DS}-V_{DS}^2]
\] where \(I_D\) and \(V_G\) is fixed
Then \(V_S\) can be expressed with
\(V_D\), that is \[
V_S = V_{GT} - \sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}
\] where \(V_{GT}=V_G-V_{TH}\),
\(V_{dsat}\) is \(V_{DS}\) saturation voltage \[
g_m =
\mu_nC_{ox}\frac{W}{L}\left(V_D-V_{GT}+\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}\right)
\] Then \[
\frac{\partial g_m}{\partial V_D} \propto 1 -
\frac{V_{GT}-V_D}{\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}} \gt 0
\]
We get \(I_{\Delta_{V_{TH}}}\simeq
1.71\%\) and \(I_{\Delta_{WL}} \simeq
1.73\%\)
Biasing
current source and global variation Monte Carlo
iwl: biased by mirror
iwl_ideal: biased by vdc source, whose
value is typical corner
For local variation, constant voltage bias
(vb_const in schematic) help reduce variation from \(\sqrt{2}\Delta V_{th}\) to \(\Delta V_{th}\)
For global variation, all device have same
variation, mirror help reduce variation by sharing same \(V_{gs}\)
global variation + local variation (All MC)
local variation (Mismatch MC)
global variation (Process MC)
We had better bias mos gate with mirror rather than the vdc
source while simulating sub-block.
This is real situation due to current source are always biased by
mirror and vdc biasing don't give the right result in global
variation Monte Carlo simulation (542.8n is too pessimistic,
13.07p is right result)
For any given constant values of u and v, the
constant values of variables that solve the the feed back relationship
are called the operating points, or equilibrium
points.
Operating points can be either stable or
unstable.
An operating point is unstable if any or some small perturbation near
it causes divergence away from that operating point.
If the loop gain evaluated at an operating point is less than
one, that operating point is stable.
This is a sufficient condition
With \(m_{1\to 2} = 1\)\[
\text{Loop Gain} \simeq \frac{V_{BN}-V_{T2}}{V_{BN}-V_{T2} + V_R}
\tag{LG\_0}
\] Assuming all MOS in strong inv operation, \(I\), \(V_{BN}\) and \(V_R\) is obtain \[\begin{align}
I &= \frac{2\beta _1 + 2\beta _2 - 4\sqrt{\beta _1 \beta
_2}}{R^2\beta _1 \beta _2} \\
V_{BN} &= V_{T2} + \frac{2}{R\beta _2}(1- \sqrt{\frac{\beta
_2}{\beta _1}}) \\
IR &= \frac{2}{R}\left( \frac{1}{\sqrt{\beta_2}}
- \frac{1}{\sqrt{\beta_1}} \right)
\end{align}\]
Substitute \(V_{BN}\) and \(V_R\) of \((LG\_0)\)\[\begin{align}
\text{Loop Gain} & \simeq
\frac{1-\sqrt{\frac{\beta_2}{\beta_1}}}{\frac{\beta_2}{\beta_1} -
3\sqrt{\frac{\beta_2}{\beta_1}}+2} \\
&= \frac{1}{2-\sqrt{\frac{\beta_2}{\beta_1}}} \tag{LG\_1}
\end{align}\]
Alternative approach for
Loop Gain
using derivation of large signal
❗❗❗ R should not be on the other side
Self-Biasing Cascode
reference
B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog
Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3,
pp. 6-16, Summer 2021, doi: 10.1109/MSSC.2021.3088963
spurs are carrier or clock frequency spectral
imperfections measured in the frequency domain just like phase noise.
However, unlike phase noise they are discrete frequency
components.
Spurs are deterministic.
Spur power is independent of bandwidth.
Spurs contribute bounded peak jitter in the time domain.
Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System
Perspectives and Circuit Design Aspects. John Wiley & Sons.
H. M. S. Fazeel, L. Raghavan, C. Srinivasaraman and M. Jain,
"Reduction of Current Mismatch in PLL Charge Pump," 2009 IEEE
Computer Society Annual Symposium on VLSI, Tampa, FL, USA, 2009,
pp. 7-12, doi: 10.1109/ISVLSI.2009.45.
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it
down
Decimating by \(L\) means
frequency register only added once every \(L\) UI, thus integral path gain
reduced by \(L\) in linear
model
Decimation by Summing
In DSP this is called boxcar filter
\(\sum d_n\), where \(d_n \in \{-1, 0, 1\}\)
Decimation via boxcar filter produces a DC gain, \(K_b\), corresponding to the decimation
factor.
Compared to the boxcar filter, voting is able to reduce the loop
delay and lower the output noise of the MMPD
Decimation via voting has a reduced gain, \(K_V\), which can be determined through
simulation
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006
Pavan Hanumolu, ISSCC 2015 tutorial. "Clock and Data Recovery
Architectures & Circuits"
Liu, Tao, Tiejun Li, Fangxu Lv, Bin Liang, Xuqiang Zheng, Heming
Wang, Miaomiao Wu, Dechao Lu, and Feng Zhao. 2021. "Analysis and
Modeling of Mueller-Muller Clock and Data Recovery Circuits"
Electronics 10, no. 16: 1888.
https://doi.org/10.3390/electronics10161888
Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen
& Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data
Recovery Circuits with a Linearized Model.
10.21203/rs.3.rs-1817774/v1.
BER with Quantization Noise
\[
\text{Var}(X) = E[X^2] - E[X]^2
\]
Impulse Response or Pulse
Response
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link
Foundations Standards, Link Budgets & Models," 2019 IEEE Custom
Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95,
doi: 10.1109/CICC.2019.8780223.
Johnson, M., Hudson, E.: A variable delay line PLL for
CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits
23(10), 1218–1223 (1988) [https://sci-hub.se/10.1109/4.5947]
why 2nd loop filter ?
PI (proportional - integral) Loop Filter
Switched Capacitor Banks
Q: why \(R_b\) ?
A: TODO 📅
Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in
RF/millimeter-wave oscillators for 5G communications." PhD diss.,
2019.
S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough
analysis of the tank quality factor in LC oscillators with switched
capacitor banks," Proceedings of 2010 IEEE International Symposium
on Circuits and Systems, Paris, France, 2010, pp. 1903-1906
Injection Lock
TODO 📅
Phase Interpolator (PI)
!!! Clock Edges
And for a phase interpolator, you need those reference clocks to be
completely the opposite. Ideally they would be
triangular shaped
four input clocks given by the cyan, black, magenta, red
even-stage ring oscillator ( multipath ring oscillators)
DLL: harmonic locking, stuck locking
different frequency
clock impact on edge
ck1 is div2 of ck0
edge of ck0 is affected differently by ck1
edge of ck1 is affected equally by ck0
limit cycle & hunting
jitter
hunting jitter is also called as dithering
jitter
CDR Loop Latency
Denoting the CDR loop latency by \(\Delta
T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The
resulting right-half-plane zero, \(f_z\) degrades the phase margin and must
remain about one decade beyond the BW\[
f_z\simeq \frac{1}{2\pi \Delta T}
\]
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of
Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
clock distribution
X. Mo, J. Wu, N. Wary and T. C. Carusone, "Design Methodologies for
Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the
Solid-State Circuits Society, vol. 1, pp. 94-103, 2021
PFD
symmetric???
Feedback Dividers
Large values of N lowers the loop BW which is bad for jitter
Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF,
Analog and Mixed Signal Circuits and Systems. Aalborg: River
Publishers, 2017.
clock gating
PLL Type & Order
Type: # of integrators within the loop
Order: # of poles in the closed-loop
transfer function
Type \(\leq\) Order
Why Type 2 PLL ?
That is, to have a wide bandwidth, a high loop gain is required
More importantly, the type 1 PLL has the problem of a static phase
error for the change of an input frequency
AC-coupled buffer
Since duty-cycle error is high frequency component, the
high-pass filter suppresses the duty-cycle error propagating to the
output
The AC-coupling capacitor blocks the low-frequency component of the
input
The feedback resistor sets common mode voltage to the crossover
voltage
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
Casper B, O’Mahony F. Clocking analysis, implementation and
measurement techniques for high-speed data links: A tutorial. IEEE
Transactions on Circuits and Systems I: Regular Papers.
2009;56(1):17–39
Clock Division with
Jitter and Phase Noise
Multiplying the frequency of a signal by a factor of N using an
ideal frequency multiplier increases the phase noise of
the multiplied signal by \(20\log(N)\)
dB.
Similarly dividing a signal frequency by N reduces the phase noise
of the output signal by \(20\log(N)\)
dB
The sideband offset from the carrier in the frequency
multiplied/divided signal is the same as for the original signal.
The 20log(N) Rule
If the carrier frequency of a clock is divided down by a factor of
\(N\) then we expect the phase noise to
decrease by \(20\log(N)\).The primary
assumption here is a noiseless conventional digital
divider.
The \(20\log(N)\) rule only applies
to phase noise and not integrated phase noise or phase
jitter. Phase jitter should generally measure about the
same.
What About Phase Jitter?
We integrate SSB phase noise L(f) [dBc/Hz] to
obtain rms phase jitter in seconds as follows for “brick wall”
integration from f1 to f2 offset frequencies in Hz and where f0 is the
carrier or clock frequency.
Note that the rms phase jitter in seconds is inversely proportional
to f0. When frequency is divided down, the phase noise, L(f),
goes down by a factor of 20log(N). However, since the frequency goes
down by N also, the phase jitter expressed in units of time is
constant.
Therefore, phase noise curves, related by 20log(N), with the same
phase noise shape over the jitter bandwidth, are expected to
yield the same phase jitter in seconds.
where \(\mu = (1)\times
\mathrm{P}(\text{late}|\phi) + (-1)\times
\mathrm{P}(\text{early}|\phi)\)
Both jitter and amplitude noise distribution are same, just scaled by
slope
Self-Noise Term
One price we pay for BB PD versus linear PD is the
self-noise term. For small phase errors BB output noise is the full
magnitude of the sliced data.
BB-PD don't have any measure as to how early or how late and the way
that tell loop is locked, is over a long time average, BB-PD have an
equal number of earlies and lates
John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and
Data Recovery
Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data
Recovery in Serial Data Transmission Systems. [pdf]
- Clock and Data Recovery for Serial Data Communications, focusing on
bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]
PLL bandwidth test
A step response test is an easy way to determine the
bandwidth.
Sum a small step into the control voltage of your oscillator
(VCO or NCO), and measure the 90% to 10% fall time of the
corrected response at the output of the loop filter as shown in this
block diagram
a first order loop \[
BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}
\] Where \(BW\) is the 3 dB
bandwidth in Hz and \(𝑡\) is the
10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7
this relationship is closer to: \[
BW = \frac{0.33}{t}\space\space\space\space \text{(second order system,
damping factor = 0.7)}
\]
A sine wave with phase modulation is expressed as \[
y(t) = A_0 \sin(2\pi f_0 t + \phi _0 +\phi (t))
\] where \(\phi (t)\) is a
time-varying phase modulation function
Assuming a narrowband phase modulation (PM), that is, the
absolute amount of modulated phase is small enough
otherwise the modulation becomes frequency modulation (FM) and
its analysis becomes more complex
\[
y(t) \simeq A_0 \sin(2\pi f_0 t +\phi _0) + A_0 \phi (t)\cos(2\pi f_0 t
+ \phi _0)
\]
Because \(\cos \phi(t)\) and \(\sin \phi(t)\) are approximated to \(1\) and \(\phi
(t)\), respectively
The Fourier transform of \(y(t)\) is
\[
Y(f) = \frac{1}{2}A_0 e^{j\phi _0}\delta(f-f_0)
-\frac{1}{2}A_0e^{-j\phi_0}\delta(f+f_0)+\frac{1}{2}A_0e^{j\phi_0}\Phi(f-f_0)-\frac{1}{2}A_0e^{-j\phi_0}\Phi(f+f_0)
\]
where \(\Phi(f)\) is the Fourier
transform pair of \(\phi(t)\)
Fourier transform of \(R(\tau)\) is
\[
S_y(f) = \frac{1}{4}A_0^2 \delta (f-f_0) + \frac{1}{4}A_0\delta(f+f_0) +
\frac{1}{4}A_0^2S_\phi (f-f_0)+\frac{1}{4}A_0^2S_\phi (f+f_0)
\]
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
approximation limitation
Don't retain the same total power
Leeson's model
Leeson's equation is an empirical expression that describes
an oscillator's phase noise spectrum
Limitation:
that the PSD diverges to infinity for very low values of
the frequency offset \(f\)
Lorentzian Spectrum
We typically use the two spectra, \(S_{\phi
n}(f)\) and \(S_{out}(f)\),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal \(x(t)\) can be
expanded in Fourier series as:
Assume that the signal is subject to excess phase noise, which is
modeled by adding a time-dependent noise component \(\alpha(t)\). The noisy signal can be
written \(x(t+\alpha(t))\), the added
excess phase \(\phi(t)=
\frac{\alpha(t)}{\omega_0}\)
The autocorrelation of the noisy signal is by definition:
The autocorrelation averaged over time results in:
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal \(x(t + \alpha(t))\) can
be expressed as
It is also interesting to note how the integral in Equation 9.80
around each harmonic is equal to the power of the harmonic itself \(|X_n|^2\)
The integral \(S_x(f)\) around
harmonic is \[\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}\]
The phase noise does not affect the total power in the signal, it
only affects its distribution.
Without phase noise, \(S_v(f)\) is
a series of impulse functions at the harmonics of \(f_o\).
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
To avoid spectral leakage completely, the method of
coherent sampling is recommended. Coherent sampling
requires that the input- and clock-frequency generators are
phase locked, and that the input frequency be chosen
based on the following relationship: \[
\frac{f_{\text{in}}}{f_{\text{s}}}=\frac{M_C}{N_R}
\]
where:
\(f_{\text{in}}\) = the desired
input frequency
\(f_s\) = the clock frequency of
the data converter under test
\(M_C\) = the number of cycles in
the data window (to make all samples unique, choose odd or prime
numbers)
\(N_R\) = the data record length
(for an 8192-point FFT, the data record is 8192s long)
An irreducible ratio ensures identical code
sequences not to be repeated multiple times. Unnecessary repetition of
the same code is not desirable as it increases ADC test time.
Given that \(\frac{M_C}{N_R}\) is
irreducible, and \(N_R\) is a power of
2, an odd number for \(M_C\) will always produce an
irreducible ratio
Assuming there is a common factor \(k\) between \(M_C\) and \(N_R\), i.e. \(\frac{M_C}{N_R}=\frac{k M_C'}{k
N_R'}\)
So, the samples is repeated \(y[n] =
y[n+N_R']\). Usually, no additional information is gained by
repeating with the same sampling points.
Example\[
N \cdot \frac{1}{F_s} = M \cdot \frac{1}{F_{in}}
\]
where \(F_s\) is sample frequency,
\(F_{in}\) input signal frequency.
And \(N\) often is 256, 512; M is 3,
5, 7, 11.
channel loss
skin effect loss
dielectric loss
phase delay & group delay
Phase delay directly measures the device or system time delay of
individual sinusoidal frequency components in the
steady-state conditions.
In the ideal case the envelope delay is equal to the phase
delay
envelope delay is a more sensitive measure of aberrations than phase
delay
phase delay
If the phase delay peaks (exceeds the low-frequency value) you can
expect to see high-frequency components late in the step response. This
causes ringing.
group delay
steady-state at this frequency is a polarity flip; a 180 degrees
phase shift; which is a transfer function of H(s)=-1. \[
H(s) = e^{j\pi}
\] That is \(\phi(\omega) =
\pi\)\[
\tau_p = \frac{\pi}{\omega}
\] and \[
\tau_g = \frac{\partial \pi}{\partial \omega}=0
\]
Hollister, Allen L. Wideband Amplifier Design. Raleigh, NC:
SciTech Pub., 2007.
A sampled system almost always has more stability problems than arise
in continuous-time systems.
In particular, an analog, second-order PLL is unconditionally stable
for any value of loop gain
but the sampled equivalent will go unstable if the gain is made too
large
F. Gardner, "Charge-Pump Phase-Lock Loops," in IEEE Transactions
on Communications, vol. 28, no. 11, pp. 1849-1858, November 1980,
doi: 10.1109/TCOM.1980.1094619
Feedback Rearrange
The closed loop transfer function of \(Y/X\) and \(Y_1/X_1\) are almost same, except sign
define \(-Y_1=Y_n\), then \[
\frac{Y_n}{X_1} = \frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)}
\]
Saurabh Saxena, IIT Madras. Clocking for Serial Links - Frequency and
Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery
Convolution of
probability distributions
The probability distribution of the sum of two or more
independent random variables is the
convolution of their individual distributions.
Thermal noise
Thermal noise in an ideal resistor is approximately
white, meaning that its power spectral density is
nearly constant throughout the frequency spectrum.
When limited to a finite bandwidth and viewed in the time
domain, thermal noise has a nearly Gaussian amplitude
distribution
Barkhausen criteria
Barkhausen criteria are necessary but not sufficient
conditions for sustainable oscillations
Control of Steady-State Error to Polynomial Inputs: System Type
control systems are assigned a type number according
to the maximum degree of the input polynominal for which the
steady-state error is a finite constant. i.e.
Type 0: Finite error to a step (position error)
Type 1: Finite error to a ramp (velocity error)
Type 2: Finite error to a parabola (acceleration error)
The open-loop transfer function can be expressed as \[
T(s) = \frac{K_n(s)}{s^n}
\]
where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),
The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform
is \[
R(s) = \frac{1}{s^{k+1}}
\]
Then the equation for the error is simply \[
E(s) = \frac{1}{1+T(s)}R(s)
\]
Application of the Final Value Theorem to the error formula
gives the result
\(H(j\omega)\) is obtained as below
\[
H(j\omega) = \frac{1}{1+j\omega}
\]
Initial Value Theorem
& Final Value Theorem
Two valuable Laplace transform theorem
Initial Value Theorem, which states that it is always possible to
determine the initial value of the time function \(f(t)\) from its Laplace transform \[
\lim _{s\to \infty}sF(s) = f(0^+)
\]
Final Value Theorem allows us to compute the constant
steady-state value of a time function given its Laplace
transform \[
\lim _{s\to 0}sF(s) = f(\infty)
\]
If \(f(t)\) is step response, then
\(f(0^+) = H(\infty)\) and \(f(\infty) = H(0)\), where \(H(s)\) is transfer function
Butterworth filter
function varargout = butter(n, Wn, varargin)
% BUTTER Butterworth digital and analog filter design.
% [B,A] = BUTTER(N,Wn) designs an Nth order lowpass digital
% Butterworth filter and returns the filter coefficients in
length
% N+1 vectors B (numerator) and A (denominator). The coefficients
% are listed in descending powers of z. The cutoff frequency
% Wn must be 0.0 < Wn < 1.0, with 1.0
corresponding to
% half the sample rate.
\[
w_n = \frac{f_c}{0.5f_s}
\]
where \(f_c\) is cutoff frequency,
\(f_s\) is sampling frequency
Given \(f_c\) is 300 Hz and \(f_s\) is 1000 Hz, we get \[
\omega_n = \frac{f_c}{0.5*f_s} = 0.6
\] and in rad/sample unit, cutoff frequency is \[
\Phi = \pi * \omega_n = 0.6 \pi \text {, unit: rad/sample}
\]
The numerator (b) and denominator (a)
depend on the cutoff frequency and the order; the cutoff frequency is
denominated with \(\omega_n\) . Just
multiply the \(\pi\), we get the
Z-transform \(\Phi\) rad/sample, which
is the plot of freqz(b, a)
figure(3) % assume x is sampled by fs x = rand(1, 50); y = filter(b, a, x); xt = (1:50); plot(xt, x, '-s', xt, y, '-o') legend('input', 'output') xlabel('Sample') ylabel('mag') title('filter in Time domain') grid on;
Bilinear Transformation
Bilinear Transformation, also known as
Bilinear Approximation, an algebraic transformation
between the variables \(s\) and \(z\) that maps the entire \(j\Omega\)-axis in the \(s\)-plane to one revolution of the unit
circle in the \(z\)-plane.
That is, with this approach, \(-\infty \le
\Omega \le +\infty\) maps onto \(-\pi
\le \omega \le +\pi\), the transformation between the
continuous-time and discrete-time frequency variables is necessarily
nonlinear.
With \(H_c(s)\) denoting the
continuous-time system function and \(H(z)\) the discrete-time system function,
the bilinear transformation corresponds to replacing \(s\) by \[
s=\frac{2}{T_d}\left( \frac{1-z^{-1}}{1+z^{-1}} \right)
\]
that is, \[
H(z) = H_c\left( \frac{2}{T_d}\left( \frac{1-z^{-1}}{1+z^{-1}} \right)
\right)
\]
Different Variants of
the PSD Definition
In the practice of engineering, it has become customary to use
slightly different variants of the PSD definition, depending on the
particular application or research field.
Two-Sided PSD, \(S_x(f)\)
this is a synonym of the PSD defined as the Fourier Transform of the
autocorrelation.
One-Sided PSD, \(S'_x(f)\)
this is a variant derived from the two-sided PSD by
considering only the positive frequency semi-axis.
To conserve the total power, the value of the
one-sided PSD is twice that of the two-sided PSD \[
S'_x(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_x(f) & : \ f = 0 \\
2S_x(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the one-sided PSD definition makes sense only if the
two-sided is an even function of \(f\)
If \(S'_x(f)\) is even
symmetrical around a positive frequency \(f_0\), then two additional definitions can
be adopted:
Single-Sideband PSD, \(S_{SSB,x}(f)\)
This is obtained from \(S'_x(f)\) by moving the origin of the
frequency axis to \(f_0\)\[
S_{SSB,x}(f) =S'_x(f+f_0)
\] This concept is particularly useful for describing phase or
amplitude modulation schemes in wireless communications, where \(f_0\) is the carrier frequency.
Note that there is no difference in the values of the one-sided
versus the SSB PSD; it is just a pure translation on the frequency
axis.
Double-Sideband PSD, \(S_{DSB,x}(f)\)
this is a variant of the SSB PSD obtained by considering only the
positive frequency semi-axis.
As in the case of the one-sided PSD, to conserve total power, the
value of the DSB PSD is twice that of the SSB \[
S_{DSB,x}(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_{SSB,x}(f) & : \ f = 0 \\
2S_{SSB,x}(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the DSB definition makes sense only if the SSB PSD is even
symmetrical around zero
Poles and Zeros of
transfer function
poles
\[
H(s) = \frac{1}{1+s/\omega_0}
\]
magnitude and phase at \(\omega_0\)
and \(-\omega_0\)\[\begin{align}
H(j\omega_0) &= \frac{1}{1+j} = \frac{1}{\sqrt{2}}e^{-j\pi/4} \\
H(-j\omega_0) &= \frac{1}{1-j} = \frac{1}{\sqrt{2}}e^{j\pi/4}
\end{align}\]
The aliasing of the noise, or noise
folding, plays an important role in switched-capacitor as it
does in all switched-capacitor filters
Assume for the moment that the switch is always closed (that
there is no hold phase), the single-sided noise density would be
\(v_s[n]\) is the sampled version of
\(v_{RC}(t)\), i.e. \(v_s[n]= v_{RC}(nT_C)\)\[
S_s(e^{j\omega}) = \frac{1}{T_C}
\sum_{k=-\infty}^{\infty}S_{RC}(j(\frac{\omega}{T_C}-\frac{2\pi
k}{T_C})) \cdot d\omega
\] where \(\omega \in [-\pi,
\pi]\), furthermore \(\frac{d\omega}{T_C}= d\Omega\)\[
S_s(j\Omega) = \sum_{k=-\infty}^{\infty}S_{RC}(j(\Omega-k\Omega_s))
\cdot d\Omega
\]
The noise in \(S_{RC}\) is a
stationary process and so is uncorrelated over \(f\) allowing the \(N\) rectangles to be combined by simply
summing their noise powers
Matt Pharr, Wenzel Jakob, and Greg Humphreys. 2016. Physically Based
Rendering: From Theory to Implementation (3rd. ed.). Morgan Kaufmann
Publishers Inc., San Francisco, CA, USA.
for N=[2^62^82^102^12] wd = rectwin(N); nbw = enbw(wd)/N; snr_shift = 10*log10(nbw * 2); disp(snr_shift); end
output:
1 2 3 4 5 6 7
-15.0515
-21.0721
-27.0927
-33.1133
The solution to the scaling problem in the case of a PSD obtained
from a sine-wave scaled FFT is similarly simple. All we need do is
provide the value of NBW
APPENDIX A - SPECTRAL ESTIMATION - A.2 Scaling and Noise
Bandwidth
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016.
Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
For a filter with infinitely steep roll-off, the noise bandwidth
(NBW) is equal to the filter's bandwidth,
while for a filter with a single-pole roll-off, NBW
is 2 times the 3-dB bandwidth
Pharr, Matt; Humphreys, Greg. (28 June 2010). Physically Based
Rendering: From Theory to Implementation. Morgan Kaufmann. ISBN
978-0-12-375079-2. Chapter
7 (Sampling and reconstruction)
Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing,
3rd edition
we get \(C_\text{out,eq}=
(1+\frac{1}{A_v})C_c\simeq C_c\)
cascode compensation
Of course, , if the capacitance at the gate of \(M_1\) is taken into account, pole splitting
is less pronounced.
including \(r_\text{o2}\)
\[
\frac{V_{out}}{I_{in}} \approx
\frac{-g_{m1}R_SR_L(g_{m2}+C_Cs)}{\frac{R_S+r_\text{o2}}{r_\text{o2}}R_LC_LC_Cs^2+g_{m1}g_{m2}R_LR_SC_Cs+g_{m2}}
\] The poles as
and zero is not affected, which is \(\omega_z =\frac{g_{m2}}{C_C}\)
the above model simulation result is shown below
the zero is located between two poles
take into the capacitance at the gate of \(M_1\) and all other second-order effect
intuitive analysis of zero
miller compensation
zero in the right half plane \[
g_\text{m1}V_P = sC_c V_P
\]
cascode compensation
zero in the left half plane \[
g_\text{m2}V_X = - sC_c V_X
\]
How to Mitigate Impact of
Zero
dominant pole\[
\omega_\text{p,d} = \frac {1} {R_\text{eq}g_\text{m9}R_{L}C_{c}}
\]first nondominant pole\[
\omega_\text{p,nd} = \frac {g_\text{m4}R_\text{eq}g_\text{m9}} {C_L}
\]zero\[
\omega_\text{z} = (g_\text{m4}R_\text{eq})(\frac {g_\text{m9}} {C_c})
\] a much greater magnitude than \(g_\text{m9}/C_C\)
Lectures
EE 240B: Advanced Analog Circuit Design, Prof. Bernhard E. Boser [OTA
II, Multi-Stage]
Papers
B. K. Ahuja, "An improved frequency compensation technique for CMOS
operational amplifiers," in IEEE Journal of Solid-State Circuits, vol.
18, no. 6, pp. 629-633, Dec. 1983, doi: 10.1109/JSSC.1983.1052012.
D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS
op amps with improved PSRR and common-mode input range," in IEEE Journal
of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984, doi:
10.1109/JSSC.1984.1052246.
Abo, Andrew & Gray, Paul. (1999). A 1.5V, 10-bit, 14MS/s CMOS
Pipeline Analog-to-Digital Converter.
Book's chapters
Design of analog CMOS integrated circuits, Behzad Razavi
10.5 Compensation of Two-Stage Op Amps
10.7 Other Compensation Techniques
Analog Design Essentials, Willy M.C. Sansen
chapter #5 Stability of operational amplifiers - Compensation of
positive zero
Analysis and Design of Analog Integrated Circuits 5th Edition, Paul
R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer
9.4.3 Two-Stage MOS Amplifier Compensation
CMOS Analog Circuit Design 3rd Edition, Phillip E. Allen, Douglas R.
Holberg
6.2.2 Miller Compensation of the Two-Stage Op Amp
reference
B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS
Operational Amplifiers," IEEE 1. Solid-State Circuits, vol. 18, no. 6,
pp. 629-633, Dec. 1983.
U. Dasgupta, "Issues in "Ahuja" frequency compensation technique",
IEEE International Symposium on Radio-Frequency Integration Technology,
2009.
R. 1. Reay and G. T. A. Kovacs, "An unconditionally stable two-stage
CMOS amplifier," IEEE 1. Solid-State Circuits, vol. 30, no. 5, pp. 591-
594, May 1995.
A. Garimella and P. M. Furth, "Frequency compensation techniques for
op-amps and LDOs: A tutorial overview," 2011 IEEE 54th International
Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp. 1-4, doi:
10.1109/MWSCAS.2011.6026315.
H. Aminzadeh, R. Lotfi and S. Rahimian, "Design Guidelines for
Two-Stage Cascode-Compensated Operational Amplifiers," 2006 13th IEEE
International Conference on Electronics, Circuits and Systems, 2006, pp.
264-267, doi: 10.1109/ICECS.2006.379776.
H. Aminzadeh and K. Mafinezhad, "On the power efficiency of cascode
compensation over Miller compensation in two-stage operational
amplifiers," Proceeding of the 13th international symposium on Low power
electronics and design (ISLPED '08), Bangalore, India, 2008, pp.
283-288, doi: 10.1145/1393921.1393995.
