KNOW-HOW

TODO 📅

Linear phase

[https://web.ece.ucsb.edu/~yoga/courses/DSP/P10_Linear_phase_FIR.pdf]

Digital DC Offset Correction

\[ X- Y\cdot \beta z^{-1}\cdot \frac{1}{1-z^{-1}} = Y \] therefore \[ \frac{Y}{X} = \frac{1-z^{-1}}{1-(1-\beta)z^{-1}} \]

VDD Droop Mitigation

speed of voltage monitor does matter

reference

B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and Applications (2nd ed.). John Wiley & Sons, Inc.

Simon O. Haykin (2014), "Adaptive Filter Theory" Prentice-Hall, Inc. 5rd edition

Diniz, P. S. R. (2020). Adaptive Filtering: Algorithms and Practical Implementation (5th ed.). Springer

Jiang X, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge University Press; 2015.

Albert Jerng. ISSCC2012 T7: Digital Calibration for RF Transceivers [pdf]

Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in ADCs [pdf]

Salvatore Levantino. ISSCC2024 T5: Calibration Techniques in PLLs [pdf]

A. Chan Carusone and D. A. Johns, "Analog Filter Adaptation Using a Dithered Linear Search Algorithm," IEEE Int. Symp. Circuits and Syst., May 2002. [PDF], [Slides]

—, Ph. D. Thesis, "Digital Algorithms for Analog Adaptive Filters", Feb. 2002. [http://www.eecg.utoronto.ca/~tcc/thesis.pdf]

—, "Analog Adaptive Filters," tutorial at the IEEE Int. Symp. Circuits and Syst., Bangkok, Thailand, May 2003. [http://www.eecg.utoronto.ca/~tcc/iscas03_tutorial.pdf]

David Johns, "Integrated Circuits for Digital Communications" [https://www.eecg.toronto.edu/~johns/nobots/courses/ece1392/slides.pdf]

Tai-Haur Kuo "Advanced Analog IC Design for Communications" [http://msic.ee.ncku.edu.tw/course/AdvancedAnalogICDesign/AdvancedAnalogICDesign.html]

Chadi Jabbour, Telecom Paristech. ISCAS 2019 T12: Digitally Enhanced Mixed Signal Systems [https://www.youtube.com/watch?v=rACuCSDm5jQ]

Reference

DaVE - tools regarding on analog modeling,validation, and generation, [https://github.com/StanfordVLSI/DaVE]

Lim, Byong Chan,Ph.D. Dissertation 2012. "Model validation of mixed-signal systems" [https://stacks.stanford.edu/file/druid:xq068rv3398/bclim-thesis-submission-augmented.pdf]

—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog Design: Enabling Mixed-Signal System Validation," in IEEE Design & Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim, Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

—, M. Horowitz, "Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1, pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]

Ben Yochret Sabrine, 2020, "BEHAVIORAL MODELING WITH SYSTEMVERILOG FOR MIXED-SIGNAL VALIDATION" [https://di.uqo.ca/id/eprint/1224/1/Ben-Yochret_Sabrine_2020_memoire.pdf]

"Creating Analog Behavioral Models VERILOG-AMS ANALOG MODELING" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/CDN_Creating_Analog_Behavioral_Models.pdf]

Rainer Findenig, Infineon Technologies. "Behavioral Modeling for SoC Simulation Bridging Analog and Firmware Demands" [https://www.coseda-tech.com/files/Files/Dokumente/Behavioral_Modeling_for_SoC_Simulation_COSEDA_UGM_2018.pdf]

AC-coupling vs DC-coupling

TODO 📅

Linearity & Even-Order Distortion

Odd-order distortion: symmetry

Even-Order Distortion: non-symmetry (Effect of Mismatch)

S. Stegemann, W. Mathis. MOS-AK 2012: Interference and Distortion Analysis for Nonlinear Analog Circuits [https://www.mos-ak.org/dresden_2012/publications/T8_Stegemann_MOS-AK_Desden_12.pdf]

Ali Sheikholeslami. A-SSCC 2024 insight: Noise and Distortion, [https://youtu.be/bvsJgHJ19jI?si=1CKDJvTy5EQdPLB4]

B. Razavi, "Design considerations for direct-conversion receivers," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]

[http://cc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter_09_Nonlinearity%20and%20Mismatch.pdf]

PAM4

Eye-Diagram and Bit-Error-Ratio (BER)

Noman Hai, Synopsys. CICC 2025 Circuit Insights: Basics of Wireline Transmitter Circuits [https://youtu.be/oofViBGlrjM?si=WZnOqtDVG3iDnBHI]

JTOL btw DSP-based vs Analog PAM4 RX

CC Chen, Why Analog PAM4 Receiver? [https://youtu.be/J2ojSMYiuBs?si=7y41W91ciIw_hme2]

challenges in DSP-based SerDes

Parallel implementation

Loop-Unrolling DFE

Corresponding to the three distinct voltage thresholds in the PAM4 systems, it would need 12 slicers, 3 multiplexers, and one thermometer-to-binary decoder in each deserialized data path, even if only one tap of the DFE is unrolled

Look-Ahead Multiplexing DFE

The look-ahead multiplexing technique brings the key benefit that the timing constraint can be significantly relaxed, as the iteration bound is doubled at the expense of extra hardware

Synopsys Italia, Tech Talk: Introduction to DSP-based SerDes [https://youtu.be/puEP0DlVZGI?si=lFiu1Kl4AKsg3O9f]

Chen, Kuan-Chang (2022) Energy-Efficient Receiver Design for High-Speed Interconnects. Dissertation (Ph.D.), California Institute of Technology. [https://thesis.library.caltech.edu/14318/9/chen_kuan-chang_2022_thesis_final.pdf]

Trellis Coding

TODO 📅

Convolutional Code

TODO 📅

Forward Error Correction (FEC)

It is called "forward" error correction because it can correct errors even in the common situations where there is no backward channel

Keysight Technologies. Tutorial – Why Use Forward Error Correction (FEC) [https://youtu.be/56nF4c61KR0?si=jYJSH50q9M3pIvQt]

Paul McLellan, What the FEC is Forward Error Correction? [https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/fec]

Baseline Wander

TODO 📅

Pete Anslow, Ciena. Baseline wander with FEC [https://www.ieee802.org/3/bs/public/17_05/anslow_3bs_03_0517.pdf]

Vladimir Dmitriev-Zdorov. Baseline Wander, its Time Domain and Statistical Analysis [https://ibis.org/summits/feb19/dmitriev-zdorov.pdf]

Pavel Zivny, Tektronix. Baseline Wander: Systematic Approach to Rapid Simulation and Measurement [pdf]

Update on Performance Studies of 100 Gigabit Ethernet Enabled by Advanced Modulation Formats [https://www.ieee802.org/3/bm/public/sep12/wei_01_0912_optx.pdf]

Sampling Front-End (SFE) Pulse Response

sweep the setup time between ideal pulse input and clock, sample the output of SFE at falling edge

ISI & DDJ filtering

Modulation and SNR

Data and noise mutually uncorrelated

\[ x_{RX,n}[p] = d[p]h_{RX}[0] +\sum \text{ISI} + n[p] \]

"ISI cancellation" based equalization is conceptually more straightforward but suffers from SNR penalty or error propagation

Jitter Amplification by Passive Channels

CDR Loop Latency

loop latency is represented as \(e^{-sD}\) in linear model

Sensitivity to Loop Latency

Enhancing Resolution with a \(\Delta \Sigma\) Modulator

Sub-Resolution Time Averaging

\(\Delta \Sigma\) modulator effectively dithers the LSB bit between zero and one, such that you can get the effective resolution of a much higher resolution DAC in the number of bits

Decimation

how they affect sampling phase

DLF's input bit-width can be reduced by decimating BBPD's output. Decimation is typically performed by realizing either majority voting (MV) or boxcar filtering.

Note that deserialization is inherent to both MV and boxcar filtering

• Decimation is commonly employed to alleviate the high-speed requirement. However, decimation increases loop-latency which causes excessive dither jitter.
• Decimation is basically, widen the data and slowing it down
• Decimating by \(L\) means frequency register only added once every \(L\) UI, thus integral path gain reduced by \(L\) in linear model
• proportional path gain is unchanged

CDR Linear Model

condition:

Linear model of the CDR is used in a frequency lock condition and is approaching to achieve phase lock

Using this model, the power spectral density (PSD) of jitter in the recovered clock \(S_{out}(f)\) is \[ S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f) \] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they come from independent sources.

Jitter Transfer

\[ H_T(s) = \frac{\varphi_{out}(s)}{\varphi_{in}(s)}|_{\varphi_{vco}=0}=\frac{K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}}{s^2+K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}} \]

Using below notation \[\begin{align} \omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\ \xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2} \end{align}\]

We can rewrite transfer function as follows \[ H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2} \]

The jitter transfer represents a low-pass filter whose magnitude is around 1 (0 dB) for low jitter frequencies and drops at 20 dB/decade for frequencies above \(\omega_n\)

• the recovered clock track the low-frequency jitter of the input data
• the recovered clock DONT track the high-frequency jitter of the input data

The recovered clock does not suffer from high-frequency jitter even though the input signal may contain high-frequency jitter, which will limit the CDR tolerance to high-frequency jitter.

Jitter Peaking in Jitter Transfer Function

The peak, slightly larger than 1 (0dB) implies that jitter will be amplified at some frequencies in the CDR, producing a jitter amplitude in the recovered clock, and thus also in the recovered data, that is slightly larger than the jitter amplitude in the input data.

This is certainly undesirable, especially in applications such as repeaters.

Jitter Generation

If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the recovered clock comes directly from the VCO jitter. The transfer function that relates the VCO jitter to the recovered clock jitter is known as jitter generation. \[ H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi \omega_n s+\omega_n^2} \] Jitter generation is high-pass filter with two zeros, at zero frequency, and two poles identical to those of the jitter transfer function

Jitter Tolerance

To quantify jitter tolerance, we often apply a sinusoidal jitter of a fixed frequency to the CDR input data and observe the BER of the CDR

The jitter tolerance curve DONT capture a CDR's true tolerance to random jitter. Because we are applying "sinusoidal" jitter, which is deterministic signal.

We can deal only with the jitter's amplitude and frequency instead of the PSD of the jitter thanks to deterministic sinusoidal jitter signal. \[ JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad \text{for a fixed BER} \] Where the subscript \(\text{pp-max}\) indicates the maximum peak-to-peak amplitude. We can further expand this equation as follows \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot |\varphi_e(f)|_{pp-max} \]

Relative jitter, \(\varphi_e\) must be less than 1UIpp for error-free operation

In an ideal CDR, the maximum peak-to-peak amplitude of \(|\varphi_e(f)|\) is 1UI, i.e.,\(|\varphi_e(f)|_{pp-max}=1UI\)

Accordingly, jitter tolerance can be expressed in terms of the number of UIs as \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad \text{[UI]} \] Given the linear CDR model, we can write \[ JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad \text{[UI]} \] Expand \(H_{LF}(f)\) for the CDR, we can write \[ JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) - \left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]} \]

At frequencies far below and above the natural frequency, the jitter tolerance can be approximated by the following \[ JTOL(f) = \left\{ \begin{array}{cl} \left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\ 1 & : \ f\gg f_n \end{array} \right. \]

the jitter tolerance at very high jitter frequencies is limited to 1UIpp

OJTF

Concepts of JTF and OJTF

Simplified Block Diagram of a Clock-Recovery PLL

Jitter Transfer Function (JTF)

• Input Signal Versus Recovered Clock
• JTF, by jitter frequency, compares how much input signal jitter is transferred to the output of a clock-recovery's PLL (recovered clock)
  • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter that is faithfully transferred (closed-loop gain) to the clock recovery PLL's output signal. JTF in this situation is approximately 1.
  • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in decreasing jitter (open-loop gain) on the clock recovery PLL's output, because the jitter is filtered out and no longer reaches the PLL's VCO

Observed Jitter Transfer Function

• Input Signal Versus Sampled Signal
• OJTF compares how much input signal jitter is transferred to the output of a receiver's decision making circuit as effected by a clock recovery's PLL. As the recovered clock is the reference for detecting the input signal
  • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter on the recovered clock which reduces the amount of jitter that can be detected. The input signal and clock signal are closer in phase
  • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in reduced jitter on the recovered clock which increases the amount of jitter that can be detected. The input signal and clock signal are more out of phase. Jitter that is on both the input and clock signals can not detected or is reduced

JTF and OJTF for 1st Order PLLs

The observed jitter is a complement to the PLL jitter transfer response OJTF=1-JTF (Phase matters!)

OTJF gives the amount of jitter which is tracked and therefore not observed at the output of the CDR as a function of the jitter rate applied to the input.

Jitter Measurement

\[ J_{\text{measured}} = JTF_{\text{DUT}} \cdot OJTF_{\text{instrument}} \]

The combination of the OJTF of a jitter measurement device and the JTF of the clock generator under test gives the measured jitter as a function of frequency.

For example, a clock generator with a type 1, 1st order PLL measured with a jitter measurement device employing a golden PLL is \[ J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2} \]

Accurate measurement of the clock JTF requires that the OJTF cutoff of the jitter measurement be significantly below that of the clock JTF and that the measurement is compensated for the instrument's OJTF.

The overall response is a band pass filter because the clock JTF is low pass and the jitter measurement device OJTF is high pass.

The compensation for the instrument OJTF is performed by measuring the jitter of the reference clock at each jitter rate being tested and comparing the reference jitter with the jitter measured at the output of the DUT.

The lower the cutoff frequency of the jitter measurement device the better the accuracy of the measurement will be.

The cutoff frequency is limited by several factors including the phase noise of the DUT and measurement time.

Digital Sampling Oscilloscope

How to analyze jitter:

• TIE (Time Interval Error) track
• histogram
• FFT

TIE track provides a direct view of how the phase of the clock evolves over time.

histogram provides valuable information about the long term variations in the timing.

FFT allows jitter at specific rates to be measured down to the femto-second range.

Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop bandwidth minimizes the response error

reference

Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and Phase Noise: A Circuits and Systems Perspective.” (2018).

neuhelium, 抖动、眼图和高速数字链路分析基础 URL: http://www.neuhelium.com/ueditor/net/upload/file/20200826/DSOS254A/03.pdf

Keysight JTF & OJTF Concepts, https://rfmw.em.keysight.com/DigitalPhotonics/flexdca/FlexPLL-UG/Content/Topics/Quick-Start/jtf-pll-theory.htm?TocPath=Quick%20Start%7C_____4

Complementary Transmitter and Receiver Jitter Test Methodlogy, URL: https://www.ieee802.org/3/bm/public/mar14/ghiasi_01_0314_optx.pdf

SerDesDesign.com CDR_BangBang_Model URL: https://www.serdesdesign.com/home/web_documents/models/CDR_BangBang_Model.pdf

M. Schnecker, Jitter Transfer Measurement in Clock Circuits, LeCroy Corporation, DesignCon 2009. URL: http://cdn.teledynelecroy.com/files/whitepapers/designcon2009_lecroy_jitter_transfer_measurement_in_clock_circuits.pdf

Link Budgets

VCO model

TODO 📅

respone to vctrl focus on phase

[https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va]

ADC Spec

TODO 📅

ENOB - Not sufficient & not accurate enough

• Based on SNDR
• Assume unbounded Gaussian distribution

quantization noise is ~ bounded uniform distribution

Using unbounded Gaussian -> pessimistic BER prediction

AFE Nonlinearity

"total harmonic distortion" (THD) in AFE

Relative to NRZ-based systems, PAM4 transceivers require more stringent circuit linearity, equalizers which can implement multi-level inter-symbol interference (ISI) cancellation, and improved sensitivity

Because if it compresses, it turns out you have to use a much more complicated feedback filter. As long as it behaves linearly, the feedback filter itself can remain a linear FIR

Linearity can actually be a critical constraint in these signal paths, and you really want to stay as linear as you can all the way up until the point where you've canceled all of the ISI

A. Roshan-Zamir, O. Elhadidy, H. -W. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sept. 2017 [https://people.engr.tamu.edu/spalermo/ecen689/2017_reconfigurable_16_32Gbps_NRZ_PAM4_SERDES_roshanzamir_jssc.pdf]

Hongtao Zhang, designcon2016. "PAM4 Signaling for 56G Serial Link Applications − A Tutorial"[https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers"

BER with Quantization Noise

\[ \text{Var}(X) = E[X^2] - E[X]^2 \]

Impulse Response or Pulse Response

TX FFE

TX FFE suffers from the peak power constraint, which in effect attenuates the average power of the outgoing signal - the low-frequency signal content has been attenuated down to the high-frequency level

[https://www.signalintegrityjournal.com/articles/1228-feedforward-equalizer-location-study-for-high-speed-serial-systems]

S. Palermo, "CMOS Nanoelectronics Analog and RF VLSI Circuits," Chapter 9: High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems, McGraw-Hill, 2011.

Eye-Opening Monitor (EOM)

An architecture that evaluates the received signal quality

data slicers, phase slicers, error slicers, scope slicers

Analui, Behnam & Rylyakov, Alexander & Rylov, Sergey & Meghelli, Mounir & Hajimiri, Ali. (2006). A 10-Gb/s two-dimensional eye-opening monitor in 0.13-??m standard CMOS. Solid-State Circuits, IEEE Journal of. 40. 2689 - 2699, [https://chic.caltech.edu/wp-content/uploads/2013/05/B-Analui_JSSC_10-Gbs_05.pdf]

reference

G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link Foundations Standards, Link Budgets & Models," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95 [https://youtu.be/OABG3u2H2J4?si=CxryBSGbxrUpZNBT]

Paul Muller Yusuf Leblebici École Polytechnique Fédérale de Lausanne (EPFL). Pattern generator model for jitter-tolerance simulation; VHDL-AMS models

Savo Bajic, ECE1392, Integrated Circuits for Digital Communications: StatOpt in Python [https://savobajic.ca/projects/academic/statopt]

Anritsu Company, "Measuring Channel Operating Margin," 2016. [https://dl.cdn-anritsu.com/en-us/test-measurement/files/Technical-Notes/White-Paper/11410-00989A.pdf]

JLSD - Julia SerDe [https://github.com/kevjzheng/JLSD]

Kiran Gunnam, Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part I: Modeling," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 97-109, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10608184]

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part II: Optimization and Performance Assessment," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]

G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10184121]

loop dynamic

Dithering Jitter in Bang-bang PLL

hunting jitter is also called as dithering jitter the time error between data clock and input data

• proportional gain
• loop latency

where the proportional gain (\(K_P\)), heavily damped systems means that \(K_P \gg K_I\)

Hanumolu, Pavan Kumar. 2006. Design Techniques for Clocking High Performance Signaling Systems. : Oregon State University. https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]

Hae-Chang Lee, "An Estimation Approach To Clock And Data Recovery" [https://www-vlsi.stanford.edu/people/alum/pdf/0611_HaechangLee_Phase_Estimation.pdf]

R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” in Phase-Locking in High-Performance Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]

J. Kim, Design of CMOS Adaptive-Supply Serial Links, Ph.D. Thesis, Stanford University, December 2002. [https://www-vlsi.stanford.edu/people/alum/pdf/0212_Kim_______Design_Of_CMOS_AdaptiveSu.pdf]

P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps Digital Clock and Data Recovery Circuit," IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]

Da Dalt N. A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]

Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phasefrequency detection. IEEE Transactions on Circuits and Systems II: Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]

CDR Loop Latency

Denoting the CDR loop latency by \(\Delta T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The resulting right-half-plane zero, \(f_z\) degrades the phase margin and must remain about one decade beyond the BW \[ f_z\simeq \frac{1}{2\pi \Delta T} \]

This assumption is true in practice since the bandwidth of the CDR (few mega Hertz) is much smaller than the data rate (multi giga bits/second).

Fernando , Marvell Italy."Considerations for CDR Bandwidth Proposal" [https://www.ieee802.org/3/bs/public/16_03/debernardinis_3bs_01_0316.pdf]

Loop Bandwidth

The closed-loop −3-dB bandwidth is sometimes called the “loop bandwidth”

Continuous-Time Approximation Limitations

A rule of thumb often used to ensure slow changes in the loop is to select the loop bandwidth approximately equal to one-tenth of the input frequency.

Gardner, F.M. (1980). Charge-Pump Phase-Lock Loops. IEEE Trans. Commun., 28, 1849-1858.

Homayoun, Aliakbar and Behzad Razavi. “On the Stability of Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and Systems I: Regular Papers 63 (2016): 741-750.

N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021

Deog-Kyoon Jeong, Topics in IC Design - 2.1 Introduction to Phase-Locked Loop [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%202%20-%20Charge-Pump%20PLL%2C%20Freuqency%20Synthesizers%2C%20and%20SSCG.pdf]

Limit Cycle Oscillation

limit cycles imply self-sustained oscillators due nonlinear nature

Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]

BB PD

It's ternary, because early, late and no transition

Linearing BB-PD

BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),

BB only produces output for a transition and this de-rates the gain. Transition density = 0.5 for random data

\[ K_{BB} = \frac{1}{2}\frac {\partial \mu}{\partial \phi} \]

where \(\mu = (1)\times \mathrm{P}(\text{late}|\phi) + (-1)\times \mathrm{P}(\text{early}|\phi)\)

Both jitter and amplitude noise distribution are same, just scaled by slope

Self-Noise Term

One price we pay for BB PD versus linear PD is the self-noise term. For small phase errors BB output noise is the full magnitude of the sliced data

The PD output should be almost 0 for small phase errors. i.e. ideal PD output noise should be 0

\[ \sigma_{BB}^2 = 1^2 \cdot \mathrm{P}(\text{trans}) + 0^2\cdot (1-\mathrm{P}(\text{trans})) = 0.5 \]

Input referred jitter from BB PD is proportional to incoming jitter

John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and Data Recovery

Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems. [pdf]

- Clock and Data Recovery for Serial Data Communications, focusing on bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]

Digital CDR Category

• DCO part is analogous so that it cannot be perfectly modeled
• Digital-to-phase converter is well-defined phase output, thus, very good to model real situation

DCO

limit cycle

Z-domain modeling

The difference equation is \[ \phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi \] z-transform is \[ \frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}} \]

where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)

\(\Delta \Sigma\)-dithering in DCO

Quantization noise

Here, \(\alpha_T\) is data transition density

BBPD quantization noise

DAC quantization noise

M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]

Time to Digital Converter (TDC)

Digital to Phase Converter (DPC)

IIR low pass filter

simple approximation: \[ z = 1 + sT \] bilinear-z transform \[ z =\frac{}{} \]

Peak-to-peak jitter in ADPLL with BBPD

Accumulate-and-dump (AAD) decimator

accumulating the input for \(N\) cycles and then latching the result and resetting the integrator

It adds up \(N\) succeeding input samples at rate \(1/T\) and delivers their sum in a single sample at the output. Therefore, the process comprises a filter (in the accumulation) and a down-sampler (in the dump)

Moving Average and CIC Filters

cascade-integrator-comb (CIC) decimator

TODO 📅

An Intuitive Look at Moving Average and CIC Filters [web, code]

A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

FAQ

PLL vs. CDR

PLL or FD(Frequency Detector) for frequency detecting in CDR

reference

J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]

P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and Circuits" [slides]

Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery Circuits"

Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]

M. Perrott. 6.976 High Speed Communication Circuits and Systems (lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT OpenCourseWare, [lec21.pdf]

Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental Concepts To Future Trends" [T5.pdf]

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

—, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

Fernando De Bernardinis, eSilicon. "Introduction to DSP Based Serial Links" [https://www.corsi.univr.it/documenti/OccorrenzaIns/matdid/matdid835215.pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10630516]

Marinaci, Stefano. "Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate" [https://cds.cern.ch/record/2870334/files/CERN-THESIS-2023-147.pdf]

P. Palestri et al., "Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol. 41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]

M.H. Perrott. CICC 2009 "Tutorial on Digital Phase-Locked Loops" [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

—, Short Course On Phase-Locked Loops and Their Applications Day 4, PM Lecture "Examples of Leveraging Digital Techniques in PLLs" [https://www.cppsim.com/PLL_Lectures/day4_pm.pdf]

—, Short Course On Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA "Digital Frequency Synthesizers" [https://www.cppsim.com/PLL_Lectures/digital_pll.pdf]

Gain Kim, "Equalization, Architecture, and Circuit Design for High-Speed Serial Link Receiver" [pdf]

Deog-Kyoon Jeong Topics in IC(Wireline Transceiver Design) - 3.1. Introduction to All Digital PLL [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

—, Topics in IC(Wireline Transceiver Design) - 6.1 Introduction to Clock and Data Recovery [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

High-speed Serial Interface Lect. 16 – Clock and Data Recovery 3 [http://tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect16_CDR-3.pdf]

Shiva Kiran. Phd thesis 2018. Modeling and Design of Architectures for High-Speed ADC-Based Serial Links [https://hdl.handle.net/1969.1/192031]

—, et al., "Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 3, pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]

K. Zheng, "System-Driven Circuit Design for ADC-Based Wireline Data Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]

S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo, "Statistical modeling of metastability in ADC-based serial I/O receivers," 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems [pdf]

John M. Cioffi. "Decoding Methods" [https://cioffi-group.stanford.edu/doc/book/chap7.pdf]

—. "Equalization" [https://cioffi-group.stanford.edu/doc/book/chap3.pdf]

Iain. [https://youtu.be/rnjy4_gXLAg?si=PC3aowaon-e_mhXX]

—. [https://youtu.be/IJE94FhyygM?si=BMMQ-GmirBWNf4ep]

Phase Noise Definition

Eq. (3.25) is widely adopted by industry and academia

using the narrow angle assumption, the two definitions above are equivalent

If the narrow angle condition is not satisfied, however, the two definitions differ

Phase Noise Profile

Power Spectral Density of Brownian Motion despite non-stationary [https://dsp.stackexchange.com/a/75043/59253]

white noise

\(1/f^2\) Phase Noise Profile

Sudhakar Pamarti. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8?si=tbav3J2yag38HyZx]

flicker noise

\(1/f^3\) Phase Noise Profile

\[ S_{\phi n} = \frac{K}{f}\left(\frac{K_{VCO}}{2\pi f}\right)^2 \propto \frac{1}{f^3} \]

[https://dsp.stackexchange.com/a/75152/59253]

Free-running Oscillator

Note that \(f_{min}\) is related to the observation time. The longer we observe the device under test, the smaller \(f_{min}\) must be

Ali Sheikholeslami ISSCC 2008 T5: Basics of Chip-to-Chip and Backplane Signaling [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T5.pdf]

B. Casper and F. O'Mahony, "Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links-A Tutorial," in IEEE Transactions on Circuits and Systems I. [https://people.engr.tamu.edu/spalermo/ecen689/clocking_analysis_hs_links_casper_tcas1_2009.pdf]

Lorentzian spectrum

We typically use the two spectra, \(S_{\phi n}(f)\) and \(S_{out}(f)\), interchangeably, but we must resolve these inconsistencies. voltage spectrum is called Lorentzian spectrum

The periodic signal \(x(t)\) can be expanded in Fourier series as:

Assume that the signal is subject to excess phase noise, which is modeled by adding a time-dependent noise component \(\alpha(t)\). The noisy signal can be written \(x(t+\alpha(t))\), the added excess phase \(\phi(t)= \frac{\alpha(t)}{\omega_0}\)

The autocorrelation of the noisy signal is by definition:

The autocorrelation averaged over time results in:

By taking the Fourier transform of the autocorrelation, the spectrum of the signal \(x(t + \alpha(t))\)​ can be expressed as

It is also interesting to note how the integral in Equation 9.80 around each harmonic is equal to the power of the harmonic itself \(|X_n|^2\)

The integral \(S_x(f)\) around harmonic is \[\begin{align} P_{x,n} &= \int_{f=-\infty}^{\infty} |X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega +n\omega_0)^2}df \\ &= |X_n|^2\int_{\Delta f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f \\ &= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta f}{\beta})|_{-\infty}^{\infty} \\ &= |X_n|^2 \end{align}\]

The phase noise does not affect the total power in the signal, it only affects its distribution

• Without phase noise, \(S_v(f)\) is a series of impulse functions at the harmonics of \(f_o\).
• With phase noise, the impulse functions spread, becoming fatter and shorter but retaining the same total power

[https://community.cadence.com/cadence_technology_forums/f/rf-design/51484/comparing-transient-noise-pnoise-and-pnoise-with-lorentian-approximation-of-a-ring-oscillator/1382911]

Phase perturbed by a stationary noise with Gaussian PDF

If keep \(\phi_{rms}\) in \(R_x(\tau)\), i.e. \[ R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0 \tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0 \tau)(1+R_\phi(\tau)) \] The PSD of the signal is \[ S_x(f) = \mathcal{F} \{ R_x(\tau) \} = \frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] + \frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right] \] ❗❗above Eq isn't consistent with stationary white noise process - the following section

Phase perturbed by a stationary WHITE noise process

Assuming that the delay line is noiseless

Expanding the cosine function we get \[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\} \end{align}\]

where, both the process \(\phi(t)-\phi(t-\tau)\) and \(\phi(t)+\phi(t-\tau)\) are independent of time \(t\), i.e. \(E[\cos(\phi(t)+\phi(t-\tau))] = m_{\cos+}(\tau)\), \(E[\cos(\phi(t)-\phi(t-\tau))] = m_{\cos-}(\tau)\), \(E[\sin(\phi(t)+\phi(t-\tau))] = m_{\sin+}(\tau)\) and \(E[\sin(\phi(t)-\phi(t-\tau))] = m_{\sin-}(\tau)\)

we obtain \[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) - \sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D))m_{\cos+}(\tau) - \sin(4\pi f_0(t+\tau/2-T_D))m_{\sin+}(\tau) \right\} \end{align}\]

The second term in the above expression is periodic in \(t\) and to estimate its PSD, we compute the time-averaged autocorrelation function \[ R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) - \sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\} \]

After nontrivial derivation

Phase perturbed by a Weiner process

The phase process \(\phi(t)\) is also gaussian but with an increasing variance which grows linearly with time \(t\)

\[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D)E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi f_0(t+\tau/2-T_D)E[\sin(\phi(t)+\phi(t-\tau))] \right\} \end{align}\]

The spectrum of \(y(t)\) is determined by the asymptotic behavior of \(R_y(t,\tau)\) as \(t\to \infty\)

❗❗ \(\lim_{t\to\infty}R_y(t,\tau)\) rather than time-averaged autocorrelation function of cyclostationary process, ref. Demir's paper

We define \(\zeta(t, \tau)=\phi(t)+\phi(t-\tau) = \phi(t)-\phi(t-\tau) + 2\phi(t-\tau)\), the expected value of \(\zeta(t,\tau)\) is 0, the variance is \(\sigma_{\zeta}^2=(k\sigma)^2(\tau + 4(t-\tau))=(k\sigma)^2(4t-3\tau)\) \[ E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi \sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta = e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)} \] i.e., \(\lim _{t\to \infty} E[\cos(\zeta(t,\tau))] = \lim_{t\to \infty}e^{-(k\sigma)^2(4t-\tau)} = 0\)

For \(E[\sin(\zeta(t,\tau))]\), we have \[ E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi \sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta \] i.e., \(E[\sin(\zeta(t,\tau))]\) is odd function, therefore \(E[\sin(\zeta(t,\tau))]=0\)

Finally, we obtain

Amplitude Noise

P.E. Allen - 2003. ECE 6440 - Frequency Synthesizers: Lecture 160 – Phase Noise - II [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L160-PhNoII(2UP).pdf]

reference

A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," in IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [paper], [slides]

—, "Corrections to "A General Theory of Phase Noise in Electrical Oscillators"" [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=678662]

—, RFIC2024 "Noise in Oscillators from Understanding to Design"

Carlo Samori, "Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-VCO-short.pdf]

—, "Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits," in IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 81-91, Fall 2016 [https://picture.iczhiku.com/resource/eetop/whIgTikLswaaTVBv.pdf]

—, ISSCC2016, "Understanding Phase Noise in LC VCOs"

A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in oscillators: a unifying theory and numerical methods for characterization," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674, May 2000 [https://sci-hub.se/10.1109/81.847872]

Dalt, Nicola Da and Ali Sheikholeslami. "Understanding Jitter and Phase Noise: A Circuits and Systems Perspective." (2018) [https://picture.iczhiku.com/resource/eetop/WykRGJJoHQLaSCMv.pdf]

F. L. Traversa, M. Bonnin and F. Bonani, "The Complex World of Oscillator Noise: Modern Approaches to Oscillator (Phase and Amplitude) Noise Analysis," in IEEE Microwave Magazine, vol. 22, no. 7, pp. 24-32, July 2021 [https://iris.polito.it/retrieve/handle/11583/2903596/e384c433-b8f5-d4b2-e053-9f05fe0a1d67/MM%20noise%20-%20v5.pdf]

Poddar, Ajay & Rohde, Ulrich & Apte, Anisha. (2013). How Low Can They Go?: Oscillator Phase Noise Model, Theoretical, Experimental Validation, and Phase Noise Measurements. Microwave Magazine, IEEE. [http://time.kinali.ch/rohde/noise/how_low_can_they_go-2013-poddar_rohde_apte.pdf]

Pietro Andreani, "RF Harmonic Oscillators Integrated in Silicon Technologies" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto.pdf]

Chembiyan T, "Brownian Motion And The Oscillator Phase Noise" [link]

—, "Jitter and Phase Noise in Oscillators" [link]

—, "Jitter and Phase Noise in Phase Locked Loops" [link]

—, "PLLs and reference spurs" [link]

Godone, A. & Micalizio, Salvatore & Levi, Filippo. (2008). RF spectrum of a carrier with a random phase modulation of arbitrary slope. [https://sci-hub.se/10.1088/0026-1394/45/3/008]

Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices, 2020)

• proportional term (P) depends on the present error
• integral term (I) depends on past errors
• derivative term (D) depends on anticipated future errors

PID controller makes use of linear extrapolation of the measured output

PI controller does not make use of any prediction of the future state of the system

The prediction by linear extrapolation (D) can generate large undesired control signals because measurement noise is amplified, that's why D is not used widely

---

limit cycle

reference

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. Feedback Control of Dynamic Systems, Global Edition (8th Edition). Pearson. [https://mrce.in/ebooks/Feedback%20Control%20of%20Dynamic%20Systems%208th%20Ed.pdf]

Åström, K.J. & Murray, Richard. (2021). Feedback Systems: An Introduction for Scientists and Engineers Second Edition [https://www.cds.caltech.edu/~murray/books/AM08/pdf/fbs-public_24Jul2020.pdf]

Yan Lu, ISSCC2021 T10: Fundamentals of Fully Integrated Voltage Regulators [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T10.pdf]

charge pumps are capacitive DC-DC converters. The two most common switched capacitor voltage converters are the voltage inverter and the voltage doubler circuit

voltage doubler

output buffer capacitor

To achieve a stable DC output voltage

Step-Wise Ramp-Up

without load

\[ V_{in} C_p + V_{out,n-1}C_o = (V_{out,n}-V_{in})C_p + V_{out,n}C_o \]

We derive a recursive equation that describes the output voltage \(V_{out,n}\) after the \(n\)th clock cycle \[ V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o} \]

Voltage Ripple & Droop

\[\begin{align} (V_t - V_h)(C_p + C_o) &= \frac{I_{load}}{2f_{sw}} \\ (V_h - V_b)C_o &= \frac{I_{load}}{2f_{sw}} \end{align}\]

we obtain \[ V_t - V_b = \frac{I_{load}}{f_{sw}C_o}\left(1 - \frac{C_p}{2(C_p + C_o)}\right) \] That is, peak-to-peak ripple \[ \Delta V_{out,p2p} \approx \frac{I_{load}}{f_{sw}C_o} \space\space\space\space \text{if}\space\space C_o \gg C_p \]

Then, with aforementioned Step-Wise Ramp-Up equation, \(V_t = \frac{2V_{in}C_p + V_bC_o}{C_p + C_o}\) \[\begin{align} V_b &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p}{2C_o}\right) \\ V_t &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 - \frac{C_p}{2(C_p+C_o)}\right) \end{align}\]

Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right) \approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p} \] which results in a simple expression for the output voltage droop

\[ \Delta V_{out} = \frac{I_{load}}{f_{sw}C_p} \]

The charge pump can be modeled as a voltage source with a source resistance \(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage drop across \(R_\text{out}\) due to the load current:

\[ R_{out} = \frac{\Delta V_{out}}{I_{load}} = \frac{1}{f_{sw}C_p} \]

multiphase CP

\[ (V_t - V_b) (C_p + C_o) = I_{load}\Delta t \]

Therefore peak-to-peak ripple \[ \Delta V_{out,p2p} = \frac{I_{load}\Delta t}{C_p+C_o} = \frac{I_{load}\Delta t}{C_{tot}} \]

where \(C_{tot} = C_p+C_o\)

with \[ \left\{ \begin{array}{cl} V_b &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} \\ V_t &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} + \frac{I_{load}\Delta t}{C_p+C_o} \end{array} \right. \]

Then \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}\Delta t}{C_p}\cdot \frac{C_p+2C_o}{2C_p+2C_o} \approx 2V_{in} - \frac{I_{load}\Delta t}{C_p} \] That is output voltage droop \[ \Delta V_{out} = \frac{I_{load}\Delta t}{C_p} \]

reference

Bernhard Wicht, "Design of Power Management Integrated Circuits". 2024 Wiley-IEEE Press

Breussegem, T. v., & Steyaert, M. (2013). CMOS integrated capacitive DC-DC converters. Springer

Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023).

Anton Bakker, Tim Piessens., ISSCC2014 T9: Charge Pump and Capacitive DC-DC Converter Design

Wicht, B., ISSCC2020 T2: Analog Building Blocks of DC-DC Converters [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T2Visuals.pdf]

Hoi Lee, ISSCC2018 T8: Fundamentals of Switched-Mode Power Converter Design [slides,transcript]

alternative view of sampling, assuming DC value is \(A\)

• \(x_c(t)\) and \(x_s(t)\)

  \(\overline{x_c} = A\); \(\overline{x_s}=\frac{A}{T}\): therefore \(X_s(j0) = \frac{1}{T}X_c(j0)\)

• \(x[n]\) and \(x_d[n]\)

  \(\overline{x} = A\); \(\overline{x_d}=\frac{A}{2}\): therefore \(X_d(e^{j0}) = \frac{1}{2}X(e^{j0})\)

expander

• \(x[n]\) and \(x_e[n]\)

  \(\overline{x} = A\); \(\overline{x_e}=A\): therefore \(X_e(e^{j0}) = X(e^{j0})\)

  Fourier transform of the output of the expander is a frequency-scaled version of the Fourier transform of the input

Subsampling or Downsampling

• Eqs. (4.72)

  the superposition of an infinite set of amplitude-scaled copies of \(X_c(j\Omega)\), frequency scaled through \(\omega = \Omega T_d\) and shifted by integer multiples of \(2\pi\)

• Eq. (4.77)

  the superposition of \(M\) amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by \(M\) and shifted by integer multiples of \(2\pi\)

downsampled by a factor of \(M = 2\)

Upsampling or Zero Insertion

Assuming \(X(e^{j\omega_1}) = U_f(e^{j\omega_1})\) with \(\omega_1 = \Omega T_1\), upsampled by ratio \(L\), then obtain

\[ Y(e^{j\omega_2})=X(e^{j\omega_2 L}) = U_f(e^{j\omega_2 L}) \]

by EQ. (4.85), i.e. substitute \(\omega_1\) with \(\omega_2 L\), where with \(\omega_2 = \Omega T_2\) and \(T_2 L = T_1\)

Provided that \(\xi = e^{j\omega_1}\) and \(z = e^{j\omega_2}\), we have \(U_f(\xi)\) upsampled to \(U_f(z^L)\)

Interpolation filter

Pavan, Schreier and Temes, "Understanding Delta-Sigma Data Converters, Second Edition"

Markus Nentwig. Polyphase filter / Farrows interpolation [https://www.dsprelated.com/showarticle/22.php]

sampling identities

downsampling identity

upsampling identity

Polyphase Decomposition

where \(e_k[n]=h[nM+k]\)

Polyphase Implementation of Decimation Filters & Interpolation Filters

	Decimation system	Interpolation system
sampling identity

LPTV Implementation

TODO 📅

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a zero-order hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

Dr. Deepa Kundur, Multirate Digital Signal Processing: Part I [pdf, https://www.comm.utoronto.ca/dkundur/course/discrete-time-systems/]

ZOH interpolator

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a Zero-Order Hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

\[ F_1(z) = X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \]

Split the \(1:LM\) hold process into a \(1 : L\) hold followed by a \(1 : M\) hold \[ Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}} \] then \[\begin{align} F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\ &=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \end{align}\]

That is \(F_1(z)=F_2(z)\), i.e. they are equivalent

Random Signals & Multirate Systems

Balu Santhanam, Probability Theory & Stochastic Process 2020: Random Signals & Multirate Systems [https://ece-research.unm.edu/bsanthan/ece541/rand.pdf]

Decimation by Summing

proportional path

The loop gain of a proportional path is unchanged

In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is \[ LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}} \]

In (b), Accumulate-and-dump (AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \] Hence \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot \frac{1}{1-\eta^{-1}} \end{align}\]

After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align} \phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}} \end{align}\] i.e., \[ LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \]

When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx 1\)

Therefore \[ LG_b(z) \approx \frac{1}{1-z^{-1}} \]

In the end \[ LG_a(z) \approx LG_b(z) \]

Assume PD output is constant

integral path

integral path gain reduced by \(L\)

In (a), \(\phi_o(z)=\frac{1}{(1-z^{-1})^2}\), i.e. \[ LG_a(z) = \frac{1}{(1-z^{-1})^2} \]

In (b), after Accumulate-and-dump (AAD), \(\phi_(\eta)\) is \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \]

After frequency integrator and phase integrator \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \cdot \frac{1}{(1-\eta^{-1})^2} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \cdot \frac{1}{(1-\eta^{-1})^2} \end{align}\] Then \(\phi_f(z)\) is shown as below \[\begin{align} \phi_f(z) &= \phi_o(z^L)\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{(1-z^{-L})^2}\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} \end{align}\]

That is, \[ LG_b(z) = \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} = \frac{1}{L}\cdot LG_a(z) \]

Assume PD output is constant

\[ \lim_{n\to +\infty} \frac{\Delta P_1}{\Delta P_0} = \lim_{n\to +\infty}\frac{n+2L}{nL+\alpha L+\beta L^2} = \frac{1}{L} \]

Decimation by Voting

In above screenshot

1. \(K_D\) is just relative value
2. frug shall not be scaled by decimator factor

proved as below

DC gain \(K_B\) of summing (boxcar filter) is decimation factor \(M\) , voting gain \(K_V\) is about \(0.54K_b=0.54M\)

1. downsampling \(\frac{1}{M}\) and ZOH \(\frac{1-z^{-M}}{1-z^{-1}}\) can be canceled out at low frequency
2. decimation gain: accumulator \(\frac{1-z^{-M}}{1-z^{-1}}\) replaced with linearizing gain \(K_B\) and majority voting replaced with \(K_V\)

proportional path: \[\begin{align} LG_{ph} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{1-z^{-M}} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{1-z^{-M}} \end{align}\]

integral path: \[\begin{align} LG_{fr} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{(1-z^{-M})^2}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{(1-z^{-M})^2} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{(1-z^{-M})^2} \end{align}\]

J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

J. Sonntag and J. Stonick, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]

J. Liang, A. Sheikholeslami, "On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits" [https://tspace.library.utoronto.ca/bitstream/1807/91138/3/Liang_Joshua_201706_PhD_thesis.pdf]

J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]

J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]

M. M. Khanghah, K. D. Sadeghipour, D. Kelly, C. Antony, P. Ossieur and P. D. Townsend, "A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers [https://cora.ucc.ie/bitstreams/7ae5bfaa-8dd9-45a7-8276-99676b7b6078/download]

[CDR CIRCUIT-BLOCKS: DESIGN AND VERIFICATION USING VERILOG - 2.6. DECIMATOR]

Michael H. Perrott, Tutorial on Digital Phase-Locked Loops, CICC 2009, San Jose, CA, Sept. 13, 2009 [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

Liu, Tao, Tiejun Li, Fangxu Lv, Bin Liang, Xuqiang Zheng, Heming Wang, Miaomiao Wu, Dechao Lu, and Feng Zhao. 2021. "Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits" Electronics 10 [https://www.mdpi.com/2079-9292/10/16/1888/pdf?version=1628492599]

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1. [https://assets-eu.researchsquare.com/files/rs-1817774/v1_covered.pdf?c=1664188179]

Chen, Junkun, Youzhi Gu, Xinjie Feng, Runze Chi, Jiangfeng Wu, and Yongzhen Chen. 2024. "Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model" Electronics [https://mdpi-res.com/electronics/electronics-13-04218/article_deploy/electronics-13-04218-v2.pdf?version=1730106095]

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9910561]

TODO 📅

Tristate: \(\alpha=1\)

XOR: \(\alpha=1\)

\(\frac{1}{T}\) in Divider

Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]

\(\frac{1}{T}\) & \(T\) come from CT-DT & DT-CT

H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10630516]

Sonntag JSSC 2006

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clear;
close all;
clc;


Tb = 200e-12;
Ts = Tb*8;			% the decimation factor was 8
z = tf('z', Ts);

Kdpc = 1/2^9;
Kv = 8*0.54;
Kpd = 10.6;
phug = 2^-3;
frug = 2^-12;
Nel = 18;

options = bodeoptions;
options.FreqUnits = 'MHz';
options.XLim = [1e-2, 1e1];
options.YLim = [-10, 5];

L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-11;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-10;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

legend('frug=2^{-12}','frug=2^{-11}', 'frug=2^{-10}', 'FontSize',10)
grid on;
title('phase transfer function', 'FontSize', 12)
xlabel('frequency', 'FontSize',10)
ylabel('frequency response', 'FontSize',10)

Full View

Kpd, Kb, Kv

Both decimation factor and factor for voting are 4

• Kpd formula: 12.467; Kpd_bb_0 12.465
• Kpd_Kb: 49.860; Kpd_Kv 27.265
• Kb: 4.00; Kv 2.19

That is

1. gain of BoxCar is the decimation factor
2. Voting across 4 inputs had a 54% reduced gain relative to boxcar filter

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import numpy as np
from scipy.stats import norm
import itertools
from collections import defaultdict
import matplotlib.pyplot as plt

sigmai = 0.032  #UI, input jitter
Ptrans = 0.5    # Transition density
deci_factor = 4

phase_error = np.linspace(-0.1, 0.1, 201)     #UI, phase offset
pd_late = norm.cdf(phase_error/sigmai)
pd_early = 1.0 - pd_late
pd_avg = pd_late*1.0 - 1.0*pd_early

Kpd_bb = (pd_avg[1:] - pd_avg[:-1])/(phase_error[1:] - phase_error[:-1])*Ptrans
Kpd_bb_0 = np.max(Kpd_bb)

## by formula
Kpd_calc = 1.0/(sigmai*np.sqrt(2*np.pi))

print(f'Kpd formula: {Kpd_calc:.3f}; Kpd_bb_0 {Kpd_bb_0:.3f}')  # Kpd formula: 12.467; Kpd_bb_0 12.465

plt.figure()
plt.plot(phase_error, pd_avg, color='r', linewidth=3)
plt.title('!! PD average output vs timing offset(UI)')
plt.grid()
plt.show()


prob = np.zeros((phase_error.shape[0],3))
prob[:,0] = pd_early*Ptrans     # -1
prob[:,1] = 1.0 - Ptrans        # 0
prob[:,2] = pd_late*Ptrans      # 1

pd_out = np.array([-1.0,0.0,1.0])
idxs = list([[0,1,2] for _ in range(deci_factor)])
boxcar_avg = []
voting_avg = []
for i in range(phase_error.shape[0]):
    prob_i = prob[i,:]
    boxcar_tmp = 0.0
    voting_tmp = 0.0
    for idxs_tmp in itertools.product(*idxs):
        pd_list = pd_out[[idxs_tmp]]
        prob_list = prob_i[[idxs_tmp]]
        pd_sum = np.sum(pd_list)
        pd_vote = 1.0 if pd_sum > 0.0 else -1.0 if pd_sum <0.0 else 0.0
        prob_prod = np.prod(prob_list)
        boxcar_tmp += pd_sum*prob_prod
        voting_tmp += pd_vote*prob_prod
    boxcar_avg.append(boxcar_tmp)
    voting_avg.append(voting_tmp)

boxcar_avg = np.array(boxcar_avg)
voting_avg = np.array(voting_avg)

plt.figure()
plt.plot(phase_error,boxcar_avg, label='FIR BoxCar', color='r', linewidth=3)
plt.plot(phase_error,voting_avg, label='Voting', color='b', linewidth=3, linestyle='--')
plt.legend()
plt.title('!!PD+BoxCar / !!PD+Voting vs timing offset(UI)')
plt.grid()
plt.show()


Kpd_Kb = (boxcar_avg[1:] - boxcar_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_Kv = (voting_avg[1:] - voting_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_kb_0 = np.max(Kpd_Kb)
Kpd_kv_0 = np.max(Kpd_Kv)
print(f'Kpd_Kb: {Kpd_kb_0:.3f}; Kpd_Kv {Kpd_kv_0:.3f}')     # Kpd_Kb: 49.860; Kpd_Kv 27.265

plt.figure()
plt.plot(phase_error[:-1], Kpd_Kb, color='r', linewidth=3)
plt.plot(phase_error[:-1], Kpd_Kv, color='b', linewidth=3, linestyle='--')
plt.legend(['Kpd_Kb', 'Kpd_Kv'])
plt.title('Kpd*Kb / Kpd*Kv vs timing offset(UI)')
plt.grid()
plt.show()

Kb = Kpd_kb_0 / Kpd_bb_0
Kv = Kpd_kv_0 / Kpd_bb_0
print(f'Kb: {Kb:.2f}; Kv {Kv:.2f}')     # Kb: 4.00; Kv 2.19

reference

Alan V Oppenheim, Ronald W. Schafer. 2010. Discrete-Time Signal Processing, 3rd edition

R. E. Crochiere and L. R. Rabiner, "Multirate Digital Signal Processing", Prentice Hall, 1983.

John G. Proakis and Dimitris G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th edition, 2007.

D. Sundararajan. 2024. Digital Signal Processing: An Introduction 2nd Edition

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Switched Capacitor Circuits

Negar Reiskarimian. CICC 2025 Insight: Switched Capacitor Circuits [https://www.youtube.com/watch?v=SL3-9ZMwdJQ]

Integrator

TODO 📅

[https://www.eecg.utoronto.ca/~johns/ece1371/slides/10_switched_capacitor.pdf]

[https://www.seas.ucla.edu/brweb/papers/Journals/BRWinter17SwCap.pdf]

[https://class.ece.iastate.edu/ee508/lectures/EE%20508%20Lect%2029%20Fall%202016.pdf]

Push-Pull

TODO 📅

Rinaldo Castello, "LINEARIZATION TECHNIQUES FOR PUSH-PULL AMPLIFIERS" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/AMPLIFIERS_Stanf_Tor_2016_Last.pdf]

MOS parasitic Rd&Rs, Cd&Cs

Decrease the parasitic R&C

priority: \(R_s \gt R_d\), \(C_s \gt C_d\)

XCP as Negative Impedance Converter (NIC)

The Cross-Coupled Pair (XCP) can operate as an impedance negator [a.k.a. a negative impedance converter (NIC)]

A common application is to create a negative capacitance that can cancel the positive capacitance seen at a port, thereby improving the speed

\[ I_{NIC} =\frac{V_{im} - V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}} = \frac{-2V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}} \] Therefore \[ Z_{NIC} = \frac{V_{ip} - V_{im}}{I_{NIC}}=\frac{2V_{ip}}{I_{NIC}} =- \frac{2}{g_m}-\frac{1}{sC_c} \] half-circuit

If \(C_{gd}\) is considered, and apply miller effect. half equivalent circuit is shown as below

B. Razavi, "The Cross-Coupled Pair - Part III [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Issue. 1, pp. 10-13, Winter 2015. [https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine3.pdf]

S. Galal and B. Razavi, "10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18um CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2138-2146, Dec. 2003. [https://www.seas.ucla.edu/brweb/papers/Journals/G&RDec03_2.pdf]

source follower

A. Sheikholeslami, "Voltage Follower, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457

—, ESSCIRC2023 Circuit Insights [https://youtu.be/2xFIZM5_FPw?si=536cMdIXyIny27Uk]

—, CICC2025 Circuit Insights: From Simple to Super Source Follower [https://youtu.be/CWfMKltPIQ8?si=s0npv2GSQKYBv513]

Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits (5th. ed.). Wiley Publishing. [pdf]

Super-source follower (SSF)

Flipped Voltage Follower (FVF)

T&H buffer in ADC

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_flipped-voltage-follower-fvf-basics-activity-7118482840803020800-qwyX?utm_source=share&utm_medium=member_desktop]

Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.

Double differential Pair

\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end

assume input and reference common voltage are same

Pros of (b)

• larger input range i.e., \(\gt \pm \sqrt{2}V_\text{ov}\) of (a), it works even one differential is off due to lower voltage
• larger \(g_m\) (smaller input difference of pair)

Cons of (b)

• sensitive to the difference of common voltage between \(V_\text{ip}\), \(V_\text{im}\) and \(V_\text{rp}\), \(V_\text{rm}\)

common-mode voltage difference

copy aforementioned formula here for convenience \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

at sample phase \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}= V_\text{cmr}\)

• \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\)
• \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

at compare start

• \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{cmr}+\Delta\), \(V_\text{rp}= V_\text{cmr}-\Delta\)

• \(I_\text{ip}\lt I_\text{ip0}\), \(I_\text{rp} \gt I_\text{rp0}\)

• \(I_\text{im}\gt I_\text{im0}\), \(I_\text{rm} \lt I_\text{rm0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to increase \(V_\text{ip}\) and decrease \(V_\text{im}\).

at the compare finish

\[\begin{align} V_\text{ip}= V_\text{cmi} + \Delta \\ V_\text{im}= V_\text{cmi} - \Delta \end{align}\]

and \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\), \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

If \(V_\text{cmr} - V_\text{cmi} = \sqrt{2}V_{OV} + \delta\), and \(\delta \gt 0\). one transistor carries the entire tail current

• \(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\), all the time

At the end, \(V_\text{im} = V_\text{cmi} - (\Delta - \delta)\), the error is \(\delta\)

In closing, \(V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV}\) for normal work

Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to limited impedance of current source and input pair offset

In the end \[ V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS} \]

Under the condition, every transistor of pairs are on in equilibrium

pair mismatch

\[\begin{align} I_{SE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \\ I_{DE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \end{align}\]

The input equivalient offset voltage \[\begin{align} V_{os,SE} &= \frac{I_{SE}}{2g_m} = \frac{\sigma_{vth,0} + \sigma_{vth,1}}{2} \\ V_{os,DE} &= \frac{I_{DE}}{g_m} = \sigma_{vth,0} + \sigma_{vth,1} \end{align}\]

Then \[\begin{align} \sigma_{vos,SE} &= \sqrt{\frac{2\sigma_{vth}^2}{4}} = \frac{\sigma_{vth}}{\sqrt{2}} \\ \sigma_{vos,DE} &= \sqrt{2\sigma_{vth}^2} = \sqrt{2}\sigma_{vth} \end{align}\]

We obtain \[ \sigma_{vos,DE} = 2\sigma_{vos,SE} \]

peaking without inductor

TODO 📅

How to generate complex poles without inductor? [https://a2d2ic.wordpress.com/2020/02/19/basics-on-active-rc-low-pass-filters/]

Input Diff-Pair

DM Distortion

CM Distortion

Resistive Degeneration

Resistive degeneration in differential pairs serves as one major technique for linear amplifier

The linear region for CMOS differential pair would be extended by \(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align} V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\ &= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \end{align}\]

Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf

Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]

Biasing Tradeoffs in Resistive-Degenerated Diff Pair

Todd Brooks, Broadcom "Input Programmable Gain Amplifier (PGA) Design for ADC Signal Conditioning" [https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/OSU%20Classroom%20Presentaton%20042511.ppt]

Source-Degenerated Differential Pairs

TODO 📅

reference

Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers" [https://picture.iczhiku.com/resource/eetop/wHKfZPYpAleAKXBV.pdf]

Byungsub Kim, ISSCC 2022, "T11: Basics of Equalization Techniques: Channels, Equalization, and Circuits"

Minsoo Choi et al., "An Approximate Closed-Form Channel Model for Diverse Interconnect Applications," IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct. 2014.

K. Yadav, P. -H. Hsieh and A. Chan Carusone, "Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications," in IEEE Open Journal of Circuits and Systems, [link]

"Quantizers" and "truncators", and "integrators" and "accumulators" are used in delta-sigma ADCs and DACs, respectively

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

• a delta–sigma ADC consists of an analog modulator followed by a digital filter
• a delta–sigma DAC consists of a digital modulator followed by an analog filter

Analog Delta Sigma Modulators (ADSM) are used in the context of analog-to-digital conversion

• In a CT delta-sigma ADC, there is no need for an anti-aliasing filter or a front-end sampler

Digital Delta Sigma Modulators (DDSM) are commonly used in digital to-analog conversion and fractional-N frequency synthesis

• In a DDSM, the input is digital and the filters are implemented digitally
• the input to the DDSM is often a constant digital word, this covers delta-sigma fractional-N synthesizers in the frequency generation application

Oversampling Advantage

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

[https://dsp.stackexchange.com/a/40261/59253]

output vs. error-feedback

The error-feedback architecture is problematic for analog implementation, since it is sensitive to variations of its parameters (subtractor realization)

• The error-feedback structure is thus of limited utility in \(\Delta \Sigma\) ADCs
• The error-feedback structure is very useful and applied in digital loops required in \(\Delta \Sigma\) DACs

ADC

DAC

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

Time and Frequency Domain

ADC

hackaday. Tearing Into Delta Sigma ADC’s [https://hackaday.com/2016/07/07/tearing-into-delta-sigma-adcs-part-1/]

DAC

an interpolation filter effectively up-samples its low-rate input and lowpass-filters the resulting high-rate data to produce a high-rate output devoid of images

P.E. Allen -CMOS Analog Circuit Design: Lecture 39 – Oversampling ADCs – Part I (6/26/14) [https://aicdesign.org/wp-content/uploads/2018/08/lecture39-140626.pdf]

P.E. Allen -CMOS Analog Circuit Design: Lecture 40 – Oversampling ADCs – Part II (7/17/15) [https://aicdesign.org/wp-content/uploads/2018/08/lecture40-150717.pdf]

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

interpolation filter

Notice that the requirements of the first stage are very demanding

No delay-free loops

Any such physically feasible device will take a finite time to operate – in other words, the quantized output will only be available a small time after the quantizer has "looked" at the input - insert a one-sample delay

there cannot be a "delay free loop" is a common idea in sequential digital state machine design

Both integrator and quantizer are delay free

NTF realizability criterion: No delay-free loops in the modulator

linear settling & GBW of amplifier

TODO 📅

Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.

MOD1 & MOD2

MOD1: first-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD2: second-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD1

\[ V(z) = U(z) +(1-z^{-1})E(z) \]

• A binary DAC (and hence a binary modulator) is inherently linear
• With a CT loop filter, MOD1 has inherent anti-alising

\[\begin{align} v[1] &= u - (0) + e[1] \\ v[2] &= 2u - (v[1]) + e[2] \\ v[3] &= 3u - (v[1]+v[2]) + e[3] \\ v[4] &= 4u - (v[1]+v[2]+v[3]) + e[4] \end{align}\]

That is \[ v[n] = nu - \sum_{k=1}^{n-1}v[k] + e[n] \] Therefore, we have \(v[n-1] = (n-1)u - \sum_{k=1}^{n-2}v[k] + e[n-1]\), then \[\begin{align} v[n] &= nu - \sum_{k=1}^{n-1}v[k] + e[n] \\ &= u + \left((n-1)u - \sum_{k=1}^{n-2}v[k]\right) - v[n-1] + e[n] \\ &= u + v[n-1] - e[n-1] -v[n-1] + e[n] \\ &= u + e[n] - e[n-1] \end{align}\]

Dout, the low frequency component of ADC out is same with Vin

MOD2

MOD1 with DC Excitation

TODO 📅

decimation filter

The combination of the the digital post-filter and downsampler is called the decimation filter or decimator

\(\text{sinc}\) filter

Provided that \(T=1\) \[ H_1(e^{j2\pi f}) = \frac{\text{sinc}(Nf)}{\text{sinc}(f)} = \frac{1}{N}\frac{\sin(\pi Nf)}{\sin(\pi f)} \] that is \(\lim_{f\to 0^+}H_1(e^{j2\pi f}) = 1\) and \(H_1 = 0\) when \(f=\frac{n}{N}, n\in \mathbb{Z}\)

\(\text{sinc}^2\) filter

https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/First-Order_D-S_ADC_Scan2.pdf

https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/Lecture%20Notes/First-Order%20D-S%20ADC.pdf

Truncation DAC

The noise-shaping loop output must contain a faithful reproduction of the input signal \(u_0[n]\) in the baseband,

but it will also include the filtered truncation noise caused by the reduction of the word length in the loop.

Idealy, the DAC will reproduce its input digital signal in an analog form without any distortion

with \(\frac{y}{2^{m_2}} + q= v\), where \(v = \lfloor\frac{y}{2^{m_2}}\rfloor\)

\[ \left\{ \begin{array}{cl} Y + 2^{m_2} Q &= 2^{m_2}V \\ U - z^{-1}2^{m_2}Q &= Y \end{array} \right. \]

The STF & NTF is shown as below \[ V = \frac{1}{2^{m_2}}U + (1-z^{-1})Q \]

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m1 = 4  # MSBs
m2 = 2  # LSBs
Vmax = 2**(m1 + m2) - 1

u = 1

ylist = [0]
vlist = [0]
elist = []

Niter = 2**10
for _ in range(Niter):
    ecur = vlist[-1] - ylist[-1]
    elist.append(ecur)
    ycur = (u - ecur) % Vmax	# overflow
    ylist.append(ycur)
    ycur_bin = format(ycur, '06b')
    vcur = int(ycur_bin[:-2]+'00', 2)
    vlist.append(vcur)

print(ylist)
print(vlist)
print(sum(vlist)/len(vlist))

u	v_avg
0		0000_00
1		0000_01
60		1111_00
61		1111_01
62		1111_10

!!! The \(u\) is limited between 0 and 60 (MSBs_LSBs - LSBs)

Tuan Minh Vo, S. Levantino and C. Samori, "Analysis of fractional-n bang-bang digital PLLs using phase switching technique," 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, [https://sci-hub.se/10.1109/PRIME.2016.7519545]

An implementation of a high-resolution integral path using a digital delta-sigma modulator, low-resolution Nyquist DAC, and a lowpass filter

• \(\Delta \Sigma\) truncates \(n\)-bit accumulator output to \(m\)-bits with \(m\le n\)
• A \(m\)-bit Nyquist DAC outputs current, which is fed into a low pass filter that suppresses \(\Delta \Sigma\)'s quantization noise

The remaining 11 bits are truncated to 3-levels using a second-order delta-sigma modulator (DSM), thus, obviating the need for a high resolution DAC

Hanumolu, Pavan Kumar. "Design techniques for clocking high performance signaling systems" [https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]

1st order DDSM

Mismatch Shaping

Data-Weighted Averaging (DWA)

\[\begin{align} \sum_{i=0}^{n}v[i] + e_\text{DAC}[n] &= y[n] \\ \sum_{i=0}^{n-1}v[i] + e_\text{DAC}[n-1] &= y[n-1] \end{align}\]

and we have \(w[n] = y[n] - y[n-1]\), then \[ w[n] = v[n] + e_\text{DAC}[n] - e_\text{DAC}[n-1] \] i.e. \[ W = V + (1-z^{-1})e_\text{DAC} \]

Element Rotation:

[http://individual.utoronto.ca/schreier/lectures/12-2.pdf], [http://individual.utoronto.ca/trevorcaldwell/course/Mismatch.pdf]

LSB Dither

dithering break periodicity and convert them to noise while input is constant

drawback of Integer-N PLL

integer-N PLL frequency synthesizers

• the frequency resolution, is equal to the reference frequency, meaning that only integer multiples of the reference frequency can be synthesized

• if fine tuning is required, only choice in an integer-N PLL is to decrease the reference frequency

• Stability requirements limit the loop bandwidth to about one tenth of the reference frequency; therefore, decreasing the reference frequency increases the settling time as the loop bandwidth also has to be decreased

• Another drawback of the integer-N PLL is the trade-off between phase noise and settling time when the divider ratio becomes large (The contributions to the output phase noise of almost all PLL building blocks, except the VCO, are multiplied by the division ratio)

  [https://people.engr.tamu.edu/spalermo/ecen620/lecture03_ee620_pll_system.pdf]

  

• if a small reference frequency is chosen, the reference spur in the output phase noise is located at a smaller offset frequency

Fractional-N PLL

\[ \tau[n-1] + (N+y[n])T_{PLL} - (N+\alpha)T_{PLL} = \tau[n] \]

i.e. \[ \tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL} \]

where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV}, desired}\)

In \(z\)-domain \[ \left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y \right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y \] That is \[ Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2 \] In time domain \[\begin{align} y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\ &= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2] \end{align}\]

quantizer overload

TODO 📅

reference

R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data Converters

Shanthi Pavan, ISSCC2013 T5: Simulation Techniques in Data Converter Design [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T5.pdf]

Bruce A. Wooley , 2012, "The Evolution of Oversampling Analog-to-Digital Converters" [https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf]

B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016. [http://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

Horowitz, P., & Hill, W. (2015). The art of electronics (3rd ed.). Cambridge University Press. [pdf]

P. M. Aziz, H. V. Sorensen and J. vn der Spiegel, "An overview of sigma-delta converters," in IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 61-84, Jan. 1996 [https://sci-hub.st/10.1109/79.482138]

Richard E. Schreier, ECE 1371 Advanced Analog Circuits - 2015 [http://individual.utoronto.ca/schreier/ece1371-2015.html]

Gabor C. Temes. ECE 627-Oversampled Delta-Sigma Data Converters [https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/lecturenotes.html]

Boris Murmann, ISSCC2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [link]

Ian Galton. Delta-Sigma Fractional-N Phase-Locked Loops [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2022/10/fnpll_ieee_tutorial_2003_corrected.pdf]

Joshua Reiss. Understanding sigma delta modulation: the solved and unsolved issues

[https://www.eecs.qmul.ac.uk/~josh/documents/2008/Reiss-JAES-UnderstandingSigmaDeltaModulation-SolvedandUnsolvedIssues.pdf]

Ian Galton ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]

V. Medina, P. Rombouts and L. Hernandez-Corporales, "A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation [Feature]," in IEEE Circuits and Systems Magazine, vol. 24, no. 2, pp. 80-97, Secondquarter 2024

Sudhakar Pamarti. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8?si=tbav3J2yag38HyZx]

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2017/05/2007-TCASI-S.-Pamarti-Statistics-of-the-Quantization-Noise-in-1-Bit-Dithered-Single-Quantizer-Digital-Delta-Sigma-Modulators.pdf]

S. Pamarti and I. Galton, "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]

Michael Peter Kennedy. An Introduction to Digital Delta-Sigma Modulators [https://site.ieee.org/scv-cas/files/2014/07/2014Kennedy.pdf]

Kaveh Hosseini , Michael Peter Kennedy. Springer 2011. Minimizing Spurious Tones in Digital Delta-Sigma Modulators

Multipliers

TODO 📅

Adders

TODO 📅

overlapped tuning range

TODO 📅

Mueller-Muller PD

Mueller-Muller type A timing function

Mueller-Muller type B timing function

Least-Mean-Square (LMS)

minimum mean square error (MMSE)

This simplified version of LMS algorithm is identical to the zero-forcing algorithm which minimizes the ISI at data samples

Sign-Sign LMS (SS-LMS)

T11: Basics of Equalization Techniques: Channels, Equalization, and Circuits, 2022 IEEE International Solid-State Circuits Conference

V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005, doi: 10.1109/JSSC.2004.842863.

Jinhyung Lee, Design of High-Speed Receiver for Video Interface with Adaptive Equalization; Phd thesis, August 2019. thesis link

Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, 5th edition

E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008

DFE h0 Estimator

summer output \[ r_k = a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=1}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right) \] error slicer analog output \[ e_k=r_k-\hat{a}_k \hat{h}_0 \] error slicer digital output \[ \hat{e}_k=|e_k| \] It's NOT possible to implement \(e_k\), which need to determine \(\hat{a}_k=|r_k|\) in no time. One method to approach this problem is calculate \(e_k^{a_k=1}=r_k-\hat{a}_k \hat{h}_0\) and \(e_k^{a_k=-1}=r_k+\hat{a}_k \hat{h}_0\), then select the right one based on \(\hat{a}_k\)

The update equation based on Sign-Sign-Least Mean square (SS-LMS) and loss function \(L(\hat{h}_{\text{0~ntap}})=E(e_k^2)\) \[ \hat{h}_n(k+1) = \hat{h}_n(k)+\mu \cdot |e_k|\cdot \hat{a}_{k-n} \] Where \(n \in [0,...,\text{ntap}]\). This way, we can obtain \(\hat{h}_0\), \(\hat{h}_1\), \(\hat{h}_2\), ...

\(\hat{h}_0\) is used in AFE adaptation

We may encounter difficulty if the first tap of DFE is unrolled, its \(e_k\) is modified as follow \[ r_k = a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=2}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right) \] Where there is NO \(\hat{h}_1\)

To find \(\hat{h}_1\), we shall use different pattern for even and odd error slicer

Maximum Likelihood Sequence Estimator (MLSE)

[IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s https://static1.squarespace.com/static/5fb343ad64be791dab79a44f/t/63d807441bcd266de258b975/1675102025481/SLIDES_Track02_IBIS_AMI_Modeling_and_Correlation_Tyshchenko.pdf]

M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A. Sheikholeslami, "Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 97-108, 2022, doi: 10.1109/OJCAS.2022.3173686.

Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link. Undergraduate Research Scholars Program. Available electronically from [https://hdl.handle.net/1969.1/166485]

There are several variants of MLSD (Maximum Likelihood Sequence Detection), including:

• Viterbi Algorithm
• Decision Feedback Sequence Estimation (DFSE)
• Soft-Output MLSD

[Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches. https://semiengineering.com/evolution-of-equalization-techniques-in-high-speed-serdes-for-extended-reaches/]

Mueller-Muller CDR

MMPD infers the channel response from baud-rate samples of the received data, the adaptation aligns the sampling clock such that pre-cursor is equal to the post-cursor in the pulse response

Faisal A. Musa. "HIGH-SPEED BAUD-RATE CLOCK RECOVERY" [https://www.eecg.utoronto.ca/~tcc/thesis-musa-final.pdf]

Faisal A. Musa."CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS" [https://www.eecg.utoronto.ca/~tcc/faisal_iscas03.pdf]

Eduardo Fuentetaja. "Analysis of the M&M Clock Recovery Algorithm" [https://edfuentetaja.github.io/sdr/m_m_analysis/]

Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin & Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao & Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits. Electronics. 10. 1888. 10.3390/electronics10161888.

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1.

Baud-Rate CDRs [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010, pp. 366-367, doi: 10.1109/ISSCC.2010.5433823.

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022

Jaeduk Han, "Design and Automatic Generation of 60Gb/s Wireline Transceivers" [https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.pdf]

SS-MM CDR

\(h_1\) is necessary

• without DFE

  SS-MMPD locks at the point (\(h_1=h_{-1}\)​)

• With a 1-tap DFE

  1-tap adaptive DFE that forces the \(h_1\) to be zero, the SS-MMPD locks wherever the \(h_{-1}\)​ is zero and drifts eventually.

  Consequently, it suffers from a severe multiple-locking problem with an adaptive DFE

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

Pattern filter

During adapting, we make

• \(s_{011}\) & \(s_{110}\) are approaching to each other
• \(s_{100}\) & \(s_{001}\) are approaching to each other

Then, \(h_{-1}\) and \(h_1\) are same, which is desired

Bang-Bang CDR

alexander PD or !!PD

The alexander PD locks that edge clock (clkedge) is located at zero crossings of the data. The \(h_{-0.5}\) and \(h_{0.5}\) are equal at the lock point, where the \(h_{-0.5}\) and \(h_{0.5}\) are the cursors located at -0.5 UI and 0.5 UI.

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

Shahramian, Shayan, "Adaptive Decision Feedback Equalization With Continuous-time Infinite Impulse Response Filters" [https://tspace.library.utoronto.ca/bitstream/1807/77861/3/Shahramian_Shayan_201606_PhD_thesis.pdf]

MENIN, DAVIDE, "Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization" [https://air.uniud.it/retrieve/e27ce0ca-15f7-055e-e053-6605fe0a7873/Modelling%20and%20Design%20of%20High-Speed%20Wireline%20Transceivers%20with%20Fully-Adaptive%20Equalization.pdf]

reference

Stojanovic, Vladimir & Ho, A. & Garlepp, B. & Chen, Fred & Wei, J. & Alon, Elad & Werner, C. & Zerbe, J. & Horowitz, M.A.. (2004). Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 348 - 351. 10.1109/VLSIC.2004.1346611.

A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design Optimization for Wireline SerDes Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2023.3328807.

Masum Hossain, ISSCC2023 T11: "Digital Equalization and Timing Recovery Techniques for ADC-DSP-based Highspeed Links" [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T11.pdf]

—, "LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/SSCS_invited_talk.pdf]

A. Sharif-Bakhtiar, A. Chan Carusone, "A Methodology for Accurate DFE Characterization," IEEE RFIC Symposium, Philadelphia, Pennsylvania, June 2018. [PDF] [Slides – PDF]

Tony Chan Carusone. High Speed Communications Part 11 – SerDes DSP Interactions [https://youtu.be/YIAwLskuVPc?si=MYIbXLwFqQj0EElU]

Alphawave IP CEO. How DSP is Killing the Analog in SerDes [https://youtu.be/OY2Dn4EDPiA?si=czIYfFrHpY4F-lKK]