Extensive work on DFEs has produced a multitude of architectures,
which can be broadly categorized as "direct"" or
"unrolled" (speculative) DFEs with
"full-rate" or "half-rate"
clocking
S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for
20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol.
46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]
Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of
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Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity
Technologies to Accelerate AI
H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an
LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET,"
2025 IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2025
Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed
Wireline Interconnects: Design Challenges and Innovations in 224G SerDes
[https://www.youtube.com/live/wHNOlxHFTzY]
the resistance of MOS is not highly controlled -> \(R_T + Z_N\)
Peak power constraint of TX
FIR
Due to circuit limitation, circuit cannot have arbitrarily large
voltage on the output, i.e. a limited maximum swing. In order
to create the high frequency shape, the best we can do is lower DC
gain (low frequency gain < 1)
FIR is not increasing the amplitude on the edges
FIR is reducing the inner eye diagram
The maximum swing stays the same, \(\sum_i
|c_i|=1\)
Sharing termination keep a constant current through leg, which
improve TX speed in this way. On the other hand, the sharing termination
facilitate drain/source sharing technique in layout.
pull-up and pull-down
resistor
Original stacked structure
Pro's:
โ smaller static current when both pull up and pull down path is
on
Con's:
โ slowly switching due to parasitic capacitance behind pull-up and
pull-down resistor
with single shared linearization resistor
Pro's:
โ The parasitic capacitance behind the resistor still exists but is
now always driven high or low actively
Con's:
โ more static current
VM
Driver Equalization - differential ended termination
\[
V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1}
\]
where \(D_n \in \{-1, 1\}\)
\[
V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2}
\] With \(R_u=(L+M+N)R_T\)
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\
V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N}
\end{align}\] So \[
V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N}
\] which is same with differential ended termination
Equation-2
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \\
V_{\text{rxm}} &= 0
\end{align}\] So \[
V_{M}= \frac{1}{2}
\] which is same with differential ended termination
Which can be simpified as \[\begin{align}
V_{\text{rx}} &= \frac{1}{2}(V_p - V_m) \\
&= \frac{1}{2}(\frac{2}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-1) \\
&=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2}
\end{align}\]
The above eqations demonstrate that the output \(V_{\text{rx}}\) is the linear sum of
MSB and LSB; LSB and
MSB have relative weight, i.e. 1 for LSB and
2 for MSB.
Assume pre cusor has \(L\) legs,
main cursor \(M\) legs and post cursor
\(N\) legs, which is same with the
convention in "Voltage-Mode Driver Equalization"
The number of legs connected with supply can expressed as \[
n_{up} = (1-d_{n+1})L + d_{n}M + (1-d_{n-1})N
\] Where \(d_n \in \{0, 1\}\),
or \[
n_{up} = \frac{1}{2}(-D_{n+1}+1)L + \frac{1}{2}(D_{n}+1)M +
\frac{1}{2}(-D_{n-1}+1)N
\] Where \(D_n \in \{-1,
+1\}\)
Then the number of legs connected with ground is \[
n_{dn}=L+M+N-n_{up}
\] where \(n_{up}+n_{dn}=L+M+N\)
Voltage resistor divider \[\begin{align}
V_o &=
\frac{\frac{R_{U}}{n_{dn}}}{\frac{R_U}{n_{dn}}+\frac{R_U}{n_{up}}} \\
&= \frac{1}{2}- \frac{1}{2}D_{n+1}\frac{L}{L+M+N}+
\frac{1}{2}D_{n}\frac{M}{L+M+N}-\frac{1}{2}D_{n-1}\frac{N}{L+M+N} \\
&= \frac{1}{2}-\frac{1}{2}D_{n+1}\cdot l+ \frac{1}{2}D_{n}\cdot
m-\frac{1}{2}D_{n-1}\cdot n
\end{align}\]
where \(l+m+n=1\)
\(V_{\text{MSB}}\) and \(V_{\text{LSB}}\) can be obtained
\[\begin{align}
V_{\text{MSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \\
V_{\text{LSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n
\end{align}\]
Substitute the above equation into \(V_{\text{rx}}\), we obtain the relationship
between driver legs and FFE coefficients
After scaling, we obtain \[
V_{\text{rx}} = -l\cdot(2 \cdot
D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ m\cdot(2\cdot
D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) - n \cdot(2\cdot
D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1})
\] Where \(C_{-1} = l\), \(C_0 = m\) and \(C_{1}=n\), which is same with that of
NRZ
J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial
Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of
Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012, doi:
10.1109/JSSC.2012.2216414.
C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm
CMOS," 2018 IEEE International Solid - State Circuits Conference -
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E. Chong et al., "A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based
Transmitter in 7nm FinFET," ESSCIRC 2021 - IEEE 47th European Solid
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10.1109/ESSCIRC53450.2021.9567801.
Wang, Z., Choi, M., Lee, K., Park, K., Liu, Z., Biswas, A., Han, J.,
Du, S., & Alon, E. (2022). An Output Bandwidth Optimized 200-Gb/s
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J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm
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Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB
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[paper]
K. Kwon et al., "A 212.5Gb/s Pam-4 Receiver With Mutual
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Technology and Circuits (VLSI Technology and Circuits), Kyoto,
Japan, 2025
RX Equalization Noise
Enhancement
Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall
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The periodic signal on VCTRL modulates the
VCO, giving rise to deterministic jitter
Timing Offsets Between Up and Dn Pulses
Mismatch Between Charge-Pump Current Sources
Incomplete Settling of Charge-Pump Currents
Finite Output Resistance of the Charge Pump
Up/Dn Timing Offset
If Dn pulse arrives \(\Delta T\)
after the Up pulse, the steady-state VCTRL will be slightly
lower than it would be without the \(\Delta T\) mismatch so as to return the
VCO's phase to match the reference clocks.
Vice versa, if If Up pulse arrives \(\Delta
T\) after the Dn pulse, the steady-state VCTRL will be slightly
higher than without \(\Delta
T\) mismatch
Current Sources Mismatch
Incomplete Settling
TODO ๐
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
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Cowan G. Mixed-Signal CMOS for Wireline Communication:
Transistor-Level and System-Level Design Considerations. Cambridge
University Press; 2024
2nd loop filter
PI (proportional - integral) Loop Filter
PFD Deadzone
Dead zone induced by incomplete settling of charge-pump
currents
This situation can be avoided by adding additional delay to the
AND gate in the PFD
For the sake of simplicity, \(V_{ctr}\) looks like a rectangular pulse
with an amplitude of \(I_{CP}R_1\) and
a duty ratio of (\(I_{leak}/I_{CP}\)),
whose first coefficient of Fourier series is
where \(I_\text{leak} \ll I_{CP}\)
is assumed
Then, the peak frequency deviation \(\Delta f\)\[
\Delta f = a_1 \cdot K_v = 2I_\text{leak}R_1 K_v
\] using narrowband FM approximation, we have \[
P_\text{spur} = 20\log\left(\frac{\Delta f}{2f_\text{ref}}\right) =
20\log\left(\frac{I_\text{leak}R_1 K_v}{f_\text{ref}}\right)
\]
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]
โ. Yu, Z., 2024. Phase-Locked Loops: System Perspectives and
Circuit Design Aspects. John Wiley & Sons
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007.
Hunting jitter is often referred to as
dithering jitter, the periodic time
error between data clock and input data, which exhibits a
limit-cycle behavior
BB PD
Youngdon Choi, Deog-Kyoon Jeong and W. Kim, "Jitter transfer analysis
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[slides]
It's ternary, because early, late
and no transition
notice the transition density = 1 in
digital PLL
Linearization
The effective PD gain is a function of the input jitter
pdf, it enables one to anticipate the effects of input jitter
on loop characteristics
BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),
BB only produces output for a transition and this de-rates the gain.
Transition density = 0.5 for
random data
Input referred jitter from BB PD is
proportional to incoming jitter
gain simulation
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
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2016 [https://sci-hub.st/10.1109/JSSC.2016.2519391]
# polyfit coef_fit = np.polyfit(dt, et, 1) print(f'coef_fit: {coef_fit}')
x = np.linspace(-3.5, 3.5, 1000) y = coef_fit[0]*x + coef_fit[1]
plt.figure(figsize=(12,6)) plt.plot(dt, et, 'o') plt.plot(x, y, linewidth=2, linestyle='--')
# Calculate histogram counts and bin edges counts, bin_edges = np.histogram(dt, bins=100) # Find the maximum count max_count = counts.max() # Create weights to normalize the maximum height to 1 weights = np.ones_like(dt) / max_count plt.hist(dt, bins=100, weights=weights)
That is \[
P_{x_s x_s} (f)= \frac{1}{T_s}P_{xx}(f)
\] In going from discrete time to continuous
time, we must add a scale factor \(1/T\), the sample period
Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp
Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
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Daniel Boschen. GRCon24 - Quick Start on Control Loops with Python
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Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
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hunting jitter
S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim and D. -K. Jeong,
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[phd
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Pulse-Injection Driver Achieving โ255.2dB FoMJ Including the XO Power
and Noise," 2025 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2025
If \(m=0\)\[
\phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\] If \(m\neq 0\) and \(m=n\)\[
\phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\]
\(m\omega_0 +\Delta \omega \ge
0\)
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\omega)t]\) and \(m \ge 1\)
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for osr_cur in osr_list dt = tui/osr_cur; # Simulation time step tt = [0:dt:tlen_ir-dt;] ir = ฯ*exp.(-tt*ฯ); ir_dt_sum = sum(ir*dt); push!(ir_dt_sum_list, ir_dt_sum) end
p = plot(osr_list, ir_dt_sum_list, label = "OSR") gui(p)
Elastic Buffer
the elastic buffer approach would be the most general for modeling
say frequency offsets between TX and RX (will be addressed in future
development)
generate PAM symbols
here Big Endian
1 2 3 4 5
#generate PAM symbols fill!(So, zero(Float64)) #reset So to all 0 for n = 1:bits_per_sym @. So = So + 2^(bits_per_sym-n)*So_bits[n:bits_per_sym:end] end
1 2 3 4 5 6
function int2bits(num, nbit) return [Bool((num>>k)%2) for k in nbit-1:-1:0] end
Sanders, Anthony, Michael Resso and John D'Ambrosia. โChannel
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(2004).
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vol. 29, no. 7, pp. 1370-1378, July 2021, doi:
10.1109/TVLSI.2021.3082208.
HSPICEยฎ User Guide: Signal Integrity Modeling and Analysis, Version
Q-2020.03, March 2020
IA Title: Common Electrical I/O (CEI) - Electrical and Jitter
Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+
bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]
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Interconnects of Packages: A Review," in IEEE Access, vol. 12,
pp. 22880-22891, 2024 [pdf]
function bist_prbs_gen(;poly, inv, Nsym, seed) seq = Vector{Bool}(undef,Nsym) for n = 1:Nsym seq[n] = inv for p in poly seq[n] โป= seed[p] end seed .= [seq[n]; seed[1:end-1]] end return seq, seed end
1 2 3 4 5 6 7 8 9 10 11 12
%% Matlab
function[seq, seed] = bist_prbs_gen(poly,inv, Nsym, seed) seq = zeros(1,Nsym); for n = 1:Nsym seq(n) = inv; for p = poly seq(n) = xor(seq(n), seed(p)); end seed = [seq(n), seed(1:end-1)]; end end
function ber_check_prbs(rcvd_bits; poly, inv, seed, lock_status, lock_cnt, lock_threshold, ber_err_cnt, ber_tot_cnt) nbits_rcvd = lastindex(rcvd_bits) if lock_status #if prbs already locked, use prbs_gen for reference bits ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv, Nsym=nbits_rcvd, seed=seed) ber_err_cnt += sum(rcvd_bits .โป ref_bits) ber_tot_cnt += nbits_rcvd
else# if not locked yet, use received bits as seed for n = 1:nbits_rcvd brcv = rcvd_bits[n] btst = inv for p in poly btst โป= seed[p] end seed .= [brcv; seed[1:end-1]]
#need consecutive non-error for lock. reset when error happens lock_cnt = (btst == brcv) ? lock_cnt+1 : 0
if lock_cnt == lock_threshold lock_status = true println("prbs locked") #run prbs till end ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv, Nsym=nbits_rcvd-n, seed=seed) ber_err_cnt += sum(rcvd_bits[n+1:end] .โป ref_bits) ber_tot_cnt += nbits_rcvd - n
break end end end
return seed, lock_status, lock_cnt, ber_err_cnt, ber_tot_cnt end
Lim, Byong Chan, M. Horowitz, "Error Control and Limit Cycle
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XMODEL [pdf]
Then rise time of 20% to 80% is \[
T_{r} = \tau_{RC}\cdot \ln\frac{0.8}{0.2} = 1.3863 \cdot \tau_{RC}
\] we have \[
f_{3dB} = \frac{1}{2\pi}\frac{1}{\tau_{RC}} = \frac{1}{2\pi}\frac{
1.3863}{T_r} = \frac{0.22}{T_r}
\]
\(0.5/T_r\)
TODO ๐
CMI & DMI
Ahmed Sada Staff Silicon Validation Engineer, Synopsys. Don't Be
Intimidated: Manual Calibration for Stressed Eye Testing
Patrick Kennedy, Impact of Noise Coupler on 128 GT/s Rx Calibration
and DUT Testing
Anritsu White paper: PCIeยฎ 6.0: Testing for a New Generation [link]
sinusoidal differential mode interference
(DMI), and common mode interference
(CMI)
Since we have (ideally) no return current, the ground
reference becomes less important. The ground potential can
even be different at the sender and receiver or moving around within a
certain acceptable range. However, you need to be careful because
DC-coupled differential signaling (such as USB, RS-485, CAN) generally
requires a shared ground potential to ensure that the signals stay
within the interface's maximum and minimum allowable common-mode
voltage.
To understand the impact of the clock jitter on the performance of a
wireline system, the transfer functions of the PLL in the
transmitter side and the CDR loop in the receiver should
be taken into consideration
the minimum jitter occurs at the point
where the transmit PLL UGB is minimum and the
CDR UGB is maximized
the net rms jitter that impacts the performance of a wireline
transceiver is much lower than the rms jitter of the transmit PLL
the jitter requirements of the transmit PLL on the wireline system
is much more relaxed compared to the wireless transceiver
B. Razavi, "Design considerations for direct-conversion receivers,"
in IEEE Transactions on Circuits and Systems II: Analog and Digital
Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]
Even-Order Distortion
Odd-order distortion: symmetry
Even-Order Distortion: non-symmetry
(Effect of Mismatch)
Corresponding to the three distinct voltage thresholds in the
PAM4 systems, it would need 12 slicers, 3
multiplexers, and one thermometer-to-binary decoder in
each deserialized data path, even if only one tap of the DFE is
unrolled
Look-Ahead Multiplexing DFE
The look-ahead multiplexing technique brings the key benefit that the
timing constraint can be significantly relaxed, as the iteration bound
is doubled at the expense of extra
hardware
"ISI cancellation" based equalization is conceptually more
straightforward but suffers from SNR penalty or error propagation
Jitter Amplification
by Passive Channels
Enhancing
Resolution with a \(\Delta \Sigma\)
Modulator
Sub-Resolution Time Averaging
\(\Delta \Sigma\) modulator
effectively dithers the LSB bit
between zero and one, such that you can get the effective
resolution of a much higher resolution DAC in the number of bits
Decimation
how they affect sampling phase
DLF's input bit-width can be reduced by decimating BBPD's
output. Decimation is typically performed by realizing either
majority voting (MV) or boxcar
filtering.
Note that deserialization is inherent to both
MV and boxcar filtering
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it down
Decimating by \(L\) means frequency
register only added once every \(L\)
UI, thus integral path gain reduced by \(L\) in linear model
proportional path gain is unchanged
CDR Linear Model
condition:
Linear model of the CDR is used in a frequency lock
condition and is approaching to achieve phase
lock
Using this model, the power spectral density (PSD) of jitter in the
recovered clock \(S_{out}(f)\) is \[
S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f)
\] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they
come from independent sources.
Using below notation \[\begin{align}
\omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\
\xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2}
\end{align}\]
We can rewrite transfer function as follows \[
H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2}
\]
The jitter transfer represents a low-pass filter
whose magnitude is around 1 (0 dB) for low jitter frequencies and drops
at 20 dB/decade for frequencies above \(\omega_n\)
the recovered clock track the low-frequency
jitter of the input data
the recovered clock DONT track the
high-frequency jitter of the input data
The recovered clock does not suffer from high-frequency jitter even
though the input signal may contain high-frequency jitter, which will
limit the CDR tolerance to high-frequency jitter.
Jitter Peaking in
Jitter Transfer Function
The peak, slightly larger than 1 (0dB) implies that jitter will be
amplified at some frequencies in the CDR, producing a
jitter amplitude in the recovered clock, and thus also in the recovered
data, that is slightly larger than the jitter amplitude
in the input data.
This is certainly undesirable, especially in applications such as
repeaters.
Jitter Generation
If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the
recovered clock comes directly from the VCO jitter. The transfer
function that relates the VCO jitter to the recovered clock jitter is
known as jitter generation. \[
H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi
\omega_n s+\omega_n^2}
\] Jitter generation is high-pass filter with
two zeros, at zero frequency, and two poles identical to those of the
jitter transfer function
Jitter Tolerance (JTOL)
To quantify jitter tolerance, we often apply a sinusoidal jitter of a
fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR's true
tolerance to random jitter. Because we are applying
"sinusoidal" jitter, which is deterministic signal.
We can deal only with the jitter's amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
\[
JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad
\text{for a fixed BER}
\] Where the subscript \(\text{pp-max}\) indicates the
maximum peak-to-peak amplitude. We can further expand
this equation as follows \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_\text{pp-max}
\]
Relative jitter, \(\varphi_e\) must
be less than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude
of \(|\varphi_e(f)|\) is
1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
\] Given the linear CDR model, we can write \[
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
\] Expand \(H_{LF}(f)\) for the
CDR, we can write \[
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
\] At frequencies far below and above the natural frequency, the
jitter tolerance can be approximated by the following \[
JTOL(f) = \left\{ \begin{array}{cl}
\left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\
1 & : \ f\gg f_n
\end{array} \right.
\]
the jitter tolerance at very high jitter frequencies
is limited to 1UIpp
1 2 3 4 5 6 7 8 9 10 11 12 13 14
clc; clear all;
f_fn = logspace(-1, 2, 60); for xi = [2, 1, 0.5, 0.2] jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2); loglog(f_fn, jtol,LineWidth=2) disp(["min(JTpp)=", min(jtol),"@\xi=",xi]) hold on end grid on; xlabel("f/f_n") ylabel('JT_{pp}') legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')
JTF, by jitter frequency, compares how much input signal jitter is
transferred to the output of a clock-recovery's PLL (recovered
clock)
Input signal jitter that is within the clock recovery PLL's loop
bandwidth results in jitter that is faithfully transferred (closed-loop
gain) to the clock recovery PLL's output signal. JTF in this situation
is approximately 1.
Input signal jitter that is outside the clock recovery PLL's loop
bandwidth results in decreasing jitter (open-loop gain) on the clock
recovery PLL's output, because the jitter is filtered out and no longer
reaches the PLL's VCO
Observed Jitter Transfer Function
Input Signal Versus Sampled Signal
OJTF compares how much input signal jitter is transferred to the
output of a receiver's decision making circuit as
effected by a clock recovery's PLL. As the recovered clock is the
reference for detecting the input signal
Input signal jitter that is within the clock
recovery PLL's loop bandwidth results in jitter on the recovered clock
which reduces the amount of jitter that can be detected. The input
signal and clock signal are closer in phase
Input signal jitter that is outside the clock
recovery PLL's loop bandwidth results in reduced jitter on the
recovered clock which increases the amount of jitter that can
be detected. The input signal and clock signal are more out of phase.
Jitter that is on both the input and clock signals can not detected or
is reduced
JTF and OJTF for 1st Order PLLs
The observed jitter is a complement to the PLL jitter transfer
response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not
observed at the output of the CDR as a function of the jitter rate
applied to the input.
The combination of the OJTF of a jitter measurement device and the
JTF of the clock generator under test gives the measured jitter as a
function of frequency.
For example, a clock generator with a type 1, 1st order PLL measured
with a jitter measurement device employing a golden PLL is \[
J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2}
\]
Accurate measurement of the clock JTF requires that the OJTF cutoff
of the jitter measurement be significantly below that of the clock JTF
and that the measurement is compensated for the instrument's OJTF.
The overall response is a band pass filter because the clock JTF is
low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring
the jitter of the reference clock at each jitter rate being tested and
comparing the reference jitter with the jitter
measured at the output of the DUT.
The lower the cutoff frequency of the jitter measurement device the
better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the
phase noise of the DUT and measurement time.
Digital Sampling
Oscilloscope
How to analyze jitter:
TIE (Time Interval Error) track
histogram
FFT
TIE track provides a direct view of how the phase of
the clock evolves over time.
histogram provides valuable information about the
long term variations in the timing.
FFT allows jitter at specific rates to be measured
down to the femto-second range.
Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop
bandwidth minimizes the response error
reference
Dalt, Nicola Da and Ali Sheikholeslami. โUnderstanding Jitter and
Phase Noise: A Circuits and Systems Perspective.โ (2018).
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
AFE Nonlinearity
"total harmonic distortion" (THD) in
AFE
Relative to NRZ-based systems, PAM4 transceivers require more
stringent circuit linearity, equalizers which can implement multi-level
inter-symbol interference (ISI) cancellation, and improved
sensitivity
Because if it compresses, it turns out you have to use a much more
complicated feedback filter. As long as it behaves linearly,
the feedback filter itself can remain a linear FIR
Linearity can actually be a critical constraint in these signal
paths, and you really want to stay as linear as you can all the way up
until the point where you've canceled all of the ISI
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline
Receivers"
BER with Quantization Noise
\[
\text{Var}(X) = E[X^2] - E[X]^2
\]
Impulse Response or Pulse
Response
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline
Links-Part II: Optimization and Performance Assessment," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024
[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
R. Walker, โDesigning Bang-Bang PLLs for Clock and Data Recovery in
Serial Data Transmission Systems,โ in Phase-Locking in High-Performance
Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
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Da Dalt N. A design-oriented study of the nonlinear dynamics of
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Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop
gain tracking all-digital PLL using autocorrelation of bangโbang phase
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CDR Loop Latency
Denoting the CDR loop latency by \(\Delta
T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The
resulting right-half-plane zero, \(f_z\) degrades the phase margin and must
remain about one decade beyond the BW\[
f_z\simeq \frac{1}{2\pi \Delta T}
\]
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. โOn the Stability of
Charge-Pump Phase-Locked Loops.โ IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
limit cycles imply self-sustained oscillators due nonlinear
nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC
LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van
Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design.
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Digital CDR Category
DCO part is analogous so that it cannot be perfectly
modeled
Digital-to-phase converter is well-defined phase output, thus, very
good to model real situation
Z-domain modeling
The difference equation is \[
\phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi
\] z-transform is \[
\frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}}
\]
where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)
\(\Delta
\Sigma\)-dithering in DCO
Quantization noise
Here, \(\alpha_T\) is data
transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang
Controlled Timing Circuits," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
Time to Digital Converter
(TDC)
Digital to Phase Converter
(DPC)
IIR low pass filter
simple approximation: \[
z = 1 + sT
\] bilinear-z transform \[
z =\frac{}{}
\]
FAQ
PLL vs. CDR
PLL
CDR
Clock edge periodic
Data edge random
Phase & Frequency detecting possible
Phase detecting possible , Frequency detecting impossible
PLL or FD(Frequency Detector) for frequency detecting in CDR
reference
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and
Circuits" [slides]
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems
(lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT
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J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
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