KNOW-HOW

Delta-Sigma Data Converters

Posted on 2024-09-08 Edited on 2023-07-10 In analog

The average output of DSM tracks the input signal

$Δ Σ$ modulators are nonlinear systems since a quantizer is implemented in the $Δ Σ$ -loop

No delay-free loops

Both integrator and quantizer are delay free

NTF realizability criterion: No delay-free loops in the modulator

linear settling & GBW of amplifier

TODO 📅

Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.

Delta Modulator

$\begin{aligned} (V_{i n} - V_{F}) & = D_{o u t} \\ D_{o u t} & = s V_{F} \end{aligned}$

Therefore $V_{i n} - \frac{D_{o u t}}{s} = D_{o u t}$ $D_{o u t} = \frac{s}{s + 1} V_{i n}$

attenuates the low-frequency content of the signal, and amplifies high-frequency noise.

MOD1

A binary DAC (and hence a binary modulator) is inherently linear
With a CT loop filter, MOD1 has inherent anti-alising

$\begin{aligned} v [1] & = u - (0) + e [1] \\ v [2] & = 2 u - (v [1]) + e [2] \\ v [3] & = 3 u - (v [1] + v [2]) + e [3] \\ v [4] & = 4 u - (v [1] + v [2] + v [3]) + e [4] \end{aligned}$

That is $v [n] = n u - \sum_{k = 1}^{n - 1} v [k] + e [n]$ Therefore, we have $v [n - 1] = (n - 1) u - \sum_{k = 1}^{n - 2} v [k] + e [n - 1]$ , then $\begin{aligned} v [n] & = n u - \sum_{k = 1}^{n - 1} v [k] + e [n] \\ = u + ((n - 1) u - \sum_{k = 1}^{n - 2} v [k]) - v [n - 1] + e [n] \\ = u + v [n - 1] - e [n - 1] - v [n - 1] + e [n] \\ = u + e [n] - e [n - 1] \end{aligned}$

MOD2

decimation filter

The combination of the the digital post-filter and downsampler is called the decimation filter or decimator

$sinc$ filter

${sinc}^{2}$ filter

https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/First-Order_D-S_ADC_Scan2.pdf

https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/Lecture%20Notes/First-Order%20D-S%20ADC.pdf

Truncation DAC

An implementation of a high-resolution integral path using a digital delta-sigma modulator, low-resolution Nyquist DAC, and a lowpass filter

$Δ Σ$ truncates $n$ -bit accumulator output to $m$ -bits with $m \leq n$
A $m$ -bit Nyquist DAC outputs current, which is fed into a low pass filter that suppresses $Δ Σ$ 's quantization noise

The remaining 11 bits are truncated to 3-levels using a second-order delta-sigma modulator (DSM), thus, obviating the need for a high resolution DAC

Hanumolu, Pavan Kumar. "Design techniques for clocking high performance signaling systems" [https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]

Mismatch Shaping

Data-Weighted Averaging (DWA)

$\begin{aligned} \sum_{i = 0}^{n} v [i] + e_{DAC} [n] & = y [n] \\ \sum_{i = 0}^{n - 1} v [i] + e_{DAC} [n - 1] & = y [n - 1] \end{aligned}$

and we have $w [n] = y [n] - y [n - 1]$ , then $w [n] = v [n] + e_{DAC} [n] - e_{DAC} [n - 1]$ i.e. $W = V + (1 - z^{- 1}) e_{DAC}$

Element Rotation:

[http://individual.utoronto.ca/schreier/lectures/12-2.pdf], [http://individual.utoronto.ca/trevorcaldwell/course/Mismatch.pdf]

reference

R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data Converters

Shanthi Pavan, ISSCC2013 T5: Simulation Techniques in Data Converter Design [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T5.pdf]

Bruce A. Wooley , 2012, "The Evolution of Oversampling Analog-to-Digital Converters" [https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf]

B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016. [http://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

Richard E. Schreier, ECE 1371 Advanced Analog Circuits - 2015 [http://individual.utoronto.ca/schreier/ece1371-2015.html]

Gabor C. Temes. ECE 627-Oversampled Delta-Sigma Data Converters [https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/lecturenotes.html]

Equalization & Timing Recovery

Posted on 2024-09-03 Edited on 2023-07-10 In dsp

Multipliers

TODO 📅

Adders

TODO 📅

overlapped tuning range

TODO 📅

Mueller-Muller PD

Mueller-Muller type A timing function

Mueller-Muller type B timing function

Least-Mean-Square (LMS)

minimum mean square error (MMSE)

This simplified version of LMS algorithm is identical to the zero-forcing algorithm which minimizes the ISI at data samples

Sign-Sign LMS (SS-LMS)

T11: Basics of Equalization Techniques: Channels, Equalization, and Circuits, 2022 IEEE International Solid-State Circuits Conference

V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005, doi: 10.1109/JSSC.2004.842863.

Jinhyung Lee, Design of High-Speed Receiver for Video Interface with Adaptive Equalization; Phd thesis, August 2019. thesis link

Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, 5th edition

E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008

DFE h0 Estimator

summer output $r_{k} = a_{k} h_{0} + (\sum_{n = - \infty, n \neq 0}^{+ \infty} a_{k - n} h_{n} - \sum_{n = 1}^{ntap} {\hat{a}}_{k - n} {\hat{h}}_{n})$ error slicer analog output $e_{k} = r_{k} - {\hat{a}}_{k} {\hat{h}}_{0}$ error slicer digital output ${\hat{e}}_{k} = | e_{k} |$ It's NOT possible to implement $e_{k}$ , which need to determine ${\hat{a}}_{k} = | r_{k} |$ in no time. One method to approach this problem is calculate $e_{k}^{a_{k} = 1} = r_{k} - {\hat{a}}_{k} {\hat{h}}_{0}$ and $e_{k}^{a_{k} = - 1} = r_{k} + {\hat{a}}_{k} {\hat{h}}_{0}$ , then select the right one based on ${\hat{a}}_{k}$

The update equation based on Sign-Sign-Least Mean square (SS-LMS) and loss function $L ({\hat{h}}_{0~ntap}) = E (e_{k}^{2})$ ${\hat{h}}_{n} (k + 1) = {\hat{h}}_{n} (k) + μ \cdot | e_{k} | \cdot {\hat{a}}_{k - n}$ Where $n \in [0, . . ., ntap]$ . This way, we can obtain ${\hat{h}}_{0}$ , ${\hat{h}}_{1}$ , ${\hat{h}}_{2}$ , ...

${\hat{h}}_{0}$ is used in AFE adaptation

We may encounter difficulty if the first tap of DFE is unrolled, its $e_{k}$ is modified as follow $r_{k} = a_{k} h_{0} + (\sum_{n = - \infty, n \neq 0}^{+ \infty} a_{k - n} h_{n} - \sum_{n = 2}^{ntap} {\hat{a}}_{k - n} {\hat{h}}_{n})$ Where there is NO ${\hat{h}}_{1}$

To find ${\hat{h}}_{1}$ , we shall use different pattern for even and odd error slicer

Maximum Likelihood Sequence Estimator (MLSE)

[IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s https://static1.squarespace.com/static/5fb343ad64be791dab79a44f/t/63d807441bcd266de258b975/1675102025481/SLIDES_Track02_IBIS_AMI_Modeling_and_Correlation_Tyshchenko.pdf]

M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A. Sheikholeslami, "Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 97-108, 2022, doi: 10.1109/OJCAS.2022.3173686.

Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link. Undergraduate Research Scholars Program. Available electronically from [https://hdl.handle.net/1969.1/166485]

There are several variants of MLSD (Maximum Likelihood Sequence Detection), including:

Viterbi Algorithm
Decision Feedback Sequence Estimation (DFSE)
Soft-Output MLSD

[Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches. https://semiengineering.com/evolution-of-equalization-techniques-in-high-speed-serdes-for-extended-reaches/]

Mueller-Muller CDR

MMPD infers the channel response from baud-rate samples of the received data, the adaptation aligns the sampling clock such that pre-cursor is equal to the post-cursor in the pulse response

Faisal A. Musa. "HIGH-SPEED BAUD-RATE CLOCK RECOVERY" [https://www.eecg.utoronto.ca/~tcc/thesis-musa-final.pdf]

Faisal A. Musa."CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS" [https://www.eecg.utoronto.ca/~tcc/faisal_iscas03.pdf]

Eduardo Fuentetaja. "Analysis of the M&M Clock Recovery Algorithm" [https://edfuentetaja.github.io/sdr/m_m_analysis/]

Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin & Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao & Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits. Electronics. 10. 1888. 10.3390/electronics10161888.

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1.

Baud-Rate CDRs [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010, pp. 366-367, doi: 10.1109/ISSCC.2010.5433823.

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022

Jaeduk Han, "Design and Automatic Generation of 60Gb/s Wireline Transceivers" [https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.pdf]

SS-MM CDR

$h_{1}$ is necessary

without DFE

SS-MMPD locks at the point ( $h_{1} = h_{- 1}$ )
With a 1-tap DFE

1-tap adaptive DFE that forces the $h_{1}$ to be zero, the SS-MMPD locks wherever the $h_{- 1}$ is zero and drifts eventually.

Consequently, it suffers from a severe multiple-locking problem with an adaptive DFE

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

Pattern filter

pattern	main cursor
011	$s_{011} = - h_{1} + h_{0} + h_{- 1}$
110	$s_{110} = h_{1} + h_{0} - h_{- 1}$
100	$s_{100} = h_{1} - h_{0} - h_{- 1}$
001	$s_{001} = - h_{1} - h_{0} + h_{- 1}$

During adapting, we make

$s_{011}$ & $s_{110}$ are approaching to each other
$s_{100}$ & $s_{001}$ are approaching to each other

Then, $h_{- 1}$ and $h_{1}$ are same, which is desired

Bang-Bang CDR

alexander PD or !!PD

The alexander PD locks that edge clock (clkedge) is located at zero crossings of the data. The $h_{- 0.5}$ and $h_{0.5}$ are equal at the lock point, where the $h_{- 0.5}$ and $h_{0.5}$ are the cursors located at -0.5 UI and 0.5 UI.

Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]

Shahramian, Shayan, "Adaptive Decision Feedback Equalization With Continuous-time Infinite Impulse Response Filters" [https://tspace.library.utoronto.ca/bitstream/1807/77861/3/Shahramian_Shayan_201606_PhD_thesis.pdf]

MENIN, DAVIDE, "Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization" [https://air.uniud.it/retrieve/e27ce0ca-15f7-055e-e053-6605fe0a7873/Modelling%20and%20Design%20of%20High-Speed%20Wireline%20Transceivers%20with%20Fully-Adaptive%20Equalization.pdf]

reference

Stojanovic, Vladimir & Ho, A. & Garlepp, B. & Chen, Fred & Wei, J. & Alon, Elad & Werner, C. & Zerbe, J. & Horowitz, M.A.. (2004). Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 348 - 351. 10.1109/VLSIC.2004.1346611.

A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design Optimization for Wireline SerDes Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2023.3328807.

Masum Hossain, ISSCC2023 T11: "Digital Equalization and Timing Recovery Techniques for ADC-DSP-based Highspeed Links" [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T11.pdf]

—, "LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/SSCS_invited_talk.pdf]

A. Sharif-Bakhtiar, A. Chan Carusone, "A Methodology for Accurate DFE Characterization," IEEE RFIC Symposium, Philadelphia, Pennsylvania, June 2018. [PDF] [Slides – PDF]

Clocked Comparators

Posted on 2024-09-02 Edited on 2023-07-10 In analog

Noise Analysis

TODO 📅

The StrongARM latch completes switching actions and noise injections even before the output begins to change

slower rise time improve input-referred noise

Noise Simulation

PSS + Pnoise Method

SNR during sampling region and decision region increase

SNR during regeneration region is constant, where noise is critical

$SNR = \frac{V_{o, s i g}^{2}}{V_{o, n}^{2}} = \frac{V_{i, s i g}^{2}}{V_{i, n}^{2}}$

we can get $V_{i, n}^{2} = \frac{V_{i, s i g}^{2}}{SNR}$ , which is constant also

That is $V_{i, n}^{2} = \frac{V_{i, s i g}^{2}}{V_{o, s i g}^{2}} V_{o, n}^{2} = \frac{V_{o, n}^{2}}{A_{v}^{2}}$ where $V_{i, s i g}$ is constant signal is applied to input of comparator

Transient Noise Method

Noise Fmax sets the bandwidth of the random noise sources that are injected at each time point in the transient analysis

We can identify the RMS noise value easily by looking at 15.9% or 84.1% of CDF ( $1 σ$ ), the input-referred noise in the RMS is 0.9mV

Thus, if $V_{S}$ is chosen so as to reduce the probability of zeros to 16%, then $V_{S} = 1 σ$ , which is also the total root-mean square (rms) noise referred to the input.

Comparison of two methods

It seems that $σ_{pnoise} = \sqrt{2} σ_{trannoise}$ , the factor $\sqrt{2}$ is implicitly in formula in ADC Rak of Cadence

E. Gillen, G. Panchanan, B. Lawton and D. O'Hare, "Comparison of transient and PNOISE simulation techniques for the design of a dynamic comparator," 2022 33rd Irish Signals and Systems Conference (ISSC), Cork, Ireland, 2022, pp. 1-5

Chenguang Yang, "Comparator Design for High Speed ADC" [https://lup.lub.lu.se/luur/download?func=downloadFile&recordOId=9164380&fileOId=9164388]

J. Conrad, J. Kauffman, S. Wilhelmstatter, R. Asthana, V. Belagiannis and M. Ortmanns, "Confidence Estimation and Boosting for Dynamic-Comparator Transient-Noise Analysis," 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada, 2024, pp. 1-5

Common-Mode (Vcmi) Variation Effects

offset simulation

TODO 📅

T. Caldwell. ECE 1371S Advanced Analog Circuits [http://individual.utoronto.ca/trevorcaldwell/course/comparators.pdf]

Eric Chang. EECS240-s18 Discussion 9

Graupner, Achim & Sobe, Udo. (2007). Offset-Simulation of Comparators. [https://designers-guide.org/analysis/comparator.pdf]

Comment on "Offset-Simulation of Comparators"

If the input referred offset follows a normal distribution than it is sufficient to apply a single offset voltage to calculate the offset voltage.
See details in Razavi, B., The StrongARM Latch [A Circuit for All Seasons], IEEE Solid-State Circuits Magazine, Volume:7, Issue: 2, Spring 2015

Omran, Hesham. (2019). Fast and accurate technique for comparator offset voltage simulation. Microelectronics Journal. 89. 10.1016/j.mejo.2019.05.004.

Matthews, Thomas W. and Perry L. Heedley. “A simulation method for accurately determining DC and dynamic offsets in comparators.” 48th Midwest Symposium on Circuits and Systems, 2005. (2005): 1815-1818 Vol. 2. [https://athena.ecs.csus.edu/~pheedley/MSDL/MSDL_DOTB_cmp_test_bench_MWSCAS05.pdf]

Hysteresis

P. Bruschi: Notes on Mixed Signal Design http://www2.ing.unipi.it/~a008309/mat_stud/MIXED/archive/2019/Optional_notes/Chap_3_4_Comparators.pdf

TODO 📅

Kickback Noise

Kickback noise trades with the dimensions of the input transistors and hence with the offset voltage

affects the comparator's own decision
corrupts the input voltage while it is sensed by other circuits

Tetsuya Iizuka,VLSI2021_Workshop3 "Nyquist A/D Converter Design in Four Days"

Figueiredo, Pedro & Vital, João. (2006). Kickback noise reduction techniques for CMOS latched comparators. Circuits and Systems II: Express Briefs, IEEE Transactions on. 53. 541 - 545. 10.1109/TCSII.2006.875308. [https://sci-hub.se/10.1109/TCSII.2006.875308]

P. M. Figueiredo and J. C. Vital, "Low kickback noise techniques for CMOS latched comparators," 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, BC, Canada, 2004, pp. I-537 [https://sci-hub.se/10.1109/ISCAS.2004.1328250]

Lei, Ka Meng & Mak, Pui-In & Martins, R.P.. (2013). Systematic analysis and cancellation of kickback noise in a dynamic latched comparator. Analog Integrated Circuits and Signal Processing. 77. 277-284. 10.1007/s10470-013-0156-1. [https://rto.um.edu.mo/wp-content/uploads/docs/ruimartins_cv/publications/journalpapers/57.pdf]

O. M. Ívarsson, "Comparator Kickback Reduction Techniques for High-Speed ADCs," Dissertation, 2024. [https://liu.diva-portal.org/smash/get/diva2:1872476/FULLTEXT01.pdf]

CMOS Latch

TODO 📅

$V_{o, f b}^{+} - V_{o, f b}^{-} = \frac{g_{m}}{s C_{L}} (V_{o}^{+} - V_{o}^{-}) = A (s) \cdot (V_{o}^{+} - V_{o}^{-})$

We have $A (s) \cdot (V_{i} + V_{o}) = V_{o}$

that is $V_{o} = \frac{A (s)}{1 - A (s)} V_{i} = \frac{1}{s - g_{m} / C_{L}} \cdot \frac{g_{m} V_{i}}{C_{L}}$

therefore $V_{o} (t) = \frac{g_{m} V_{i}}{C_{L}} \cdot \exp (\frac{g_{m}}{C_{L}} t) = V_{o} (t = 0) \cdot \exp (\frac{g_{m}}{C_{L}} t)$

Asad Abidi, ISSCC 2023: Circuit Insights "The CMOS Latch" [https://youtu.be/sVe3VUTNb4Q?si=Pl75jWiA0kNPOlOs]

Metastability

TODO 📅

If the comparator can not generate a well-defined logical output in half of the clock period, we say the circuit is "metastable"

Pre-amp (preamplifier)

preampSong202412181018

Vishal Saxena "CMOS Comparator Design Extra Slides" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Comparator%20Slides.pdf]

Math Background

Relating $Φ$ and erf

Error Function (Erf) of the standard Normal distribution $Erf (x) = \frac{2}{\sqrt{π}} \int_{0}^{x} e^{- t^{2}} d t .$ Cumulative Distribution Function (CDF) of the standard Normal distribution $Φ (x) = \frac{1}{\sqrt{2 π}} \int_{- \infty}^{x} e^{- z^{2} / 2} d z .$

$\begin{aligned} Φ (x) & = \frac{Erf (x / \sqrt{2}) + 1}{2} . \\ Φ (x \sqrt{2}) & = \frac{Erf (x) + 1}{2} \end{aligned}$

Considering the mean and standard deviation $Φ (x, μ, σ) = \frac{1}{2} (1 + Erf (\frac{x - μ}{σ \sqrt{2}}))$

John D. Cook. Relating Φ and erf [https://www.johndcook.com/erf_and_normal_cdf.pdf]

reference

Xu, H. (2018). Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs. UCLA. ProQuest ID: Xu_ucla_0031D_17380. Merritt ID: ark:/13030/m5f52m8x. Retrieved from [https://escholarship.org/uc/item/88h8b5t3]

A. Abidi and H. Xu, "Understanding the Regenerative Comparator Circuit," Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-8. [https://picture.iczhiku.com/resource/ieee/WHiYwoUjPHwZPXmv.pdf]

T. Sepke, P. Holloway, C. G. Sodini and H. -S. Lee, "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009 [https://dspace.mit.edu/bitstream/handle/1721.1/61660/Speke-2009-Noise%20Analysis%20for%20Comparator-Based%20Circuits.pdf]

Sepke, Todd. "Comparator design and analysis for comparator-based switched-capacitor circuits." (2006). [https://dspace.mit.edu/handle/1721.1/38925]

P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008 [https://picture.iczhiku.com/resource/eetop/SYirpPPPaAQzsNXn.pdf]

J. Kim, B. S. Leibowitz, J. Ren and C. J. Madden, "Simulation and Analysis of Random Decision Errors in Clocked Comparators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1844-1857, Aug. 2009, doi: 10.1109/TCSI.2009.2028449. URL:https://people.engr.tamu.edu/spalermo/ecen689/simulation_analysis_clocked_comparators_kim_tcas1_2009.pdf

J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 386-391, doi: 10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]

Jaeha Kim, Lecture 12. Aperture and Noise Analysis of Clocked Comparators URL:https://ocw.snu.ac.kr/sites/default/files/NOTE/7038.pdf

Sam Palermo. ECEN720: High-Speed Links Circuits and Systems Spring 2023 Lecture 6: RX Circuits [https://people.engr.tamu.edu/spalermo/ecen689/lecture6_ee720_rx_circuits.pdf]

Y. Luo, A. Jain, J. Wagner and M. Ortmanns, "Input Referred Comparator Noise in SAR ADCs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 718-722, May 2019. [https://sci-hub.se/10.1109/TCSII.2019.2909429]

Art Schaldenbrand, Senior Product Manager, Keeping Things Quiet: A New Methodology for Dynamic Comparator Noise Analysis URL:https://www.cadence.com/content/dam/cadence-www/global/en_US/videos/tools/custom-_ic_analog_rf_design/NoiseAnalyisposting201612Chalk%20Talk.pdf

X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April 2020 [https://sci-hub.se/10.1109/JSSC.2019.2960485]

Chen, Long & Sanyal, Arindam & Ma, Ji & Xiyuan, Tang & Sun, Nan. (2016). Comparator Common-Mode Variation Effects Analysis and its Application in SAR ADCs. 10.1109/ISCAS.2016.7538972. [https://labs.engineering.asu.edu/mixedsignals/wp-content/uploads/sites/58/2017/08/ISCAS_comp_long_2016.pdf]

V. Stojanovic, and V. G. Oklobdzija, "Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536–548, April 1999. [https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Clocking/Vlada-Latches-JoSSC-Apr-1999.pdf]

C. Mangelsdorf, "Metastability: Deeply misunderstood [Shop Talk: What You Didn’t Learn in School]," in IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 8-15, Spring 2024

B. Razavi, "The Design of a Comparator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 12, Issue. 4, pp. 8-14, Fall 2020. https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2020.pdf

B. Razavi, "The StrongARM Latch [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Issue. 2, pp. 12-17, Spring 2015. https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine4.pdf

CHUNG-CHUN (CC) CHEN. Why Transient Noise (Trannoise) Analysis for A Strong-arm Latch / Comparator? [https://youtu.be/gpQggSM9_PE?si=apMd6yWVO1JHOHm_]

CHUNG-CHUN (CC) CHEN. Why A Dedicated Noise Analysis for A Strong-arm Latch / Comparator? [https://youtu.be/S5GnvFxuxUA?si=w38iLvzjr0azhu43]

Rabuske, Taimur & Fernandes, Jorge. (2014). Noise-aware simulation-based sizing and optimization of clocked comparators. Analog Integr. Circuits Signal Process.. 81. 723-728. 10.1007/s10470-014-0428-4. [https://sci-hub.se/10.1007/s10470-014-0428-4]

Rabuske, Taimur & Fernandes, Jorge. (2016). Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications. 10.1007/978-3-319-39624-8.

Fourier Transform

Posted on 2024-08-30 Edited on 2023-07-10 In dsp

discrete-time frequency: $\hat{ω} = ω T_{s}$ , units are radians per sample

Below diagram show the windowing effect and sampling

NinDFT.drawio

For general window function, we know $W (e^{j \hat{ω}}) = \frac{1}{T_{s}} W_{c} (j ω)$ ,

and $\frac{W_{c} (j ω | ω = 0)}{T_{s}} = \frac{T_{s} W (e^{j \hat{ω}} | \hat{ω} = 0)}{T_{s}} = W (e^{j \hat{ω}} | \hat{ω} = 0) = \sum_{n = - N_{w}}^{+ N_{w}} w [n]$

e.g. $\frac{W_{c} (j ω | ω = 0)}{T_{s}} = N$ for Rectangular Window, shown in above figure

warmup

	Continuous-time signals $x_{c} (t)$	Discrete-time signals $x [n]$
Aperiodic signals	Continuous Fourier transform	Discrete-time Fourier transform
Periodic signals	Fourier series	Discrete Fourier transform

Continuous Time Fourier Series (CTFS)

$\begin{aligned} a_{k} & = \frac{1}{T} \int_{T} x (t) e^{- j k (2 π / T)) t} d t \\ x (t) & = \sum_{k = - \infty}^{+ \infty} a_{k} e^{j k (2 π / T) t} \end{aligned}$

Continuous-Time Fourier transform (CTFT)

$\begin{aligned} X (j ω) & = \int_{- \infty}^{+ \infty} x (t) e^{- j ω t} d t \\ x (t) & = \frac{1}{2 π} \int_{- \infty}^{+ \infty} X (j ω) e^{j ω t} d ω \end{aligned}$

[https://www.rose-hulman.edu/class/ee/yoder/ece380/Handouts/Fourier%20Transform%20Tables%20w.pdf]

Discrete-Time Fourier Transform (DTFT)

$\begin{aligned} X (e^{j \hat{ω}}) & = \sum_{n = - \infty}^{+ \infty} x [n] e^{- j \hat{ω} n} \\ x [n] & = \frac{1}{2 π} \int_{2 π} X (e^{j \hat{ω}}) e^{j \hat{ω} n} d \hat{ω} \end{aligned}$

DTFT is defined for infinitely long signals as well as finite-length signal

DTFT is continuous in the frequency domain

We could verify that is the correct inverse DTFT relation by substituting the definition of the DTFT and rearranging terms

Discrete-Time Fourier Series (DTFS)

TODO 📅

Discrete Fourier Series (DFS)

TODO 📅

Discrete Fourier Transform (DFT)

Two steps are needed to change the DTFT sum into a computable form:

the continuous frequency variable $\hat{ω}$ must be sampled

the limits on the DTFT sum must be finite

$\begin{aligned} X [k] & = \sum_{n = 0}^{N - 1} x [n] e^{- j (2 π / N) k n} k = 0, 1, . . ., N - 1 \\ x [n] & = \frac{1}{N} \sum_{k = 0}^{N - 1} X [k] e^{j (2 π / N) k n} n = 0, 1, . . ., N - 1 \end{aligned}$

Part of the proof is given by the following step:

DFT $X [k]$ is a sampled version of the DTFT $X (e^{j \hat{ω}})$ , where $\hat{ω_{k}} = \frac{2 π k}{N}$

impulse train

CTFT:

using time-sampling property

DTFT:

Given $x [n] = \sum_{k = - \infty}^{\infty} δ (n - k)$

$\begin{aligned} X (e^{j \hat{ω}}) & = X_{s} (j \frac{\hat{ω}}{T}) \\ = \frac{2 π}{T} \sum_{k = - \infty}^{\infty} δ (\frac{\hat{ω}}{T} - \frac{2 π k}{T}) \\ = \frac{2 π}{T} \sum_{k = - \infty}^{\infty} T δ (\hat{ω} - 2 π k) \\ = 2 π \sum_{k = - \infty}^{\infty} δ (\hat{ω} - 2 π k) \end{aligned}$

[http://courses.ece.ubc.ca/359/notes/notes_part1_set4.pdf]

Fourier series of impulse train

Dirac delta (impulse) function

[https://bingweb.binghamton.edu/~suzuki/Math-Physics/LN-7_Dirac_delta_function.pdf]

Topic 3 The $δ$ -function & convolution. Impulse response & Transfer function [https://www.robots.ox.ac.uk/~dwm/Courses/2TF_2011/2TF-N3.pdf]

impulse scaling

$δ (α t) = \frac{1}{α} δ (t)$

where $α$ is scaling ratio

Multiplication

aka Modulation or Windowing Theorem

CTFT: $x_{1} (t) x_{2} (t) \overset{F T}{⟶} \frac{1}{2 π} X_{1} (ω) * X_{2} (ω)$

DTFT:

Duality

Conjugate Symmetry

Parseval's Relation

CTFT:

DTFT:

DFT:

Eigenfunctions & frequency response

Complex exponentials are eigenfunctions of LTI systems, that is,

continuous time: $e^{j ω t} \to H (j ω) e^{j ω t}$

discrete time: $e^{j \hat{ω} n} \to H (e^{j \hat{ω}}) e^{j \hat{ω} n}$

where $H (j ω)$ , $H (e^{j \hat{ω}})$ is frequency response of continuous-time systems and discrete-time systems, which is the function of $ω$ and $\hat{ω}$ $\begin{aligned} H (j ω) & = \int_{- \infty}^{+ \infty} h (t) e^{- j ω t} d t \\ H (e^{j \hat{ω}}) & = \sum_{n = - \infty}^{+ \infty} h [n] e^{- j \hat{ω} n} \end{aligned}$

The frequency response of discrete-time LTI systems is always a periodic function of the frequency variable $\hat{ω}$ with period $2 π$

Sampling Theorem

time-sampling theorem: applies to bandlimited signals

spectral sampling theorem: applies to timelimited signals

Aliasing

The frequencies $f_{sig}$ and $N f_{s} \pm f_{sig}$ ( $N$ integer), are indistinguishable in the discrete time domain.

Given below sequence $X [n] = A e^{j ω T_{s} n}$

$k f_{s} + Δ f$

$\begin{aligned} x [n] & = A e^{j (k f_{s} + Δ f) 2 π T_{s} n} + A e^{j (- k f_{s} - Δ f) 2 π T_{s} n} \\ = A e^{j Δ f \cdot 2 π T_{s} n} + A e^{- j Δ f \cdot 2 π T_{s} n} \end{aligned}$

$k f_{s} - Δ f$

$\begin{aligned} x [n] & = A e^{j (k f_{s} - Δ f) 2 π T_{s} n} + A e^{j (- k f_{s} + Δ f) 2 π T_{s} n} \\ = A e^{- j Δ f \cdot 2 π T_{s} n} + A e^{j Δ f \cdot 2 π T_{s} n} \end{aligned}$

complex signal

$\begin{aligned} A e^{j (ω_{s} + Δ ω) T_{s} n} & = A e^{j (k ω_{s} + Δ ω) T_{s} n} \\ A e^{j (ω_{s} - Δ ω) T_{s} n} & = A e^{j (k ω_{s} - Δ ω) T_{s} n} \end{aligned}$

CTFS & CTFT

Fourier transform of a periodic signal with Fourier series coefficients ${a_{k}}$ can be interpreted as a train of impulses occurring at the harmonically related frequencies and for which the area of the impulse at the $k$ th harmonic frequency $k ω_{0}$ is $2 π$ times the $k$ th Fourier series coefficient $a_{k}$

inverse CTFT & inverse DTFT

	time domain	frequency domain
inverse CTFT	$δ (t)$	$\int_{\infty} d ω$
inverse DTFT	$δ [n]$	$\int_{2 π} d \hat{ω}$

inverse CTFT shall integral from $- \infty$ to $+ \infty$ to obtain $δ (t)$ in time domain, e.g., $x_{s} (t)$ impulse train

spectral sampling

spectral sampling by $ω_{0}$ , and $\frac{2 π}{ω_{0}} > τ$ $X_{n ω_{0}} (ω) = \sum_{n = - \infty}^{\infty} X (n ω_{0}) δ (ω - n ω_{0})$ Periodic repetition of $x (t)$ is $x_{n ω_{0}} (t) = \frac{1}{ω_{0}} \sum_{n = - \infty}^{\infty} x (t - n \frac{2 π}{ω_{0}}) = \frac{T_{0}}{2 π} \sum_{n = - \infty}^{\infty} x (t - n T_{0})$

Then, if $x_{T_{0}} (t)$ , a periodic signal formed by repeating $x (t)$ every $T_{0}$ seconds ( $T_{0} > τ$ ), its CTFT is $X_{T_{0}} (ω) = \frac{2 π}{T_{0}} \cdot X_{n ω_{0}} (ω) = \frac{2 π}{T_{0}} \sum_{n = - \infty}^{\infty} X (n ω_{0}) δ (ω - n ω_{0})$ Then $x_{T_{0}} (t)$ can be expressed with inverse CTFT as $\begin{aligned} x_{T_{0}} (t) & = \frac{1}{2 π} \int_{- \infty}^{\infty} X_{T_{0}} (ω) e^{j ω t} d ω \\ = \frac{1}{T_{0}} \sum_{n = - \infty}^{\infty} X (n ω_{0}) e^{j n ω_{0} t} = \sum_{n = - \infty}^{\infty} \frac{1}{T_{0}} X (n ω_{0}) e^{j n ω_{0} t} \end{aligned}$

i.e. the coefficients of the Fourier series for $x_{T_{0}} (t)$ is $D_{n} = \frac{1}{T_{0}} X (n ω_{0})$

alternative method by direct Fourier series

Why DFT ?

We can use DFT to compute DTFT samples and CTFT samples

$\overset{―}{x} (t) = \sum_{n = 0}^{N_{0} - 1} x (n T) δ (t - n T)$ applying the Fourier transform yieds $\overset{―}{X} (ω) = \sum_{n = 0}^{N_{0} - 1} x [n] e^{- j n ω T}$ But $\overset{―}{X} (ω)$ , the Fourier transform of $\overset{―}{x} (t)$ is $X (ω) / T$ , assuming negligible aliasing. Hence, $X (ω) = T \overset{―}{X} (ω) = T \sum_{n = 0}^{N_{0} - 1} x [n] e^{- j n ω T}$ and $X (k ω_{0}) = T \sum_{n = 0}^{N_{0} - 1} x [n] e^{- j n k ω_{0} T}$ with ${\hat{ω}}_{0} = ω_{0} T$ $X (k ω_{0}) = T \sum_{n = 0}^{N_{0} - 1} x [n] e^{- j n k {\hat{ω}}_{0}}$ i.e. the relationship between CTFT and DFT is $X (k ω_{0}) = T \cdot X [k]$ , DFT is a tool for computing the samples of CTFT

C/D

Sampling with a periodic impulse train, followed by conversion to a discrete-time sequence

The periodic impulse train is $s (t) = \sum_{n = - \infty}^{\infty} δ (t - n T)$ $x_{s} (t)$ can be expressed as $x_{s} (t) = \sum_{n = - \infty}^{\infty} x_{c} (n T) δ (t - n T)$ i.e., the size (area) of the impulse at sample time $n T$ is equal to the value of the continuous-time signal at that time.

$x_{s} (t)$ is, in a sense, a continuous-time signal (specifically, an impulse train)

samples of $x_{c} (t)$ are represented by finite numbers in $x [n]$ rather than as the areas of impulses, as with $x_{s} (t)$

Frequency-Domain Representation of Sampling

The relationship between the Fourier transforms of the input and the output of the impulse train modulator $X_{s} (j ω) = \frac{1}{T} \sum_{k = - \infty}^{\infty} X_{c} (j (ω - k ω_{s}))$ where $ω_{s}$ is the sampling frequency in radians/s

$X (e^{j \hat{ω}})$ , the discrete-time Fourier transform (DTFT) of the sequence $x [n]$ , in terms of $X_{s} (j ω)$ and $X_{c} (j ω)$

continuous-time Fourier transform	discrete-time Fourier transform
$x_{s} (t) = \sum_{n = - \infty}^{\infty} x_{c} (n T) δ (t - n T)$	$x [n] = x_{c} (n T)$
$X_{s} (j ω) = \sum_{n = - \infty}^{\infty} x_{c} (n T) e^{- j ω T n}$	$X (e^{j \hat{ω}}) = \sum_{n = - \infty}^{\infty} x_{c} (n T) e^{- j \hat{ω} n}$

$X (e^{j ω T}) = \frac{1}{T} \sum_{k = - \infty}^{\infty} X_{c} (j (ω - k ω_{s}))$ or equivalently, $X (e^{j \hat{ω}}) = \frac{1}{T} \sum_{k = - \infty}^{\infty} X_{c} (j (\frac{\hat{ω}}{T} - \frac{2 π k}{T}))$

$X (e^{j \hat{ω}})$ is a frequency-scaled version of $X_{s} (j ω)$ with the frequency scaling specified by $\hat{ω} = ω T$

Ref. 9.5 DTFT connection with the CTFT

Here, $Ω = ω T$

The factor $\frac{1}{T}$ in $X (e^{j \hat{ω}})$ is misleading, actually $x [n]$ is not scaled by $\frac{1}{T}$ when taking $\hat{ω}$ variable of integration into account $\begin{aligned} x_{r} [n] & = \frac{1}{2 π} \int_{2 π} X (e^{j \hat{ω}}) e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \int_{2 π} \frac{1}{T} \sum_{k = - \infty}^{+ \infty} X_{c} [j (\frac{\hat{ω}}{T} - \frac{2 π k}{T})] e^{j \hat{ω} n} d \hat{ω} \\ \approx \frac{1}{2 π} \frac{1}{T} \int_{2 π} X_{c} (\frac{\hat{ω}}{T}) e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \frac{1}{T} \int_{2 π} [\int_{\infty} X_{c} (Φ) δ (Φ - \frac{\hat{ω}}{T}) d Φ] e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \frac{1}{T} \int_{\infty} X_{c} (Φ) d Φ \int_{2 π} δ (Φ - \frac{\hat{ω}}{T}) e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \frac{1}{T} \int_{\infty} X_{c} (Φ) d Φ \int_{2 π} T \cdot δ (Φ T - \hat{ω}) e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \int_{\infty} X_{c} (Φ) e^{j Φ T n} d Φ \end{aligned}$

That is $\begin{aligned} x_{r} [n] & = \frac{1}{2 π} \int_{2 π} \frac{1}{T} X_{c} (\frac{\hat{ω}}{T}) e^{j \hat{ω} n} d \hat{ω} \\ (31) & = \frac{1}{2 π} \int_{\infty} X_{c} (ω) e^{j ω T n} d ω \end{aligned}$

assuming Nyquist–Shannon sampling theorem is met

$\begin{aligned} x_{r} [n] & = \frac{1}{2 π} \int_{\infty} X_{c} (ω) e^{j ω T n} d ω \\ = \frac{1}{2 π} \int_{\infty} X_{c} (ω) e^{j ω t_{n}} d ω \\ = x_{c} (t_{n}) \end{aligned}$

where $t_{n} = T n$ , then $x_{r} [n] = x_{c} (n T)$

Assuming $x_{c} (t) = \cos (ω_{0} t)$ , $x_{s} (t) = \sum_{n = - \infty}^{\infty} x_{c} (n T) δ (t - n T)$ and $x [n] = x_{c} (n T)$ , that is $\begin{aligned} x_{c} (t) & = \cos (ω_{0} t) \\ x_{s} (t) & = \sum_{n = - \infty}^{\infty} \cos (ω_{0} n T) δ (t - n T) \\ x [n] & = \cos (ω_{0} n T) \end{aligned}$

$X_{c} (j ω)$ , the Fourier Transform of $x_{c} (t)$ $X_{c} (j ω) = π [δ (ω - ω_{0}) + δ (ω + ω_{0})]$
$X (e^{j \hat{ω}})$ , the the discrete-time Fourier transform (DTFT) of the sequence $x [n]$ $X (e^{j \hat{ω}}) = \sum_{k = - \infty}^{+ \infty} π [δ (\hat{ω} - {\hat{ω}}_{0} - 2 π k) + δ (\hat{ω} + {\hat{ω}}_{0} - 2 π k)]$
$X_{s} (j ω)$ , the Fourier Transform of $x_{s} (t)$ $X_{s} (j ω) = \frac{1}{T} \sum_{k = - \infty}^{+ \infty} π [δ (ω - ω_{0} - k ω_{s}) + δ (ω + ω_{0} - k ω_{s})]$

Express $X (e^{j \hat{ω}})$ in terms of $X_{s} (j ω)$ and $X_{c} (j ω)$ $X (e^{j \hat{ω}}) = \frac{1}{T} \sum_{k = - \infty}^{+ \infty} π [δ (\frac{\hat{ω}}{T} - ω_{0} - k ω_{s}) + δ (\frac{\hat{ω}}{T} + ω_{0} - k ω_{s})]$ Inverse $X (e^{j \hat{ω}})$ $\begin{aligned} x_{r} [n] & = \frac{1}{2 π} \int_{2 π} X (e^{j \hat{ω}}) e^{j \hat{ω} n} d \hat{ω} \\ = \frac{1}{2 π} \int_{2 π} π [δ (\frac{\hat{ω}}{T} - ω_{0}) + δ (\frac{\hat{ω}}{T} + ω_{0})] e^{j \hat{ω} n} d \frac{\hat{ω}}{T} \\ = \frac{1}{2 π} \int_{2 π} π [δ (\frac{\hat{ω}}{T} - ω_{0}) e^{j {\hat{ω}}_{0} n} + δ (\frac{\hat{ω}}{T} + ω_{0}) e^{- j {\hat{ω}}_{0} n}] d \frac{\hat{ω}}{T} \\ = \frac{1}{2} [e^{j {\hat{ω}}_{0} n} \int_{2 π} [δ (\frac{\hat{ω}}{T} - ω_{0}) d \frac{\hat{ω}}{T} + e^{- j {\hat{ω}}_{0} n} \int_{2 π} [δ (\frac{\hat{ω}}{T} + ω_{0}) d \frac{\hat{ω}}{T}] \\ = \frac{1}{2} [e^{j {\hat{ω}}_{0} n} + e^{- j {\hat{ω}}_{0} n}] \\ = \cos ({\hat{ω}}_{0} n) \end{aligned}$

or follow EQ.(31)

$\begin{aligned} x_{r} [n] & = \frac{1}{2 π} \int_{\infty} X_{c} (ω) e^{j ω T n} d ω \\ = \frac{1}{2 π} \int_{\infty} π [δ (ω - ω_{0}) + δ (ω + ω_{0})] e^{j ω T n} d ω \\ = \frac{1}{2} (e^{j ω_{0} T n} + e^{- j ω_{0} T n}) \\ = \cos ({\hat{ω}}_{0} n) \end{aligned}$

where ${\hat{ω}}_{0} = ω_{0} T$

D/C

zero padding

This option increases $N_{0}$ , the number of samples of $x (t)$ , by adding dummy samples of 0 value. This addition of dummy samples is known as zero padding.

We should keep in mind that even if the fence were transparent, we would see a reality distorted by aliasing.

Zero padding only allows us to look at more samples of that imperfect reality

Gotcha

A remarkable fact of linear systems is that the complex exponentials are eigenfunctions of a linear system, as the system output to these inputs equals the input multiplied by a constant factor.

Both amplitude and phase may change
but the frequency does not change

For an input $x (t)$ , we can determine the output through the use of the convolution integral, so that with $x (t) = e^{s t}$ $\begin{aligned} y (t) & = \int_{- \infty}^{+ \infty} h (τ) x (t - τ) d τ \\ = \int_{- \infty}^{+ \infty} h (τ) e^{s (t - τ)} d τ \\ = e^{s t} \int_{- \infty}^{+ \infty} h (τ) e^{- s τ} d τ \\ = e^{s t} H (s) \end{aligned}$

Take the input signal to be a complex exponential of the form $x (t) = A e^{j ϕ} e^{j ω t}$

$\begin{aligned} y (t) & = h (t) * x (t) \\ = H (j ω) A e^{j ϕ} e^{j ω t} \end{aligned}$

The frequency response at $- ω$ is the complex conjugate of the frequency response at $+ ω$ , given $h (t)$ is real

$\begin{aligned} H^{*} (t) & = {(\int_{- \infty}^{+ \infty} h (t) e^{- j ω t} d t)}^{*} \\ = \int_{- \infty}^{+ \infty} h^{*} (t) e^{+ j ω t} d t \\ = \int_{- \infty}^{+ \infty} h (t) e^{- j (- ω t)} d t \\ = H (- j ω) \end{aligned}$

The real cosine signal is actually composed of two complex exponential signals: one with positive frequency and the other with negative $c o s (ω t + ϕ) = \frac{e^{j (ω t + ϕ)} + e^{- j (ω t + ϕ)}}{2}$

The sinusoidal response is the sum of the complex-exponential response at the positive frequency $ω$ and the response at the corresponding negative frequency $- ω$ because of LTI systems's superposition property

input: $\begin{aligned} x (t) & = A c o s (ω t + ϕ) \\ = \frac{1}{2} A e^{ϕ} e^{ω t} + \frac{1}{2} A e^{- ϕ} e^{- ω t} \end{aligned}$
output with $H (j ω) = G e^{j θ}$ : $\begin{aligned} y (t) & = H (j ω) \frac{1}{2} A e^{ϕ} e^{ω t} + H (- j ω) \frac{1}{2} A e^{- ϕ} e^{- ω t} \\ = G e^{j θ} \frac{1}{2} A e^{ϕ} e^{ω t} + G e^{- j θ} \frac{1}{2} A e^{- ϕ} e^{- ω t} \\ = G A c o s (ω t + ϕ + θ) \end{aligned}$

Its phase shift is $θ$ and gain is $G$ , which is same with $H (j ω)$ .

reference

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]

B.P. Lathi, Roger Green. Linear Systems and Signals (The Oxford Series in Electrical and Computer Engineering) 3rd Edition [pdf]

Alan V. Oppenheim, Alan S. Willsky, and S. Hamid Nawab. 1996. Signals & systems (2nd ed.) [pdf]

James H. McClellan, Ronald Schafer, and Mark Yoder. 2015. DSP First (2nd. ed.). Prentice Hall Press, USA

SAR ADC

Posted on 2024-08-20 Edited on 2023-07-10 In analog

CDAC intuition

The charge redistribution capacitor network is used to sample the input signal and serves as a digital-to-analog converter (DAC) for creating and subtracting reference voltages

sampling charge $Q = V_{i n} C_{t o t}$ conversion charge $Q = - C_{t o t} V_{c} + V_{r e f} C_{Δ}$ That is $V_{c} = \frac{C_{Δ}}{C_{t o t}} V_{r e f} - V_{i n}$

CDAC is actually working as a capacitive divider during conversion phase, the charge of internal node retain (charge conservation law)

assuming $Δ V_{i}$ is applied to series capacitor $C_{1}$ and $C_{2}$

cap_divider.drawio $(Δ V_{i} - Δ V_{x}) C_{1} = Δ V_{x} \cdot C_{2}$ Then $Δ V_{x} = \frac{C_{1}}{C_{1} + C_{2}} Δ V_{i}$

$V_{x} = V_{x, 0} + Δ V_{x}$

CDAC settling accuracy

cdac-tau.drawio $\begin{aligned} V_{x} (s) & = \frac{C_{1} + C_{2}}{R C_{1} C_{2}} \cdot \frac{1}{s + \frac{C_{1} + C_{2}}{R C_{1} C_{2}}} \cdot V_{i} (s) \\ = \frac{1}{τ} \cdot \frac{1}{s + \frac{1}{τ}} \cdot \frac{1}{s} \\ = \frac{1}{τ} \cdot τ (\frac{1}{s} - \frac{1}{s + \frac{1}{τ}}) = \frac{1}{s} - \frac{1}{s + \frac{1}{τ}} \end{aligned}$

inverse Laplace Transform is $V_{x} (t) = 1 - e^{- t / τ}$

$\begin{aligned} V_{y} (s) & = V_{x} \frac{C_{1}}{C_{1} + C_{2}} \\ = \frac{C_{1}}{C_{1} + C_{2}} (\frac{1}{s} - \frac{1}{s + \frac{1}{τ}}) \end{aligned}$

inverse Laplace Transform is $V_{y} (t) = \frac{C_{1}}{C_{1} + C_{2}} (1 - e^{- t / τ})$

$V_{x} (t)$ and $V_{y} (t)$ prove that the settling time is same

$τ = R \frac{C_{1} C_{2}}{C_{1} + C_{2}}$ , which means usually worst for MSB capacitor (largest) > both $τ$ and $Δ V$ are the maximum

A popular way to improve the settling behavior, again, is to employ unit-element DACs that statistically reduce the switching activities, which, unfortunately, exhibits unnecessary complications to the power, area and speed tradeoffs of the design

CDAC Energy Consumption

$E_{V r e f} = \int P (t) d t = \int V_{r e f} I (t) d t = V_{r e f} \int I (t) d t = V_{r e f} \cdot Δ Q$

Given $V_{c, 0} = \frac{1}{2} V_{r e f} - V_{i n}$ and $V_{c, 1} = \frac{3}{4} V_{r e f} - V_{i n}$ $\begin{aligned} Q_{b 0, 0} & = (V_{r e f} - V_{c, 0}) \cdot 2 C = (\frac{1}{2} V_{r e f} + V_{i n}) \cdot 2 C \\ Q_{b 1, 0} & = (0 - V_{c, 0}) \cdot C = (- \frac{1}{2} V_{r e f} + V_{i n}) \cdot C \\ Q_{b 0, 1} & = (V_{r e f} - V_{c, 1}) \cdot 2 C = (\frac{1}{4} V_{r e f} + V_{i n}) \cdot 2 C \\ Q_{b 1, 1} & = (V_{r e f} - V_{c, 1}) \cdot C = (\frac{1}{4} V_{r e f} + V_{i n}) \cdot C \end{aligned}$

Therefore $E_{V r e f} = V_{r e f} \cdot (Q_{b 0, 1} + Q_{b 1, 1} - Q_{b 0, 0} - Q_{b 1, 0}) = \frac{1}{4} C V_{r e f}^{2}$

CDAC total energy change $\begin{aligned} Δ E_{t o t} & = \frac{1}{2} \cdot 2 C \cdot (U_{2 c, 1}^{2} - U_{2 c, 0}^{2}) + \frac{1}{2} \cdot C \cdot (U_{c, 1}^{2} - U_{c, 0}^{2}) + \frac{1}{2} \cdot C \cdot (U_{c 1, 1}^{2} - U_{c 1, 0}^{2}) \\ = (- \frac{3}{16} V_{r e f}^{2} - \frac{1}{2} V_{r e f} V_{i n} - \frac{3}{32} V_{r e f}^{2} + \frac{3}{4} V_{r e f} V_{v i n} + \frac{5}{32} V_{r e f}^{2} - \frac{1}{4} V_{r e f} V_{i n}) C \\ = - \frac{1}{8} C V_{r e f}^{2} \end{aligned}$

alternative method

CapEnergy.drawio $Δ E_{t o t} = \frac{1}{2} \cdot \frac{3}{4} C \cdot V_{r e f}^{2} - \frac{1}{2} \cdot C \cdot V_{r e f}^{2} = - \frac{1}{8} C V_{r e f}^{2}$

The total energy decreases by $- \frac{1}{8} C V_{r e f}^{2}$ , though $V_{r e f}$ provides $\frac{1}{4} C V_{r e f}^{2}$

The charge redistribution change the CDAC energy

cap_redis_energy.drawio

$E_{c, 0} = \frac{1}{2} C V^{2}$ After charge redistribution $E_{c, 1} = \frac{1}{2} \cdot 2 C \cdot {(\frac{1}{2} V)}^{2} = \frac{1}{4} C V^{2}$

That make sense, charge redistribution consume energy

Comparator input cap effect

$- V_{i n} \cdot 2^{N} C = V_{c} (2^{N} C + C_{p})$ Then $V_{c} = - \frac{2^{N} C}{2^{N} C + C_{p}} V_{i n}$ , i.e. this capacitance reduce the voltage amplitude by the factor

During conversion $\begin{aligned} V_{c} & = - \frac{2^{N} C}{2^{N} C + C_{p}} V_{i n} + V_{r e f} \sum_{n = 0}^{N - 1} \frac{b_{n} \cdot 2^{n} C}{2^{N} C + C_{p}} \\ = \frac{2^{N} C}{2^{N} C + C_{p}} (- V_{i n} + V_{r e f} \sum_{n = 0}^{N - 1} \frac{b_{n}}{2^{N - n}}) \end{aligned}$

That is, it does not change the sign

Comparator offset effect

Synchronous SAR ADC

It also divides a full conversion into several comparison stages in a way similar to the pipeline ADC, except the algorithm is executed sequentially rather than in parallel as in the pipeline case.

However, the sequential operation of the SA algorithm has traditionally been a limitation in achieving high-speed operation

a clock running at least $(N + 1) \cdot F_{s}$ is required for an $N$ -bit converter with conversion rate of $F_{s}$
every clock cycle has to tolerate the worst case comparison time
every clock cycle requires margin for the clock jitter

The power and speed limitations of a synchronous SA design comes largely from the high-speed internal clock

Split Arrary CDAC

Split capacitor, double-array cap

attenuation capacitance $C_{a}$

splitArray.drawio

$\begin{aligned} Δ V_{d a c} & = \frac{1}{2} b_{3} + \frac{1}{4} b_{2} + \frac{1}{4} (\frac{1}{2} b_{1} + \frac{1}{4} b_{0}) \\ = \frac{1}{2} b_{3} + \frac{1}{4} b_{2} + \frac{1}{8} b_{1} + \frac{1}{16} b_{0} \end{aligned}$

Asynchronous processing

The maximum resolving time reduction between synchronous and asynchronous case is two fold

reference

Andrea Baschirotto, "T6: SAR ADCs" ISSCC2009

Pieter Harpe, ISSCC 2016 Tutorial: "Basics of SAR ADCs Circuits & Architectures"

Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006

—. "Power Efficient System and A/D Converter Design for Ultra-Wideband Radio" [http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-71.pdf]

—. "Asynchronous SAR ADC: Past, Present and Beyond" [https://viterbi-web.usc.edu/~swchen/index_files/async_sar_tutorial_chen_final.pdf]

C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010 [https://sci-hub.se/10.1109/JSSC.2010.2042254]

L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021 [pdf]

W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011 [https://sci-hub.st/10.1109/JSSC.2011.2163556]

Data Converter

Posted on 2024-08-18 Edited on 2023-07-10 In analog

Track Time

TODO 📅

ADC Calibration

Offset Calibration

long-term average of all 32 sub-ADC samples = 0

Gain Calibration

long-term average of absolute values of all 32 sub-ADC samples should be equal

Background vs. foreground calibration

TODO 📅

Ahmed Ali, ISSCC 2021 T5: Calibration Techniques in ADCs [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T5.pdf]

Jiang, Xicheng, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015.

Differential top-plate sampling

TODO 📅

Maintain constant common-mode during conversion

Redundancy

Max tolerance of comparator offset is $\pm V_{F S} / 4$

$b_{j}$ error is $\pm 1$
$b_{j + 1}$ error is $\pm 2$ , wherein $b_{j + 1}$ : $0 \to 2$ or $1 \to - 1$

i.e. complementary analog and digital errors cancel each other, $V_{o} + Δ V_{o}$ should be in over-/under-range comparators ( $- V_{F S} / 2 \sim 3 V_{F S} / 2$ )

$\begin{aligned} V_{i n, j} & = (b_{j} + Δ b_{j}) \cdot \frac{V_{F S}}{2} + \frac{V_{o u t, j} + Δ V_{o u t, j}}{2} \\ V_{i n, j + 1} & = (b_{j + 1} + Δ b_{j + 1}) \cdot \frac{V_{F S}}{2} + \frac{V_{o u t, j + 1} + Δ V_{o u t, j + 1}}{2} \end{aligned}$

with $V_{i n, j + 1} = V_{o u t, j} + Δ V_{o u t, j}$

$\begin{aligned} V_{i n, j} & = (b_{j} + Δ b_{j}) \cdot \frac{V_{F S}}{2} + \frac{1}{2} {(b_{j + 1} + Δ b_{j + 1}) \cdot \frac{V_{F S}}{2} + \frac{V_{o u t, j + 1} + Δ V_{o u t, j + 1}}{2}} \\ = (b_{j} + Δ b_{j}) \cdot \frac{V_{F S}}{2} + \frac{1}{2} (b_{j + 1} + Δ b_{j + 1}) \cdot \frac{V_{F S}}{2} + \frac{1}{2} \frac{V_{i n, j + 2}}{2} \\ = \tilde{b_{j}} \cdot \frac{V_{F S}}{2} + \tilde{b_{j + 1}} \cdot \frac{V_{F S}}{4} + \frac{1}{4} V_{i n, j + 2} \end{aligned}$

where $b_{j}$ is 1-bit residue without redundancy and $\tilde{b_{j}}$ is redundant bits

Uniform Sub-Radix-2 SAR ADC

Minimal analog complexity, no additional decoding effort

Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." (2013). [https://dspace.mit.edu/bitstream/handle/1721.1/82177/861702792-MIT.pdf]

Kuttner, Franz. "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS." 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 1 (2002): 176-177 vol.1. [https://sci-hub.se/10.1109/ISSCC.2002.992993]

T. Ogawa, H. Kobayashi, et. al., "SAR ADC Algorithm with Redundancy and Digital Error Correction." IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A (2010): 415-423. [paper, slides]

B. Murmann, “On the use of redundancy in successive approximation A/D converters,” International Conference on Sampling Theory and Applications (SampTA), Bremen, Germany, July 2013. [https://www.eurasip.org/Proceedings/Ext/SampTA2013/papers/p556-murmann.pdf]

Krämer, M. et al. (2015) High-resolution SAR A/D converters with loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].

sarthak, "Visualising redundancy in a 1.5 bit pipeline ADC“ [https://electronics.stackexchange.com/a/523489/233816]

Testing

TODO 📅

Kent H. Lundberg "Analog-to-Digital Converter Testing" [https://www.mit.edu/~klund/A2Dtesting.pdf]

Tai-Haur Kuo, Da-Huei Lee "Analog IC Design: ADC Measurement" [http://msic.ee.ncku.edu.tw/course/aic/202309/ch13%20(20230111).pdf] [http://msic.ee.ncku.edu.tw/course/aic/aic.html]

ESE 6680: Mixed Signal Design and Modeling "Lec 20: April 10, 2023 Data Converter Testing" [https://www.seas.upenn.edu/~ese6680/spring2023/handouts/lec20.pdf]

Degang Chen. "Distortion Analysis" [https://class.ece.iastate.edu/djchen/ee435/2017/Lecture25.pdf]

ADC INL/DNL

TODO 📅

Endpoint method
BestFit method

INL/DNL Measurements for High-Speed Analog-to Digital Converters (ADCs) [https://picture.iczhiku.com/resource/eetop/sYKTSqLfukeHSmMB.pdf]

Code Density Test

Apply a linear ramp to ADC input

Mid-Rise & Mid-Tread Quantizer

The difference between the lowest and highest levels is called the full-scale (FS) of the quantizer

Bootstrapped Switch

A. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to Digital Converter," IEEE J. Solid-State Circuits, pp. 599, May 1999 [https://sci-hub.se/10.1109/4.760369]

Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electronics Letters, Jan. 1999. [https://sci-hub.se/10.1049/EL:19990028]

B. Razavi, "The Bootstrapped Switch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15Switch.pdf]

B. Razavi, "The Design of a bootstrapped Sampling Circuit [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 13, Issue. 1, pp. 7-12, Summer 2021. [http://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_1_2021.pdf]

Quantization Noise & its Spectrum

Quantization noise is less with higher resolution as the input range is divided into a greater number of smaller ranges

This error can be considered a quantization noise with RMS

ENOB & SQNR

The quantization noise power $P_{Q}$ for a uniform quantizer with step size $Δ$ is given by $P_{Q} = \frac{Δ^{2}}{12}$ For a full-scale sinusoidal input signal with an amplitude equal to $V_{F S} / 2$ , the input signal is given by $x (t) = \frac{V_{F S}}{2} \sin (ω t)$

Then input signal power $P_{s}$ is $P_{s} = \frac{V_{F S}^{2}}{8}$ Therefore, the signal-to-quantization noise ratio (SQNR) is given by $SQNR = \frac{P_{s}}{P_{Q}} = \frac{V_{F S}^{2} / 8}{Δ^{2} / 12} = \frac{V_{F S}^{2} / 8}{V_{F S}^{2} / (12 \times 2^{2 N})} = \frac{3 \times 2^{2 N}}{2}$ where $N$ is the number of quantization bits

When represented in dBs $SQNR(dB) = 10 \log (\frac{P_{s}}{P_{Q}}) = 10 \log (\frac{3 \times 2^{2 N}}{2}) = 20 N \log (2) + 10 \log (\frac{3}{2}) = 6.02 N + 1.76$

Quantization is NOT Noise

DAC DNL

One difference between ADC and DAC is that DAC DNL can be less than -1 LSB

In a DAC, DNL < -1LSB implies non-monotonicity

DAC INL

The worst INL of three DAC Architecture is same

$A = \sum_{j = 1}^{k} I_{j}$ , $B = \sum_{j = k + 1}^{N} I_{j}$
A and B are independent with $σ_{A}^{2} = k σ_{u}^{2}$ and $σ_{B}^{2} = (N - k) σ_{u}^{2}$

Therefore $Var (\frac{X}{Y}) ≃ \frac{k^{2}}{N^{2}} (\frac{σ_{i}^{2}}{k I_{u}^{2}} + \frac{σ_{i}^{2}}{N I_{u}^{2}} - 2 \frac{cov (X, Y)}{k N I_{u}^{2}})$ and $\begin{aligned} cov (X, Y) & = E [X Y] - E [X] E [Y] = E [A (A + B)] - k N I_{u}^{2} \\ = E [A^{2}] + E [A] E [B] - k N I_{u}^{2} = σ_{A}^{2} + E [A]^{2} + k (N - k) I_{u}^{2} - k N I_{u}^{2} \\ = k σ_{i}^{2} + k^{2} I_{u}^{2} + k (N - k) I_{u}^{2} - k N I_{u}^{2} \\ = k σ_{i}^{2} \end{aligned}$

Finally, $Var (\frac{X}{Y}) ≃ \frac{k^{2}}{N^{2}} (\frac{σ_{i}^{2}}{k I_{u}^{2}} + \frac{σ_{i}^{2}}{N I_{u}^{2}} - 2 \frac{k σ_{i}^{2}}{k N I_{u}^{2}}) = \frac{k^{2}}{N^{2}} (\frac{1}{k} - \frac{1}{N}) σ_{u}^{2}$ i.e. $Var (INL (k)) = k^{2} (\frac{1}{k} - \frac{1}{N}) σ_{u}^{2} = k (1 - \frac{k}{N}) σ_{u}^{2}$

Standard deviation of INL is maximum at mid-scale (k=N/2)

Bottom plate sampling

Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling

[https://indico.cern.ch/event/1064521/contributions/4475393/attachments/2355793/4078773/esi_sampling_and_converters2022.pdf]

EE 435 Spring 2024 Analog VLSI Circuit Design - Switched-Capacitor Amplifiers Other Integrated Filters, https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf

Hold Mode Feedthrough

P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 544-634

B. Sedighi, A. T. Huynh and E. Skafidas, "A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 113-116

Tania Khanna, ESE 568: Mixed Signal Circuit Design and Modeling [https://www.seas.upenn.edu/~ese5680/fall2019/handouts/lec11.pdf]

Summing Interleaved Alias

The sampling function - impulse train is $s (t) = \sum_{n = - \infty}^{\infty} [δ (t - n 4 T_{s}) + δ (t - n 4 T_{s} - T_{s}) + δ (t - n 4 T_{s} - 2 T_{s}) + δ (t - n 4 T_{s} - 3 T_{s})]$

Its Fourier transform is $\begin{aligned} S (f) & = \frac{2 π}{4 T} \sum_{k = - \infty}^{\infty} [δ (f - k \frac{f_{s}}{4}) + e^{- j 2 π f \cdot T_{s}} δ (f - k \frac{f_{s}}{4}) + e^{- j 2 π f \cdot 2 T_{s}} δ (f - k \frac{f_{s}}{4}) + e^{- j 2 π f \cdot 3 T_{s}} δ (f - k \frac{f_{s}}{4})] \\ = \frac{2 π}{4 T} \sum_{k = - \infty}^{\infty} (1 + e^{- j 2 π \frac{f}{f_{s}}} + e^{- j 4 π \frac{f}{f_{s}}} + e^{- j 6 π \frac{f}{f_{s}}}) δ (f - k \frac{f_{s}}{4}) \\ = \frac{2 π}{4 T} \sum_{k = - \infty}^{\infty} (1 + e^{- j k \frac{π}{2}} + e^{- j k π} + e^{- j k \frac{3 π}{2}}) δ (f - k \frac{f_{s}}{4}) \end{aligned}$

We define $M [k] = 1 + e^{- j k \frac{π}{2}} + e^{- j k π} + e^{- j k \frac{3 π}{2}}$ , which is periodic, i.e. $M [k] = M [k + 4]$ $M [k] = {\begin{array}{cl} 4 & : k = 4 m \\ 0 & : k = 4 m + 1 \\ 0 & : k = 4 m + 2 \\ 0 & : k = 4 m + 3 \end{array}$

That is $S (f) = \frac{2 π}{T} \sum_{k = - \infty}^{\infty} δ (f - k f_{s})$

Alias has same frequency for each slice but different phase: Alias terms sum to zero if all slices match exactly

John P. Keane, ISSCC2020, T5: "Fundamentals of Time-Interleaved ADCs"

Random Chopping in TI-ADC

$D_{n} (k T) = (G_{n} R (k T) V (k T) + O_{n}) R (k T) = C_{n} V (k T) + R (k T) O_{n}$

coherent sampling

integer # of cycles or Windowing
- avoid spectral leakage
$f_{in}$ and $f_{s}$ are co-prime
- avoid periodic quantization errors, manifested as harmonic distortions

To avoid spectral leakage completely, the method of coherent sampling is recommended. Coherent sampling requires that the input- and clock-frequency generators are phase locked, and that the input frequency be chosen based on the following relationship: $\frac{f_{in}}{f_{s}} = \frac{M_{C}}{N_{R}}$

where:

$f_{in}$ = the desired input frequency
$f_{s}$ = the clock frequency of the data converter under test
$M_{C}$ = the number of cycles in the data window (to make all samples unique, choose odd or prime numbers)
$N_{R}$ = the data record length (for an 8192-point FFT, the data record is 8192s long)

$\begin{aligned} f_{in} & = \frac{f_{s}}{N_{R}} \cdot M_{C} \\ = f_{res} \cdot M_{C} \end{aligned}$

irreducible ratio

An irreducible ratio ensures identical code sequences not to be repeated multiple times. Unnecessary repetition of the same code is not desirable as it increases ADC test time.

Given that $\frac{M_{C}}{N_{R}}$ is irreducible, and $N_{R}$ is a power of 2, an odd number for $M_{C}$ will always produce an irreducible ratio

Assuming there is a common factor $k$ between $M_{C}$ and $N_{R}$ , i.e. $\frac{M_{C}}{N_{R}} = \frac{k M_{C}^{'}}{k N_{R}^{'}}$

The samples ( $n \in [1, N_{R}]$ )

$y [n] = \sin (ω_{in} \cdot t_{n}) = \sin (ω_{in} \cdot n \frac{1}{f_{s}}) = \sin (ω_{in} \cdot n \frac{1}{f_{in}} \frac{M_{C}}{N_{R}}) = \sin (2 π n \frac{M_{C}}{N_{R}})$

Then

$y [n + N_{R}^{'}] = \sin (2 π (n + N_{R}^{'}) \frac{M_{C}}{N_{R}}) = \sin (2 π n \frac{M_{C}}{N_{R}} + 2 π N_{R}^{'} \frac{M_{C}}{N_{R}}) = \sin (2 π n \frac{M_{C}}{N_{R}} + 2 π N_{R}^{'} \frac{k M_{C}^{'}}{k N_{R}^{'}}) = \sin (2 π n \frac{M_{C}}{N_{R}})$

So, the samples is repeated $y [n] = y [n + N_{R}^{'}]$ . Usually, no additional information is gained by repeating with the same sampling points.

samples of every input cycle are the same - periodic

Thermometer to Binary encoder

Pipeline ADC

CMP reference voltage is 0.5vref, DAC output is 0.5vref or 0

pipelineADC.drawio

residual error $V_{r, n} = (V_{r, n - 1} - \frac{1}{2} b_{n}) \cdot 2$ and $V_{r, - 1} = V_{i}$ $V_{r, n - 1} = 2^{n} V_{i} - \sum_{k = 0}^{n - 1} 2^{n - k - 1} b_{k} = 2^{n} (V_{i} - \sum_{k = 0}^{n - 1} \frac{b_{k}}{2^{k + 1}})$

here, $b_{0}$ is first stage and MSB

It divides the process into several comparison stages, the number of which is proportional to the number of bits

Due to the pipeline structure of both analog and digital signal path, inter-stage residue amplification is needed which consumes considerable power and limits high speed operation

Vishal Saxena, "Pipelined ADC Design - A Tutorial"[https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20NonIdealities%20Slides%20v1_0.pdf] [https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20Slides%20v1_2.pdf]

Bibhu Datta Sahoo, Analog-to-Digital Converter Design From System Architecture to Transistor-level [http://smdpc2sd.gov.in/downloads/IGF/IGF%201/Analog%20to%20Digital%20Converter%20Design.pdf]

Bibhu Datta Sahoo, Associate Professor, IIT, Kharagpur, [https://youtu.be/HiIWEBAYRJY?si=pjQnIdi03i5N7805]

R-2R & C-2C

TODO 📅

Conceptually, area goes up linearly with number of bit slices

drawback of the R-2R DAC

$N_{b}$ bit binary + $N_{t}$ bit thermometer DAC

R-2R.drawio

$N_{b}$ bit binary can be simplified with Thevenin Equivalent $V_{B} = \sum_{n = 0}^{N_{b} - 1} \frac{B_{n}}{2^{N_{b} - n}}$ with thermometer code

$\begin{aligned} V_{o} & = V_{B} \frac{\frac{2 R}{2^{N_{t}} - 1}}{\frac{2 R}{2^{N_{t}} - 1} + 2 R} + \sum_{n = 0}^{2^{N_{t}} - 2} T_{n} \frac{\frac{2 R}{2^{N_{t}} - 1}}{\frac{2 R}{2^{N_{t}} - 1} + 2 R} \\ = \frac{V_{B}}{2^{N_{t}}} + \frac{\sum_{n = 0}^{2^{N_{t}} - 2} T_{n}}{2^{N_{t}}} \\ = \sum_{n = 0}^{N_{b} - 1} \frac{B_{n}}{2^{N_{t} + N_{b} - n}} + \frac{\sum_{n = 0}^{2^{N_{t}} - 2} T_{n}}{2^{N_{t}}} \end{aligned}$

B. Razavi, "The R-2R and C-2C Ladders [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 10-15, Summer 2019 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2019.pdf]

4bit binary R2R DAC with Ru=1kOhm

RVB equivalent R

Binary-Weighted (BW) DAC

During $Φ_{1}$ , all capacitor are shorted, the net charge at $V_{x}$ is 0

During $Φ_{2}$ , the charge at bottom plate of CDAC $Q_{D A C, b t m} = \sum_{i = 0}^{N - 1} (b_{i} \cdot V_{R} - V_{x}) \cdot 2^{i} C_{u} = C_{u} V_{R} \sum_{i = 0}^{N - 1} b_{i} 2^{i} - (2^{N} - 1) C_{u} V_{x}$ the charge at the internal plate of integrator $Q_{i n t g} = V_{x} C_{p} + (V_{x} - V_{o}) 2^{N} C_{u}$ and we know $- V_{x} A = V_{o}$ and $Q_{D A C, b t m} = Q_{i n t g}$ $C_{u} V_{R} \sum_{i = 0}^{N - 1} b_{i} 2^{i} - (2^{N} - 1) C_{u} V_{x} = V_{x} C_{p} + (V_{x} - V_{o}) 2^{N} C_{u}$ i.e. $C_{u} V_{R} \sum_{i = 0}^{N - 1} b_{i} 2^{i} = (2^{N} - 1) C_{u} V_{x} + V_{x} C_{p} + (V_{x} - V_{o}) 2^{N} C_{u}$ therefore $- V_{o} = \frac{2^{N} C_{u}}{\frac{(2^{N + 1} - 1) C_{u} + C_{p}}{A} + 2^{N} C_{u}} \sum_{i = 0}^{N - 1} b_{i} (2^{i} \frac{V_{R}}{2^{N}}) \approx \sum_{i = 0}^{N - 1} b_{i} (2^{i} \frac{V_{R}}{2^{N}})$

Midscale (MSB Transition) often is the largest DNL error

$C_{4}$ and $C_{1} + C_{2} + C_{3}$ are independent (can't cancel out) and their variance is two largest ( $16 σ_{u}^{2}$ , $15 σ_{u}^{2}$ , ), the total standard deviation is $\sqrt{16 σ_{u}^{2} + 15 σ_{u}^{2}} = \sqrt{31} σ_{u}$

reference

Aaron Buchwald, ISSCC2010 T1: "Specifying & Testing ADCs" [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Tutorials/T1.pdf]

John P. Keane, ISSCC2020, T5: "Fundamentals of Time-Interleaved ADCs" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T5Visuals.pdf]

Yun Chiu, ISSCC2023 T3: "Fundamentals of Data Converters" [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T3.pdf]

—， "Design and Calibration Techniques for SAR and Pipeline ADCs"

Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]

Aaron Buchwald, ISSCC 2008 T2 Pipelined A/D Converters:The Basics [pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

M. Gu, Y. Tao, Y. Zhong, L. Jie and N. Sun, "Timing-Skew Calibration Techniques in Time-Interleaved ADCs," in IEEE Open Journal of the Solid-State Circuits Society [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623]

everynanocounts. Memos on FFT With Windowing. URL: https://a2d2ic.wordpress.com/2018/02/01/memos-on-fft-with-windowing/

How to choose FFT depth for ADC performance analysis (SINAD, ENOB). URL:https://dsp.stackexchange.com/a/38201

Computation of Effective Number of Bits, Signal to Noise Ratio, & Signal to Noise & Distortion Ratio Using FFT. URL:https://cdn.teledynelecroy.com/files/appnotes/computation_of_effective_no_bits.pdf

Kester, Walt. (2009). Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor. URL:https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

T. C. Hofner: Dynamic ADC testing part I. Defining and testing dynamic ADC parameters, Microwaves & RF, 2000, vol. 39, no. 11, pp. 75-84,162

T. C. Hofner: Dynamic ADC testing part 2. Measuring and evaluating dynamic line parameters, Microwaves & RF, 2000, vol. 39, no. 13, pp. 78-94

AN9675: A Tutorial in Coherent and Windowed Sampling with A/D Converters https://www.renesas.com/us/en/document/apn/an9675-tutorial-coherent-and-windowed-sampling-ad-converters

APPLICATION NOTE 3190: Coherent Sampling Calculator (CSC) https://www.stg-maximintegrated.com/en/design/technical-documents/app-notes/3/3190.html

Coherent Sampling (Very Brief and Simple) https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple

Signal Chain Basics #160: Making sense of coherent and noncoherent sampling in data-converter testing https://www.planetanalog.com/signal-chain-basics-160-making-sense-of-coherent-and-noncoherent-sampling-in-data-converter-testing/

Signal Chain Basics #104: Understanding noise in ADCs https://www.planetanalog.com/signal-chain-basics-part-104-understanding-noise-in-adcs/

Signal Chain Basics #101: ENOB Degradation Analysis Over Frequency Due to Jitter https://www.planetanalog.com/signal-chain-basics-part-101-enob-degradation-analysis-over-frequency-due-to-jitter/

Clock jitter analyzed in the time domain, Part 1, Texas Instruments Analog Applications Journal (slyt379), Aug 2010 https://www.ti.com/lit/an/slyt379/slyt379.pdf

Clock jitter analyzed in the time domain, Part 2 https://www.ti.com/lit/slyt389

Measurement of Total Harmonic Distortion and Its Related Parameters using Multi-Instrument [pdf]

Application Note AN-4: Understanding Data Converters' Frequency Domain Specifications [pdf]

Belleman, J. (2008). From analog to digital. 10.5170/CERN-2008-003.131. [pdf]

HandWiki. Coherent sampling [link]

Luis Chioye, TI. Leverage coherent sampling and FFT windows when evaluating SAR ADCs (Part 1) [link]

Coherent Sampling vs. Window Sampling | Analog Devices https://www.analog.com/en/technical-articles/coherent-sampling-vs-window-sampling.html

Understanding Effective Number of Bits https://robustcircuitdesign.com/signal-chain-explorer/understanding-effective-number-of-bits/

ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise? [https://www.analog.com/en/resources/analog-dialogue/articles/adc-input-noise.html]

Walt Kester, Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care [https://www.analog.com/media/en/training-seminars/tutorials/MT-001.pdf]

Dan Boschen, "How to choose FFT depth for ADC performance analysis (SINAD, ENOB)", [https://dsp.stackexchange.com/a/38201]

B. Razavi, "A Tale of Two ADCs - Pipelined Versus SAR" IEEE Solid-State Circuits Magazine, Volume. 7, Issue. 30, pp. 38-46, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15ADC.pdf))]

Bias Circuit

Posted on 2024-07-27 Edited on 2023-07-10 In analog

replica biasing

TODO 📅

current mirror with source follower

icurrent_sf.drawio

source follower alleviate gate leakage impact on reference current

Curvature compensation

Tutorials | 08012023 | 1.2.1 Bandgap Voltage Regular |, [https://youtu.be/dz067SOX0XQ?si=PlYczw9UdneAX6Na]

Subthreshold Conduction

By square-law, the Eq $g_{m} = \sqrt{2 μ C_{o x} \frac{W}{L} I_{D}}$ , it is possible to obtain a higer transconductance by increasing $W$ while maintaining $I_{D}$ constant. However, if $W$ increases while $I_{D}$ remains constant, then $V_{G S} \to V_{T H}$ and device enters the subthreshold region. $I_{D} = I_{0} \exp \frac{V_{G S}}{ξ V_{T}}$

where $I_{0}$ is proportional to $W / L$ , $ξ > 1$ is a nonideality factor, and $V_{T} = k T / q$

As a result, the transconductance in subthreshold region is $g_{m} = \frac{I_{D}}{ξ V_{T}}$

which is $g_{m} \propto I_{D}$

PTAT with subthreshold MOS

MOS working in the weak inversion region ("subthreshold conduction") have the similar characteristics to BJTs and diodes, since the effect of diffusion current becomes more significant than that of drift current

Hongprasit, Saweth, Worawat Sa-ngiamvibool and Apinan Aurasopon. "Design of Bandgap Core and Startup Circuits for All CMOS Bandgap Voltage Reference." Przegląd Elektrotechniczny (2012): 277-280.

VBE

temperature coefficient of $V_{B E}$ itself depends on the temperature,
temperature coefficient of the $V_{B E}$ at a given temperature T depends on the magnitude of $V_{B E}$ itself

$\frac{k T}{q}$ is approximately 26mV, at room temperature 300K

In advanced node, N4P, $V_{B E}$ is about -1.45mV/K

constant-gm

aka. Beta-multiplier reference

$I_{out}$ is PTAT in case temperature coefficient of $R_{s}$ is less than that of $μ_{n}$

Body effect of M2

Boris Murmann, Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables

S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias Circuits," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022

S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver , May 2004

Why MOS in saturation ?

$g_{m}$ , $g_{ds}$ at fixed $V_{GS}$

$g_{d s}$ is constant in saturation region

in triode region $g_{d s} = μ_{n} C_{o x} \frac{W}{L} (V_{G S} - V_{T H} - V_{D S})$

Interestingly, $g_{m}$ in the saturation region is equal to the inverse of $R_{on}$ in the deep triode region.

gds_vgs.drawio

$g_{m}$ , $g_{ds}$ at fixed $I_{d}$ , $V_{G}$

In triode region $I_{D} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} [2 (V_{G S} - V_{T H}) V_{D S} - V_{D S}^{2}]$ where $I_{D}$ and $V_{G}$ is fixed

Then $V_{S}$ can be expressed with $V_{D}$ , that is $V_{S} = V_{G T} - \sqrt{(V_{G T} - V_{D})^{2} + V_{d s a t}^{2}}$ where $V_{G T} = V_{G} - V_{T H}$ , $V_{d s a t}$ is $V_{D S}$ saturation voltage $g_{m} = μ_{n} C_{o x} \frac{W}{L} (V_{D} - V_{G T} + \sqrt{(V_{G T} - V_{D})^{2} + V_{d s a t}^{2}})$ Then $\frac{\partial g_{m}}{\partial V_{D}} \propto 1 - \frac{V_{G T} - V_{D}}{\sqrt{(V_{G T} - V_{D})^{2} + V_{d s a t}^{2}}} > 0$

That is, $g_{m} \propto V_{D}$

$\begin{aligned} g_{d s} & = μ_{n} C_{o x} \frac{W}{L} (V_{G S} - V_{T H} - V_{D S}) \\ = μ_{n} C_{o x} \frac{W}{L} (V_{G T} - V_{D}) \end{aligned}$

That is, $g_{d s} \propto - V_{D}$

Both gain and speed degrade once entering triode region, though Id is constant

Cascode MOS

The low threshold voltage of cascode MOS don't help decrease the minimum output voltage

cascode_vth.drawio

Channel-length modulation

❗ There it not channel-length modulation in the triode region

$\begin{aligned} I_{D} & = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{G S} - V_{T H})^{2} (1 + \frac{Δ L}{L}) \\ I_{D} & = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{G S} - V_{T H})^{2} (1 + λ V_{D S}) \\ I_{D} & = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{G S} - V_{T H})^{2} (1 + \frac{V_{D S}}{V_{A}}) \end{aligned}$

where $\frac{Δ L}{L} = λ V_{D S}$ and $V_{A} = \frac{1}{λ}$

$λ$ is channel length modulation parameter

$V_{A}$ , i.e. Early voltage is equal to inverse of channel length modulation parameter

The output resistance $r_{o}$

$\begin{aligned} r_{o} & = \frac{\partial V_{D S}}{\partial I_{D}} \\ = \frac{1}{\partial I_{D} / \partial V_{D S}} \\ = \frac{1}{λ I_{D}} \\ = \frac{V_{A}}{I_{D}} \end{aligned}$

Due to $λ \propto 1 / L$ , i.e. $V_{A} \propto L$ $r_{o} \propto \frac{L}{I_{D}}$

The output resistance is almost doubled using Stacked FET in saturation region

$V_{t}$ and mobility $μ_{n, p}$ are sensitive to temperature

$V_{t}$ decreases by 2-mV for every 1 $^{o} C$ rise in temperature

mobility $μ_{n, p}$ decreases with temperature

Overall, increase in temperature results in lower drain currents

current mirror mismatch

The current mismatch consists of two components.

The first depends on threshold voltage mismatch and increases as the overdrive $(V_{G S} - V_{t})$ is reduced.
The second is geometry dependent and contributes a fractional current mismatch that is independent of bias point.

$Δ I_{D} = g_{m} \cdot Δ V_{T H} + I_{D} \cdot \frac{Δ (W / L)}{W / L}$

where mismatches in $μ_{n} C_{o x}$ are neglected

$\begin{aligned} Δ V_{T H} & = \frac{A_{V T H}}{\sqrt{W L}} \\ \frac{Δ (W / L)}{W / L} & = \frac{A_{W L}}{\sqrt{W L}} \end{aligned}$

summary:

Size	$g_{m}$	$Δ V_{T H}$	$\frac{Δ (W / L)}{W / L}$	mismatch (%)	simu (%)
W, L	1	1	1	$I_{Δ_{V_{T H}}} + I_{Δ_{W L}}$	3.44
W, 2L	$1 / \sqrt{2}$	$1 / \sqrt{2}$	$1 / \sqrt{2}$	$I_{Δ_{V_{T H}}} / 2 + I_{Δ_{W L}} / \sqrt{2}$	1.98
2W, L	$\sqrt{2}$	$1 / \sqrt{2}$	$1 / \sqrt{2}$	$I_{Δ_{V_{T H}}} + I_{Δ_{W L}} / \sqrt{2}$	2.93
We get $I_{Δ_{V_{T H}}} ≃ 1.71 %$ and $I_{Δ_{W L}} ≃ 1.73 %$

Biasing current source and global variation Monte Carlo

iwl: biased by mirror

iwl_ideal: biased by vdc source, whose value is typical corner

For local variation, constant voltage bias (vb_const in schematic) help reduce variation from $\sqrt{2} Δ V_{t h}$ to $Δ V_{t h}$

For global variation, all device have same variation, mirror help reduce variation by sharing same $V_{g s}$

global variation + local variation (All MC)

local variation (Mismatch MC)

global variation (Process MC)

We had better bias mos gate with mirror rather than the vdc source while simulating sub-block.

This is real situation due to current source are always biased by mirror and vdc biasing don't give the right result in global variation Monte Carlo simulation (542.8n is too pessimistic, 13.07p is right result)

Small gain theorem

Dr. Degang Chen, EE 501: CMOS Analog Integrated Circuit Design [https://class.ece.iastate.edu/djchen/ee501/2020/References.ppt]

For any given constant values of u and v, the constant values of variables that solve the the feed back relationship are called the operating points, or equilibrium points.

Operating points can be either stable or unstable.

An operating point is unstable if any or some small perturbation near it causes divergence away from that operating point.

If the loop gain evaluated at an operating point is less than one, that operating point is stable.

This is a sufficient condition

With $m_{1 \to 2} = 1$ $\begin{matrix} (L G_{0}) & Loop Gain ≃ \frac{V_{B N} - V_{T 2}}{V_{B N} - V_{T 2} + V_{R}} \end{matrix}$ Assuming all MOS in strong inv operation, $I$ , $V_{B N}$ and $V_{R}$ is obtain $\begin{aligned} I & = \frac{2 β_{1} + 2 β_{2} - 4 \sqrt{β_{1} β_{2}}}{R^{2} β_{1} β_{2}} \\ V_{B N} & = V_{T 2} + \frac{2}{R β_{2}} (1 - \sqrt{\frac{β_{2}}{β_{1}}}) \\ I R & = \frac{2}{R} (\frac{1}{\sqrt{β_{2}}} - \frac{1}{\sqrt{β_{1}}}) \end{aligned}$

Substitute $V_{B N}$ and $V_{R}$ of $L G_{0}$ $\begin{aligned} Loop Gain & ≃ \frac{1 - \sqrt{\frac{β_{2}}{β_{1}}}}{\frac{β_{2}}{β_{1}} - 3 \sqrt{\frac{β_{2}}{β_{1}}} + 2} \\ (L G_{1}) & = \frac{1}{2 - \sqrt{\frac{β_{2}}{β_{1}}}} \end{aligned}$

Alternative approach for Loop Gain

using derivation of large signal

❗❗❗ R should not be on the other side

Self-Biasing Cascode

cascode_selfbias.drawio

v2i.drawio

cap network

pi_Cap.drawio

$\begin{aligned} (V_{a} - V_{a 0}) C_{0} + (\overset{―}{V_{a} - V_{b}} - \overset{―}{V_{a 0} - V_{b 0}}) C_{1} & = Δ Q_{a} \\ (V_{b} - V_{b 0}) C_{0} + (\overset{―}{V_{b} - V_{a}} - \overset{―}{V_{b 0} - V_{a 0}}) C_{1} & = Δ Q_{b} \end{aligned}$

therefore we obtain $\begin{aligned} V_{a} + V_{b} & = \frac{Δ Q_{a} + Δ Q_{b}}{C_{0}} + V_{a 0} + V_{b 0} \\ V_{a} - V_{b} & = \frac{Δ Q_{a} - Δ Q_{b}}{C_{0} + 2 C_{1}} + V_{a 0} - V_{b 0} \end{aligned}$ Then $\begin{aligned} V_{a} & = \frac{Δ Q_{a} (C_{0} + C_{1}) + Δ Q_{b} C_{1}}{C_{0} (C_{0} + 2 C_{1})} + V_{a 0} \\ V_{b} & = \frac{Δ Q_{a} C_{1} + Δ Q_{b} (C_{0} + C_{1})}{C_{0} (C_{0} + 2 C_{1})} + V_{b 0} \end{aligned}$

rearrange the above equation $\begin{aligned} V_{a} & = \frac{Δ Q_{a}}{C_{0}} + \frac{Δ Q_{b} - Δ Q_{a}}{C_{0} (\frac{C_{0}}{C_{1}} + 2)} + V_{a 0} \\ V_{b} & = \frac{Δ Q_{b}}{C_{0}} + \frac{Δ Q_{a} - Δ Q_{b}}{C_{0} (\frac{C_{0}}{C_{1}} + 2)} + V_{b 0} \end{aligned}$

The difference between $V_{a}$ and $V_{b}$ $V_{a} - V_{b} = \frac{I_{a} - I_{b}}{C_{0} + 2 C_{1}} t + V_{a 0} - V_{b 0}$

$C_{1}$ save total capacitor area while obtaining same $V_{a} - V_{b}$ due to $Δ I_{a, b}$ corresponding to $C_{0}$

at autozero phase $\begin{aligned} I_{a 0} & = \frac{1}{2} μ C_{O X} \frac{W}{L} (V_{a 0} - V_{T H})^{2} \\ I_{R b} & = \frac{1}{2} μ C_{O X} \frac{W}{L} (V_{b 0} - V_{T H})^{2} \end{aligned}$

then $Δ I_{0} = \frac{1}{2} (V_{a 0} - V_{b 0}) (g_{m, a 0} + g_{m, b 0})$ where $g_{m, a 0} + g_{m, b 0} = μ C_{O X} \frac{W}{L} (V_{a 0} + V_{b 0} - 2 V_{T H})$

at comparison phase $\begin{aligned} I_{a 1} & = \frac{1}{2} μ C_{O X} \frac{W}{L} (V_{a 1} - V_{T H})^{2} \\ I_{b 1} & = \frac{1}{2} μ C_{O X} \frac{W}{L} (V_{b 1} - V_{T H})^{2} \end{aligned}$

then $Δ I_{1} = \frac{1}{2} (V_{a 1} - V_{b 1}) (g_{m, a 1} + g_{m, b 1})$ That is, $g_{m, a 1} + g_{m, b 1} = μ C_{O X} \frac{W}{L} (V_{a 1} + V_{b 1} - 2 V_{T H})$

To minimize the difference between $Δ I_{1}$ and $Δ I_{0}$ , the drift of both differential and common mode between $V_{a}$ and $V_{b}$ shall be alleviated

reference

B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 6-16, Summer 2021, doi: 10.1109/MSSC.2021.3088963

Precision Techniques

Posted on 2024-07-17 Edited on 2023-07-10 In analog

Autozeroing

offset is sampled and then subtracted from the input

Measure the offset somehow and then subtract it from the input signal

low gain comparator

Residual Noise of Auto-zeroing

pnosie Noise Type: timeaverage

Chopping

offset is modulated away from the signal band and then filtered out

Modulate the offset away from DC and then filter it out

Good: Magically reduces offset, 1/f noise, drift

Bad: But creates switching spikes, chopper ripple and other artifacts …

Chopping in the Frequency Domain

Square-wave Modulation

definition of convolution $y (t) = x (t) * h (t) = \int_{- \infty}^{\infty} x (τ) h (t - τ) d τ$

for real signal $H (j ω)^{*} = H (- j ω)$

$H (j \hat{ω}) * H (j \hat{ω}) = \int_{- \infty}^{\infty} H (j ω) H (j (\hat{ω} - ω)) d ω$

sq_mod.drawio

The Fourier Series of squarewave $x (t)$ with amplitudes $\pm 1$ , period $T_{0}$

$C_{n} = {\begin{array}{cl} 0 & n = 0 \\ 0 & n = even \\ | \frac{2}{n π} | & n = \pm 1, \pm 5, \pm 9, . . . \\ - | \frac{2}{n π} | & n = \pm 3, \pm 7, \pm 11, . . . \end{array}$

The Fourier transform of $s (t) = x (t) x (t)$ , and we know $\begin{aligned} S (j 2 n ω_{0}) & = \frac{1}{2 π} \int X (j (2 n ω_{0} - ω)) X (j ω) d ω \\ = \frac{1}{2 π} \int X (j (ω - 2 n ω_{0})) X (j ω) d ω \end{aligned}$

Therefore $n = 0$ $S (j 0) = \frac{1}{2 π} (2 π)^{2} \cdot \frac{4}{π^{2}} 2 \sum_{n = 0}^{+ \infty} \frac{1}{(2 n + 1)^{2}} δ (ω) = 2 π δ (ω)$

if $n = 1$

$\begin{aligned} S (j 2 ω_{0}) & = \frac{1}{2 π} (2 π)^{2} \cdot \frac{4}{π^{2}} (1 - 2 \sum_{n = 0}^{+ \infty} \frac{1}{(2 n + 1) (2 n + 3)}) \\ = \frac{1}{2 π} (2 π)^{2} \cdot \frac{4}{π^{2}} (1 - 2 \sum_{n = 0}^{+ \infty} \frac{1}{2} [\frac{1}{2 n + 1} - \frac{1}{2 n + 3}]) \\ = 0 \end{aligned}$

$n = 2$ $\begin{aligned} \sum & = - \frac{2}{3} + 2 (\frac{1}{1 \times 5} + \frac{1}{3 \times 7} + \frac{1}{5 \times 9} + \frac{1}{7 \times 11} + . . .) \\ = - \frac{2}{3} + 2 \cdot \frac{1}{4} (\frac{1}{1} - \frac{1}{5} + \frac{1}{3} - \frac{1}{7} + \frac{1}{5} - \frac{1}{9} + \frac{1}{7} - \frac{1}{11} + . . .) \\ = - \frac{2}{3} + 2 \cdot \frac{1}{4} \frac{4}{3} = 0 \end{aligned}$

That is, the input signal remains the same after chopping or squarewave up/down modulation

EXAMPLE 2.7 in R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

Prove that $π^{2} / 8 = 1 + 1 / 3^{2} + 1 / 5^{2} + 1 / 7^{2} + \dots$ [https://math.stackexchange.com/a/2348996]

Bandwidth & Gain Accuracy

lower effective gain: DC level at the output of the amplifiers is a bit less than what it should be
chopping artifacts at the even harmonics: frequency of output is $2 f_{c h}$

Below we justify $A_{eff} = A (1 - 4 τ / T_{ch})$ $\begin{aligned} V_{o} (t) & = A + (V_{0} - A) e^{- t / τ} \\ V_{o} (T / 2) & = - V_{0} \end{aligned}$

then $V_{0} = - A \frac{1 - e^{- T / 2 τ}}{1 + e^{- T / 2 τ}}$ Then DC level is $A_{eff} = \frac{1}{T / 2} \int_{0}^{T / 2} V_{o} (t) d t = A (1 - \frac{4 τ}{T} \cdot \frac{1 - e^{- T / 2 τ}}{1 + e^{- T / 2 τ}}) \approx A (1 - \frac{4 τ}{T})$

where assuming $τ ≪ T$

REF. [https://raytroop.github.io/2023/01/01/insight/#rc-charge-and-discharge]

chopping_OTA_limitedBW.drawio

Residual Offset of Chopping

assume input spikes can be expressed as $V_{spike} (t) = V_{o} e^{- \frac{t}{τ}}$

Then, residual offset is

$\begin{aligned} \overset{―}{V_{os}} & = \frac{2 \int_{0}^{T_{c h} / 2} V_{spike} (t) d t}{T_{c h}} \\ = 2 f_{c h} V_{o} \int_{0}^{T_{c h} / 2} e^{- \frac{t}{τ}} d t \\ = 2 f_{c h} V_{o} τ \int_{0}^{T_{c h} / 2 τ} e^{- \frac{t}{τ}} d \frac{t}{τ} \\ \approx 2 f_{c h} V_{o} τ \end{aligned}$

Ripple Cancellation after Chopping

On-chip analog filter is not good enough due to limited cutoff frequency

TODO 📅

Dynamic Element Matching (DEM)

TODO 📅

Galton, Ian. (2010). Why dynamic-element-matching DACs work. Circuits and Systems II: Express Briefs, IEEE Transactions on. 57. 69 - 74. 10.1109/TCSII.2010.2042131. [https://sci-hub.se/10.1109/TCSII.2010.2042131]

KHIEM NGUYEN. Analog Devices Inc, "Practical Dynamic Element Matching Techniques for 3-level Unit Elements" [https://picture.iczhiku.com/resource/eetop/shihEDaaoJjFdCVc.pdf]

reference

C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," in Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996, doi: 10.1109/5.542410. [http://www2.ing.unipi.it/~a008309/mat_stud/MIXED/archive/2019/Articles/Offset_canc_Enz_Temes_96.pdf]

Kofi Makinwa. Precision Analog Circuit Design: Coping with Variability, [https://youtu.be/nA_DZtRqrTQ?si=6uyOpJhdnYm3iG9d] [https://youtu.be/uwRpP20Lprc?si=SGPta86jRCdECSob]

Chung-chun Chen, Why Design Challenge in Chopping Offset & Flicker Noise? [https://youtu.be/ydjca2KrXgc?si=2raCIB99vXriMPsq]

—, Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise? [https://youtu.be/y7TzJtHE7IA?si=kUeP_ESofVxp3IT_]

Qinwen Fan, Evolution of precision amplifiers

Kofi Makinwa, ISSCC 2007 Dynamic-Offset Cancellation Techniques in CMOS [https://picture.iczhiku.com/resource/eetop/sYkywlkpwIQEKcxb.pdf]

Axel Thomsen, Silicon Laboratories ISSCC2012Visuals-T8: "Managing Offset and Flicker Noise" [slides,transcript]

Systems, Modulation and Noise

Posted on 2024-05-25 Edited on 2023-07-10 In dsp

asymmetric sideband

The spectrum of the narrowband FM signal is very similar to that of an amplitude modulation (AM) signal but has the phase reversal for the other sideband component

Assume the modulation frequency of PM and AM are same, $ω_{m}$

$\begin{aligned} x (t) & = (1 + A_{m} \cos ω_{m} t) \cos (ω_{0} t + P_{m} \sin ω_{m} t) \\ = \cos (ω_{0} t + P_{m} \sin ω_{m} t) + A_{m} \cos ω_{m} t \cos (ω_{0} t + P_{m} \sin ω_{m} t) \\ = X_{p m} (t) + X_{a p m} (t) \end{aligned}$

$X_{p m} (t)$ , PM only part $X_{p m} (t) = \cos ω_{0} t - \frac{P_{m}}{2} \cos (ω_{0} - ω_{m}) t + \frac{P_{m}}{2} \cos (ω_{0} + ω_{m}) t$ $X_{a p m} (t)$ , AM & PM part $\begin{aligned} X_{a p m} (t) & = A_{m} \cos ω_{m} t (\cos ω_{0} t - P_{m} \sin ω_{m} t \sin ω_{0} t) \\ = \frac{A_{m}}{2} [\cos (ω_{0} + ω_{m}) t + \cos (ω_{0} - ω_{m}) t] - \frac{A_{m} P_{m}}{2} \sin (2 ω_{m} t) \sin (ω_{0} t) \\ = \frac{A_{m}}{2} \cos (ω_{0} + ω_{m}) t + \frac{A_{m}}{2} \cos (ω_{0} - ω_{m}) t - \frac{A_{m} P_{m}}{4} \cos (ω_{0} - 2 ω_{m}) t + \frac{A_{m} P_{m}}{4} \cos (ω_{0} + 2 ω_{m}) t \end{aligned}$

That is $\begin{aligned} x (t) & = \cos ω_{0} t + \frac{A_{m} - P_{m}}{2} \cos (ω_{0} - ω_{m}) t + \frac{A_{m} + P_{m}}{2} \cos (ω_{0} + ω_{m}) t \\ - \frac{A_{m} P_{m}}{4} \cos (ω_{0} - 2 ω_{m}) t + \frac{A_{m} P_{m}}{4} \cos (ω_{0} + 2 ω_{m}) t \end{aligned}$

For general case, $x (t) = (1 + A_{m} \cos ω_{a m} t) \cos (ω_{0} t + P_{m} \sin ω_{p m} t)$ , i.e., PM is $ω_{p m}$ , AM is $ω_{a m}$

$\begin{aligned} x (t) & = \cos ω_{0} t - \frac{P_{m}}{2} \cos (ω_{0} - ω_{p m}) t + \frac{P_{m}}{2} \cos (ω_{0} + ω_{p m}) t \\ + \frac{A_{m}}{2} \cos (ω_{0} - ω_{a m}) t + \frac{A_{m}}{2} \cos (ω_{0} + ω_{a m}) t \\ - \frac{A_{m} P_{m}}{4} \cos (ω_{0} - ω_{p m} - ω_{a m}) t + \frac{A_{m} P_{m}}{4} \cos (ω_{0} + ω_{p m} + ω_{a m}) t \\ + \frac{A_{m} P_{m}}{4} \cos (ω_{0} + ω_{p m} - ω_{a m}) t - \frac{A_{m} P_{m}}{4} \cos (ω_{0} - ω_{p m} + ω_{a m}) t \end{aligned}$

Therefore, sideband is asymmetric if $ω_{p m} = ω_{a m}$

Ken Kundert, Measuring AM, PM & FM Conversion with SpectreRF [https://designers-guide.org/analysis/am-pm-conv.pdf]

Narrowband FM Approximation

$y (t) = A \cos (2 π f_{0} t + ϕ_{n} (t)) \approx A \cos (2 π f_{0} t) - A ϕ_{n} (t) \sin (2 π f_{0} t)$

$R_{x} (τ) = \frac{A^{2}}{2} \cos (2 π f_{0} τ) + \frac{A^{2}}{2} R_{ϕ} (τ) \cos (2 π f_{0} τ)$ The PSD of the signal x(t) is given by $S_{x} (f) = F {R_{x} (τ)} = \frac{P_{c}}{2} [δ (f + f_{0}) + δ (f - f_{0})] + \frac{P_{c}}{2} [S_{ϕ} (f + f_{0}) + S_{ϕ} (f - f_{0})]$ where $P_{c} = A^{2} / 2$ is the carrier power of the signal

Modulation of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: Modulation of Random Processes

modulated with a random cosine

modulated with a deterministic cosine

Hayder Radha, ECE 458 Communications Systems Laboratory Spring 2008: Lecture 7 - EE 179: Introduction to Communications - Winter 2006–2007 Energy and Power Spectral Density and Autocorrelation

Sampling of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: Impulse sampling of Random Processes

DT sequence $x [n]$

impulse train $x_{s} (t)$

That is $P_{x_{s} x_{s}} (f) = \frac{1}{T_{s}^{2}} P_{x x} (f)$ where $x [n]$ is sampled discrete-time sequence, $x_{s} (t)$ is sampled impulse train

Noise Aliasing

apply foregoing observation

Cyclostationary Noise (Modulated Noise)

[https://ece-research.unm.edu/bsanthan/ece541/cyclo.pdf]

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

White Noise Modulation

Noisy Resistor & Clocked Switch

$v_{t} (t) = v_{i} (t) \cdot m_{t} (t)$ where $v_{i} (t)$ is input white noise, whose autocorrelation is $A δ (τ)$ , and $m_{t} (t)$ is periodically operating switch, then autocorrelation of $v_{t} (t)$ $\begin{aligned} R_{t} (t_{1}, t_{2}) & = E [v_{t} (t_{1}) \cdot v_{t} (t_{2})] \\ = R_{i} (t_{1}, t_{2}) \cdot m_{t} (t_{1}) m_{t} (t_{2}) \end{aligned}$

Then $\begin{aligned} R_{t} (t, t - τ) & = R_{i} (τ) \cdot m_{t} (t) m_{t} (t - τ) \\ = A δ (τ) \cdot m_{t} (t) m_{t} (t - τ) \\ = A δ (τ) \cdot m_{t} (t) \end{aligned}$ Because $m_{t} (t) = m_{t} (t + T)$ , $R_{t} (t, t - τ)$ is is periodic in the variable $t$ with period $T$

The time-averaged ACF is denoted as $\tilde{R_{t}} (τ)$

${\tilde{R}}_{t} (τ) = m \cdot A δ (τ)$ That is, $S_{t} (f) = m \cdot S_{A} (f)$

Colored Noise Modulation

tavg_factor.drawio $\tilde{R_{t}} (τ) = R_{i} (τ) \cdot m_{t a c} (τ)$

where $m_{t} (t) m_{t} (t - τ)$ averaged on $t$ is denoted as $m_{t a c} (τ)$ or $\overset{―}{m_{t} (t) m_{t} (t - τ)}$

The DC value of $m_{t a c} (τ)$ can be calculated as below

for $m \leq 0.5$ , the DC value of $m_{t a c} (τ)$ $\frac{m \cdot m T}{T} = m^{2}$
for $m > 0.5$ , the DC value of $m_{t a c} (τ)$ $\frac{(m + 2 m - 1) (1 - m) T + (2 m - 1) {m T - (1 - m) T}}{T} = m^{2}$

Therefore, time-average power spectral density and total power are scaled by $m^{2}$ in fundamental frequency sideband

Switched-Capacitor Track signal

track signal pnoise (sc)

zoom in first harmonic by linear step of pnoise

decreasing the rising/falling time of clock, the harmonics still retain

equivalent circuit for pnoise (eq)

thermal noise of R is modulated at first
then filtered by ideal filter

sc vs eq

sc: harmonic distortion
eq: no harmonic distortion

Non-Stationary Processes

Wide-Sense-Stationary Noise

Much like sinusoidal-steady-state signal analysis, steady-state noise analysis methods assume an input x(t) of infinite duration, which is a Wide-Sense Stationary (WSS) random process

Frequency-domain Analysis

Time-domain Analysis

The output $y (t)$ of a linear time-invariant (LTI) system $h (t)$ $\begin{aligned} R_{y y} (τ) & = R_{x x} (τ) * [h (τ) * h (- τ)] \\ = S_{x x} (0) δ (τ) * [h (τ) * h (- τ)] \\ = S_{x x} (0) [h (τ) * h (- τ)] \\ = S_{x x} (0) \int_{α} h (α) h (α - τ) d α \end{aligned}$

with WSS white noise input $x (t)$ , $R_{x x} (τ) = S_{x x} (0) δ (τ)$ , therefore

Non-stationary Noise

Assuming the noise applied duration is much less than the time constant, the output voltage does not reach steady-state and WSS noise analysis does not apply

In order to determine the response of an LTI system to a step noise input, the problem is more conveniently solved in the time-domain

input signal: step ramp input

noise current: step

Time-domain Analysis

The step noise input $x (t) = ν (t) u (t)$ $R_{x x} (t_{1}, t_{2}) = E [x (t_{1}) x (t_{2})] = R_{ν ν} (t_{1}, t_{2}) u (t_{1}) u (t_{2}) = R_{ν ν} (t_{1}, t_{2})$

$R_{x y} (t_{1}, t_{2}) = E [x (t_{1}) y (t_{2})] = E [x (t_{1}) (x (t_{2}) * h (t_{2}))] = E (x (t_{1}) x (t_{2})) * h (t_{2}) = R_{x x} (t_{1}, t_{2}) * h (t_{2})$

$R_{y y} (t_{1}, t_{2}) = E [y (t_{1}) y (t_{2})] = E [(x (t_{1}) * h (t_{1})) y (t_{2})] = E [x (t_{1}) y (t_{2})] * h (t_{1}) = R_{x y} (t_{1}, t_{2}) * h (t_{1})$

the absolute value of each time index is important for a non-stationary signal, and only the time difference was important for WSS signals

$\begin{aligned} R_{y y} (t_{1}, t_{2}) & = h (t_{1}) * R_{ν ν} (t_{1}, t_{2}) * h (t_{2}) \\ = h (t_{1}) * S_{x x} (0) δ (t_{2} - t_{1}) * h (t_{2}) \\ = S_{x x} (0) h (t_{1}) * (δ (t_{2} - t_{1}) * h (t_{2})) \\ = S_{x x} (0) h (t_{1}) * h (t_{2} - t_{1}) \\ = S_{x x} (0) \int_{τ} h (τ) h (t_{2} - t_{1} + τ)) d τ \end{aligned}$

That is $σ_{y}^{2} (t) = R_{y y} (t_{1}, t_{2}) |_{t_{1} = t_{2} = t} = S_{x x} (0) \int_{- \infty}^{t} | h (τ) |^{2} d τ$

$t$ , the upper limit of integration is just intuitive, which lacks strict derivation

Because stable systems have impulse responses that decay to zero as time goes to infinity, the output noise variance approaches the WSS result as time approaches infinity

Frequency-domain Analysis

Because the definition of the PSD assumes that the variance of the noise process is independent of time, the PSD of a non-stationary process is not very meaningful

Input Referred Noise

Noise Voltage to Timing Jitter Conversion & noise gain

with a step ramp input $v_{X} (t) = M t u (t)$

The noise gain is $| A_{N} (t_{i}) | = A_{0} (1 - e^{t_{i} / τ_{o}}) u (t)$ where $t_{i}$ is crossing time of ideal threshold comparator
$\begin{aligned} \overset{―}{v_{n}^{2}} & = \frac{\overset{―}{v_{o n}^{2}}}{| A_{N} |^{2}} \\ = \frac{G_{n}}{G_{m}} \frac{k T}{C} \frac{1}{A_{0}} \frac{1 + e^{- t_{i} / τ_{o}}}{1 - e^{- t_{i} / τ_{o}}} \\ = 4 k T \frac{G_{n}}{G_{m}^{2}} \frac{1}{4 R_{o} C} \coth (\frac{t_{i}}{2 τ_{o}}) \\ = 4 k T R_{n} \frac{1}{4 τ_{o}} \coth (\frac{t_{i}}{2 τ_{o}}) \end{aligned}$

where $R_{n} = \frac{G_{n}}{G_{m}^{2}}$ , the equivalent thermal noise resistance

reference

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]

R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

John G. Proakis and Masoud Salehi, Fundamentals of communication systems 2nd ed [pdf]

Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons

Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers, oscillators, samplers, and logic: an introduction to cyclostationary noise." Proceedings of the IEEE 2000 Custom Integrated Circuits Conference. [pdf, slides]

Antoni, J., "Cyclostationarity by examples", Mechanical Systems and Signal Processing, vol. 23, no. 4, pp. 987–1036, 2009 [https://docente.unife.it/docenti/dleglc/a-a-2010-2011-dmsm/ciclostazionarieta.pdf]

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF. URL:https://designers-guide.org/analysis/sc-filters.pdf

STEADY-STATE AND CYCLO-STATIONARY RTS NOISE IN MOSFETS [https://ris.utwente.nl/ws/portalfiles/portal/6038220/thesis-Kolhatkar.pdf]

Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]

Sepke, Todd. "Comparator design and analysis for comparator-based switched-capacitor circuits." (2006). [https://dspace.mit.edu/handle/1721.1/38925]

analog design environment

Posted on 2024-05-24 Edited on 2023-07-10 In cad

Loockup Table vs Equations Model in Verilog-A

Solar Cell Verilog Model for Cadence [https://miscircuitos.com/solar-cell-verilog-model-for-cadence/]

How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-A [https://miscircuitos.com/how-to-create-a-model-in-verilog-a-with-a-lockup-table/]

with Equation

/////////////////////////////////////////////////////////////////////////////
//
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell IXYS
//
// Change history: 1/7/2018
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"

module SolarCell( EN, Vsolar, GND);

input EN;
electrical EN;

output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

parameter real vdd = 1.2;
parameter real vthreshold = 0.6;
parameter real fc = 10M;
parameter real light = 6;

//Curve parameters
real gm;
real A;
real factor;
real Vop;
real vcp;

integer light_i;
integer en;
analog begin

    @(initial_step)    begin 
        en = 0;
        A = 1;    
        Vop = 1;
        factor = 10;
    end
//Enable digitalization
    @(cross(V(EN)-vthreshold,1)) begin
        if(V(EN)&gt;=vthreshold) en = 1;
        else en = 0;
    end
        
    case(light):
            0: begin A = 0; Vop = 0; end
            1: begin A = -1.2; Vop = 1.71; end
            2: begin A = -0.8; Vop = 1.64; end
            3: begin A = -0.4; Vop = 1.50; end
            4: begin A = 0.1; Vop = 1.43; end
            5: begin A = 0.7; Vop = 1.36; end
            6: begin A = 1.1; Vop = 1.22; end
            default: begin A = -1.2; Vop = 1.71; end
        endcase

    //gm = A + atan(factor*(Vop-V(Vsolar))); //Transconductance

    vcp=laplace_nd(V(Vsolar,GND),{1},{1,1/(6.28*fc)});

    I(Vsolar,GND) &lt;+  (A + atan(factor*(vcp -Vop)))/1000;

end //analog
endmodule

V-I-simulation-for-solare-cell

with lookup table

///////////////////////////////////////////////////////////////////////////
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell photodiode
//
// Change history: 11/Sept/2019
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"
 
module SolarCell_Table( EN, Vsolar, GND);
 
input EN;
electrical EN;
 
output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

 
//Curve parameters
parameter real light =1;
parameter real vthreshold = 0.6;

real Vcp;
real iout, itemp;
real i1,i2, i3, i4, i5;
integer en;
analog begin
 
    @(initial_step)    begin 
        en = 0;
    end

//Enable function
    @(cross(V(EN) -vthreshold,1)) begin
        if(V(EN)>=vthreshold) en = 1;
        else en = 0;
    end

    Vcp = V(Vsolar,GND)*1000;

    i1 =  -$table_model (Vcp, "ph4_1.tbl", "1C")/1000000;
    i2 =  -$table_model (Vcp, "ph4_2.tbl", "1C")/1000000;
    i3 =  -$table_model (Vcp, "ph4_3.tbl", "1C")/1000000;
    i4 =  -$table_model (Vcp, "ph4_4.tbl", "1C")/1000000;
    i5 =  -$table_model (Vcp, "ph4_5.tbl", "1C")/1000000;

//    if(itemp <0 ) iout = itemp;
//    else iout = 0;
    case (light)
        1: iout = i1;
        2: iout = i2;
        3: iout = i3;
        4: iout = i4;
        5: iout = i5;
        default: iout = 0;
    endcase
    
    if(en== 0) iout = 0;

    I(Vsolar,GND) <+  iout;
 
end //analog
endmodule

PEX LAYER_MAP

// *LAYER_MAP
// *1 POLY
// *2 CONT
// *3 M1
...
*RES
8 ENL:30 ENL:34 0.525075 // $lvl=3
9 ENL ENL:30 0.07 // $lvl=3

[https://picture.iczhiku.com/resource/eetop/wYItYWLPleWrpvNV.pdf]

nodeset & initial condition

A nodeset steers the convergence in a particular direction - useful to speed up DC convergence
An initial condition is useful when you want to force the circuit to start a transient in a particular condition

[https://community.cadence.com/cadence_technology_forums/f/rf-design/29843/ade--difference-between-node-set-and-initial-condition/1335460]

Remove prefix from multiple files in Linux console

Bash

1	for file in prefix*; do mv "$file" "${file#prefix}"; done;

The for loop iterates over all files with the prefix. The do removes from all those files iterated over the prefix.

Here is an example to remove "bla_" form the following files:

bla_1.txt
bla_2.txt
bla_3.txt
blub.txt

Command

1	for file in bla_*; do mv "$file" "${file#bla_}";done;

Result in file system:

1.txt
2.txt
3.txt
blub.txt

[https://gist.github.com/guisehn/5438bbc22138435665c6e996493fe02b]

remove .cdslck

 #!/bin/sh
tree -if | grep 'cdslck' > txt
var=`cat txt`
for i in $var; do
	rm -i $i
done
rm -i txt

[https://wikis.ece.iastate.edu/vlsi/index.php?title=Tips_%26_Tricks#Locked_Files_in_Cadence]

Custom Bindkey

schBindKeys.il

schematic

alias bk hiSetBindKey
when ( isCallable('schGetEnv')
bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")")
bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")")
bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")")
bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()")
bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)")
)
unalias bk

leBindKeys.il

layout

alias bk hiSetBindKey
when ( isCallable('leGetEnv)
    bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" )
    ; M1-VIA1-M2
    bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" )
    ; M2-VIA2-M3
    bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" )
    ; M3-VIA3-M4
    bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" )
    ; M4-VIA4-M5
	; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them
    bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" )
    ; all visiable
    bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" )
)
unalias bk

Design Variable in vpwlf

PWL File as Design Var? parameter in vpwlf cell is convenient for sweep simulation or corner simulation, wherein there are multiple pwl files .

The file path should be surrounded with double-quotes to be protected from evaluation.

save option

none:

Does not save any data (currently does save one node chosen at random)

selected:

Saves only signals specified with save statements. The default setting.

lvlpub:

Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.

lvl:

Saves all signals up to nestlvl deep in the subcircuit hierarchy. This option is relevant for subcircuits.

allpub:

Saves only signals that are normally useful.

all:

Saves all signals.

Signals that are "normally useful" include the shared node voltages and currents through voltage sources and iprobes, and exclude the internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain, source on a FET, and so on). It also excludes currents through inductors, controlled sources, transmission lines, transformers, etc.

If you use lvl or all instead of lvlpub or allpub, you will also get internal node voltages and currents through other components that happen to compute current.

Thus, using *pub excludes internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain and source on a FET, etc). It also excludes the currents through inductors, controlled sources, transmission lines, transformers, etc.

nestlvl

This variable is used to save groups of signals as results and when signals are saved in subcircuits. The nestlvl parameter also specifies how many levels deep into the subcircuit hierarchy you want to save signals.

virtuoso "dlopen failed to open 'libdl.so'"

1	$ sudo yum install glibc-devel

Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST.                                                         
Dependencies resolved.
=========================================================================================================================================
 Package                            Architecture              Version                                    Repository                 Size
=========================================================================================================================================
Installing:
 glibc-devel                        x86_64                    2.28-189.5.el8_6                           baseos                     78 k
Installing dependencies:
 glibc-headers                      x86_64                    2.28-189.5.el8_6                           baseos                    482 k
 kernel-headers                     x86_64                    4.18.0-372.26.1.el8_6                      baseos                    9.4 M
 libxcrypt-devel                    x86_64                    4.1.1-6.el8                                baseos                     24 k

Transaction Summary
=========================================================================================================================================
Install  4 Packages

SpiceIn foundary's standard cell's spice netlist

use SpiceIn GUI feature to map MOS parameter correctly in generated schematic

Input

The mos's total width (parameter name "w") value will update during SpiceIn trigger CDF callback automatically

Output

Device Map

User Prop Mapping is significant setup, both xxx.spi and Edit CDF provide the essential information.

The map syntax is spice_para0 cdf_para0 spice_para1 cdf_para01 ... spice_paraN cdf_paraN

reference

Article (20488179) Title: How to use SpiceIn GUI feature to map MOS parameter correctly in generated schematic URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdPWEAY

Article (11724692) Title: SpiceIn maps the netlist parameter to the CDF parameter incorrectly on the generated schematic devices (e.g. w to wf) URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nZ2CEAU

Model Library Setup

In order to set up model files automatically in the Model Library Setup form for Spectre or AMS simulator in ADE Explorer or ADE Assembler

Add the following line in your .cdsinit

1	envSetVal( "spectre.envOpts" "modelFiles" 'string "<path_to model_file>/myModels.scs")

1	envSetVal("spectre.envOpts" "modelFiles" 'string "moreModels;ff mymodels;tt")

DSPF for each corner

Create a new file with an extension scs like myDSPF_Files.scs

* DSPF files to use with Corner Definitions
* This is an example file showing how to define different dspf files for different corners
* using model files for individual components as the
* building blocks.
simulator lang=spectre
library dspf_files_corners

section rctyp_25
dspf_include "DSPF_RC_TYPNOM25.spf"
endsection rctyp_25

section rctyp_125
dspf_include "DSPF_RC_TYP125.spf"
endsection rctyp_125

section rcworst_25
dspf_include "DSPF_RC_WORSE25.spf"
end section rcworst_25

section rcworst_125
dspf_include "DSPF_RC_WORSE125.spf"
end section rcworst_125

endlibrary dspf_files_corners

Add the file created above ‘myDSPF_File.scs’ in ‘Add/Edit Model Files’ of Corners setup form

split pins in dspf_emir

dspf extract using starrc

multiple label and rectangle in vssa net

general dspf

SHORT_PINS: YES

other pin are short together
dspf for emir analysis

It seems that dspf_emir don't contain the rectangle pin information.

only label is necessary

setup			spectre result
netlist type	dspf option	emir analysis
dspf	/	disable	✓
dspf_emir	/	disable	✗
dspf_emir	=shortPins=”yes”	disable	✓
dspf_emir	=shortPins=”no”	disable	✗
dspf_emir	/	enable	✓
dspf_emir	=shortPins=”yes”	enable	✓
dspf_emir	=shortPins=”no”	enable	✓

shortPins=”yes” is preferred default option for dspf_emir, which has split pins

DSPF Syntax

::=*|P ? describes pins in the net. Multiple pin descriptions can be listed in one line.
::=( {}?) represents the name of the pin. represents the type of the pin. It can be any of the following: I (Input), O (Output),

B (Bidirectional), X (don’t care), S (Switch), and J (Jumper). represents the capacitance value associated with the pin. is optional. It represents the location of the pin. Multiple pin locations are allowed

split pins

*|P (avss_1 O 0 207.7555 59.9170)
*|P (avss_10 O 0 181.1610 151.1130)
*|P (avss_11 O 0 186.6330 151.1130)
*|P (avss_12 O 0 192.1050 151.1130)
*|P (avss_13 O 0 197.5770 151.1130)

reference

Article (20467964) Title: Difference in result on running Spectre APS with EMIR and without EMIR analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000679GRUAY

StarRC User Guide and Command Reference Version O-2018.06, June 2018

DSPF Options

Case Sensitivity

netlist format	default option
Spectre netlist	case sensitive
dspf format	case insensitive

For a dspf format, it will be treated as a spice netlist format, which is by default case insensitive

Pay attention to VerilogIn block, which may contain upper case / lower case net name, e.g NET1 and net1.

The extracted DSPF using extraction tool also contain NET1 and net1, which shall not be shorted together.

Port Order

If you use .dspf_include, the following rules apply:

The subcircuit description is taken from the DSPF file even if the same subcircuit description is available in the schematic netlist.

Depending on the port_order option, the port order of the subcircuit definition is taken from the pre-layout schematic netlist or from the DSPF file subcircuit definition, as shown below.

port_order=sch – (Default). The port order is taken from schematic subcircuit definition. The same port number and names are required. If the schematic subcircuit definition is not available, a warning is issued in the log file, and DSPF port order is used.

port_order=spf – The port order is taken from the DSPF subcircuit definition.

SPICE_SUBCKT_FILE of StarRC

The StarRC tool reads the files specified by the SPICE_SUBCKT_FILE command to obtain port ordering information. The files control the port ordering of the top cell as well. The port order and the port list members read from the .subckt for a skip cell are preserved in the output netlist.

The file usually is the cdl netlist of extracted cell, this way, port order is not problem

CDF termOrder

DSPF same order

DSPF

input.scs

different order

manual change DSPF's pin order shown as below

port_order=sch

dspf port is mapping to schematic by name, and the simulation result is right

port_order=spf

dspf pin order is retained, and no mapping between spectre netlist and dspf.

The simulation result is wrong

bus_delim="_ <>"

The way this works is that the first part of bus_delim is the "schematic" delimiter (i.e. what's in the spectre netlist), and the other part is the DSPF delimiter

reference

Article (20502176) Title: How does Spectre understand case-sensitive net names when using various post-layout netlists such as dspf, av_extracted view, or smart view? URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fthoEAA

spf in cadence https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31326/spf-in-cadence/1342278#1342278

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1

StarRC™ User Guide and Command Reference Version O-2018.06, June 2018

Virtual Connectivity

Normally, if the layout connectivity extractor finds disjoint, unconnected geometries with the same net name text attached, the extractor will view this as an open circuit.

Virtual connection results in the extraction of a single net from two or more disjoint physical nets when the physical net segments share the same name.
Virtual connectivity is triggered by the rule file VIRTUAL CONNECT COLON and VIRTUAL CONNECT NAME specification statements.
Virtual connectivity can also be specified through the Calibre Interactive GUI.

VIRTUAL CONNECT COLON

Virtual Connect Colon is used to virtually connect nets that share a common prefix before a colon, like VDD:1, VDD:2, and so forth.

If you specify YES, then the connectivity extractor first strips off all characters from the first colon to the end of the label names.

Next, the extractor forms a virtual connection between any two labels that have the same name and that originally contained a colon.

Colons can appear anywhere in the name with the exception that a colon at the beginning of a name is treated as a regular character (that is, it has no special effect).

up to the first colon character encountered

The colon is discarded in the extracted net name

VIRTUAL CONNECT NAME

Virtual Connect Name virtually connects nets that share the same name

Each name is a net name and can be optionally enclosed in quotes.

The connectivity extractor forms a virtual connection between any two labels having the same name such that the label name appears in a Virtual Connect Name specification statement in the rule file.

VIRTUAL CONNECT NAME ? == Connect all nets by name

Note that if Virtual Connect Colon YES is also specified, then Virtual Connect Name operates on names after all colon suffixes have been stripped off.

reference

Calibre Fundamentals: Performing DRC/LVS Student Workbook

Calibre Verification User’s Manual Software Version 2019.3 Document Revision 7

Calibre Runsets

Calibre Interactive stores a list of your most recently opened runsets in your home directory as .cgidrcdb or .cgilvsdb for Calibre Interactive DRC or LVS, respectively.

When invoked, the Calibre DRC and LVS windows automatically load the runset used when the last session was closed.

Runsets are ASCII files that set up Calibre Interactive for a Calibre run. They contain only information that differs from the default configuration of Calibre Interactive. There is a one-to-one correspondence between entry lines in the runset file and fields and button items in the Calibre Interactive user interface. Here is as example of a DRC runset:
1
2
3
4
5
6
7
8
9
10
11
*drcRulesFile: rule_file
*drcRulesFileLastLoad: 1009224452
*drcLayoutPaths: ./lab3.gds
*drcLayoutPrimary: lab3
*drcResultsFile: ./lab3.db
*drcSummaryFile: drc_report
*drcRunTurbo: 0
*drcRunRemoteOn: Cluster
*drcRemoteLICENSEFILEName: MGLS_LICENSE_FILE
*drcRemoteLICENSEFILEValue: /scratch1/mgls/mgclicenses
*drcDontWaitForLicense: 0

The runset filename opened at startup (if no runset is specified on the command line) can also be specified by setting the MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC, and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable for LVS. If these environment variables are set, they take precedence over all other runset opening behavior options.

setenv RUNSET_DIR ../calibre
setenv MGC_CALIBRE_DRC_RUNSET_FILE $RUNSET_DIR/tsmc180nm_drc_runset
setenv MGC_CALIBRE_LVS_RUNSET_FILE $RUNSET_DIR/tsmc180nm_lvs_runset
setenv MGC_CALIBRE_PEX_RUNSET_FILE $RUNSET_DIR/tsmc180nm_pex_runset
setenv CALIBRE_DISABLE_RHEL5_WARNING 1

reference

tsmc_template. https://github.com/lnis-uofu/tsmc_template/tree/main

Calibre Verification User’s Manual

DC sweep & parametric sweep

swpuseprevic

variables with statistical distribution

Specifying Parameter Distributions Using Statistics Blocks

process: generate random number once per MC run
mismatch : generate a random number per instance

reference

Article (20498356) Title: How to vary design variables with statistical distribution to be used with Monte Carlo analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009ErHHEA0

Spectre Circuit Simulator Reference

DC operating points during TRANSIENT

Andrew Beckett over 11 years ago

Two approaches:

On the transient options form, there's a field called "infotimes" - specify the times at which you want it to output the dc operating point data. You can then annotate the "transient operating points" from any of these times after the simulation, or access them via the results browser.

Or you could get the operating point data to be continuously saved during the transient for selected devices - if so, create a file called (say) "save.scs" (make sure it has a ".scs" suffix), and put: save M1:oppoint or save M*:oppoint sigtype=dev in this file, and then reference the file via Setup->Model Libraries or as a "definition file" on Setup->Simulation Files. With this approach you can then find the operating point data for the selected devices in the results browser and plot it versus time (be cautious of saving too much though because this can generate a lot of data if you're not careful)

Regards,

Andrew.

transient options form

setup

access 1

right-click $\to$ Annotate $\to$ Transient Operating Points

access 2

tranOpTimed

save.scs

1	save M0:oppoint

How to Save Node in DSPF?

DSPF Semantics

*|DIVIDER <divider>

<divider> represents the hierarchical pathname divider. The default hierarchical character is forward slash (/).

*|DELIMITER <delimiter>

<delimiter> represents the delimiter character used to concatenate an instance name and pin name to form an instance pin name.
It is also represents the delimiter character used to concatenate a net name and subnode number to form a subnode name. The default character is colon (:)

*|BUSBIT <left_busbit_char><right_busbit_char>

<left_busbit_char> and <right_busbit_char> are used at the end of an identifier of an array to select a single object of the array.

Objects which may be indexed include nets, primary pins, and instance pins

*|NET <netName> <netCap>

<netName> represents the name of a net. It can be a user-provided net name, the name of the driving pin, or the name of the driving instance pin.
<netCap> represents the total capacitance value in farads associated with the net. This may be comprised of capacitances to ground and capacitances to nearby wires.

*|P <pinName> <pinType> <pinCap> {<coord>}

<pinName> represents the name of the pin.
<pinType> represents the type of the pin. It can be any of the following: I (Input), O (Output), B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
<pinCap> represents the capacitance value associated with the pin.
<coord> is optional. It represents the location of the pin. Multiple pin locations are allowed.

*|S <subNodeName> {<coord>}

subnodes in the net

<subNodeName> represents the name of the subnode. A subnode name is obtained by concatenating the net name and a subnode number using the delimiter specified in the DELIMITER statement. The default delimiter is colon (:).
<coord> represents the location of the subnode.

*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}

describes instance pins in the net

<instPinName> represents the name of the instance pin. An instance pin name is obtained by concatenating the <instName> and the <pinName> with a delimiting character which is specified by the DELIMITER statement
<instName> represents the name of the instance

*|DeviceFingerDelim "@"

MOS finger delimiter

For example, M8's finger is 4, then split into 4 Devices in DSPF

MM8, MM8@2, MM8@3, MM8@4

its drain terminal will be

MM8:d, MM8@2:d, MM8@3:d, MM8@4:d

DSPF Syntax

DSPF has two sections:

a net section

The net section consists of a series of net description blocks. Each net description block corresponds to a net in the physical design. A net description block begins with a net statement followed by pins, instance pins, subnodes, and parasitic resistor/capacitor (R/C) components that characterize the electrical behavior of the net.
an instance section

The instance section consists of a series of SPICE instance statements. SPICE instance statements begin with an X.

Each file consists of hierarchical cells and interconnects only.

The DSPF format is as generic and as much like SPICE as possible. While native SPICE statements describe the R/C sections, some non-native SPICE statements complete the net descriptions. These non-native SPICE statements start with the notation "*|" to differentiate them from native SPICE statements. For native SPICE statements, a continuation line begins with the conventional "+" sign in the first column.

The native SPICE statements used by the DSPF format are listed below:

.SUBCKT represents a subcircuit statement.
.ENDS represents the end of a subcircuit statement.
R represents a resistor element.
C represents a capacitor element.
E represents a voltage-controlled voltage sources element.
X represents an instance of a cell;
* represents a comment line unless it is *| or *+.
.END is an optional statement that represents the end of a simulation session

spectre netlist

hier_delimiter="."

Used to set hierarchical delimiter. Length of hier_delimiter should not be longer than 1, except the leader escape character

spfbusdelim = busdelim_schematic [busdelim_parasitic]

This option maps the bus delimiter between schematic netlist and parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus delimiter in the schematic netlist, and optionally the bus delimiter in the parasitic file. By default, the bus delimiter of the parasitic file is taken from the parasitic file header (i.e. |BUSBIT [], |BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not defined in the parasitic file header, you need to specify it by using the spfbusdelim option in schematic netlist.

Exampel

spfbusdelim=<> - A<1> in the schematic netlist is mapped to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is "_".

spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1] in the DSPF file (the bus delimiter in DSPF header will be ignored).

How to Save Net voltage in DSPF

!!! follow the name of net section in DSPF - prepend to top-level devices in the schematic with X

hierbench.drawio

Assume node n1...n4 are named as below in DSPF file (prefix X)

n1

XXosc/zip:1

n2

XXosc/zip:2

n3

XXosc/zip:3

n4

XXosc/zip:4

To save these nodes, you can add follow code in Definition Files

saveopt.scs

save Xwrapper.Xvco.XXosc\/zip\:1
save Xwrapper.Xvco.XXosc\/zip\:2
save Xwrapper.Xvco.XXosc\/zip\:3
save Xwrapper.Xvco.XXosc\/zip\:4

Escape character \ is used for hierarchical pathname divider / and subnode :

By the way, . is hierarchical delimiter of Spectre

Calibre always prepend one X to instance name of schematic in generated DSPF file

The DSPF design is flatten, the DIVIDER character indicate the hierarchy

1	save Xwrapper.Xvco.XXosc\/zip

The above save voltage, however I'm NOT sure which node it save.

To avoid this unsure problem, the MOS terminal may be better choice to save.

But keep in mind

OD resistance is lumped in the FEOL model
M0OD and above layer resistances are extracted by RC tool

How to Save Current in DSPF

!!! follow the name of instance section of DSPF - prepend to top-level devices in the schematic with XX

MOS in schematic: Xsupply.M4

MOS related information in DSPF (prefix XX in instance section):

...
// net section
*|I XXsupply/MM4:d XXsupply/MM4 d B 0.0 

...
//instance section
XXXsupply/MM4 XXsupply/MM4:d XXsupply/MM4:g XXsupply/MM4:s XXsupply/MM4:b pch_svt_mac
+ L=... W=... nfin=...
+ ...

To save drain current:

1	save Xvco.XXXsupply\/MM4:d

<instName> in *|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?} which has prefix X corresponding to schematic is NOT the instance name in DSPF. The instance name is in instance section and has prefix XX

!!! Only work for MOS terminal current. Fail to apply to block pin

Thinking about voltage and current save

MOS device always prepend with M
To save net voltage, take account of the prefix X of top-level device
To save MOS terminal, take account of the prefix XX of top-level device

Post-layout netlists are created by layout extraction tools - Mentor Calibre

Differences Between DSPF and Schematic Names

MOS Terminal Mismatch ( ‘s’ vs ‘1’)

Schematic: number '1' ,'2', '3','4'

DSPF: 'd', 'g', 's','b'

.simrc file

If DSPF files show such differences, you can set options in the .simrc file to update the save statement in the netlist so that the device names match with those in the DSPF file

Additionally, dspf_include reads all the DSPF lines starting with * (|NET, |I, *|P,*|S), while include considers all related lines as comments.

Only verified to DSPF output of Mentor Calibre

; ensure that the netlist is recreated each time
nlReNetlistAll=t

dspfFileEnvOptions = '(
        nil
        spfFileNameMappingFormat "cdl“
        spfFileTermDelimiter “:”
        spfFileHierDelimiter “/”
        spfFileFingerDelimiter “@”
        spfFileNetMapping “mixed”
        spfFileTerminalMapping “lower”
        spfFileAddPrefixToDevice t
        spfFileAddContextSensitivePrefix t
        spfFileDeviceDefaultPrefix “X”
        spfFileDevicePrefixForTermCurrent “X”
        spfFileDevicePrefixForOppoints “X“
        
)

spfFileDevicePrefixForTermCurrent and spfFileDevicePrefixForOppoints are applicable to MOS devices only.

Both @ and __ have been observed as Finger Delimiter in single DSPF . wired...

signal name saved using wildcard operator

How to find the signal name saved using wildcard operator with save statement in spectre?

method 1

From ADE L or ADE XL Test Editor, you can use menu Simulation → Options → Analog→ Miscellaneous → Addition arguments field:dump_wildcard_info=yes

method 2

add below in netlist file or Simulation Files → Definition Files:saveopt.scs

saveopt.scs

1	wcOption options dump_wildcard_info=yes

saved file

After running simulation, saved wildcard summary is save into file <netlist_file_name>.wildcard.out*

Wildcard match summary:

save * nodes: 68
    0
    vdd!
    I0.net10
    I0.net15
    I0.I8.net30

Save and Plot terminal voltage in ADE Explorer and Assembler

.cdsinit

1	envSetVal("auCore.selection" "terminalSelectionType" 'cyclic "current")

Available options are current, voltage, both or prompt and the default is current which matches the default behavior in previous releases.

The schematic will have an ellipse annotation where a current probe has been saved,
a V annotation for a voltage probe,
and both annotations for both.

NOTE: Starting with IC 6.1.8 ISR5, you can now set this from Options->Plotting/Printing

Interpreting _noxref Entries

You enable gate recognition in the Calibre nmLVS-H tool. Normally, the _noxref names are internal to the gate

Saving net with hierarchy delimiter and colon (:) in net name gives WARNING (SPECTRE-8282) during simulation

Problem

I am running simulation using an spf/spef file which has a net name definition as shown in the below example:

// input.scs
simulator lang=spice
.subckt pi_rc a z
r1 a x1a 1k
r2 x1a x1/x1:DRN 1k
cb x1/x1:DRN z 200f
.ends

xpi1 in 0 pi_rc
vdd in 0 pwl (0 0 1n 0 1.1n 10)

simulator lang=spectre
myopt options hier_ambiguity=lower
tran tran stop=2u

save xpi1.x1\/x1:DRN

The net name is x1/x1:DRN. During the simulation, the following warning is reported:

Warning from spectre during initial setup.

1 2	WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name. WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.

How can I save this net for plotting and measurements?

Solution

The colon (:) in the save statement specifies terminal current. So, the save statement used above is for terminal current and, hence, the warning messages are reported.

1	save xpi1.x1\/x1:DRN

You need to modify the save statement as below:

1	save xpi1.x1\/x1\:DRN

Now, run the simulation and the issue will be resolved.

DSPF r vs rcc

rcc

only c dspf give the lumped capacitance

EMIR via Voltus-Fi

general terminology

Imax in T*'s DRC document is the maximum allowed DC current, which depends on Length and Width only

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to Imax rules $I_{avg} = \frac{\int_{0}^{τ} I (t) d t}{τ}$ Similarly, Iabsavg rules are identical to Imax rules, too $I_{AbsAvg} = \frac{\int_{0}^{τ} | I (t) | d t}{τ}$

rms

Irms is the root-mean-square of the current through a metal line, which depends w(in um), the drawn width of the metal line and $Δ T$ , the temperature rise due to Joule heating. $I_{rms} = {[\frac{\int_{0}^{τ} I (t)^{2} d t}{τ}]}^{1 / 2}$

peak current

Ipeak in T*'s DRC document is the current at which a metal line undergoes excessive Joule heating and can begin to melt. Ipeak is corresponding to EM Current Analysis: max in Voltus-Fi Analysis Setup $I_{peak} = max (| I (t) |)$ The limit for the peak current is $I_{peak,limit} = \frac{I_{peak\_DC}}{\sqrt{r}}$ where r is the duty ratio

The relationship between Ipeak and Ipeak_DC is merged in DRC document so that there is only Ipeak equation in document

$I_{peak,limit}$ depends on $t_{D}$ , r, width and length

$r = \frac{t_{D}}{τ}$

where $t_{D}$ is equivalent duration $t_{D} = \frac{\int_{0}^{τ} | I (t) | d t}{I_{peak}}$ or $r = \frac{I_{AbsAvg}}{I_{peak}}$

where the drawn width is 1um, r is 0.1

$9.37 * (1 - 0.004) / \sqrt{0} .1 = 29.512$

acpeak/pwc

It's same with max EM Current Analysis in Voltus-Fi

dynamicACPeak

This option affect how duty ratio r is computed in max and acpeak/pwc EM current Analysis

When the dynamicACPeak variable is set to true or multiPeak $r = \frac{T_{d}}{T_{total}}$

where $T_{total} = EMIR timewindow$

$T_{d}$ = the time duration in microsecond of the total "On Time" period based on IPWC

Pulse-Wise Constant EM current calculation (IPWC)

where Tau is $T_{d}$ in above formula

!!! It seems that t*'s PDK don't support dynamicACPeak=true

IR drop filter layers

EM techfile (qrcTechFile) may take diffusion contact (n_odtap, p_odtap in DSPF file) into account during IR drop analysis. And these segment often dominate IR drop, but we as IC designer can NOT improve them. In general, the IR drop to M1 layer is enough and feasible.

Regular analysis statements in emir configuration

1 2	net name=[I0.vdd I0.vss] analysis=[vmax vavg] net name=[I0.*] analysis =[imax ivavg irms]

emirreport command

Creating reports for specific nets after simulation using emirreport

Create a new config file as shown below:

1
2
3

** test.conf**
net name=[I1.VDD I1.VSS] analysis=[iavg]
net name=[I1.VBIAS] analysis=[imax]

Run emirreport on the command line using the emirdatabase (emir*.bin) and test.conf created above in

1	% emirreport -64 -c test.conf -db <emirdatabase> -outdir newreport

database

simulation result

input.emir0_bin: The first EMIR Analysis which is DC or Transient, which depends on Analyses order

input_tran.emir0_bin: EMIR Analysis in Transient simulation

input_dcOp.emir0_bin: EMIR Analysis in DC simulation

For example

Two results are generated input.emir0_bin and input_dcOp.emir0_bin and their reports respectly

Fix Electromigration

Type	wider wire	downsize drivers	decrease fanout
RJ JMAX		✓	✓
JAVG
JABSAVG
JACPEAK
JACRMS	✓	✓	✓

Iavg

The average value of the current, which is the effective DC current

Irms

Irms rule relates to the heat or Joule-heating of metal lines

Ipeak

The main goal of the Ipeak limits is to ensure that no thermal breakdown could occur on single overshoot events. If the signal may not have a high current density but if it has a very large peak current density, then, local melting will happen and cause failures

QA

Q. Why “length” column in EM results form doesn’t show extracted length, it shows “NA”.

A. Voltus-Fi reports the “length” column only when length rules are present in the emDataFile.
Seeing different port currents with and without emir simulations for same dspf included in EMIR Direct method using dspf_include.

Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the regular spectre flow. Islands patching is only performed in EMIR only
Setting temperature for EM analysis

By Default, Voltus-FI and VPS pick up the current density limit for temperature at which simulation has been performed.

By the way, Design Variables - temperature will override the temperature in Setup toolbar which is gray in ADE Explorer
AC Peak EM analysis - Voltus-Fi

The available options within the EM current analysis section in the EMIR Analysis Setup form are:

max / avg / avgabs / rms.

In order to enable the AC Peak based information when loading the EM results, both max and avg should be selected when setting up the EMIR Analysis Setup.

With this configuration, the AC Peak option becomes available and can be used.
How to print average, rms, and peak current of device tap in Spectre/Voltus FI EMIR analysis

The following option enables you to save the average, rms, and peak tap currents in the emir0bin file and report it in the input.rpt_tapi file.
1
solver report_tapi=true
Add this option in emir.conf to enable the reporting of tap current after the Spectre EMIR simulation. The input.rpt_tapi file will be saved in the psf/raw directory.

Note: This feature is supported in SPECTRE20.1 ISR14 and later versions.
emir.conf file

emir.conf file is generated automaticaly after configure EM/IR Analysis in ADE, which is in netlist directory.
Setting default path for EM rules file in APS EMIR analysis
- set the following environment variable in your terminal
  1
  setenv EMDATAFILE < path to EM rules file>
- or set in .cdsinit
  1
  setShellEnvVar("EMDATAFILE=<path to EM rules file>")
Print node names and length associated with parasitic resistors in EM report file

export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME
- Printing the parasitic resistor length in the EM report
  1
  emirutil reportLength=true
- Printing nodes that are associated with the parasitic resistor
  1
  emirutil reportNodeName=true
  Once these are enabled, you will have the Length, Node_1, and Node_2 columns printed in the EM report file, as shown below:
Is it possible to run RMS IR Drop analysis using Voltus-Fi?

Typically, in a simulation, Power/Ground nets are always biased with a constant DC source. Hence, at present, Voltus-Fi only supports Average and Maximum (Peak) IR Drop analysis.

For a net to have data for IR analysis(vmax/vavg), the net/node must be connected to a DC vsource or a vsource which is constant within the emir time window.
Can we change the time window of EM computation after the simulation completed ?

It is not possible to modify the EM time window without re-running the full simulation.

However you can specify several time window in the emir conf file for instance for 2 time window [0 to 10n] and [10n 20n]
1
time window=[0 10n 10n 20n]
In that case it will create 2 emir_bin files and then 2 different em report files according to the 2 different time windows.

How to print segment_W values being used to compute EM limits

You can use the following option to print segment_W to the report:

1	emirutil reportSegmentWidth=[true]

This would print a Segment_w column in the report containing the segment width values used for computing the limit:

Pass/Fail %	Resistor	layer	Current	Width	PathLength	I limit	X1	Y1	X2	Y2	J/JMAX	Res	ViaArea	No of needed vias	width/#via	J limit	Segment_w
			(mA)	(um)	(um)		(um)	(um)	(um)	(um)			(nm^2)		(um/#)	(A/um)
pass-100.0	Rj3292	Met1	9.02376e-12	0.1	42.72	1.10067	0.350	11.568	0.350	11.376	8.19843e-12	0.7382	NA	NA	0.0001	0.0110067	0.1

pathLength vs Length in EM report file
- Length: parasitic resistor length, which is set by emirutil reportLength=true
- pathlength: Blech length is also known as "Short length" or "Path length", and can be explained as : The longest and continuous centerline path from edge to edge among the connected wire shapes on the same metal layer.
  - For all resistors falling on this shape, same pathLength is reported.
  - After the longest path in shape has been determined the tool applies the same blech length to all the resistor falling on that shape.
  - This resistor length is NOT used in EM analysis because EM rules consider Blech length of the resistor.
  where W is the wire width and L is the Blech length.
  - By default the tool will sum all branches of a given metal layer. In other words the path length that will be used to look up the EM density limit is :
    
    Bl = $l (R 1) +$ l(R2) + $l (R 3) +$ l(R4) + $l (R 5) +$ l(R6) + $l (R 7) +$ l(R8)
How to enable EMIR analysis in PSS simualtion ?

To enable EMIR in PSS, you have to enable DC and/or Tran simulation simultaneously. Two or more binary results file should be generated and select the file based file name or configure text file in psf directory.

(given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)

reference

AC Peak Analysis Using IPWC Rapid Adoption Kit (RAK) Product Version: IC6.1.8 ISR10, SPECTRE19.1 ISR5 April 2020

Posser, Gracieli & Sapatnekar, Sachin & Reis, Ricardo. (2017). Electromigration Inside Logic Cells. 10.1007/978-3-319-48899-8.

A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts of electromigration awareness," 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp. 527-532, doi: 10.1109/ASPDAC.2013.6509650.

Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling of electromigration in SRAMs.” (2014).

N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical approach to static signal electromigration analysis," Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 572-577, doi: 10.1109/DAC.1998.724536.

Blaauw, David & Oh, Chanhee & Zolotov, Vladimir & Dasgupta, Aurobindo. (2003). Static electromigration analysis for on-chip signal interconnects. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 22. 39 - 48. 10.1109/TCAD.2002.805728.

No delay-free loops

linear settling & GBW of amplifier

Delta Modulator

MOD1

MOD2

decimation filter

sinc filter

sinc2 filter

Truncation DAC

Mismatch Shaping

Data-Weighted Averaging (DWA)

reference

Multipliers

Adders

overlapped tuning range

Mueller-Muller PD

Least-Mean-Square (LMS)

Sign-Sign LMS (SS-LMS)

DFE h0 Estimator

Maximum Likelihood Sequence Estimator (MLSE)

Mueller-Muller CDR

SS-MM CDR

Pattern filter

Bang-Bang CDR

reference

Noise Analysis

Noise Simulation

PSS + Pnoise Method

Transient Noise Method

Comparison of two methods

Common-Mode (Vcmi) Variation Effects

offset simulation

Hysteresis

Kickback Noise

CMOS Latch

Metastability

Pre-amp (preamplifier)

Math Background

Relating Φ and erf

reference

warmup

Continuous Time Fourier Series (CTFS)

Continuous-Time Fourier transform (CTFT)

Discrete-Time Fourier Transform (DTFT)

Discrete-Time Fourier Series (DTFS)

Discrete Fourier Series (DFS)

Discrete Fourier Transform (DFT)

impulse train

Dirac delta (impulse) function

impulse scaling

Multiplication

Duality

Conjugate Symmetry

Parseval's Relation

Eigenfunctions & frequency response

Sampling Theorem

Aliasing

CTFS & CTFT

inverse CTFT & inverse DTFT

spectral sampling

Why DFT ?

C/D

Frequency-Domain Representation of Sampling

D/C

zero padding

Gotcha

reference

CDAC intuition

CDAC settling accuracy

CDAC Energy Consumption

Comparator input cap effect

Comparator offset effect

Synchronous SAR ADC

Split Arrary CDAC

Asynchronous processing

reference

Track Time

ADC Calibration

Offset Calibration

Gain Calibration

$sinc$ filter

${sinc}^{2}$ filter

Relating $Φ$ and erf

$g_{m}$ , $g_{ds}$ at fixed $V_{GS}$

$g_{m}$ , $g_{ds}$ at fixed $I_{d}$ , $V_{G}$

DT sequence $x [n]$

impulse train $x_{s} (t)$