S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan
Carusone, โAll-Digital Calibration of Timing Mismatch Error in
Time-Interleaved Analog-to-Digital Converters,โ IEEE Transactions on
VLSI Systems, Sept. 2017. [PDF, slides]
similar to increase the resolution of the flash ADC with
more parallel comparators
De-multiplexing Interleaver
it is the front-end samplers that determine
timing/bandwidth mismatch errors
Re-sampling Interleaver
back-end re-sampling occur after the front-end, two \(\frac{KT}{C}\) contribution in total noise
(De-multiplexing Interleaver only one \(\frac{KT}{C}\))
without buffer, charging distribution reduce signal and reduce SNR,
but buffers give excess noise
Interleaver Model
Interleaving Errors
Offset Mismatch Error
Gain Mismatch Error
Timing Mismatch Error
\(\pi/2\)-rad phase: the maximum
error occurs at the zero crossing and not on
the peaks (Gain Mismatch error)
Frequency-dependent: the higher frequency input signal \(f_\text{in}\), the larger error
becomes
Y. Shifman, Y. Krupnik, U. Virobnik, A. Khairi, Y. Sanhedrai and A.
Cohen, "A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz
BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm,"
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC),
Macau, Macao, 2019 [pdf]
E. -H. Chen et al., "7.1 A 212.5Gb/s DSP-Based PAM-4
Transceiver with 50dB Loss Compensation for Large AI System
Interconnects in 4nm FinFET," 2025 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2025
TODO ๐
Paper from industry
Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022 [https://sci-hub.st/10.1109/ISSCC42614.2022.9731650]
P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with
>45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and
Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025
M. S. Jalali, A. Sheikholeslami, M. Kibune and H. Tamura, "A
Reference-Less Single-Loop Half-Rate Binary CDR," in IEEE Journal of
Solid-State Circuits, vol. 50, no. 9, pp. 2037-2047, Sept. 2015 [https://www.eecg.utoronto.ca/~ali/papers/jssc2015-09.pdf]
Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB
IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International
Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]
Poulton, Ken. ISSCC2009 "Time-Interleaved ADCs, Past and Future" (slides)
โ. CICC2010 "GHz ADCs: From Exotic to Mainstream", tutorial session,
(slides)
โ. ISSCC2015 "Interleaved ADCs Through the Ages", (slides)
Ewout Martens. ESSCIRC 2019 Tutorials: Advanced Techniques for ADCs
for 5G Massive MIMO [https://youtu.be/7hYichGGU6k]
Athanasios Ramkaj. January 26, 2022, IEEE SSCS Santa Clara Valley
Section Technical Talk: Design Considerations Towards Optimal
High-Resolution Wide-Bandwidth Time-Interleaved ADCs [https://youtu.be/k3jY9NtfYlY?si=K9AdT9QzGxOnI5WG]
Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]
Extensive work on DFEs has produced a multitude of architectures,
which can be broadly categorized as "direct"" or
"unrolled" (speculative) DFEs with
"full-rate" or "half-rate"
clocking
S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for
20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol.
46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]
Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of
Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]
Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity
Technologies to Accelerate AI
H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an
LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET,"
2025 IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2025
Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed
Wireline Interconnects: Design Challenges and Innovations in 224G SerDes
[https://www.youtube.com/live/wHNOlxHFTzY]
the resistance of MOS is not highly controlled -> \(R_T + Z_N\)
Peak power constraint of TX
FIR
Due to circuit limitation, circuit cannot have arbitrarily large
voltage on the output, i.e. a limited maximum swing. In order
to create the high frequency shape, the best we can do is lower DC
gain (low frequency gain < 1)
FIR is not increasing the amplitude on the edges
FIR is reducing the inner eye diagram
The maximum swing stays the same, \(\sum_i
|c_i|=1\)
C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX
in 14nm CMOS," 2018 IEEE International Solid-State Circuits
Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 104-106 [slidespaper]
SST Driver
sharing termination in
SST transmitter
Sharing termination keep a constant current through leg, which
improve TX speed in this way. On the other hand, the sharing termination
facilitate drain/source sharing technique in layout.
pull-up and pull-down
resistor
Original stacked structure
Pro's:
โ smaller static current when both pull up and pull down path is
on
Con's:
โ slowly switching due to parasitic capacitance behind pull-up and
pull-down resistor
with single shared linearization resistor
Pro's:
โ The parasitic capacitance behind the resistor still exists but is
now always driven high or low actively
Con's:
โ more static current
VM
Driver Equalization - differential ended termination
\[
V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1}
\]
where \(D_n \in \{-1, 1\}\)
\[
V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2}
\] With \(R_u=(L+M+N)R_T\)
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\
V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N}
\end{align}\] So \[
V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N}
\] which is same with differential ended termination
Equation-2
\[\begin{align}
V_{\text{rxp}} &= \frac{1}{2} \\
V_{\text{rxm}} &= 0
\end{align}\] So \[
V_{M}= \frac{1}{2}
\] which is same with differential ended termination
Which can be simpified as \[\begin{align}
V_{\text{rx}} &= \frac{1}{2}(V_p - V_m) \\
&= \frac{1}{2}(\frac{2}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-1) \\
&=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2}
\end{align}\]
The above eqations demonstrate that the output \(V_{\text{rx}}\) is the linear sum of
MSB and LSB; LSB and
MSB have relative weight, i.e. 1 for LSB and
2 for MSB.
Assume pre cusor has \(L\) legs,
main cursor \(M\) legs and post cursor
\(N\) legs, which is same with the
convention in "Voltage-Mode Driver Equalization"
The number of legs connected with supply can expressed as \[
n_{up} = (1-d_{n+1})L + d_{n}M + (1-d_{n-1})N
\] Where \(d_n \in \{0, 1\}\),
or \[
n_{up} = \frac{1}{2}(-D_{n+1}+1)L + \frac{1}{2}(D_{n}+1)M +
\frac{1}{2}(-D_{n-1}+1)N
\] Where \(D_n \in \{-1,
+1\}\)
Then the number of legs connected with ground is \[
n_{dn}=L+M+N-n_{up}
\] where \(n_{up}+n_{dn}=L+M+N\)
Voltage resistor divider \[\begin{align}
V_o &=
\frac{\frac{R_{U}}{n_{dn}}}{\frac{R_U}{n_{dn}}+\frac{R_U}{n_{up}}} \\
&= \frac{1}{2}- \frac{1}{2}D_{n+1}\frac{L}{L+M+N}+
\frac{1}{2}D_{n}\frac{M}{L+M+N}-\frac{1}{2}D_{n-1}\frac{N}{L+M+N} \\
&= \frac{1}{2}-\frac{1}{2}D_{n+1}\cdot l+ \frac{1}{2}D_{n}\cdot
m-\frac{1}{2}D_{n-1}\cdot n
\end{align}\]
where \(l+m+n=1\)
\(V_{\text{MSB}}\) and \(V_{\text{LSB}}\) can be obtained
\[\begin{align}
V_{\text{MSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \\
V_{\text{LSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot
l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot
m-\frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n
\end{align}\]
Substitute the above equation into \(V_{\text{rx}}\), we obtain the relationship
between driver legs and FFE coefficients
After scaling, we obtain \[
V_{\text{rx}} = -l\cdot(2 \cdot
D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ m\cdot(2\cdot
D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) - n \cdot(2\cdot
D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1})
\] Where \(C_{-1} = l\), \(C_0 = m\) and \(C_{1}=n\), which is same with that of
NRZ
J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial
Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of
Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012, doi:
10.1109/JSSC.2012.2216414.
C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm
CMOS," 2018 IEEE International Solid - State Circuits Conference -
(ISSCC), 2018, pp. 104-106, doi: 10.1109/ISSCC.2018.8310205.
E. Chong et al., "A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based
Transmitter in 7nm FinFET," ESSCIRC 2021 - IEEE 47th European Solid
State Circuits Conference (ESSCIRC), 2021, pp. 523-526, doi:
10.1109/ESSCIRC53450.2021.9567801.
Wang, Z., Choi, M., Lee, K., Park, K., Liu, Z., Biswas, A., Han, J.,
Du, S., & Alon, E. (2022). An Output Bandwidth Optimized 200-Gb/s
PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE
Journal of Solid-State Circuits, 57(1), 21-31.
https://doi.org/10.1109/JSSC.2021.3109562
J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm
CMOS," 2018 IEEE International Solid - State Circuits Conference -
(ISSCC), 2018, pp. 102-104, doi: 10.1109/ISSCC.2018.8310204.
H. Kimura et al., "A 28 Gb/s 560 mW Multi-Standard SerDes
With Single-Stage Analog Front-End and 14-Tap Decision Feedback
Equalizer in 28 nm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 49, no. 12, pp. 3091-3103, Dec. 2014 [https://ieeexplore.ieee.org/ielx7/4/6963535/06894632.pdf]
Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB
IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International
Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]
Z. Li, M. Tang, T. Fan and Q. Pan, "A 56-Gb/s PAM4 Receiver Analog
Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 68, no. 9, pp. 3058-3062, Sept. 2021 [slides]
[paper]
K. Kwon et al., "A 212.5Gb/s Pam-4 Receiver With Mutual
Inductive Coupled Gm-Tia in 4nm Finfet," 2025 Symposium on VLSI
Technology and Circuits (VLSI Technology and Circuits), Kyoto,
Japan, 2025
Bae, W. (2019). CMOS Inverter as Analog Circuit: An Overview.
Journal of Low Power Electronics and Applications. [pdf]
CTLE, with Gm + TIA structure
Chongyun ZHANG, 2025, "Energy-Efficient CMOS Optical Receiver for
Short-Reach Data Center Application,". [slides,
paper]
Equalization Shaping
PCIe Gen6 Channel and Reference Package S4P Models for Rx Stressed
Eye Calibration
Above curve demonstrate that only zero is not enough to compensate
channel+pkg loss (>20 dB/decade), peaking or
Complex-Conjugate Poles is necessary
S. Shahramian et al., "30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline
Receiver Employing Enhanced Pattern Utilization CDR and Genetic
Adaptation Algorithms in 7nm CMOS," 2019 IEEE International
Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA,
2019 [pdf]
P. A. Francese et al., "10.6 continuous-time linear
equalization with programmable active-peaking transistor arrays in a
14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver," 2015
IEEE International Solid-State Circuits Conference - (ISSCC) Digest of
Technical Papers, San Francisco, CA, USA, 2015 [pdf]
Z. Li, M. Tang, T. Fan and Q. Pan, "A 56-Gb/s PAM4 Receiver Analog
Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 68, no. 9, pp. 3058-3062, Sept. 2021 [slides]
[paper]
In the active copper cable (ACC) application, it is necessary to give
different equalizations at the same frequency according to different
cable lengths, Therefore, the AFE with fixed peaking
frequency and constant bandwidth
is desirable for these applications
Low-Frequency CTLE (LF-CTLE)
S. Parikh et al., "A 32Gb/s wireline receiver with a
low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS," 2013 IEEE
International Solid-State Circuits Conference Digest of Technical
Papers, San Francisco, CA, USA, 2013 [https://sci-hub.se/10.1109/ISSCC.2013.6487622]
T. Shibasaki et al., "A 56-Gb/s receiver front-end with a
CTLE and 1-tap DFE in 20-nm CMOS," 2014 Symposium on VLSI Circuits
Digest of Technical Papers, Honolulu, HI, USA, 2014, pp. 1-2
S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery
Techniques for 10-Gb/s CMOS Serial-Link Receivers," in IEEE Journal
of Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011 [pdf]
\[
C_{d1} = C_{dd1} + (1+\frac{1}{|A_{gd}|})C_{gd1}
\] where \(A_{gd}\lt 0\)
For differential mode input, effective
input capacitance\[
C_{in} = C_{gs} +(1+A_{dm}) C_{gd}+\color{red}(1-A_{dm})C_n
\] and effective output capacitance\[
C_{out} = C_{dd} + (1+\frac{1}{A_{dm}})C_{gd}+\color{red}
(1-\frac{1}{A_{dm}})C_n
\] That is \(C_n\) deteriorate
the effective output capacitance
For common mode input, effective input
capacitance\[
C_{in} = C_{gs} + (1+A_{cm}) C_{gd}+ \color{red}(1+A_{cm})C_n
\] and effective output capacitance\[
C_{d1} = C_{dd} + (1+\frac{1}{A_{cm}})C_{gd}+\color{red}
(1+\frac{1}{A_{cm}})C_n
\] i.e., \(C_n\) deteriorate
both effective input capacitance and effective output capacitance,
unfortunately
effective input capacitance \(\Pi\)
model, which is appropriate for both differential input and common mode
input
Suppose \(C_n=C_{gd}\), effective
differential input capacitance is same with effective
common-mode input capacitance (\(C_n=\frac{A_{dm}-A_{cm}}{A_{dm}+A_{cm}}C_{gd}\))
The negative inductor \(-M\) can be
seen as capacitor \[
-j\omega M = \frac{1}{j}\omega M = \frac{1}{j\omega \frac{1}{\omega^2
M}}
\] That is \(C_{-M} = \frac{1}{\omega^2
M} \approx 10 \times C_E\)
S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension
Techniques for CMOS Amplifiers," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006 [pdf]
J. Paramesh and D. J. Allstot, "Analysis of the Bridged T-Coil
Circuit Using the Extra-Element Theorem," in IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 53, no. 12, pp. 1408-1412,
Dec. 2006 [https://sci-hub.st/10.1109/TCSII.2006.885971]
S. C. D. Roy, "Comments on "Analysis of the Bridged T-coil Circuit
Using the Extra-Element Theorem," in IEEE Transactions on Circuits and
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Deog-Kyoon Jeong. Topics in IC Design: T-Coil [pdf]
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An Overview," in IEEE Solid-State Circuits Magazine, vol. 9, no. 4, pp.
82-89, Fall 2017 [https://sci-hub.ru/10.1109/MSSC.2017.2745858]
โ, "Evolution of Broadband Amplifier Design: From Single-Stage to
Distributed Topology," in IEEE Microwave Magazine, vol. 24, no. 9, pp.
18-29, Sept. 2023
Cowan G. Mixed-Signal CMOS for Wireline Communication:
Transistor-Level and System-Level Design Considerations. Cambridge
University Press; 2024
Stariฤ, Peter and Erik Margan. โWideband amplifiers.โ (2006) [pdf]
Walling, Jeffrey & Shekhar, Sudip & Allstot, David. (2008).
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on Circuits and Systems I: Regular Papers, vol. 72, no. 9, pp.
4469-4480, Sept. 2025
S. Lin, D. Huang and S. Wong, "Pi Coil: A New Element for Bandwidth
Extension," in IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 56, no. 6, pp. 454-458, June 2009
M. Kossel et al., "A T-Coil-Enhanced 8.5 Gb/s High-Swing SST
Transmitter in 65 nm Bulk CMOS With <โ16 dB Return Loss Over 10 GHz
Bandwidth," in IEEE Journal of Solid-State Circuits, vol. 43,
no. 12, pp. 2905-2920, Dec. 2008 [https://web.mit.edu/magic/Public/papers/04684644.pdf]
S. Galal and B. Razavi, "Broadband ESD protection circuits in CMOS
technology," in IEEE Journal of Solid-State Circuits, vol. 38, no. 12,
pp. 2334-2340, Dec. 2003, doi: 10.1109/JSSC.2003.818568.
M. Ker and Y. Hsiao, "On-Chip ESD Protection Strategies for RF
Circuits in CMOS Technology," 2006 8th International Conference on
Solid-State and Integrated Circuit Technology Proceedings, 2006, pp.
1680-1683, doi: 10.1109/ICSICT.2006.306371.
M. Ker, C. Lin and Y. Hsiao, "Overview on ESD Protection Designs of
Low-Parasitic Capacitance for RF ICs in CMOS Technologies," in IEEE
Transactions on Device and Materials Reliability, vol. 11, no. 2, pp.
207-218, June 2011, doi: 10.1109/TDMR.2011.2106129.
Minsoo Choi et al., "An Approximate Closed-Form Channel Model for
Diverse Interconnect Applications," IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct.
2014.
A resonant circuit refers to an electrical
circuit using circuit elements such as an inductor (L) and a capacitor
(C) to cause resonance at a specific frequency.
There are two types of resonant circuits:
series resonant circuits
parallel resonant circuits
In a series resonant circuit, the impedance of the circuit reaches
its minimum value at resonance, whereas in a parallel resonant circuit,
the impedance reaches its maximum value
antiresonance
Resonant Frequency
\(\zeta \lt 1\):
Complex-Conjugate Poles, but not resonant
peak
Prof. M. Green / U.C. Irvine EECS 270C / Winter 2013 [pdf]
\[
s^2 + \frac{R}{L}s + \frac{1}{LC_L} = s^2 + 2\zeta \omega_n s +
\omega_n^2
\] where \(\omega_n =
\frac{1}{\sqrt{LC_L}}\) and \(\zeta=\frac{R}{2}\sqrt{\frac{C_L}{L}}\)
Resonant frequency is \[
\omega_r = \omega_n \sqrt{1-2\zeta^2} =
\frac{1}{\sqrt{LC_L}}\left(1-\frac{C_LR^2}{2L}\right)
\] To have no resonant \(\zeta^2
>\frac{1}{2}\), i.e \[
\frac{L}{C_LR^2} < \frac{1}{2}
\]
assuming \(i(t) = I_p\cos\omega_0
t\), where \(\omega_0
=1/\sqrt{LC}\) , suppose all current flow into \(R\)\[
V(t) = I_pR\cdot \cos\omega_0 t
\]\(I_C\), the current flow
through \(C\)\[
\color{red}I_C(t)=C\frac{dV(t)}{dt}=-C\omega_0\cdot I_pR\cdot
\sin\omega_0 t
\] Then, we have voltage between \(L\), given \(I_L
= -I_C\)\[
V_L(t) = L\frac{dI_L(t)}{dt} = LC\omega_0^2\cdot I_pR\cdot \cos\omega_0
t = I_pR\cdot \cos\omega_0 t
\]
Series resonance
assuming \(V(t)=V_s\cos\omega_0t\),
where \(\omega_0 =1/\sqrt{LC}\) ,
suppose all current flow into \(V_C+V_L=0\)\[
V_R(t) = V(t) = V_s\cos\omega_0t
\] then \[
I_s(t) = \frac{V_s}{R}\cos\omega_0 t
\]\(V_L(t)\) is obtained \[
V_L(t) = L\frac{dI_s(t)}{dt} = -L\omega_0\cdot \frac{V_s}{R}\sin\omega_0
t
\] Then \[
V_C(t) = V(t) - (V_L(t) + V_R(t)) = -V_L(t)
\] Therefore, \(I_C\) current
flow through \(C\)\[
I_C(t) = C\frac{dV_C(t)}{dt}= LC\omega_0^2\cdot
\frac{V_s}{R}\cos\omega_0 t= \frac{V_s}{R}\cos\omega_0 t
\] voltage potential between \(L\) and \(C\)\[
\color{red}V_m(t) = V_R(t) + V_L(t) = V_s\cos\omega_0t -L\omega_0\cdot
\frac{V_s}{R}\sin\omega_0 t = V_s\sqrt{1+L/R^2C}\cos(\omega_0t+\phi)
\]
\[
f_\text{SRF} = \frac{1}{2\pi \sqrt{LC}}
\] The SRF of an inductor is the frequency at which the parasitic
capacitance of the inductor resonates with the ideal inductance of the
inductor, resulting in an extremely high impedance. The inductance only
acts like an inductor below its SRF
For choking applications, chose an inductor
whose SRF is at or near the frequency to be attenuated
For other applications, the SRF should be at least
10 times higher than the operating frequency
it is more important to have a relatively flat inductance
curve (constant inductance vs. frequency) near the required
frequency
J. Nako, G. Tsirimokou, C. Psychalinos and A. S. Elwakil,
"Approximation of FirstโOrder Complex Resonators in the
FrequencyโDomain," in IEEE Access, vol. 13, pp. 54494-54503,
2025 [pdf]
Johnson, M., Hudson, E.: A variable delay line PLL for
CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits
23(10), 1218โ1223 (1988) [https://sci-hub.se/10.1109/4.5947]
The periodic signal on VCTRL modulates the
VCO, giving rise to deterministic jitter
Timing Offsets Between Up and Dn Pulses
Mismatch Between Charge-Pump Current Sources
Incomplete Settling of Charge-Pump Currents
Finite Output Resistance of the Charge Pump
Up/Dn Timing Offset
If Dn pulse arrives \(\Delta T\)
after the Up pulse, the steady-state VCTRL will be slightly
lower than it would be without the \(\Delta T\) mismatch so as to return the
VCO's phase to match the reference clocks.
Vice versa, if If Up pulse arrives \(\Delta
T\) after the Dn pulse, the steady-state VCTRL will be slightly
higher than without \(\Delta
T\) mismatch
Current Sources Mismatch
Incomplete Settling
TODO ๐
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]
Cowan G. Mixed-Signal CMOS for Wireline Communication:
Transistor-Level and System-Level Design Considerations. Cambridge
University Press; 2024
2nd loop filter
PI (proportional - integral) Loop Filter
PFD Deadzone
Dead zone induced by incomplete settling of charge-pump
currents
This situation can be avoided by adding additional delay to the
AND gate in the PFD
For the sake of simplicity, \(V_{ctr}\) looks like a rectangular pulse
with an amplitude of \(I_{CP}R_1\) and
a duty ratio of (\(I_{leak}/I_{CP}\)),
whose first coefficient of Fourier series is
where \(I_\text{leak} \ll I_{CP}\)
is assumed
Then, the peak frequency deviation \(\Delta f\)\[
\Delta f = a_1 \cdot K_v = 2I_\text{leak}R_1 K_v
\] using narrowband FM approximation, we have \[
P_\text{spur} = 20\log\left(\frac{\Delta f}{2f_\text{ref}}\right) =
20\log\left(\frac{I_\text{leak}R_1 K_v}{f_\text{ref}}\right)
\]
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
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Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007.
Hunting jitter is often referred to as
dithering jitter, the periodic time
error between data clock and input data, which exhibits a
limit-cycle behavior
BB PD
Youngdon Choi, Deog-Kyoon Jeong and W. Kim, "Jitter transfer analysis
of tracked oversampling techniques for multigigabit clock and data
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[slides]
It's ternary, because early, late
and no transition
notice the transition density = 1 in
digital PLL
Linearization
The effective PD gain is a function of the input jitter
pdf, it enables one to anticipate the effects of input jitter
on loop characteristics
BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),
BB only produces output for a transition and this de-rates the gain.
Transition density = 0.5 for
random data
Input referred jitter from BB PD is
proportional to incoming jitter
gain simulation
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
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T. -K. Kuan and S. -I. Liu, "A Bang Bang Phase-Locked Loop Using
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# polyfit coef_fit = np.polyfit(dt, et, 1) print(f'coef_fit: {coef_fit}')
x = np.linspace(-3.5, 3.5, 1000) y = coef_fit[0]*x + coef_fit[1]
plt.figure(figsize=(12,6)) plt.plot(dt, et, 'o') plt.plot(x, y, linewidth=2, linestyle='--')
# Calculate histogram counts and bin edges counts, bin_edges = np.histogram(dt, bins=100) # Find the maximum count max_count = counts.max() # Create weights to normalize the maximum height to 1 weights = np.ones_like(dt) / max_count plt.hist(dt, bins=100, weights=weights)
That is \[
P_{x_s x_s} (f)= \frac{1}{T_s}P_{xx}(f)
\] In going from discrete time to continuous
time, we must add a scale factor \(1/T\), the sample period
Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp
Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 69, no. 7, pp. 3030-3036, July 2022
Daniel Boschen. GRCon24 - Quick Start on Control Loops with Python
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hunting jitter
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[phd
thesis]
Carlo Samori ISSCC2016 T1: Understanding Phase Noise in LC VCOs
Leeson's limitations
Hajimiri's Model- LTV ISF
ISF model
C. Livanelioglu, L. He, J. Gong, S. Arjmandpour, G. Atzeni and T.
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(ISSCC), San Francisco, CA, USA, 2025
If \(m=0\)\[
\phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\] If \(m\neq 0\) and \(m=n\)\[
\phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\]
\(m\omega_0 +\Delta \omega \ge
0\)
A. Hajimiri and T. H. Lee, "A general theory of phase noise in
electrical oscillators," in IEEE Journal of Solid-State
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Electrical Oscillators"
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Given \(i(t) = I_m \cos[(m\omega_0 - \Delta
\omega)t]\) and \(m \ge 1\)
To compare the ring oscillator and VCO the total injected
charge to both should be the same
Demir's Model - NLTV PPV
PPV (Perturbation Projection
Vector)
A. Demir and J. Roychowdhury, "A reliable and efficient procedure for
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A. L. S. Loke et al., "A versatile low-jitter PLL in 90-nm
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\[
f=\frac{1}{2\pi\sqrt{L_p C_p}} =
\frac{1}{2\pi\sqrt{L_s\frac{Q_L^2+1}{Q_L^2} C_s\frac{Q_C^2}{Q_C^2+1}}} =
\frac{1}{2\pi\sqrt{L_sC_s}}\cdot \sqrt{\frac{1+1/Q_c^2}{1+1/Q_L^2}}
\] Assuming the tank's Q is limited by the inductor's quality
factor \(Q_L\), i.e. \(Q_L\ll Q_c\)\[
f\approx \frac{1}{2\pi\sqrt{L_sC_s}}\cdot \sqrt{1-\frac{1}{Q_L^2}}
=f_0\cdot\sqrt{1-\frac{1}{Q_L^2}}
\] where \(f_0=\frac{1}{\sqrt{L_sC_s}}\) is the first
order approximation of the resonant frequency
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