B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and
Applications (2nd ed.). John Wiley & Sons, Inc.
Simon O. Haykin (2014), "Adaptive Filter Theory" Prentice-Hall, Inc.
5rd edition
Diniz, P. S. R. (2020). Adaptive Filtering: Algorithms and
Practical Implementation (5th ed.). Springer
Jiang X, ed. Digitally-Assisted Analog and Analog-Assisted
Digital IC Design. Cambridge University Press; 2015.
Albert Jerng. ISSCC2012 T7: Digital Calibration for RF
Transceivers [pdf]
Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in
ADCs [pdf]
Salvatore Levantino. ISSCC2024 T5: Calibration Techniques in
PLLs [pdf]
A. Chan Carusone and D. A. Johns, "Analog Filter Adaptation Using a
Dithered Linear Search Algorithm," IEEE Int. Symp. Circuits and
Syst., May 2002. [PDF], [Slides]
—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog
Design: Enabling Mixed-Signal System Validation," in IEEE Design
& Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim,
Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System
Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
—, M. Horowitz, "Error Control and Limit Cycle Elimination in
Event-Driven Piecewise Linear Analog Functional Models," in IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1,
pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]
B. Razavi, "Design considerations for direct-conversion receivers,"
in IEEE Transactions on Circuits and Systems II: Analog and Digital
Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]
Corresponding to the three distinct voltage thresholds in the
PAM4 systems, it would need 12 slicers, 3
multiplexers, and one thermometer-to-binary decoder in
each deserialized data path, even if only one tap of the DFE is
unrolled
Look-Ahead Multiplexing DFE
The look-ahead multiplexing technique brings the key benefit that the
timing constraint can be significantly relaxed, as the iteration bound
is doubled at the expense of extra
hardware
"ISI cancellation" based equalization is conceptually more
straightforward but suffers from SNR penalty or error propagation
Jitter Amplification
by Passive Channels
CDR Loop Latency
loop latency is represented as \(e^{-sD}\) in linear model
Sensitivity to Loop Latency
Enhancing
Resolution with a \(\Delta \Sigma\)
Modulator
Sub-Resolution Time Averaging
\(\Delta \Sigma\) modulator
effectively dithers the LSB bit
between zero and one, such that you can get the effective
resolution of a much higher resolution DAC in the number of bits
Decimation
how they affect sampling phase
DLF's input bit-width can be reduced by decimating BBPD's
output. Decimation is typically performed by realizing either
majority voting (MV) or boxcar
filtering.
Note that deserialization is inherent to both
MV and boxcar filtering
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it down
Decimating by \(L\) means frequency
register only added once every \(L\)
UI, thus integral path gain reduced by \(L\) in linear model
proportional path gain is unchanged
CDR Linear Model
condition:
Linear model of the CDR is used in a frequency lock
condition and is approaching to achieve phase
lock
Using this model, the power spectral density (PSD) of jitter in the
recovered clock \(S_{out}(f)\) is \[
S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f)
\] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they
come from independent sources.
Using below notation \[\begin{align}
\omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\
\xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2}
\end{align}\]
We can rewrite transfer function as follows \[
H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2}
\]
The jitter transfer represents a low-pass filter
whose magnitude is around 1 (0 dB) for low jitter frequencies and drops
at 20 dB/decade for frequencies above \(\omega_n\)
the recovered clock track the low-frequency
jitter of the input data
the recovered clock DONT track the
high-frequency jitter of the input data
The recovered clock does not suffer from high-frequency jitter even
though the input signal may contain high-frequency jitter, which will
limit the CDR tolerance to high-frequency jitter.
Jitter Peaking in
Jitter Transfer Function
The peak, slightly larger than 1 (0dB) implies that jitter will be
amplified at some frequencies in the CDR, producing a
jitter amplitude in the recovered clock, and thus also in the recovered
data, that is slightly larger than the jitter amplitude
in the input data.
This is certainly undesirable, especially in applications such as
repeaters.
Jitter Generation
If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the
recovered clock comes directly from the VCO jitter. The transfer
function that relates the VCO jitter to the recovered clock jitter is
known as jitter generation. \[
H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi
\omega_n s+\omega_n^2}
\] Jitter generation is high-pass filter with
two zeros, at zero frequency, and two poles identical to those of the
jitter transfer function
Jitter Tolerance
To quantify jitter tolerance, we often apply a sinusoidal jitter of a
fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR's true
tolerance to random jitter. Because we are applying
"sinusoidal" jitter, which is deterministic signal.
We can deal only with the jitter's amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
\[
JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad
\text{for a fixed BER}
\] Where the subscript \(\text{pp-max}\) indicates the
maximum peak-to-peak amplitude. We can further expand
this equation as follows \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_\text{pp-max}
\]
Relative jitter, \(\varphi_e\) must
be less than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude
of \(|\varphi_e(f)|\) is
1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
\] Given the linear CDR model, we can write \[
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
\] Expand \(H_{LF}(f)\) for the
CDR, we can write \[
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
\] At frequencies far below and above the natural frequency, the
jitter tolerance can be approximated by the following \[
JTOL(f) = \left\{ \begin{array}{cl}
\left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\
1 & : \ f\gg f_n
\end{array} \right.
\]
the jitter tolerance at very high jitter frequencies
is limited to 1UIpp
1 2 3 4 5 6 7 8 9 10 11 12 13 14
clc; clear all;
f_fn = logspace(-1, 2, 60); for xi = [2, 1, 0.5, 0.2] jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2); loglog(f_fn, jtol,LineWidth=2) disp(["min(JTpp)=", min(jtol),"@\xi=",xi]) hold on end grid on; xlabel("f/f_n") ylabel('JT_{pp}') legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')
OJTF
Concepts of JTF and OJTF
Simplified Block Diagram of a Clock-Recovery PLL
Jitter Transfer Function (JTF)
Input Signal Versus Recovered Clock
JTF, by jitter frequency, compares how much input signal jitter is
transferred to the output of a clock-recovery's PLL (recovered
clock)
Input signal jitter that is within the clock recovery PLL's loop
bandwidth results in jitter that is faithfully transferred (closed-loop
gain) to the clock recovery PLL's output signal. JTF in this situation
is approximately 1.
Input signal jitter that is outside the clock recovery PLL's loop
bandwidth results in decreasing jitter (open-loop gain) on the clock
recovery PLL's output, because the jitter is filtered out and no longer
reaches the PLL's VCO
Observed Jitter Transfer Function
Input Signal Versus Sampled Signal
OJTF compares how much input signal jitter is transferred to the
output of a receiver's decision making circuit as
effected by a clock recovery's PLL. As the recovered clock is the
reference for detecting the input signal
Input signal jitter that is within the clock
recovery PLL's loop bandwidth results in jitter on the recovered clock
which reduces the amount of jitter that can be detected. The input
signal and clock signal are closer in phase
Input signal jitter that is outside the clock
recovery PLL's loop bandwidth results in reduced jitter on the
recovered clock which increases the amount of jitter that can
be detected. The input signal and clock signal are more out of phase.
Jitter that is on both the input and clock signals can not detected or
is reduced
JTF and OJTF for 1st Order PLLs
The observed jitter is a complement to the PLL jitter transfer
response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not
observed at the output of the CDR as a function of the jitter rate
applied to the input.
The combination of the OJTF of a jitter measurement device and the
JTF of the clock generator under test gives the measured jitter as a
function of frequency.
For example, a clock generator with a type 1, 1st order PLL measured
with a jitter measurement device employing a golden PLL is \[
J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2}
\]
Accurate measurement of the clock JTF requires that the OJTF cutoff
of the jitter measurement be significantly below that of the clock JTF
and that the measurement is compensated for the instrument's OJTF.
The overall response is a band pass filter because the clock JTF is
low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring
the jitter of the reference clock at each jitter rate being tested and
comparing the reference jitter with the jitter
measured at the output of the DUT.
The lower the cutoff frequency of the jitter measurement device the
better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the
phase noise of the DUT and measurement time.
Digital Sampling
Oscilloscope
How to analyze jitter:
TIE (Time Interval Error) track
histogram
FFT
TIE track provides a direct view of how the phase of
the clock evolves over time.
histogram provides valuable information about the
long term variations in the timing.
FFT allows jitter at specific rates to be measured
down to the femto-second range.
Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop
bandwidth minimizes the response error
reference
Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and
Phase Noise: A Circuits and Systems Perspective.” (2018).
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
AFE Nonlinearity
"total harmonic distortion" (THD) in
AFE
Relative to NRZ-based systems, PAM4 transceivers require more
stringent circuit linearity, equalizers which can implement multi-level
inter-symbol interference (ISI) cancellation, and improved
sensitivity
Because if it compresses, it turns out you have to use a much more
complicated feedback filter. As long as it behaves linearly,
the feedback filter itself can remain a linear FIR
Linearity can actually be a critical constraint in these signal
paths, and you really want to stay as linear as you can all the way up
until the point where you've canceled all of the ISI
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline
Receivers"
BER with Quantization Noise
\[
\text{Var}(X) = E[X^2] - E[X]^2
\]
Impulse Response or Pulse
Response
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link
Foundations Standards, Link Budgets & Models," 2019 IEEE Custom
Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp.
1-95 [https://youtu.be/OABG3u2H2J4?si=CxryBSGbxrUpZNBT]
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline
Links-Part II: Optimization and Performance Assessment," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024
[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in
Serial Data Transmission Systems,” in Phase-Locking in High-Performance
Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]
Da Dalt N. A design-oriented study of the nonlinear dynamics of
digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I:
Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]
Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop
gain tracking all-digital PLL using autocorrelation of bang–bang
phasefrequency detection. IEEE Transactions on Circuits and Systems II:
Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]
CDR Loop Latency
Denoting the CDR loop latency by \(\Delta
T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The
resulting right-half-plane zero, \(f_z\) degrades the phase margin and must
remain about one decade beyond the BW\[
f_z\simeq \frac{1}{2\pi \Delta T}
\]
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of
Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
limit cycles imply self-sustained oscillators due nonlinear
nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC
LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van
Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design.
Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]
BB PD
It's ternary, because early, late
and no transition
Linearing BB-PD
BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),
BB only produces output for a transition and this de-rates the gain.
Transition density = 0.5 for random data
Input referred jitter from BB PD is
proportional to incoming jitter
John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and
Data Recovery
Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data
Recovery in Serial Data Transmission Systems. [pdf]
- Clock and Data Recovery for Serial Data Communications, focusing on
bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]
Digital CDR Category
DCO part is analogous so that it cannot be perfectly
modeled
Digital-to-phase converter is well-defined phase output, thus, very
good to model real situation
DCO
limit cycle
Z-domain modeling
The difference equation is \[
\phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi
\] z-transform is \[
\frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}}
\]
where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)
\(\Delta
\Sigma\)-dithering in DCO
Quantization noise
Here, \(\alpha_T\) is data
transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang
Controlled Timing Circuits," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
Time to Digital Converter
(TDC)
Digital to Phase Converter
(DPC)
IIR low pass filter
simple approximation: \[
z = 1 + sT
\] bilinear-z transform \[
z =\frac{}{}
\]
Peak-to-peak jitter in
ADPLL with BBPD
Accumulate-and-dump (AAD)
decimator
accumulating the input for \(N\)
cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input
samples at rate \(1/T\) and delivers
their sum in a single sample at the output. Therefore, the
process comprises a filter (in the accumulation) and a
down-sampler (in the dump)
Moving Average and CIC
Filters
cascade-integrator-comb (CIC) decimator
TODO 📅
An Intuitive Look at Moving Average and CIC Filters [web,
code]
Phase detecting possible , Frequency detecting impossible
PLL or FD(Frequency Detector) for frequency detecting in CDR
reference
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and
Circuits" [slides]
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems
(lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT
OpenCourseWare, [lec21.pdf]
Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental
Concepts To Future Trends" [T5.pdf]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
—, "A digital clock and data recovery architecture for
multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom
Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
P. Palestri et al., "Analytical Modeling of Jitter in
Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol.
29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T.
King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore,
"A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit
Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital
Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol.
41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]
—, et al., "Modeling of ADC-Based Serial Link Receivers With
Embedded and Digital Equalization," in IEEE Transactions on
Components, Packaging and Manufacturing Technology, vol. 9, no. 3,
pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]
K. Zheng, "System-Driven Circuit Design for ADC-Based Wireline Data
Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]
S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo,
"Statistical modeling of metastability in ADC-based serial I/O
receivers," 2014 IEEE 23rd Conference on Electrical Performance of
Electronic Packaging and Systems [pdf]
We typically use the two spectra, \(S_{\phi
n}(f)\) and \(S_{out}(f)\),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal \(x(t)\) can be
expanded in Fourier series as:
Assume that the signal is subject to excess phase noise,
which is modeled by adding a time-dependent noise
component \(\alpha(t)\). The noisy
signal can be written \(x(t+\alpha(t))\), the added excess phase
\(\phi(t)=
\frac{\alpha(t)}{\omega_0}\)
The autocorrelation of the noisy signal is by definition:
The autocorrelation averaged over time results in:
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal \(x(t + \alpha(t))\) can
be expressed as
It is also interesting to note how the integral in Equation
9.80 around each harmonic is equal to the power of the harmonic
itself \(|X_n|^2\)
The integral \(S_x(f)\) around
harmonic is \[\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}\]
The phase noise does not affect the total power in the
signal, it only affects its distribution
Without phase noise, \(S_v(f)\) is
a series of impulse functions at the harmonics of \(f_o\).
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
Phase
perturbed by a stationary noise with Gaussian PDF
If keep \(\phi_{rms}\) in \(R_x(\tau)\), i.e. \[
R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)(1+R_\phi(\tau))
\] The PSD of the signal is \[
S_x(f) = \mathcal{F} \{ R_x(\tau) \} =
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] +
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right]
\] ❗❗above Eq isn't consistent with stationary
white noise process - the following section
Phase
perturbed by a stationary WHITE noise process
Assuming that the delay line is noiseless
Expanding the cosine function we get \[\begin{align}
R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi
f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi
f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\
&+ \frac{A^2}{2}\left\{\cos(4\pi
f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi
f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\}
\end{align}\]
where, both the process \(\phi(t)-\phi(t-\tau)\) and \(\phi(t)+\phi(t-\tau)\) are independent of
time \(t\), i.e. \(E[\cos(\phi(t)+\phi(t-\tau))] =
m_{\cos+}(\tau)\), \(E[\cos(\phi(t)-\phi(t-\tau))] =
m_{\cos-}(\tau)\), \(E[\sin(\phi(t)+\phi(t-\tau))] =
m_{\sin+}(\tau)\) and \(E[\sin(\phi(t)-\phi(t-\tau))] =
m_{\sin-}(\tau)\)
The second term in the above expression is periodic in \(t\) and to estimate its PSD, we compute the
time-averaged autocorrelation function\[
R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) -
\sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\}
\]
After nontrivial derivation
Phase perturbed by a Weiner
process
The phase process \(\phi(t)\) is
also gaussian but with an increasing variance which
grows linearly with time\(t\)
The spectrum of \(y(t)\) is
determined by the asymptotic behavior of \(R_y(t,\tau)\) as \(t\to \infty\)
❗❗ \(\lim_{t\to\infty}R_y(t,\tau)\) rather than
time-averaged autocorrelation function of cyclostationary
process, ref. Demir's paper
We define \(\zeta(t,
\tau)=\phi(t)+\phi(t-\tau) = \phi(t)-\phi(t-\tau) +
2\phi(t-\tau)\), the expected value of \(\zeta(t,\tau)\) is 0, the variance is \(\sigma_{\zeta}^2=(k\sigma)^2(\tau +
4(t-\tau))=(k\sigma)^2(4t-3\tau)\)\[
E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta
= e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)}
\] i.e., \(\lim _{t\to \infty}
E[\cos(\zeta(t,\tau))] = \lim_{t\to \infty}e^{-(k\sigma)^2(4t-\tau)} =
0\)
For \(E[\sin(\zeta(t,\tau))]\), we
have \[
E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta
\] i.e., \(E[\sin(\zeta(t,\tau))]\) is odd
function, therefore \(E[\sin(\zeta(t,\tau))]=0\)
A. Hajimiri and T. H. Lee, "A general theory of phase noise in
electrical oscillators," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [paper],
[slides]
—, ISSCC2016, "Understanding Phase Noise in LC VCOs"
A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in
oscillators: a unifying theory and numerical methods for
characterization," in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.se/10.1109/81.847872]
Godone, A. & Micalizio, Salvatore & Levi, Filippo. (2008). RF
spectrum of a carrier with a random phase modulation of arbitrary slope.
[https://sci-hub.se/10.1088/0026-1394/45/3/008]
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
proportional term (P) depends on the present error
integral term (I) depends on past errors
derivative term (D) depends on anticipated future errors
PID controller makes use of linear extrapolation of
the measured output
PI controller does not make use of any prediction of
the future state of the system
The prediction by linear extrapolation (D) can generate large
undesired control signals because measurement noise is amplified, that's
why D is not used widely
charge pumps are capacitive
DC-DC converters. The two most common switched capacitor
voltage converters are the voltage inverter and the
voltage doubler circuit
We derive a recursive equation that describes the output voltage
\(V_{out,n}\) after the \(n\)th clock cycle \[
V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o}
\]
Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is
\[
\overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} -
\frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right)
\approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p}
\] which results in a simple expression for the output
voltage droop
\[
\Delta V_{out} = \frac{I_{load}}{f_{sw}C_p}
\]
The charge pump can be modeled as a voltage source with a
source resistance\(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage
drop across \(R_\text{out}\) due to the
load current:
Fourier transform of the output of the expander is a frequency-scaled
version of the Fourier transform of the input
Subsampling or Downsampling
Eqs. (4.72)
the superposition of an infinite set of amplitude-scaled copies of
\(X_c(j\Omega)\), frequency scaled
through \(\omega = \Omega T_d\) and
shifted by integer multiples of \(2\pi\)
Eq. (4.77)
the superposition of \(M\)
amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by
\(M\) and shifted by integer multiples
of \(2\pi\)
downsampled by a factor of \(M =
2\)
Upsampling or Zero Insertion
Assuming \(X(e^{j\omega_1}) =
U_f(e^{j\omega_1})\) with \(\omega_1 =
\Omega T_1\), upsampled by ratio \(L\), then obtain
Polyphase decomposition is a powerful technique used in digital
signal processing to efficiently implement multirate systems.
where \(e_k[n]=h[nM+k]\)
Polyphase Implementation of Decimation Filters &
Interpolation Filters
Decimation system
Interpolation system
sampling identity
LPTV Implementation
TODO 📅
The interpolation filter following an up-sampler
generally is time varying and cannot be represented by
a simple transfer function. The equivalent filter in a
zero-order hold is an exception, perhaps unique, that
can be represented with a time-invariant transfer function
The interpolation filter following an up-sampler generally is
time varying and cannot be represented by a simple
transfer function. The equivalent filter in a Zero-Order
Hold is an exception, perhaps unique, that can be represented
with a time-invariant transfer function
Split the \(1:LM\) hold process into
a \(1 : L\) hold followed by a \(1 : M\) hold \[
Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}}
\] then \[\begin{align}
F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\
&=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}}
\\
&= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
\end{align}\]
That is \(F_1(z)=F_2(z)\), i.e. they
are equivalent
In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is
\[
LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}}
\]
In (b),
Accumulate-And-Dump
(AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[
\phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}
\] Hence \[\begin{align}
\phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\
&= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot
\frac{1}{1-\eta^{-1}}
\end{align}\]
After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align}
\phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\
&=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}}
\end{align}\] i.e., \[
LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1-z^{-L}}{1-z^{-1}}
\]
When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx
1\)
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
J. Sonntag and J. Stonick, "A digital clock and data recovery
architecture for multi-gigabit/s binary links," Proceedings of the
IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority
Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR,"
in IEEE Transactions on Microwave Theory and Techniques, vol.
68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]
J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with
Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]
J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum
Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State
Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
A. Sheikholeslami, "Voltage Follower, Part III [Circuit Intuitions],"
in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp.
14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457
Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.
Double differential Pair
\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
\]
In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end
assume input and reference common voltage are
same
Pros of (b)
larger input range i.e., \(\gt \pm
\sqrt{2}V_\text{ov}\) of (a), it works even one
differential is off due to lower voltage
larger \(g_m\) (smaller input
difference of pair)
Cons of (b)
sensitive to the difference of common voltage between \(V_\text{ip}\), \(V_\text{im}\) and \(V_\text{rp}\), \(V_\text{rm}\)
common-mode voltage
difference
copy aforementioned formula here for convenience \[
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
\]
at sample phase\(V_\text{ip}=
V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}=
V_\text{cmr}\)
\(I_\text{ip0}= I_\text{im0} =
I_\text{i0}\)
\(I_\text{rp0}= I_\text{rm0} =
I_\text{r0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} = 0\)
at compare start
\(V_\text{ip}= V_\text{im}=
V_\text{cmi}\) and \(V_\text{rp}=
V_\text{cmr}+\Delta\), \(V_\text{rp}=
V_\text{cmr}-\Delta\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to
increase \(V_\text{ip}\) and decrease
\(V_\text{im}\).
and \(I_\text{ip0}= I_\text{im0} =
I_\text{i0}\), \(I_\text{rp0}=
I_\text{rm0} = I_\text{r0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} = 0\)
If \(V_\text{cmr} - V_\text{cmi} =
\sqrt{2}V_{OV} + \delta\), and \(\delta
\gt 0\). one transistor carries the entire tail current
\(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\), all the time
At the end, \(V_\text{im} = V_\text{cmi} -
(\Delta - \delta)\), the error is \(\delta\)
In closing, \(V_\text{cmr} - V_\text{cmi}
\lt \sqrt{2}V_{OV}\) for normal work
Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to
limited impedance of current source and input
pair offset
In the end \[
V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS}
\]
Under the condition, every transistor of pairs are on in
equilibrium
Resistive degeneration in differential pairs serves as one
major technique for linear amplifier
The linear region for CMOS differential pair would be extended by
\(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align}
V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\
&= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2}
\end{align}\]
Byungsub Kim, ISSCC 2022, "T11: Basics of Equalization Techniques:
Channels, Equalization, and Circuits"
Minsoo Choi et al., "An Approximate Closed-Form Channel Model for
Diverse Interconnect Applications," IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct.
2014.
K. Yadav, P. -H. Hsieh and A. Chan Carusone, "Linearity Analysis of
Source-Degenerated Differential Pairs for Wireline Applications," in
IEEE Open Journal of Circuits and Systems, [link]
"Quantizers" and "truncators",
and "integrators" and "accumulators"
are used in delta-sigma ADCs and DACs,
respectively
P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma
DACS," 2003 IEEE International Symposium on Circuits and Systems
(ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]
a delta–sigma ADC consists of an analog
modulator followed by a digital filter
a delta–sigma DAC consists of a digital
modulator followed by an analog filter
Analog Delta Sigma Modulators (ADSM) are used in the
context of analog-to-digital conversion
In a CT delta-sigma ADC, there is no need for an anti-aliasing
filter or a front-end sampler
Digital Delta Sigma Modulators (DDSM) are commonly
used in digital to-analog conversion and fractional-N
frequency synthesis
In a DDSM, the input is digital and the filters are
implemented digitally
the input to the DDSM is often a constant digital word,
this covers delta-sigma fractional-N synthesizers in the frequency
generation application
plot(w1/2/pi, abs(h1), LineWidth=3) hold on plot(w2/2/pi, abs(h2), LineWidth=3) grid on legend('MOD1', 'MOD2') xlabel('fs') ylabel('mag') title('NTF of MOD1 & MOD2')
output vs.
error-feedback
The error-feedback architecture is
problematic for analog implementation, since it is
sensitive to variations of its parameters (subtractor realization)
The error-feedback structure is thus of limited utility in \(\Delta \Sigma\)ADCs
The error-feedback structure is very useful and applied in
digital loops required in \(\Delta \Sigma\)DACs
ADC
DAC
P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma
DACS," 2003 IEEE International Symposium on Circuits and Systems
(ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]
always @(*) i_func_extended = {i_func[15],i_func[15],i_func[15],i_func[15],i_func}; always @(posedge i_clk ornegedge i_res) begin if (i_res==0) begin DAC_acc_1st<=16'd0; DAC_acc_2nd<=16'd0; this_bit = 1'b0; end elseif(i_ce == 1'b1) begin if(this_bit == 1'b1) begin DAC_acc_1st = DAC_acc_1st + i_func_extended - (2**15); DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st - (2**15); end else begin DAC_acc_1st = DAC_acc_1st + i_func_extended + (2**15); DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st + (2**15); end // When the high bit is set (a negative value) we need to output a 0 and when it is clear we need to output a 1. this_bit = ~DAC_acc_2nd[19]; end end endmodule
an interpolation filter effectively
up-samples its low-rate input and
lowpass-filters the resulting high-rate data
to produce a high-rate output devoid of images
Notice that the requirements of the first stage
are very demanding
No delay-free loops
Any such physically feasible device will take
a finite time to operate – in other words, the
quantized output will only be available a small time
after the quantizer has "looked" at the input - insert a one-sample
delay
there cannot be a "delay free loop" is a
common idea in sequential digital state machine design
Both integrator and quantizer are delay free
NTF realizability criterion: No delay-free loops in the modulator
linear settling & GBW of
amplifier
TODO 📅
Switched capacitor has been the common realization technique of
discrete-time (DT) modulators, and in order to achieve a
linear settling, the sampling frequency used
in these converters needs to be significantly lower than the gain
bandwidth product (GBW) of the amplifiers.
!!! The \(u\) is limited between
0 and 60 (MSBs_LSBs - LSBs)
Tuan Minh Vo, S. Levantino and C. Samori, "Analysis of fractional-n
bang-bang digital PLLs using phase switching technique," 2016 12th
Conference on Ph.D. Research in Microelectronics and Electronics
(PRIME), Lisbon, Portugal, [https://sci-hub.se/10.1109/PRIME.2016.7519545]
An implementation of a high-resolution integral path
using a digital delta-sigma modulator, low-resolution
Nyquist DAC, and a lowpass filter
\(\Delta \Sigma\) truncates \(n\)-bit accumulator output to \(m\)-bits with \(m\le n\)
A \(m\)-bit Nyquist DAC outputs
current, which is fed into a low pass filter that suppresses \(\Delta \Sigma\)'s quantization noise
The remaining 11 bits are truncated to 3-levels using a
second-order delta-sigma modulator (DSM), thus, obviating the need for a
high resolution DAC
dithering break periodicity and convert
them to noise while input is constant
drawback of Integer-N PLL
integer-N PLL frequency synthesizers
the frequency resolution, is equal to the reference
frequency, meaning that only integer multiples of the reference
frequency can be synthesized
if fine tuning is required, only choice in an integer-N
PLL is to decrease the reference frequency
Stability requirements limit the loop bandwidth to about
one tenth of the reference frequency; therefore, decreasing the
reference frequency increases the settling time as the loop bandwidth
also has to be decreased
Another drawback of the integer-N PLL is the trade-off
between phase noise and settling time when the divider ratio
becomes large (The contributions to the output phase noise of
almost all PLL building blocks, except the VCO, are multiplied
by the division ratio)
i.e. \[
\tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL}
\]
where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV},
desired}\)
In \(z\)-domain \[
\left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y
\right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y
\] That is \[
Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2
\] In time domain \[\begin{align}
y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\
&= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2]
\end{align}\]
quantizer overload
TODO 📅
CIC filter
Cascaded
Integrator-Comb
(CIC) Filters
Let’s focus on decimation: if we decimate by a factor 4, we simply
retain one output sample out of every 4 input samples.
In the example below, the downsampler at the right drops those 3
samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input
rate \(x(n)\):
with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[
Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}}
\]
But if we're going to be throwing away 75% of the calculated values,
can't we just move the downsampler from the end of the pipeline to
somewhere in the middle? Right between the integrator stage and the comb
stage? That answer is yes, but to keep the math working, we
also need to divide the number of delay elements in the comb stage by
the decimation rate:
DC gain is used to compensate the ratio of sampling rate before and
after upsample
Given \[
X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i}
\] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)
Employ definition of DTFT, \(X(e^{j\hat{\omega}})
=\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set
\(\hat{\omega} = 0\)\[
X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n]
\] That is, \(\sum_{n=-\infty}^{+\infty}x[n] =
\sum_{n=-\infty}^{+\infty}x_e[n]\), so \[
\overline{x_e[n]} = \frac{1}{L} \overline{x[n]}
\] It also indicate that dc gain of upsampling is \(1/L\)
ZOH
Zero-Order Hold (ZOH)
dc gain = \(N\)
FOH
First-Order Hold (FOH)
dc gain = \(N\)
reference
R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data
Converters
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016.
Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
Horowitz, P., & Hill, W. (2015). The art of electronics
(3rd ed.). Cambridge University Press. [pdf]
P. M. Aziz, H. V. Sorensen and J. vn der Spiegel, "An overview of
sigma-delta converters," in IEEE Signal Processing Magazine, vol. 13,
no. 1, pp. 61-84, Jan. 1996 [https://sci-hub.st/10.1109/79.482138]
V. Medina, P. Rombouts and L. Hernandez-Corporales, "A Different View
of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation
[Feature]," in IEEE Circuits and Systems Magazine, vol. 24, no.
2, pp. 80-97, Secondquarter 2024
S. Pamarti and I. Galton, "LSB Dithering in MASH Delta–Sigma D/A
Converters," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]
This simplified version of LMS algorithm is identical to the
zero-forcing algorithm which minimizes the ISI at data
samples
Sign-Sign LMS (SS-LMS)
T11: Basics of Equalization Techniques: Channels, Equalization, and
Circuits, 2022 IEEE International Solid-State Circuits Conference
V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link
transceiver with adaptive equalization and data recovery," in IEEE
Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April
2005, doi: 10.1109/JSSC.2004.842863.
Jinhyung Lee, Design of High-Speed Receiver for Video Interface with
Adaptive Equalization; Phd thesis, August 2019. thesis
link
Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical
Implementation, 5th edition
E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for
I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State
Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008
DFE h0 Estimator
summer output \[
r_k =
a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=1}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right)
\] error slicer analog output \[
e_k=r_k-\hat{a}_k \hat{h}_0
\] error slicer digital output \[
\hat{e}_k=|e_k|
\] It's NOT possible to implement \(e_k\), which need to determine \(\hat{a}_k=|r_k|\) in no time. One method to
approach this problem is calculate \(e_k^{a_k=1}=r_k-\hat{a}_k \hat{h}_0\) and
\(e_k^{a_k=-1}=r_k+\hat{a}_k
\hat{h}_0\), then select the right one based on \(\hat{a}_k\)
The update equation based on Sign-Sign-Least Mean square (SS-LMS) and
loss function \(L(\hat{h}_{\text{0~ntap}})=E(e_k^2)\)\[
\hat{h}_n(k+1) = \hat{h}_n(k)+\mu \cdot |e_k|\cdot \hat{a}_{k-n}
\] Where \(n \in
[0,...,\text{ntap}]\). This way, we can obtain \(\hat{h}_0\), \(\hat{h}_1\), \(\hat{h}_2\), ...
\(\hat{h}_0\) is used in AFE
adaptation
We may encounter difficulty if the first tap of DFE is unrolled, its
\(e_k\) is modified as follow \[
r_k =
a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=2}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right)
\] Where there is NO \(\hat{h}_1\)
To find \(\hat{h}_1\), we shall use
different pattern for even and odd error slicer
M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A.
Sheikholeslami, "Design and Implementation of an On-Demand
Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of
Circuits and Systems, vol. 3, pp. 97-108, 2022, doi:
10.1109/OJCAS.2022.3173686.
Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing
Architecture Using Viterbi Algorithm for ADC-Based Serial Link.
Undergraduate Research Scholars Program. Available electronically from
[https://hdl.handle.net/1969.1/166485]
There are several variants of MLSD (Maximum Likelihood Sequence
Detection), including:
MMPD infers the channel response from baud-rate samples of the
received data, the adaptation aligns the sampling clock such that
pre-cursor is equal to the post-cursor in the pulse
response
F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver
with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010
IEEE International Solid-State Circuits Conference - (ISSCC), San
Francisco, CA, USA, 2010, pp. 366-367, doi:
10.1109/ISSCC.2010.5433823.
K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of
PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open
Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022
\(s_{011}\) & \(s_{110}\) are approaching to each
other
\(s_{100}\) & \(s_{001}\) are approaching to each
other
Then, \(h_{-1}\) and \(h_1\) are same, which is desired
Bang-Bang CDR
alexander PD or !!PD
The alexander PD locks that edge clock (clkedge) is located at zero
crossings of the data. The \(h_{-0.5}\)
and \(h_{0.5}\) are
equal at the lock point, where the \(h_{-0.5}\) and \(h_{0.5}\) are the cursors located at -0.5
UI and 0.5 UI.
Stojanovic, Vladimir & Ho, A. & Garlepp, B. & Chen, Fred
& Wei, J. & Alon, Elad & Werner, C. & Zerbe, J. &
Horowitz, M.A.. (2004). Adaptive equalization and data recovery in a
dual-mode (PAM2/4) serial link transceiver. IEEE Symposium on VLSI
Circuits, Digest of Technical Papers. 348 - 351.
10.1109/VLSIC.2004.1346611.
A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design
Optimization for Wireline SerDes Applications," in IEEE Transactions
on Circuits and Systems I: Regular Papers, doi:
10.1109/TCSI.2023.3328807.
A. Sharif-Bakhtiar, A. Chan Carusone, "A Methodology for Accurate DFE
Characterization," IEEE RFIC Symposium, Philadelphia,
Pennsylvania, June 2018. [PDF]
[Slides
– PDF]
\[
X- Y\cdot \beta z^{-1}\cdot \frac{1}{1-z^{-1}} = Y
\] therefore \[
\frac{Y}{X} = \frac{1-z^{-1}}{1-(1-\beta)z^{-1}}
\]
