Hunting jitter is often referred to as
dithering jitter, the time error between
data clock and input data
where the proportional gain (\(K_P\)), heavily damped systems
means that \(K_P \gg K_I\)
N. Da Dalt, "A design-oriented study of the nonlinear dynamics of
digital bang-bang PLLs," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005 [https://sci-hub.se/10.1109/TCSI.2004.840089]
S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim and D. -K. Jeong,
"An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of
Bang–Bang Phase-Frequency Detection," in IEEE Transactions on Circuits
and Systems II: Express Briefs, vol. 62, no. 9, pp. 836-840, Sept. 2015
[https://sci-hub.st/10.1109/TCSII.2015.2435691]
CC Chen. Why Hunting Jitter Happens in CDR: The Role of Input Jitter
and Latency? [https://youtu.be/hPDielPsFgY]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
Circuits Conference 2006 [https://sci-hub.se/10.1109/CICC.2006.320829]
That is \[
P_{x_s x_s} (f)= \frac{1}{T_s}P_{xx}(f)
\] In going from discrete time to continuous
time, we must add a scale factor \(1/T\), the sample period
Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp
Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 69, no. 7, pp. 3030-3036, July 2022
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 68, no. 7, pp. 2775-2786, July
2021
Da Dalt, Nicola. (2009). Linearized Analysis of a Digital Bang-Bang
PLL and Its Validity Limits Applied to Jitter Transfer and Jitter
Generation. Circuits and Systems I: Regular Papers, IEEE Transactions
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If \(m=0\)\[
\phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\] If \(m\neq 0\) and \(m=n\)\[
\phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\]
\(m\omega_0 +\Delta \omega \ge
0\)
A. Hajimiri and T. H. Lee, "A general theory of phase noise in
electrical oscillators," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998
Corrections
to "A General Theory of Phase Noise in Electrical Oscillators"
A. Hajimiri and T. H. Lee, "Corrections to "A General Theory of Phase
Noise in Electrical Oscillators"," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 6, pp. 928-928, June 1998 [https://sci-hub.se/10.1109/4.678662]
L. Lu, Z. Tang, P. Andreani, A. Mazzanti and A. Hajimiri, "Comments
on “Comments on “A General Theory of Phase Noise in Electrical
Oscillators””," in IEEE Journal of Solid-State Circuits, vol.
43, no. 9, pp. 2170-2170, Sept. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005028]
Given \(i(t) = I_m \cos[(m\omega_0 - \Delta
\omega)t]\) and \(m \ge 1\)
To compare the ring oscillator and VCO the total injected
charge to both should be the same
Tail filter
TODO 📅
P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with
>45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and
Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025
E. Hegazi, H. Sjoland and A. Abidi, "A filtering technique to lower
oscillator phase noise," 2001 IEEE International Solid-State
Circuits Conference. Digest of Technical Papers. ISSCC (Cat.
No.01CH37177), San Francisco, CA, USA, 2001 [paper,
slides]
D. Murphy, H. Darabi and H. Wu, "Implicit Common-Mode Resonance in LC
Oscillators," in IEEE Journal of Solid-State Circuits, vol. 52, no. 3,
pp. 812-821, March 2017, [https://sci-hub.st/10.1109/JSSC.2016.2642207]
—, "25.3 A VCO with implicit common-mode resonance," 2015 IEEE
International Solid-State Circuits Conference - (ISSCC) Digest of
Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.st/10.1109/ISSCC.2015.7063116]
Y. Hu, T. Siriburanon and R. B. Staszewski, "Intuitive Understanding
of Flicker Noise Reduction via Narrowing of Conduction Angle in
Voltage-Biased Oscillators," in IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019
[https://sci-hub.se/10.1109/TCSII.2019.2896483]
S. Levantino, P. Maffezzoni, F. Pepe, A. Bonfanti, C. Samori and A.
L. Lacaita, "Efficient Calculation of the Impulse Sensitivity Function
in Oscillators," in IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 59, no. 10, pp. 628-632, Oct. 2012 [https://sci-hub.se/10.1109/TCSII.2012.2208679]
S. Levantino and P. Maffezzoni, "Computing the Perturbation
Projection Vector of Oscillators via Frequency Domain Analysis," in IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 31, no. 10, pp. 1499-1507, Oct. 2012 [https://sci-hub.se/10.1109/TCAD.2012.2194493]
Y. Hu, T. Siriburanon and R. B. Staszewski, "Oscillator Flicker Phase
Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468]
A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in
oscillators: a unifying theory and numerical methods for
characterization," in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.se/10.1109/81.847872]
B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and
Applications (2nd ed.). John Wiley & Sons, Inc.
Simon O. Haykin (2014), "Adaptive Filter Theory" Prentice-Hall, Inc.
5rd edition
Diniz, P. S. R. (2020). Adaptive Filtering: Algorithms and
Practical Implementation (5th ed.). Springer
Sen M. Kuo. Real-Time Digital Signal Processing: Fundamentals,
Implementations and Applications, 3rd Edition. John Wiley & Sons
2013
Stankovic, Ljubisa. (2015). Digital Signal Processing with Selected
Topics.
A. Chan Carusone and D. A. Johns, "Analog Filter Adaptation Using a
Dithered Linear Search Algorithm," IEEE Int. Symp. Circuits and
Syst., May 2002. [PDF], [Slides]
—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog
Design: Enabling Mixed-Signal System Validation," in IEEE Design
& Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim,
Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System
Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
—, M. Horowitz, "Error Control and Limit Cycle Elimination in
Event-Driven Piecewise Linear Analog Functional Models," in IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1,
pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]
Common Refclk Rx architectures are characterized by the Tx and Rx
sharing the same Refclk source
Most of the SSC jitter sourced by the Refclk is propagated equally
through Tx and Rx PLLs, and so intrinsically tracks LF
jitter
The amount of jitter appearing at the CDR is then defined by the
difference function between the Tx and Rx PLLs multiplied by the
CDR highpass characteristic
\[
H(s)= H_1(s)e^{-sT} - \left[H_1(s)e^{-sT}(1-H_3(s)) + H_2(s)H_3(s)
\right] = [H_1(s)e^{-sT} -H_2(s)]H_3(s)
\] where \(H_3(s)\) is similar
to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Data Clocked Refclk Rx
Architecture
A data clocked Rx architecture is characterized by requiring the
receiver's CDR to track the entirety of the low frequency jitter,
including SSC
Separate Reference
Clocks with SSC (SRIS)
TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE:
Updated 10 January 2013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev.
3.0 SPONSOR: Intel, HP, AMD
\[\begin{align}
X_{LATCH}(s) &= X_1(s)H_1(s) - \left[X_1(s)H_1(s)(1-H_3(s)) +
X_2(s)H_2(s)H_3(s) \right] \\
& = \left[X_1(s)H_1(s) -X_2(s)H_2(s)\right]H_3(s)
\end{align}\] where \(H_3(s)\)
is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Separate Reference
Clocks with No SSC (SRNS)
Low-Latency PCIe
TODO 📅
AC-coupling vs DC-coupling
TODO 📅
Linearity & Even-Order
Distortion
Odd-order distortion: symmetry
Even-Order Distortion: non-symmetry
(Effect of Mismatch)
B. Razavi, "Design considerations for direct-conversion receivers,"
in IEEE Transactions on Circuits and Systems II: Analog and Digital
Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]
Corresponding to the three distinct voltage thresholds in the
PAM4 systems, it would need 12 slicers, 3
multiplexers, and one thermometer-to-binary decoder in
each deserialized data path, even if only one tap of the DFE is
unrolled
Look-Ahead Multiplexing DFE
The look-ahead multiplexing technique brings the key benefit that the
timing constraint can be significantly relaxed, as the iteration bound
is doubled at the expense of extra
hardware
"ISI cancellation" based equalization is conceptually more
straightforward but suffers from SNR penalty or error propagation
Jitter Amplification
by Passive Channels
Enhancing
Resolution with a \(\Delta \Sigma\)
Modulator
Sub-Resolution Time Averaging
\(\Delta \Sigma\) modulator
effectively dithers the LSB bit
between zero and one, such that you can get the effective
resolution of a much higher resolution DAC in the number of bits
Decimation
how they affect sampling phase
DLF's input bit-width can be reduced by decimating BBPD's
output. Decimation is typically performed by realizing either
majority voting (MV) or boxcar
filtering.
Note that deserialization is inherent to both
MV and boxcar filtering
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it down
Decimating by \(L\) means frequency
register only added once every \(L\)
UI, thus integral path gain reduced by \(L\) in linear model
proportional path gain is unchanged
CDR Linear Model
condition:
Linear model of the CDR is used in a frequency lock
condition and is approaching to achieve phase
lock
Using this model, the power spectral density (PSD) of jitter in the
recovered clock \(S_{out}(f)\) is \[
S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f)
\] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they
come from independent sources.
Using below notation \[\begin{align}
\omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\
\xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2}
\end{align}\]
We can rewrite transfer function as follows \[
H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2}
\]
The jitter transfer represents a low-pass filter
whose magnitude is around 1 (0 dB) for low jitter frequencies and drops
at 20 dB/decade for frequencies above \(\omega_n\)
the recovered clock track the low-frequency
jitter of the input data
the recovered clock DONT track the
high-frequency jitter of the input data
The recovered clock does not suffer from high-frequency jitter even
though the input signal may contain high-frequency jitter, which will
limit the CDR tolerance to high-frequency jitter.
Jitter Peaking in
Jitter Transfer Function
The peak, slightly larger than 1 (0dB) implies that jitter will be
amplified at some frequencies in the CDR, producing a
jitter amplitude in the recovered clock, and thus also in the recovered
data, that is slightly larger than the jitter amplitude
in the input data.
This is certainly undesirable, especially in applications such as
repeaters.
Jitter Generation
If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the
recovered clock comes directly from the VCO jitter. The transfer
function that relates the VCO jitter to the recovered clock jitter is
known as jitter generation. \[
H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi
\omega_n s+\omega_n^2}
\] Jitter generation is high-pass filter with
two zeros, at zero frequency, and two poles identical to those of the
jitter transfer function
Jitter Tolerance (JTOL)
To quantify jitter tolerance, we often apply a sinusoidal jitter of a
fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR's true
tolerance to random jitter. Because we are applying
"sinusoidal" jitter, which is deterministic signal.
We can deal only with the jitter's amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
\[
JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad
\text{for a fixed BER}
\] Where the subscript \(\text{pp-max}\) indicates the
maximum peak-to-peak amplitude. We can further expand
this equation as follows \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_\text{pp-max}
\]
Relative jitter, \(\varphi_e\) must
be less than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude
of \(|\varphi_e(f)|\) is
1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
\] Given the linear CDR model, we can write \[
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
\] Expand \(H_{LF}(f)\) for the
CDR, we can write \[
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
\] At frequencies far below and above the natural frequency, the
jitter tolerance can be approximated by the following \[
JTOL(f) = \left\{ \begin{array}{cl}
\left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\
1 & : \ f\gg f_n
\end{array} \right.
\]
the jitter tolerance at very high jitter frequencies
is limited to 1UIpp
1 2 3 4 5 6 7 8 9 10 11 12 13 14
clc; clear all;
f_fn = logspace(-1, 2, 60); for xi = [2, 1, 0.5, 0.2] jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2); loglog(f_fn, jtol,LineWidth=2) disp(["min(JTpp)=", min(jtol),"@\xi=",xi]) hold on end grid on; xlabel("f/f_n") ylabel('JT_{pp}') legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')
JTF, by jitter frequency, compares how much input signal jitter is
transferred to the output of a clock-recovery's PLL (recovered
clock)
Input signal jitter that is within the clock recovery PLL's loop
bandwidth results in jitter that is faithfully transferred (closed-loop
gain) to the clock recovery PLL's output signal. JTF in this situation
is approximately 1.
Input signal jitter that is outside the clock recovery PLL's loop
bandwidth results in decreasing jitter (open-loop gain) on the clock
recovery PLL's output, because the jitter is filtered out and no longer
reaches the PLL's VCO
Observed Jitter Transfer Function
Input Signal Versus Sampled Signal
OJTF compares how much input signal jitter is transferred to the
output of a receiver's decision making circuit as
effected by a clock recovery's PLL. As the recovered clock is the
reference for detecting the input signal
Input signal jitter that is within the clock
recovery PLL's loop bandwidth results in jitter on the recovered clock
which reduces the amount of jitter that can be detected. The input
signal and clock signal are closer in phase
Input signal jitter that is outside the clock
recovery PLL's loop bandwidth results in reduced jitter on the
recovered clock which increases the amount of jitter that can
be detected. The input signal and clock signal are more out of phase.
Jitter that is on both the input and clock signals can not detected or
is reduced
JTF and OJTF for 1st Order PLLs
The observed jitter is a complement to the PLL jitter transfer
response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not
observed at the output of the CDR as a function of the jitter rate
applied to the input.
The combination of the OJTF of a jitter measurement device and the
JTF of the clock generator under test gives the measured jitter as a
function of frequency.
For example, a clock generator with a type 1, 1st order PLL measured
with a jitter measurement device employing a golden PLL is \[
J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2}
\]
Accurate measurement of the clock JTF requires that the OJTF cutoff
of the jitter measurement be significantly below that of the clock JTF
and that the measurement is compensated for the instrument's OJTF.
The overall response is a band pass filter because the clock JTF is
low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring
the jitter of the reference clock at each jitter rate being tested and
comparing the reference jitter with the jitter
measured at the output of the DUT.
The lower the cutoff frequency of the jitter measurement device the
better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the
phase noise of the DUT and measurement time.
Digital Sampling
Oscilloscope
How to analyze jitter:
TIE (Time Interval Error) track
histogram
FFT
TIE track provides a direct view of how the phase of
the clock evolves over time.
histogram provides valuable information about the
long term variations in the timing.
FFT allows jitter at specific rates to be measured
down to the femto-second range.
Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop
bandwidth minimizes the response error
reference
Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and
Phase Noise: A Circuits and Systems Perspective.” (2018).
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
AFE Nonlinearity
"total harmonic distortion" (THD) in
AFE
Relative to NRZ-based systems, PAM4 transceivers require more
stringent circuit linearity, equalizers which can implement multi-level
inter-symbol interference (ISI) cancellation, and improved
sensitivity
Because if it compresses, it turns out you have to use a much more
complicated feedback filter. As long as it behaves linearly,
the feedback filter itself can remain a linear FIR
Linearity can actually be a critical constraint in these signal
paths, and you really want to stay as linear as you can all the way up
until the point where you've canceled all of the ISI
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline
Receivers"
BER with Quantization Noise
\[
\text{Var}(X) = E[X^2] - E[X]^2
\]
Impulse Response or Pulse
Response
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline
Links-Part II: Optimization and Performance Assessment," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024
[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in
Serial Data Transmission Systems,” in Phase-Locking in High-Performance
Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]
Da Dalt N. A design-oriented study of the nonlinear dynamics of
digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I:
Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]
Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop
gain tracking all-digital PLL using autocorrelation of bang–bang phase
frequency detection. IEEE Transactions on Circuits and Systems II:
Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]
CDR Loop Latency
Denoting the CDR loop latency by \(\Delta
T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The
resulting right-half-plane zero, \(f_z\) degrades the phase margin and must
remain about one decade beyond the BW\[
f_z\simeq \frac{1}{2\pi \Delta T}
\]
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of
Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
limit cycles imply self-sustained oscillators due nonlinear
nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC
LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van
Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design.
Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]
Digital CDR Category
DCO part is analogous so that it cannot be perfectly
modeled
Digital-to-phase converter is well-defined phase output, thus, very
good to model real situation
Z-domain modeling
The difference equation is \[
\phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi
\] z-transform is \[
\frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}}
\]
where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)
\(\Delta
\Sigma\)-dithering in DCO
Quantization noise
Here, \(\alpha_T\) is data
transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang
Controlled Timing Circuits," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
Time to Digital Converter
(TDC)
Digital to Phase Converter
(DPC)
IIR low pass filter
simple approximation: \[
z = 1 + sT
\] bilinear-z transform \[
z =\frac{}{}
\]
Accumulate-and-dump (AAD)
decimator
accumulating the input for \(N\)
cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input
samples at rate \(1/T\) and delivers
their sum in a single sample at the output. Therefore, the
process comprises a filter (in the accumulation) and a
down-sampler (in the dump)
Moving Average and CIC
Filters
cascade-integrator-comb (CIC) decimator
TODO 📅
An Intuitive Look at Moving Average and CIC Filters [web,
code]
Phase detecting possible , Frequency detecting impossible
PLL or FD(Frequency Detector) for frequency detecting in CDR
reference
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and
Circuits" [slides]
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems
(lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT
OpenCourseWare, [lec21.pdf]
Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental
Concepts To Future Trends" [T5.pdf]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
—, "A digital clock and data recovery architecture for
multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom
Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
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Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE
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We typically use the two spectra, \(S_{\phi
n}(f)\) and \(S_{out}(f)\),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal \(x(t)\) can be
expanded in Fourier series as:
Assume that the signal is subject to excess phase noise,
which is modeled by adding a time-dependent noise
component \(\alpha(t)\). The noisy
signal can be written \(x(t+\alpha(t))\), the added excess phase
\(\phi(t)=
\frac{\alpha(t)}{\omega_0}\)
The autocorrelation of the noisy signal is by definition:
The autocorrelation averaged over time results in:
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal \(x(t + \alpha(t))\) can
be expressed as
It is also interesting to note how the integral in Equation
9.80 around each harmonic is equal to the power of the harmonic
itself \(|X_n|^2\)
The integral \(S_x(f)\) around
harmonic is \[\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}\]
The phase noise does not affect the total power in the
signal, it only affects its distribution
Without phase noise, \(S_v(f)\) is
a series of impulse functions at the harmonics of \(f_o\).
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
Phase
perturbed by a stationary noise with Gaussian PDF
If keep \(\phi_{rms}\) in \(R_x(\tau)\), i.e. \[
R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)(1+R_\phi(\tau))
\] The PSD of the signal is \[
S_x(f) = \mathcal{F} \{ R_x(\tau) \} =
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] +
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right]
\] ❗❗above Eq isn't consistent with stationary
white noise process - the following section
Phase
perturbed by a stationary WHITE noise process
Assuming that the delay line is noiseless
Expanding the cosine function we get \[\begin{align}
R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi
f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi
f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\
&+ \frac{A^2}{2}\left\{\cos(4\pi
f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi
f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\}
\end{align}\]
where, both the process \(\phi(t)-\phi(t-\tau)\) and \(\phi(t)+\phi(t-\tau)\) are independent of
time \(t\), i.e. \(E[\cos(\phi(t)+\phi(t-\tau))] =
m_{\cos+}(\tau)\), \(E[\cos(\phi(t)-\phi(t-\tau))] =
m_{\cos-}(\tau)\), \(E[\sin(\phi(t)+\phi(t-\tau))] =
m_{\sin+}(\tau)\) and \(E[\sin(\phi(t)-\phi(t-\tau))] =
m_{\sin-}(\tau)\)
The second term in the above expression is periodic in \(t\) and to estimate its PSD, we compute the
time-averaged autocorrelation function\[
R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) -
\sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\}
\]
After nontrivial derivation
Phase perturbed by a Weiner
process
The phase process \(\phi(t)\) is
also gaussian but with an increasing variance which
grows linearly with time\(t\)
The spectrum of \(y(t)\) is
determined by the asymptotic behavior of \(R_y(t,\tau)\) as \(t\to \infty\)
❗❗ \(\lim_{t\to\infty}R_y(t,\tau)\) rather than
time-averaged autocorrelation function of cyclostationary
process, ref. Demir's paper
We define \(\zeta(t,
\tau)=\phi(t)+\phi(t-\tau) = \phi(t)-\phi(t-\tau) +
2\phi(t-\tau)\), the expected value of \(\zeta(t,\tau)\) is 0, the variance is \(\sigma_{\zeta}^2=(k\sigma)^2(\tau +
4(t-\tau))=(k\sigma)^2(4t-3\tau)\)\[
E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta
= e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)}
\] i.e., \(\lim _{t\to \infty}
E[\cos(\zeta(t,\tau))] = \lim_{t\to \infty}e^{-(k\sigma)^2(4t-\tau)} =
0\)
For \(E[\sin(\zeta(t,\tau))]\), we
have \[
E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta
\] i.e., \(E[\sin(\zeta(t,\tau))]\) is odd
function, therefore \(E[\sin(\zeta(t,\tau))]=0\)
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[slides]
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Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
proportional term (P) depends on the present error
integral term (I) depends on past errors
derivative term (D) depends on anticipated future errors
PID controller makes use of linear extrapolation of
the measured output
PI controller does not make use of any prediction of
the future state of the system
The prediction by linear extrapolation (D) can generate large
undesired control signals because measurement noise is amplified, that's
why D is not used widely
charge pumps are capacitive
DC-DC converters. The two most common switched capacitor
voltage converters are the voltage inverter and the
voltage doubler circuit
We derive a recursive equation that describes the output voltage
\(V_{out,n}\) after the \(n\)th clock cycle \[
V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o}
\]
Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is
\[
\overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} -
\frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right)
\approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p}
\] which results in a simple expression for the output
voltage droop
\[
\Delta V_{out} = \frac{I_{load}}{f_{sw}C_p}
\]
The charge pump can be modeled as a voltage source with a
source resistance\(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage
drop across \(R_\text{out}\) due to the
load current:
Fourier transform of the output of the expander is a frequency-scaled
version of the Fourier transform of the input
Subsampling or Downsampling
Eqs. (4.72)
the superposition of an infinite set of amplitude-scaled copies of
\(X_c(j\Omega)\), frequency scaled
through \(\omega = \Omega T_d\) and
shifted by integer multiples of \(2\pi\)
Eq. (4.77)
the superposition of \(M\)
amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by
\(M\) and shifted by integer multiples
of \(2\pi\)
downsampled by a factor of \(M =
2\)
Upsampling or Zero Insertion
Assuming \(X(e^{j\omega_1}) =
U_f(e^{j\omega_1})\) with \(\omega_1 =
\Omega T_1\), upsampled by ratio \(L\), then obtain
Polyphase decomposition is a powerful technique used in digital
signal processing to efficiently implement multirate systems.
where \(e_k[n]=h[nM+k]\)
Polyphase Implementation of Decimation Filters &
Interpolation Filters
Decimation system
Interpolation system
sampling identity
LPTV Implementation
TODO 📅
The interpolation filter following an up-sampler
generally is time varying and cannot be represented by
a simple transfer function. The equivalent filter in a
zero-order hold is an exception, perhaps unique, that
can be represented with a time-invariant transfer function
The interpolation filter following an up-sampler generally is
time varying and cannot be represented by a simple
transfer function. The equivalent filter in a Zero-Order
Hold is an exception, perhaps unique, that can be represented
with a time-invariant transfer function
Split the \(1:LM\) hold process into
a \(1 : L\) hold followed by a \(1 : M\) hold \[
Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}}
\] then \[\begin{align}
F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\
&=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}}
\\
&= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
\end{align}\]
That is \(F_1(z)=F_2(z)\), i.e. they
are equivalent
In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is
\[
LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}}
\]
In (b),
Accumulate-And-Dump
(AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[
\phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}
\] Hence \[\begin{align}
\phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\
&= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot
\frac{1}{1-\eta^{-1}}
\end{align}\]
After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align}
\phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\
&=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}}
\end{align}\] i.e., \[
LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1-z^{-L}}{1-z^{-1}}
\]
When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx
1\)
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