Bogatin, E. (2018). Signal and power integrity, simplified.
Prentice Hall. [pdf]
Paul, Clayton R. Inductance: Loop and Partial. Hoboken, N.J.
: [Piscataway, N.J.]: Wiley ; IEEE, 2010. [pdf]
Spartaco Caniggia. Signal Integrity and Radiated Emission of
High‐Speed Digital Systems. Wiley 2008
ISSCC2002. Special Topic Evening Discussion Sessions SE1: Inductance:
Implications and Solutions for High-Speed Digital Circuits [vSE1_Blaauw],
[vSE1_Gauthier],
[vSE1_Morton,
[vSE1_Restle]]
Y. Massoud and Y. Ismail, "Gasping the impact of on-chip inductance,"
in IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14-21, July
2001 [https://sci-hub.se/10.1109/101.950046]
magnetic field (magnetic flux density, \(B\)), is the tesla
(symbol: \(T\)), defined as one
weber per square meter (\(Wb/m^2\))
Magnetic flux \(\Phi_B\) measures
the total magnetic field (\(B\))
passing through a given surface area (\(A\)), representing the number of field
lines penetrating that area. Measured in Webers (\(Wb\)),
Vector Calculus
3Blue1Brown, Divergence and curl: The language of Maxwell's
equations, fluid flow, and more [https://youtu.be/rB83DpBJQsE]
A. Sheikholeslami, "Current Without Electrons [Circuit Intuitions],"
in IEEE Solid-State Circuits Magazine, vol. 17, no. 4, pp. 8-10, Fall
2025
—, "Current Without Electric Field [Circuit Intuitions]," in IEEE
Solid-State Circuits Magazine, vol. 18, no. 1, pp. 8-12, winter
2026
energy and information are carried by electric and magnetic fields
(\(E\) and \(H\)) rather than by electron drift
proximity effect & skin
effect
Skin effect concentrates current near the
surface of a single conductor, while
proximity effect concentrates current in specific
regions of multiple conductors due to their
interaction
Skin effect is caused by the conductor's
own magnetic field, while proximity effect is
caused by the magnetic field of a nearby
conductor
proximity effect is a redistribution of
electric current occurring in nearby parallel
electrical conductors carrying alternating current
(AC), caused by magnetic effects (eddy
currents)
skin effect is the tendency of
AC current flow near the surface (or "skin")
of a conductor, rather than throughout its cross-section, due to the
magnetic field generated by the current
itself
Cause of skin effect
A main current \(I\) flowing through
a conductor induces a magnetic field \(H\). If the current increases, as in this
figure, the resulting increase in \(H\)
induces separate, circulating eddy currents\(I_W\) which partially cancel the
current flow in the center and reinforce it near the skin
Eddy current
By Lenz's
law, an eddy current creates a magnetic field that
opposes the change in the magnetic field that
created it, and thus eddy currents react back
on the source of the magnetic field
Due to not taking loading \(C_2\)
into account, actual switched-capacitor filter deviate from equivalent
\(R_{SC}\) + \(C_2\) low pass filter as \(f_p\) approaching to \(f_s\)
Given \(\color{red}T_p = T_s\)\[
H_\mathrm{SH}(f) \approx
\mathrm{sinc}\left( \frac{f}{f_s} \right)e^{-j\pi f T_s}
\]
\[
h_{ZOH}(t) = \text{rect}(\frac{t}{T} - \frac{1}{2}) = \left\{
\begin{array}{cl}
1 & : \ 0 \leq t \lt T \\
0 & : \ \text{otherwise}
\end{array} \right.
\] The effective frequency response is the continuous Fourier
transform of the impulse response \[
H_{ZOH}(f) = \mathcal{F}\{h_{ZOH}(t)\} = T\frac{1-e^{j2\pi fT}}{j2\pi
fT}=Te^{-j\pi fT}\text{sinc}(fT)
\] where \(\text{sinc}(x)\) is
the normalized sinc function \(\frac{\sin(\pi
x)}{\pi x}\)
The Laplace transform transfer function of the ZOH is found by
substituting \(s=j2\pi f\)\[
H_{ZOH}(s) = \mathcal{L}\{h_{ZOH}(t)\}=\frac{1-e^{-sT}}{s}
\]
Carlo Samori ISSCC2016 T1: Understanding Phase Noise in LC VCOs
Leeson's limitations
Hajimiri's Model- LTV ISF
ISF model
C. Livanelioglu, L. He, J. Gong, S. Arjmandpour, G. Atzeni and T.
Jang, "19.10 A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned
Pulse-Injection Driver Achieving −255.2dB FoMJ Including the XO Power
and Noise," 2025 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2025
If \(m=0\)\[
\phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\] If \(m\neq 0\) and \(m=n\)\[
\phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta
\omega}\sin(\Delta\omega t)
\]
\(m\omega_0 +\Delta \omega \ge
0\)
A. Hajimiri and T. H. Lee, "A general theory of phase noise in
electrical oscillators," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [pdf]
Corrections to "A General Theory of Phase Noise in
Electrical Oscillators"
A. Hajimiri and T. H. Lee, "Corrections to "A General Theory of Phase
Noise in Electrical Oscillators"," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 6, pp. 928-928, June 1998 [https://sci-hub.se/10.1109/4.678662]
L. Lu, Z. Tang, P. Andreani, A. Mazzanti and A. Hajimiri, "Comments
on “Comments on “A General Theory of Phase Noise in Electrical
Oscillators””," in IEEE Journal of Solid-State Circuits, vol.
43, no. 9, pp. 2170-2170, Sept. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005028]
Given \(i(t) = I_m \cos[(m\omega_0 - \Delta
\omega)t]\) and \(m \ge 1\)
Hu, Yizhe. (2019). A Simulation Technique of Impulse Sensitivity
Function (ISF) Based on Periodic Transfer Function (PXF).
10.13140/RG.2.2.32151.60323. [link]
To compare the ring oscillator and VCO the total injected
charge to both should be the same
Demir's Model - NLTV PPV
PPV (Perturbation Projection
Vector)
A. Demir and J. Roychowdhury, "A reliable and efficient procedure for
oscillator PPV computation, with phase noise macromodeling
applications," in IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 22, no. 2, pp. 188-197, Feb.
2003 [https://sci-hub.se/10.1109/TCAD.2002.806599]
Y. Hu, T. Siriburanon and R. B. Staszewski, "Intuitive Understanding
of Flicker Noise Reduction via Narrowing of Conduction Angle in
Voltage-Biased Oscillators," in IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019
[https://sci-hub.se/10.1109/TCSII.2019.2896483]
S. Levantino, P. Maffezzoni, F. Pepe, A. Bonfanti, C. Samori and A.
L. Lacaita, "Efficient Calculation of the Impulse Sensitivity Function
in Oscillators," in IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 59, no. 10, pp. 628-632, Oct. 2012 [https://sci-hub.se/10.1109/TCSII.2012.2208679]
S. Levantino and P. Maffezzoni, "Computing the Perturbation
Projection Vector of Oscillators via Frequency Domain Analysis," in IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 31, no. 10, pp. 1499-1507, Oct. 2012 [https://sci-hub.se/10.1109/TCAD.2012.2194493]
Y. Hu, T. Siriburanon and R. B. Staszewski, "Oscillator Flicker Phase
Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468]
A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in
oscillators: a unifying theory and numerical methods for
characterization," in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.se/10.1109/81.847872]
—. "Harmonic Oscillators in CMOS—A Tutorial Overview," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021 [pdf]
C. Samori, "Tutorial: Understanding Phase Noise in LC VCOs," 2016
IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2016
—, "Understanding Phase Noise in LC VCOs: A Key Problem in RF
Integrated Circuits," in IEEE Solid-State Circuits Magazine,
vol. 8, no. 4, pp. 81-91, Fall 2016 [https://sci-hub.se/10.1109/MSSC.2016.2573979]
Jun Yin. ISSCC 2025 T10: mm-Wave Oscillator Design
Hegazi, Emad, Asad Abidi, and Jacob Rael. The Designer's Guide to
High-purity Oscillators. [New York]: Kluwer Academic Publishers,
2005. The Designer's Guide to High-Purity Oscillators [pdf]
A conventional inverter-based ring oscillator consists of a single
loop of an odd number of inverters. While compact, easy
to design and tunable over a wide frequency range, this oscillator
suffers from several limitations.
it is not possible to increase the number of phases while
maintaining the same oscillation frequency since the frequency is
inversely proportional to the number of inverters in the loop. In other
words, the time resolution of the oscillator is limited to one inverter
delay and cannot be improved below this limit.
the number of phases that can be obtained from this oscillator is
limited to odd values. Otherwise, if an even number of
inverters is used, the circuit remains in a latched state and
does not oscillate.
To overcome the limitations of conventional ring oscillators,
multi-paths ring oscillator (MPRO) is proposed. Each phase can be driven
by two or more inverters, or multi-paths instead of having each
phase in oscillator driven by a single inverter, or single
path.
One thing that makes the MPRO design problem even more complicated is
its property of having multiple possible oscillation
modes. Without a clear understanding of what makes one of these
modes dominant, it is very likely that a designer might end-up having an
oscillator that can start-up each time in a different oscillation mode
depending on the initial state of the oscillator.
In practive, the oscillator starts first from a linear mode of
operation where all the buffers are indeed acting as linear
transconductors. All oscillation modes that have mode gains, \(a_n\), lower than the actual dc gain of the
inverter, \(a_0\), start to grow.
As the oscillation amplitude grows, the effective gain of the
inverter drops due to nonlinearity. Consequently, modes with higher
mode gain die out and only the mode that requires the minimum gain
continues to oscillate and hence is the dominant mode.
The dominant mode is dependent only on the relative sizing vector
maximum oscillation
frequency
The oscillation frequency of the dominant mode of any MPRO having any
arbitrary coupling structure and number of phases is \[
f_{n^*} = \frac {1}{2\pi}\frac {(a_0-1) \cdot \sum_{i=1}^{N}x_isin\left
( \frac {2\pi n^*(i-1)}{N} \right)}{(a_0\tau _p - \tau _o)\cdot
\sum_{i=1}^{N}-x_icos\left( \frac{2\pi n^*(i-1)}{N}+(\tau _o - \tau _p)
\right)}
\]
A linear increase in the maximum possible normalized
oscillation frequency as the number of stages increases provided
that the dc gain of the buffer sufficient to provide the required
amplification
assuming unlimited dc gain and zero mode gain margins
mode stability
A common problem in MPRO design is the stability of the dominant
oscillation mode. Mode stability refers to whether the MPRO always
oscillates at the same mode regardless of the initial conditions of the
oscillator. This problem is especially pronounced for MPROs with a large
number of phases. This is due to the existence of many modes and the
very small differences in the value of the mode gain of adjacent modes
if the MPRO is not well designed.
In general, when the mode gain difference between two modes is small,
the oscillator can operate in either one depending on initial
conditions.
coupling
configurations and simulation results
Abou-El-Sonoun, A. A. (2012). High Frequency Multiphase Clock
Generation Using Multipath Oscillators and Applications. UCLA.
ProQuest ID: AbouElSonoun_ucla_0031D_10684. Merritt ID:
ark:/13030/m57p9288. Retrieved from
https://escholarship.org/uc/item/75g8j8jt
frequency stability
A problem associated with the design of MPROs is the existence of
different possible modes of oscillation. Each of these modes is
characterized by a different frequency, phase shift and phase noise.
Linear delay-stage model
(mode gain)
mode gain is based on the linear model, independent
of process but depends on coupling structure (coupling configuration,
size ratio).
The inverting buffer modeled as a linear transconductor. The
input-output relationship of a single buffer scaled by \(h_i\) and driving the input capacitance of
a similar buffer can be expressed as \[\begin{align}
h_ig_mv_{in}(t) + h_ig_oV_{out}(t)+h_iC_g\frac {dV_{out}(t)}{dt} &=
0 \\
a_nV_{in}(t)+V_{out}(t)+\tau \frac {V_{out}(t)}{dt} &= 0
\end{align}\] where \(g_m\) is
the transconductance, \(g_o\) is the
output conductance, \(C_g\) is the
buffer input capacitance which also acts as the load capacitance for the
driving buffer, and \(a_n = \frac
{g_m}{g_o}\) is the linear dc gain of the
buffer, and \(\tau=\frac {C_g}{g_o}\)
is a time constant.
Similarly, \(V_1\), the output of
the first stage in MPRO can be expressed \[
\sum_{i=1}^{N}h_ig_mV_i(t)+\sum_{i=1}^{N}h_ig_oV_i(t)+\sum_{i=1}^{N}h_iC_g\frac
{dV_it(t)}{dt} = 0
\] Defining the fractional sizing factors and the total sizing
factor as \(x_i=\frac{h_i}{H}\) and
\(H=\sum_{i=1}^{N}h_i\)\[
a_n\sum_{i=1}^{N}x_iV_i(t) + V_1(t)+\tau\frac {dV_i(t)}{dt} = 0
\] where \(a_n = \frac
{g_m}{g_o}\) and \(\tau=\frac
{C_g}{g_o}\) are same dc gain and time constant defined
previously
Since the total phase shift around the loop should be multiples of
\(2\pi\), the oscillation waveform at
the ith node can be expressed as \[
V_i(t) = V_o \cos(\omega_nt-\Delta \varphi \cdot i)
\] where \(\omega_n\) is the
oscillation frequency and \(\Delta \varphi =
\frac {2\pi n}{N}\), \(N\) is
the number of stages in the oscillator and \(n\) can take values between \(0\) and \(N-1\)
Plug \(V_i(t)\) into differential
equation, we get \[
a_n\sum_{i=1}^{N}x_i\cos(\omega_n t-\frac{2\pi n}{N}i)+\cos(\omega_n
t-\frac{2\pi n}{N}) - \omega_n \tau \sin(\omega_n t-\frac{2\pi n}{N}) =
0
\] By equating the \(cos(\omega_n
t)\) and \(sin(\omega_n t)\)
terms of the above equation, we get expressions for the
oscillation frequency of the nth mode and the
minimum dc gain required for this mode to exist. we refer to
this gain as the mode gain\[\begin{align}
\omega_n\tau &= \frac {\sum_{i=1}^{N}x_i \cdot \sin(\frac{2\pi
n}{N}(i-1))}{-\sum_{i=1}^{N}x_i \cdot \cos(\frac{2\pi n}{N}(i-1))} \\
a_n &= \frac {1}{-\sum_{i=1}^{N}x_i \cdot \cos(\frac{2\pi
n}{N}(i-1))}
\end{align}\] where \(a_n\)
should be greater than \(0\) for a
existent mode
In practice, the oscillator starts first from a linear mode of
operation where all the buffers are indeed acting as linear
transconductors. All oscillation modes that have mode gains \(a_n\) lower than the actual dc gain of the
inverter \(a_o\) start to grow. As the
oscillation amplitude grows, the effective gain of the inverter drops
due to nonlinearity. Consequently, modes with higher mode gain die
out and only the mode that requires the minimum gain continues to
oscillate and hence is the dominant mode
A. A. Hafez and C. K. Yang, "Design and Optimization of Multipath
Ring Oscillators," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 58, no. 10, pp. 2332-2345, Oct. 2011, doi:
10.1109/TCSI.2011.2142810.
Simulation-based approach
GCHECK is an automated verification tool that
validate whether a ring oscillator always converges to the desired mode
of operation regardless of the initial conditions and
variability conditions. This is the first tool ever
reported to address the global convergence failures in presence of
variability. It has been shown that the tool can successfully validate a
number of coupled ring oscillator circuits with various global
convergence failure modes (e.g. no oscillation, false oscillation, and
even chaotic oscillation) with reasonable computational costs such as
running 1000-point Monte-Carlo simulations for 7~60 initial conditions
(maximum 4 hours).
The verification is performed using a predictive global
optimization algorithm that looks for a problematic initial
state from a discretized state space
despite the finite number of initial state
candidates considered and finite number of Monte-Carlo
samples to model variability, the proposed algorithm can verify
the oscillator to a prescribed confidence level
The observation that the responses of a circuit with nearby initial
conditions are strongly correlated with respect to common variability
conditions enables us to explore a discretized version
of the initial condition space instead of the continuous one.
the settling time increases as the initial state gets farther away
from the equilibrium state allowed us to use the settling time as a
guidance metric to find a problematic initial condition.
Selecting the Next Initial Condition Candidate to
Evaluate
To determine whether the algorithm should continue or terminate the
search for a new maximum, the algorithm estimates the probability of
finding a new initial condition with the longer settling
time, based on the information obtained with the
previously-evaluated initial conditions.
GCHECK EXAMPLE
1
python gcheck_osc.py input.scs
output log:
1 2 3 4 5 6 7 8
Step 1/4: Simulating the setting-time distribution with the reference initial condition ... Step 2/4: Simulating the setting-time distribution for randomly-selected initial probes ... Step 3/4: Searching for Problematic Initial Conditions ... Step 4/4: Reporting Verification Results and Statistics ...
T. Kim, D. -G. Song, S. Youn, J. Park, H. Park and J. Kim, "Verifying
start-up failures in coupled ring oscillators in presence of variability
using predictive global optimization," 2013 IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), 2013, pp. 486-493 GCHECK:
Global Convergence Checker for
Oscillators](https://mics.snu.ac.kr/wiki/GCHECK)
Mathuranathan, Line code – demonstration in Matlab and Python [link]
For unipolar NRZ line coded signal, the average value of the
signal is not zero and hence they have a significant DC
component
The DC impulses in the PSD do not carry any information and it also
causes the transmission wires to heat up. This is a wastage of
communication resource
The bipolar NRZ signal is devoid of a significant impulse at the
zero frequency (DC component is very close to zero)
Furthermore, it has more power than the unipolar line code (note: PSD
curve for bipolar NRZ is slightly higher compared to that of unipolar
NRZ). Therefore, bipolar NRZ signals provide better signal-to-noise
ratio (SNR) at the receiver.
Both Unipolar and Bipolar NRZ signal lacks embedded clock
information, which posses synchronization problems at the receiver when
the binary information has long runs of 0s and 1s
Baseline Wander
David A. Johns, ECE1392H - Integrated Circuits for Digital
Communications - Fall 2001 [Equalization]
Then rise time of 20% to 80% is \[
T_{r} = \tau_{RC}\cdot \ln\frac{0.8}{0.2} = 1.3863 \cdot \tau_{RC}
\] we have \[
f_{3dB} = \frac{1}{2\pi}\frac{1}{\tau_{RC}} = \frac{1}{2\pi}\frac{
1.3863}{T_r} = \frac{0.22}{T_r}
\]
Since we have (ideally) no return current, the ground
reference becomes less important. The ground potential can
even be different at the sender and receiver or moving around within a
certain acceptable range. However, you need to be careful because
DC-coupled differential signaling (such as USB, RS-485, CAN) generally
requires a shared ground potential to ensure that the signals stay
within the interface's maximum and minimum allowable common-mode
voltage.
Corresponding to the three distinct voltage thresholds in the
PAM4 systems, it would need 12 slicers, 3
multiplexers, and one thermometer-to-binary decoder in
each deserialized data path, even if only one tap of the DFE is
unrolled
Look-Ahead Multiplexing DFE
The look-ahead multiplexing technique brings the key benefit that the
timing constraint can be significantly relaxed, as the iteration bound
is doubled at the expense of extra
hardware
Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity
Technologies to Accelerate AI
Jitter Performance
Limitations
Aliasing of baud-rate
sampling
The most significant impairments are considered to be the sensitivity
to sampling phase, and the effect of aliasing out of band signal and
noise into the baseband
D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J.
Savory, "A baud-rate sampled coherent transceiver with digital pulse
shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]
Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end
Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]
Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for
High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]
"ISI cancellation" based equalization is conceptually more
straightforward but suffers from SNR penalty or error propagation
Jitter Amplification
by Passive Channels
Enhancing
Resolution with a \(\Delta \Sigma\)
Modulator
Sub-Resolution Time Averaging
\(\Delta \Sigma\) modulator
effectively dithers the LSB bit
between zero and one, such that you can get the effective
resolution of a much higher resolution DAC in the number of bits
Decimation
how they affect sampling phase
DLF's input bit-width can be reduced by decimating BBPD's
output. Decimation is typically performed by realizing either
majority voting (MV) or boxcar
filtering.
Note that deserialization is inherent to both
MV and boxcar filtering
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it down
Decimating by \(L\) means frequency
register only added once every \(L\)
UI, thus integral path gain reduced by \(L\) in linear model
proportional path gain is unchanged
CDR Linear Model
condition:
Linear model of the CDR is used in a frequency lock
condition and is approaching to achieve phase
lock
Using this model, the power spectral density (PSD) of jitter in the
recovered clock \(S_{out}(f)\) is \[
S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f)
\] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they
come from independent sources.
Using below notation \[\begin{align}
\omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\
\xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2}
\end{align}\]
We can rewrite transfer function as follows \[
H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2}
\]
The jitter transfer represents a low-pass filter
whose magnitude is around 1 (0 dB) for low jitter frequencies and drops
at 20 dB/decade for frequencies above \(\omega_n\)
the recovered clock track the low-frequency
jitter of the input data
the recovered clock DONT track the
high-frequency jitter of the input data
The recovered clock does not suffer from high-frequency jitter even
though the input signal may contain high-frequency jitter, which will
limit the CDR tolerance to high-frequency jitter.
Jitter Peaking in
Jitter Transfer Function
The peak, slightly larger than 1 (0dB) implies that jitter will be
amplified at some frequencies in the CDR, producing a
jitter amplitude in the recovered clock, and thus also in the recovered
data, that is slightly larger than the jitter amplitude
in the input data.
This is certainly undesirable, especially in applications such as
repeaters.
Jitter Generation
If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the
recovered clock comes directly from the VCO jitter. The transfer
function that relates the VCO jitter to the recovered clock jitter is
known as jitter generation. \[
H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi
\omega_n s+\omega_n^2}
\] Jitter generation is high-pass filter with
two zeros, at zero frequency, and two poles identical to those of the
jitter transfer function
Jitter Tolerance (JTOL)
To quantify jitter tolerance, we often apply a sinusoidal jitter of a
fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR's true
tolerance to random jitter. Because we are applying
"sinusoidal" jitter, which is deterministic signal.
We can deal only with the jitter's amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
\[
JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad
\text{for a fixed BER}
\] Where the subscript \(\text{pp-max}\) indicates the
maximum peak-to-peak amplitude. We can further expand
this equation as follows \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_\text{pp-max}
\]
Relative jitter, \(\varphi_e\) must
be less than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude
of \(|\varphi_e(f)|\) is
1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
\] Given the linear CDR model, we can write \[
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
\] Expand \(H_{LF}(f)\) for the
CDR, we can write \[
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
\] At frequencies far below and above the natural frequency, the
jitter tolerance can be approximated by the following \[
JTOL(f) = \left\{ \begin{array}{cl}
\left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\
1 & : \ f\gg f_n
\end{array} \right.
\]
the jitter tolerance at very high jitter frequencies
is limited to 1UIpp
1 2 3 4 5 6 7 8 9 10 11 12 13 14
clc; clear all;
f_fn = logspace(-1, 2, 60); for xi = [2, 1, 0.5, 0.2] jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2); loglog(f_fn, jtol,LineWidth=2) disp(["min(JTpp)=", min(jtol),"@\xi=",xi]) hold on end grid on; xlabel("f/f_n") ylabel('JT_{pp}') legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')
JTF, by jitter frequency, compares how much input signal jitter is
transferred to the output of a clock-recovery's PLL (recovered
clock)
Input signal jitter that is within the clock recovery PLL's loop
bandwidth results in jitter that is faithfully transferred (closed-loop
gain) to the clock recovery PLL's output signal. JTF in this situation
is approximately 1.
Input signal jitter that is outside the clock recovery PLL's loop
bandwidth results in decreasing jitter (open-loop gain) on the clock
recovery PLL's output, because the jitter is filtered out and no longer
reaches the PLL's VCO
Observed Jitter Transfer Function
Input Signal Versus Sampled Signal
OJTF compares how much input signal jitter is transferred to the
output of a receiver's decision making circuit as
effected by a clock recovery's PLL. As the recovered clock is the
reference for detecting the input signal
Input signal jitter that is within the clock
recovery PLL's loop bandwidth results in jitter on the recovered clock
which reduces the amount of jitter that can be detected. The input
signal and clock signal are closer in phase
Input signal jitter that is outside the clock
recovery PLL's loop bandwidth results in reduced jitter on the
recovered clock which increases the amount of jitter that can
be detected. The input signal and clock signal are more out of phase.
Jitter that is on both the input and clock signals can not detected or
is reduced
JTF and OJTF for 1st Order PLLs
The observed jitter is a complement to the PLL jitter transfer
response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not
observed at the output of the CDR as a function of the jitter rate
applied to the input.
The combination of the OJTF of a jitter measurement device and the
JTF of the clock generator under test gives the measured jitter as a
function of frequency.
For example, a clock generator with a type 1, 1st order PLL measured
with a jitter measurement device employing a golden PLL is \[
J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2}
\]
Accurate measurement of the clock JTF requires that the OJTF cutoff
of the jitter measurement be significantly below that of the clock JTF
and that the measurement is compensated for the instrument's OJTF.
The overall response is a band pass filter because the clock JTF is
low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring
the jitter of the reference clock at each jitter rate being tested and
comparing the reference jitter with the jitter
measured at the output of the DUT.
The lower the cutoff frequency of the jitter measurement device the
better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the
phase noise of the DUT and measurement time.
Digital Sampling
Oscilloscope
How to analyze jitter:
TIE (Time Interval Error) track
histogram
FFT
TIE track provides a direct view of how the phase of
the clock evolves over time.
histogram provides valuable information about the
long term variations in the timing.
FFT allows jitter at specific rates to be measured
down to the femto-second range.
Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop
bandwidth minimizes the response error
reference
Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and
Phase Noise: A Circuits and Systems Perspective.” (2018).
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
AFE Nonlinearity
"total harmonic distortion" (THD) in
AFE
Relative to NRZ-based systems, PAM4 transceivers require more
stringent circuit linearity, equalizers which can implement multi-level
inter-symbol interference (ISI) cancellation, and improved
sensitivity
Because if it compresses, it turns out you have to use a much more
complicated feedback filter. As long as it behaves linearly,
the feedback filter itself can remain a linear FIR
Linearity can actually be a critical constraint in these signal
paths, and you really want to stay as linear as you can all the way up
until the point where you've canceled all of the ISI
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline
Receivers"
BER with Quantization Noise
\[
\text{Var}(X) = E[X^2] - E[X]^2
\]
Impulse Response or Pulse
Response
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline
Links-Part II: Optimization and Performance Assessment," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024
[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in
Serial Data Transmission Systems,” in Phase-Locking in High-Performance
Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps
Digital Clock and Data Recovery Circuit," IEEE Custom Integrated
Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]
Da Dalt N. A design-oriented study of the nonlinear dynamics of
digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I:
Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]
Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop
gain tracking all-digital PLL using autocorrelation of bang–bang phase
frequency detection. IEEE Transactions on Circuits and Systems II:
Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]
CDR Loop Latency
Denoting the CDR loop latency by \(\Delta
T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The
resulting right-half-plane zero, \(f_z\) degrades the phase margin and must
remain about one decade beyond the BW\[
f_z\simeq \frac{1}{2\pi \Delta T}
\]
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of
Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
limit cycles imply self-sustained oscillators due nonlinear
nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC
LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van
Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design.
Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]
Digital CDR Category
DCO part is analogous so that it cannot be perfectly
modeled
Digital-to-phase converter is well-defined phase output, thus, very
good to model real situation
Z-domain modeling
The difference equation is \[
\phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi
\] z-transform is \[
\frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}}
\]
where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)
\(\Delta
\Sigma\)-dithering in DCO
Quantization noise
Here, \(\alpha_T\) is data
transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang
Controlled Timing Circuits," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
Time to Digital Converter
(TDC)
Digital to Phase Converter
(DPC)
IIR low pass filter
simple approximation: \[
z = 1 + sT
\] bilinear-z transform \[
z =\frac{}{}
\]
FAQ
PLL vs. CDR
PLL
CDR
Clock edge periodic
Data edge random
Phase & Frequency detecting possible
Phase detecting possible , Frequency detecting impossible
PLL or FD(Frequency Detector) for frequency detecting in CDR
reference
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and
Circuits" [slides]
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems
(lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT
OpenCourseWare, [lec21.pdf]
Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental
Concepts To Future Trends" [T5.pdf]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
—, "A digital clock and data recovery architecture for
multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom
Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
P. Palestri et al., "Analytical Modeling of Jitter in
Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol.
29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T.
King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore,
"A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit
Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital
Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol.
41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]
—, et al., "Modeling of ADC-Based Serial Link Receivers With
Embedded and Digital Equalization," in IEEE Transactions on
Components, Packaging and Manufacturing Technology, vol. 9, no. 3,
pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]
K. Zheng, "System-Driven Circuit Design for ADC-Based Wireline Data
Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]
S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo,
"Statistical modeling of metastability in ADC-based serial I/O
receivers," 2014 IEEE 23rd Conference on Electrical Performance of
Electronic Packaging and Systems [pdf]
We typically use the two spectra, \(S_{\phi
n}(f)\) and \(S_{out}(f)\),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal \(x(t)\) can be
expanded in Fourier series as:
Assume that the signal is subject to excess phase noise,
which is modeled by adding a time-dependent noise
component \(\alpha(t)\). The noisy
signal can be written \(x(t+\alpha(t))\), the added excess phase
\(\phi(t)=
\frac{\alpha(t)}{\omega_0}\)
The autocorrelation of the noisy signal is by definition:
The autocorrelation averaged over time results in:
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal \(x(t + \alpha(t))\) can
be expressed as
It is also interesting to note how the integral in Equation
9.80 around each harmonic is equal to the power of the harmonic
itself \(|X_n|^2\)
The integral \(S_x(f)\) around
harmonic is \[\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}\]
The phase noise does not affect the total power in the
signal, it only affects its distribution
Without phase noise, \(S_v(f)\) is
a series of impulse functions at the harmonics of \(f_o\).
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
Phase
perturbed by a stationary noise with Gaussian PDF
If keep \(\phi_{rms}\) in \(R_x(\tau)\), i.e. \[
R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)(1+R_\phi(\tau))
\] The PSD of the signal is \[
S_x(f) = \mathcal{F} \{ R_x(\tau) \} =
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] +
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right]
\] ❗❗above Eq isn't consistent with stationary
white noise process - the following section
Phase
perturbed by a stationary WHITE noise process
Assuming that the delay line is noiseless
Expanding the cosine function we get \[\begin{align}
R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi
f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi
f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\
&+ \frac{A^2}{2}\left\{\cos(4\pi
f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi
f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\}
\end{align}\]
where, both the process \(\phi(t)-\phi(t-\tau)\) and \(\phi(t)+\phi(t-\tau)\) are independent of
time \(t\), i.e. \(E[\cos(\phi(t)+\phi(t-\tau))] =
m_{\cos+}(\tau)\), \(E[\cos(\phi(t)-\phi(t-\tau))] =
m_{\cos-}(\tau)\), \(E[\sin(\phi(t)+\phi(t-\tau))] =
m_{\sin+}(\tau)\) and \(E[\sin(\phi(t)-\phi(t-\tau))] =
m_{\sin-}(\tau)\)
The second term in the above expression is periodic in \(t\) and to estimate its PSD, we compute the
time-averaged autocorrelation function\[
R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) -
\sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\}
\]
After nontrivial derivation
Phase perturbed by a Weiner
process
The phase process \(\phi(t)\) is
also gaussian but with an increasing variance which
grows linearly with time\(t\)
The spectrum of \(y(t)\) is
determined by the asymptotic behavior of \(R_y(t,\tau)\) as \(t\to \infty\)
❗❗ \(\lim_{t\to\infty}R_y(t,\tau)\) rather than
time-averaged autocorrelation function of cyclostationary
process, ref. Demir's paper
We define \(\zeta(t,
\tau)=\phi(t)+\phi(t-\tau) = \phi(t)-\phi(t-\tau) +
2\phi(t-\tau)\), the expected value of \(\zeta(t,\tau)\) is 0, the variance is \(\sigma_{\zeta}^2=(k\sigma)^2(\tau +
4(t-\tau))=(k\sigma)^2(4t-3\tau)\)\[
E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta
= e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)}
\] i.e., \(\lim _{t\to \infty}
E[\cos(\zeta(t,\tau))] = \lim_{t\to \infty}e^{-(k\sigma)^2(4t-\tau)} =
0\)
For \(E[\sin(\zeta(t,\tau))]\), we
have \[
E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta
\] i.e., \(E[\sin(\zeta(t,\tau))]\) is odd
function, therefore \(E[\sin(\zeta(t,\tau))]=0\)
A. Hajimiri and T. H. Lee, "A general theory of phase noise in
electrical oscillators," in IEEE Journal of Solid-State
Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [paper],
[slides]
A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in
oscillators: a unifying theory and numerical methods for
characterization," in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.se/10.1109/81.847872]
Godone, A. & Micalizio, Salvatore & Levi, Filippo. (2008). RF
spectrum of a carrier with a random phase modulation of arbitrary slope.
[https://sci-hub.se/10.1088/0026-1394/45/3/008]
Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices,
2020)
proportional term (P) depends on the present error
integral term (I) depends on past errors
derivative term (D) depends on anticipated future errors
PID controller makes use of linear extrapolation of
the measured output
PI controller does not make use of any prediction of
the future state of the system
The prediction by linear extrapolation (D) can
generate large undesired control signals because measurement noise is
amplified, that's why D is not used widely
The Problem of
"Sinusoids Running Around Loops"
The representative of Fourier transform \(\frac{1}{j\omega+j\omega_0}\) back in the
time domain \(e^{-j\omega_0 t}\) is
infinite extent in time
Running around a loop, chasing one's tail — these are thought
pictures that only work in a discretized, time-sequenced conceptual
framework that has a beginning and an end
Fix in your mind that oscillations are a type of
resonance
System Type
Control of Steady-State Error to Polynomial Inputs: System Type
control systems are assigned a type number according
to the maximum degree of the input polynominal for which the
steady-state error is a finite constant. i.e.
Type 0: Finite error to a step (position error)
Type 1: Finite error to a ramp (velocity error)
Type 2: Finite error to a parabola (acceleration error)
If we consider tracking the reference input alone and set \(W = V = 0\)
The open-loop transfer function can be expressed as
\[
T(s) = \frac{K_n(s)}{s^n}
\]
where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),
The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform
is \[
R(s) = \frac{1}{s^{k+1}}
\]
Then the equation for the error, \(R(s)-Y(s)\) is simply \[
E(s) = \frac{1}{1+T(s)}R(s)
\]
Application of the Final Value Theorem to the error formula
gives the result
charge pumps are capacitive
DC-DC converters. The two most common switched capacitor
voltage converters are the voltage inverter and the
voltage doubler circuit
We derive a recursive equation that describes the output voltage
\(V_{out,n}\) after the \(n\)th clock cycle \[
V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o}
\]
Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is
\[
\overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} -
\frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right)
\approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p}
\] which results in a simple expression for the output
voltage droop
\[
\Delta V_{out} = \frac{I_{load}}{f_{sw}C_p}
\]
The charge pump can be modeled as a voltage source with a
source resistance\(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage
drop across \(R_\text{out}\) due to the
load current:
\[\begin{align}
N_a &= L_a I_a + \color{red}M_{ab}I_b \\
N_b &= L_b I_b + \color{red}M_{ab}I_a
\end{align}\]
\[
L_\text{series} = L_1 + L_{12} + L_2 +L_{12} = L_1 + L_2 + 2L_{12}
\]
