A resonant circuit refers to an electrical
circuit using circuit elements such as an inductor (L) and a capacitor
(C) to cause resonance at a specific frequency.
There are two types of resonant circuits:
series resonant circuits
parallel resonant circuits
In a series resonant circuit, the impedance of the
circuit reaches its minimum value at resonance, whereas
in a parallel resonant circuit, the impedance reaches
its maximum value
antiresonance
Resonant Frequency
\(\zeta \lt 1\):
Complex-Conjugate Poles, but not resonant
peak
Prof. M. Green / U.C. Irvine EECS 270C / Winter 2016 Week5 [pdf]
with \(L' = \frac{L}{1 -
CR_s^2/L}\)
resonant frequency in right equivalent circuit \[
\omega_r^2 = \frac{1}{L'C} = \frac{1}{LC} -
\left(\frac{R_s}{L}\right)^2
\] which shows that the equivalent circuit preserves the resonant
frequency of the original network.
assuming \(i(t) = I_p\cos\omega_0
t\), where \(\omega_0
=1/\sqrt{LC}\) , suppose all current flow into \(R\)\[
V(t) = I_pR\cdot \cos\omega_0 t
\]\(I_C\), the current flow
through \(C\)\[
\color{red}I_C(t)=C\frac{\mathrm{d}V(t)}{\mathrm{d}t}=-C\omega_0\cdot
I_pR\cdot \sin\omega_0 t
\] Then, we have voltage between \(L\), given \(I_L
= -I_C\)\[
V_L(t) = L\frac{\mathrm{d}I_L(t)}{\mathrm{d}t} = LC\omega_0^2\cdot
I_pR\cdot \cos\omega_0 t = I_pR\cdot \cos\omega_0 t
\]
Series resonance
assuming \(V(t)=V_s\cos\omega_0t\),
where \(\omega_0 =1/\sqrt{LC}\) ,
suppose all current flow into \(V_C+V_L=0\)\[
V_R(t) = V(t) = V_s\cos\omega_0t
\] then \[
I_s(t) = \frac{V_s}{R}\cos\omega_0 t
\]\(V_L(t)\) is obtained \[
V_L(t) = L\frac{\mathrm{d}I_s(t)}{\mathrm{d}t} = -L\omega_0\cdot
\frac{V_s}{R}\sin\omega_0 t
\] Then \[
V_C(t) = V(t) - (V_L(t) + V_R(t)) = -V_L(t)
\] Therefore, \(I_C\) current
flow through \(C\)\[
I_C(t) = C\frac{\mathrm{d}V_C(t)}{\mathrm{d}t}= LC\omega_0^2\cdot
\frac{V_s}{R}\cos\omega_0 t= \frac{V_s}{R}\cos\omega_0 t
\] voltage potential between \(L\) and \(C\)\[
\color{red}V_m(t) = V_R(t) + V_L(t) = V_s\cos\omega_0t -L\omega_0\cdot
\frac{V_s}{R}\sin\omega_0 t = V_s\sqrt{1+L/R^2C}\cos(\omega_0t+\phi)
\]
In the series circuit, the open-circuit voltage at P1–P2 is just
\(V_n\), since no current flows and L
drops nothing:
\[
\overline{v_{P1P2}^2} = 4kTR
\]
In the parallel circuit, \(I_n\)
flows into \(R_p \parallel j\omega
L_p\). By construction of the transformation, that impedance
equals \(R + j\omega L\) at this ω.
Using \(R^2 + \omega^2L^2 =
R^2(1+Q_s^2)\) and \(R_p =
R(1+Q_s^2)\):
\[
f_\text{SRF} = \frac{1}{2\pi \sqrt{LC}}
\] The SRF of an inductor is the frequency at which the parasitic
capacitance of the inductor resonates with the ideal inductance of the
inductor, resulting in an extremely high impedance. The inductance only
acts like an inductor below its SRF
For choking applications, chose an inductor
whose SRF is at or near the frequency to be attenuated
For other applications, the SRF should be at least
10 times higher than the operating frequency
it is more important to have a relatively flat inductance
curve (constant inductance vs. frequency) near the required
frequency
RLC inspection
For analyzing RLC circuits, Log-Log is indeed the best
choice.
J. Nako, G. Tsirimokou, C. Psychalinos and A. S. Elwakil,
"Approximation of First–Order Complex Resonators in the
Frequency–Domain," in IEEE Access, vol. 13, pp. 54494-54503,
2025 [pdf]
Dead zone induced by incomplete settling of charge-pump
currents
This situation can be avoided by adding additional delay to the
AND gate in the PFD
D. Turker et al., "A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm
FinFET for integrated RF-data-converter SoCs," 2018 IEEE International
Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018
[[https://sci-hub.ru/10.1109/ISSCC.2018.8310342](
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
PFD ZOH
PFD ZOH half
reference cycle delay in Open-Loop PLL Gain
\(\color{red}T_\text{pfd}/2\) term
is typically an equivalent delay caused by the sampled-data nature of the PFD/charge-pump
Divider delay
An ideal feedback divider does
not introduce propagation delay in phase
domain
The feedback divider provides a sampled version of the scaled VCO
phase, and the PFD obtains the sampled phase error between that feedback
phase and the reference phase
There is no delay between oscillator output phase and feedback
divider output phase if C2Q and logic propagation delays are
neglected
If the real divider has C2Q delay \(t_{CQ}\), then it becomes approximately
\[
\boxed{T_d \approx t_{\mathrm{CQ}} + \frac{T_{\mathrm{pfd}}}{2}}
\]
retimer at divider output
Darabi H. Radio Frequency Integrated Circuits and Systems. 2nd ed.
Cambridge University Press; 2020.
extra one cycle
delay vs reducing accumulated
noise from the last DFF retiming DFF
The periodic signal on VCTRL modulates the
VCO, giving rise to deterministic jitter
Timing Offsets Between Up and Dn Pulses
Mismatch Between Charge-Pump Current Sources
Incomplete Settling of Charge-Pump Currents
Finite Output Resistance of the Charge Pump
Up/Dn Timing Offset
If Dn pulse arrives \(\Delta T\)
after the Up pulse, the steady-state VCTRL will be slightly
lower than it would be without the \(\Delta T\) mismatch so as to return the
VCO's phase to match the reference clocks.
Vice versa, if If Up pulse arrives \(\Delta
T\) after the Dn pulse, the steady-state VCTRL will be slightly
higher than without \(\Delta
T\) mismatch
Johnson, M., Hudson, E.: A variable delay line PLL for
CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits
23(10), 1218–1223 (1988) [https://sci-hub.se/10.1109/4.5947]
D. Turker et al., "A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm
FinFET for integrated RF-data-converter SoCs," 2018 IEEE International
Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018
[https://sci-hub.ru/10.1109/ISSCC.2018.8310342]
charge pump with amplifier
off-state leakage
TODO 📅
Incomplete Settling
TODO 📅
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]
Cowan G. Mixed-Signal CMOS for Wireline Communication:
Transistor-Level and System-Level Design Considerations. Cambridge
University Press; 2024
2nd loop filter
PI (proportional - integral) Loop Filter
LPF leakage
For the sake of simplicity, \(V_{ctr}\) looks like a rectangular pulse
with an amplitude of \(I_{CP}R_1\) and
a duty ratio of (\(I_{leak}/I_{CP}\)),
whose first coefficient of Fourier series is
where \(I_\text{leak} \ll I_{CP}\)
is assumed
Then, the peak frequency deviation \(\Delta f\)\[
\Delta f = a_1 \cdot K_v = 2I_\text{leak}R_1 K_v
\] using narrowband FM approximation, we have \[
P_\text{spur} = 20\log\left(\frac{\Delta f}{2f_\text{ref}}\right) =
20\log\left(\frac{I_\text{leak}R_1 K_v}{f_\text{ref}}\right)
\]
W. Rhee, "Design of high-performance CMOS charge pumps in
phase-locked loops," 1999 IEEE International Symposium on Circuits
and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]
—. Yu, Z., 2024. Phase-Locked Loops: System Perspectives and
Circuit Design Aspects. John Wiley & Sons
A step response test is an easy way to determine the
bandwidth.
Sum a small step into the control voltage of your oscillator
(VCO or NCO), and measure the 90% to 10% fall time of the
corrected response at the output of the loop filter as shown in this
block diagram
a first order loop \[
BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}
\] Where \(BW\) is the 3 dB
bandwidth in Hz and \(𝑡\) is the
10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7
this relationship is closer to: \[
BW = \frac{0.33}{t}\space\space\space\space \text{(second order system,
damping factor = 0.7)}
\]
PLL BW and peaking
by Clock Recovery Method
Rick Eads Principal Planner, Keysight Technologies, PLL
Characterization Techniques for High Precision Measurement
X. Wang and S. Elsalahi, "Multi-Rate Discrete-Time Analysis and
Behavioral Modeling of Nonlinear High-Order Fractional-N Charge-Pump
Phase Locked Loops," in IEEE Open Journal of the Solid-State
Circuits Society, doi: 10.1109/OJSSCS.2026.3737100. [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11705418]
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007.
Chembiyan T. Chargepump PLL Basics- From A Control Theoretic
Viewpoint [linkedin]
—. Challenges in Chargepump PLL Design- A Qualitative Approach [linkedin]
—. A Unified Approach to Low Noise Loop Design in Chargepump PLLs [linkedin]
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges," in IEEE Transactions on Circuits and Systems I: Regular Papers,
vol. 68, no. 10, pp. 4049-4061, Oct. 2021 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9509840]
CTLE provide only limited improvement in the pre-cursor ISI, because
of the continuous-time, analog nature of CTLE
FFE to reduce ISI in both the pre-cursor and post-cursor, because of
operating digitally in discrete-time
in the frequency domain
CTLE focuses on boosting frequency content at the
Nyquist frequency
FFE algorithm is selecting taps that effectively amplify the
odd harmonics of the Nyquist frequency
In the case of FFE, because of the nature of finite impulse response
filter, we would expect amplification and attenuation of different
harmonics of Nyquist Frequency
Until 6.5 dB of CTLE DC attenuation, the spread of the single pulse
is positive and reaches almost zero at 6.5 dB. As the
DC attenuation increases to more than 6.5 dB, the single pulse spectrum
is restored too much, resulting in a negative dip at the end of
the pulse
the maximum eye opening does not happen at maximum
DC attenuation at 9 dB
There are kinks in the eye diagram, the signature of an
opened DFE eye is different than other equalizations
DFE algorithm is reducing ISI based on the detected data
(symbol)
Since DFE assumes that past symbol decisions are correct.
Incorrect decisions from the symbol detector corrupt the filtering of
the feedback loop. As a result, the inclusion of the feedforward filter
on the front end is crucial in minimizing the probability of error
because symbol detection is nonlinear, decision feedback
equalization is also nonlinear
because of the nonlinearity of the DFE response, it must be modeled
in the time domain
FFE vs. DFE
FFE: convolution with input waveform/symbols.
Linear.
DFE: convolution with past detected symbols.
Recursive and nonlinear because of the slicer.
That is why DFE is not a simple LTI convolution system from input to
output.
1 2 3 4 5
received sample r[n] ──┬── subtract ──> slicer ──> detected symbol a_hat[n] ▲ │ │ │ └── DFE filter <─────┘ past decisions
ZFS eliminates the ISI only at the sampling points that correspond
to the equalizer taps. The equalized pulse shows ISI in the intervals
between the sample points and at sample points outside the
equalizer
The Minimum Mean-Square Error Linear Equalizer (MMSE-LE)
balances ISI reduction and noise
enhancement. The MMSE-LE always performs as well as, or
better than, the ZFE
V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link
transceiver with adaptive equalization and data recovery," IEEE Journal
of Solid-State Circuits, vol. 40, no. 4, pp. 1012–1026, Apr. 2005 [https://sci-hub.ru/10.1109/JSSC.2004.842863]
J. T. Stonick, Gu-Yeon Wei, J. L. Sonntag and D. K. Weinlader, "An
adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS," in IEEE
Journal of Solid-State Circuits, vol. 38, no. 3, pp. 436-443, March
2003, [https://sci-hub.st/10.1109/JSSC.2002.808282]
RX with SS-LMS
E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for
I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State
Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008 [https://sci-hub.ru/10.1109/JSSC.2008.2001871]
K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of
PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open
Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9910561]
S. Kim, K. K. Tokgoz and G. Kim, "Modeling and Simulation of
Mueller-Muller Clock Data Recovery System for PAM-4 Wireline
Transceivers," 2025 IEEE/IEIE International Conference on Consumer
Electronics-Asia (ICCE-Asia), Busan, Korea, Republic of, 2025, pp.
1-3, doi: 10.1109/ICCE-Asia67487.2025.11263607
# Type B: Finding the LAST minimal error before h(-1) rises indices_b = np.where(np.abs(tef_b) == np.min(np.abs(tef_b)))[0] t_lock_b = phases[indices_b][-1]
# 4. Plotting Results plt.figure(figsize=(10, 6)) plt.plot(t_cont, h_cont, 'k-', lw=2, label='Pulse Response $h(t)$') plt.axvline(t_lock_a, color='red', linestyle='--', label=f'Type A Lock: {t_lock_a:.2f}T') plt.axvline(t_lock_b, color='green', linestyle='--', label=f'Type B Lock: {t_lock_b:.2f}T') plt.plot(t_lock_b - 1, get_h(t_lock_b - 1), 'go', label='Type B: $h_{-1}=0$') plt.title('Baud Rate Lock: Type A (Symmetry) vs. Type B (Last-Zero Precursor)') plt.legend() plt.grid(True, alpha=0.3) plt.show()
Suppose 1-precursor, 1-postcursor — \(y_k =
d_{k-1}h_1 + d_k h_0 + d_{k+1}h_{-1}\)\[
\color{red}E[y_k\cdot d_{k-1}] - E[y_k\cdot d_{k+1}] =
E[|d_{k-1}|^2h_{1}] - E[|d_{k+1}|^2h_{-1}] =h_1-h_{-1}
\] MMPD infers the channel response from baud-rate samples of the
received data, the adaptation aligns the sampling clock such that
pre-cursor is equal to the post-cursor in the pulse
response
F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver
with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010
IEEE International Solid-State Circuits Conference - (ISSCC), San
Francisco, CA, USA, 2010, [https://sci-hub.ru/10.1109/ISSCC.2010.5433823]
Chen, J., Gu, Y., Feng, X., Chi, R., Wu, J., & Chen, Y. (2024).
Analysis of Mueller–Muller Clock and Data Recovery Circuits with a
Linearized Model. Electronics, 13(21), 4218 [https://www.mdpi.com/2079-9292/13/21/4218]
Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin &
Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao
& Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock
and Data Recovery Circuits. Electronics. [10.
1888. 10.3390/electronics10161888.]
Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen
& Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data
Recovery Circuits with a Linearized Model. [10.21203/rs.3.rs-1817774/v1]
Rhee, Woogeun, and Zhiping Yu. Phase-Locked Loops: System
Perspectives and Circuit Design Aspects. John Wiley & Sons,
2024.
Reference Level Choice
Chen, J., Gu, Y., Feng, X., Chi, R., Wu, J., & Chen, Y. (2024).
Analysis of Mueller–Muller Clock and Data Recovery Circuits with a
Linearized Model. Electronics, 13(21), 4218 [https://www.mdpi.com/2079-9292/13/21/4218]
Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin &
Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao
& Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock
and Data Recovery Circuits. Electronics. [10.
1888. 10.3390/electronics10161888.]
Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen
& Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data
Recovery Circuits with a Linearized Model. [10.21203/rs.3.rs-1817774/v1]
Adjust Locking Point
Avago Technologies, US8649476B2 Adjusting sampling phase in a
baud-rate CDR using timing skew [pdf]
Y. Jung, H. -J. Shin, J. Kim, S. Lee, J. -S. Park and K. Park, "A
28-Gb/s Receiver with Baud-Rate CDR Employing Integrated Pattern-Based
Phase Detector Achieving ISI Invariant Phase Locking," 2025 IEEE
Asian Solid-State Circuits Conference (A-SSCC), Daejeon, Korea,
Republic of, 2025,
R. Dokania et al., "10.5 A 5.9pJ/b 10Gb/s serial link with
unequalized MM-CDR in 14nm tri-gate CMOS," 2015 IEEE International
Solid-State Circuits Conference - (ISSCC) Digest of Technical
Papers, San Francisco, CA, USA, 2015 [https://sci-hub.jp/10.1109/ISSCC.2015.7062987]
H. Zhang, B. Jiao, Y. Liao, and G. Zhang, "A Tutorial on PAM4
Signaling for 56G Serial Link," [DesignCon
2016], [DesignCon
2017]
1-tap adaptive DFE that forces the \(h_1\) to be zero, the SS-MMPD
locks wherever the \(h_{-1}\) is zero
and drifts eventually.
Consequently, it suffers from a severe multiple-locking problem
with an adaptive DFE
Pattern filter
pattern
main cursor
011
\(s_{011}=-h_1+h_0+h_{-1}\)
110
\(s_{110}=h_1+h_0-h_{-1}\)
100
\(s_{100}=h_1-h_0-h_{-1}\)
001
\(s_{001}=-h_1-h_0+h_{-1}\)
During adapting, we make
\(s_{011}\) & \(s_{110}\) are approaching to each
other
\(s_{100}\) & \(s_{001}\) are approaching to each
other
Then, \(h_{-1}\) and \(h_1\) are same, which is desired
CDR Loop Latency
A. Amirkhany, "Tutorial: Basics of Clock-and-Data Recovery Circuits,"
2019 IEEE International Solid-State Circuits Conference -
(ISSCC), San Francisco, CA, USA, 2019, pp. 1-105, doi:
10.1109/ISSCC19946.2019.11005770.
Nhat Nguyen and Masum Hossain, ISSCC 2021 Forum 6.7:
112Gb/s-and-Beyond Long-Reach and Short-Reach Electrical Interfaces
For high-BW CDR \(\omega_{ug}\),
latency \(D\) constrain \(\phi_M\)
loop latency is represented as \(\color{red}e^{-sD}\) in linear model
""" Behavioral model of the experiment on the slides "Max dphi w/ SJ & Sweeping loop Latency" (pages 5 and 6): 8 Gb/s, PRBS7, no input RJ SJ = 10 %UI p-p @ 100 MHz T_D (loop latency) = 2 / 5 / 10 UI -> dphi = 12 / 19 / 23 %UI p-p Units: time step = 1 UI (125 ps @ 8 Gb/s), all phases in UI. Loop (digital type-II, latency T_D inserted in the feedback path): e[n] = sign(dphi[n]) on data transitions, 0 otherwise (BBPD) acc[n+1] = acc[n] + Ki * e[n-TD] (integral / freq) ph_ck[n+1] = ph_ck[n] + acc[n+1] + Kp * e[n-TD] (VCO phase) dphi[n] = ph_din[n] - ph_ck[n] Fitted gains that reproduce the three measured points: Kp = 0.60 %UI per decision, Ki = Kp/1024 -> dphi(p-p) = 12.8 / 19.3 / 23.4 %UI (measured 12 / 19 / 23) Key mechanism (confirmed by the page-6 zoom): the loop is SLEW-RATE LIMITED, not bandwidth limited. The CDR can move clock phase at most SR = Kp * eta ~ 3.0 mUI/UI (eta = PRBS7 edge density) while the SJ demands SJ_SR = pi * A_pp * f_sj / f_b ~ 3.9 mUI/UI Since SR < SJ_SR, ph_ck ramps at constant slope, falls behind, and then keeps ramping past the input after the sine turns around; T_D extends that turnaround. The result is a coherent triangular oscillation at f_sj whose amplitude EXCEEDS the input jitter. The regime boundary is f_SL = Kp * eta * f_b / (pi * A_pp) ~ 77 MHz """
defbbcdr(TD_UI=2, Kp=KP_FIT, zeta_div=ZD_FIT, ki_en=None, sj_pp=0.10, f_sj=100e6, f_b=F_B, ppm=0.0, n_ui=20000, n_settle=4000, seed=0x7F): """ One CDR run. Returns the waveforms plus p-p / peak / rms phase error measured after n_settle UI. dphi = ph_din - ph_ck (>0 : data late -> clock must be delayed) ki_en : True -> type-II (Ki = Kp/zeta_div), False -> type-I (Ki = 0), None -> follow the module-level KI_EN. """ use_ki = KI_EN if ki_en isNoneelse ki_en Ki = Kp / zeta_div if use_ki else0.0 TD = int(round(TD_UI))
\(K_P\) is the normalized DCO frequency deviation caused by one BBPD
decision, and because that deviation lasts for one UI, it
produces \(K_P\) UI of excess phase
over that interval:
defsimulate(td_ui: int, kp: float, ki: float): """ BB-CDR recursion. e[n] = phi_data[n] - phi_clk[n] q[n] = sign(e[n]) when a PRBS data transition exists. During no-transition intervals, the binary detector keeps the previous Early/Late state. qd[n] = q[n-TD] fi[n+1] = fi[n] + Ki*qd[n] df[n] = Kp*qd[n] + fi[n+1] phi_clk[n+1] = phi_clk[n] + df[n] The last line is the VCO frequency-to-phase integration. """ n = np.arange(N_UI)
# 100 MHz SJ at 8 Gb/s => period = 80 UI phi_data = SJ_PK * np.sin(2*np.pi*(F_SJ/RB)*n)
phi_clk = np.zeros(N_UI) fi = np.zeros(N_UI) # integral path; frequency correction df = np.zeros(N_UI) # total normalized frequency correction bb = np.zeros(N_UI)
last_bb = 0.0
for k inrange(N_UI - 1): phase_err_now = wrap_ui(phi_data[k] - phi_clk[k])
David Johns. ECE1392H - Integrated Circuits for Digital
Communications - Fall 2001: [Equalization],
[Timing
Recovery]
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Circuits Conference (ISSCC), San Francisco, CA, USA, 2022
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—, ISSCC2019 T6: "Basics of Clock and Data Recovery Circuits"
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Wei-Zen Chen, ISSCC2026. T9: Clocking and CDR Techniques for
High-Performance Wireline Transceiver
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2696-2708, Sept. 2018 [https://sci-hub.jp/10.1109/JSSC.2018.2839038]
Youngdon Choi, Deog-Kyoon Jeong and W. Kim, "Jitter transfer analysis
of tracked oversampling techniques for multigigabit clock and data
recovery," in IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 50, no. 11, pp. 775-783, Nov. 2003 [https://sci-hub.st/10.1109/TCSII.2003.819070]
John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and
Data Recovery
Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data
Recovery in Serial Data Transmission Systems. [pdf]
—, Clock and Data Recovery for Serial Data Communications, focusing
on bang-bang CDR design methodology, ISSCC Short Course, February 2002.
[slides]
It's ternary, because early, late
and no transition
notice the transition density = 1 in
digital PLL
Linearization
The effective PD gain is a function of the input jitter
pdf, it enables one to anticipate the effects of input jitter
on loop characteristics
BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),
BB only produces output for a transition and this de-rates the gain.
Transition density = 0.5 for
random data
Input referred jitter from BB PD is
proportional to incoming jitter
gain simulation
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]
T. -K. Kuan and S. -I. Liu, "A Bang Bang Phase-Locked Loop Using
Automatic Loop Gain Control and Loop Latency Reduction Techniques," in
IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 821-831, April
2016 [https://sci-hub.st/10.1109/JSSC.2016.2519391]
# polyfit coef_fit = np.polyfit(dt, et, 1) print(f'coef_fit: {coef_fit}')
x = np.linspace(-3.5, 3.5, 1000) y = coef_fit[0]*x + coef_fit[1]
plt.figure(figsize=(12,6)) plt.plot(dt, et, 'o') plt.plot(x, y, linewidth=2, linestyle='--')
# Calculate histogram counts and bin edges counts, bin_edges = np.histogram(dt, bins=100) # Find the maximum count max_count = counts.max() # Create weights to normalize the maximum height to 1 weights = np.ones_like(dt) / max_count plt.hist(dt, bins=100, weights=weights)
S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim and D. -K. Jeong,
"An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of
Bang–Bang Phase-Frequency Detection," in IEEE Transactions on Circuits
and Systems II: Express Briefs, vol. 62, no. 9, pp. 836-840, Sept. 2015
[https://sci-hub.st/10.1109/TCSII.2015.2435691]
[phd
thesis]
CC Chen. Why Hunting Jitter Happens in CDR: The Role of Input Jitter
and Latency? [https://youtu.be/hPDielPsFgY]
Hunting jitter is often referred to as
dithering jitter, the periodic time
error between data clock and input data, which exhibits a
limit-cycle behavior
Michael Perrott, August 14, 2008. Short Course On Phase-Locked Loops
and Their Applications Day 4, AM Lecture Digital Frequency
Synthesizers [https://www.cppsim.com/PLL_Lectures/day4_am.pdf]
—, "A modeling approach for Sigma Delta fractional-N frequency
synthesizers allowing straightforward noise analysis," in IEEE
Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038,
Aug. 2002 [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]
Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology.
"Techniques for high-performance digital frequency synthesis and phase
control." 2008. [http://hdl.handle.net/1721.1/45870]
J. R. Barry, E. A. Lee, and D. G. Messerschmitt, Digital
Communication, 3rd ed., Boston, MA: Kluwer Academic Publishers,
2003.
\(\color{red}\frac{1}{T}\) of CT-DT
originates from CT to sampled sequence to impulse train Fourier
transform, which is explicit in frequency-domain
model
\(\color{red}\frac{1}{T}\)
originates from DT spectrum to CT impulse
spectrum is implicit in
frequency-domain model
\(\color{red}T\) of DT-CT
originates from ZOH approximation following impulse
train, which is explicit in frequency-domain model
Divider Sampling Operation &
ITM
Impulse Train Modulator (ITM)
The double outline of the box in the figure is meant
to serve as a reminder that a sampling operation is
taking place
DT -> CT
\(\boxed{S_x(e^{j2\pi fT}) = S_d(f)\cdot
\textcolor{blue}{\frac{1}{T}}=S_c(f)\cdot
\textcolor{blue}{\frac{1}{T}}}\), For example, the quantization
noise spectrum is given by \(S_x(e^{j2\pi fT})
= \frac{1}{12f_s}\cdot \frac{1}{T} = \frac{1}{12}\). To convert
the sequence spectrum into a continuous impulse train spectrum, we
multiply by \(\color{blue}\frac{1}{T^2}\)\[
S_y(f) = S_x(e^{j2\pi fT}) \cdot \textcolor{blue}{T\cdot
\frac{1}{T^2}\cdot |H(f)|^2 } = S_x(e^{j2\pi fT}) \cdot
\textcolor{blue}{\frac{1}{T}|H(f)|^2}
\]
CT -> DT -> CT
Assume that the lower \(m\) bits of
the digital filter output are discarded by truncation. The truncation
error is therefore modeled as a uniformly distributed random
variable,
\[
E_t \sim U[0,2^m\text{LSB}]
\]
Because the effective output resolution is reduced, the new least
significant bit becomes
\[
\text{LSB}_t = 2^m\text{LSB}
\]
and the DAC quantization error is correspondingly modeled as
J. Stonick. ISSCC 2011 tutorials, T5: "DPLL-Based Clock and Data
Recovery"
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery
Circuits"
\(M+1\) bits ensure on overflow or
underflow in the signed adder
MRDT (Multi-rate
Discrete-Time) Modeling
Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp
Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in
IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 69, no. 7, pp. 3030-3036, July 2022 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9765581]
There are two key features associated with the behavior of DPLLs,
namely, the multi-rate and
discrete-time
properties
reference & DCO model
timestamps with
synchronous jitter for reference clock signal
periods with period
jitter for free-running
DCO
output jitter, PN & input
jitter
Determine quantitatively the system jitters and
PN from behavioral simulation of the MRDT DPLL
%% Wang, Xu and Michael Peter Kennedy. “Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers - Modeling, Simulation, Analysis, and Design Methodologies.” *Analog Circuits and Signal Processing* (2026).
function[F_mean,t_n_rms,phi_n_rms,f_PSD,PSD_phi] = acquisition(t) %% Ensure column vector [~,ncol]=size(t); if ncol ~= 1 t = t'; end %% Periods T = diff(t); %% Average period T_mean = mean(T); F_mean = 1/T_mean; %% Period jitter T_n = T - T_mean; %% Zero-mean accumulated time jitter t_n = cumsum(T_n); t_n = t_n - mean(t_n); %% RMS time jitter t_n_rms = std(t_n); %% Phase error phi_n = 2*pi/T_mean * t_n; phi_n_rms = std(phi_n); %% PSD of phase error npsd = 2^(nextpow2(length(phi_n)/8)-1); Fpsd = 1/(npsd*T_mean); f_PSD = 0:Fpsd:Fpsd*(floor(npsd/2)-1); [PSD_phi,~] = pwelch(phi_n,window(@hann,npsd),npsd/2,npsd,1/T_mean, 'two-sided'); PSD_phi = PSD_phi(1:floor(npsd/2));
cross-domain scaling
for PSD-consistent
N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its
Validity Limits Applied to Jitter Transfer and Jitter Generation," in
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55,
no. 11, pp. 3663-3675, Dec. 2008 [https://sci-hub.st/10.1109/TCSI.2008.925948]
H. Lu and P. P. Mercier, "Linear Periodically Time-Variant Digital
PLL Phase Noise Modeling Using Conversion Matrices and Uncorrelated
Upsampling," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 71, no. 12, pp. 6021-6033, Dec. 2024, doi:
10.1109/TCSI.2024.3415001
At low frequencies, the transfer function from \(t_{r}\) to \(T_{v}\) can be approximated as: \[
H_{t_r,T_v} \approx \frac{1-z^{-1}}{Nz^{-1}}
\]
\[
\boxed{ \text{For deriving Eq. (10), the }\uparrow N\text{ block must be
treated as unity-amplitude rate conversion} }
\]
and to be integrated for jitter variance in (13). Both uses require a
PSD-consistent transfer
function, and for a slow-in/fast-out path that is
not the same as the transform ratio.
Write the cross-domain path as
\[
y[n] = \sum_k h[n-kN]\,x[k]
\]
with \(x\)zero-mean, white, and of variance \(\sigma^2\) on the slow grid \(T_{r0}\), and with real-valued \(h\). Then
\[
E\{y^2[n]\} = \sigma^2\sum_k h^2[n-kN]
\]
The variance is \(N\)-periodic, but
it need not differ between output phases. The output is generally
cyclostationary; even when its variance is constant,
its autocorrelation can depend on \(n\bmod
N\).
Averaging the variance over \(N\)
fast samples: \[
\overline{\sigma_y^2} = \frac{\sigma^2}{N}\sum_j h^2[j]
\]
Now demand the ordinary form \[
S_y = c\,|H|^2 S_x
\]
With the paper's convention \(S_x(f) =
T_{r0}\sigma^2\), integrating over the fast Nyquist band \(F = N/T_{r0}\) and applying Parseval \(\int_{-F/2}^{F/2}|H|^2\,df = F\sum_j
h^2[j]\):
So the transfer function you may legitimately plug into \(S_y = |H|^2 S_x\) is \(\textcolor{red}{H/N}\), not \(H\). That is equation
(10)
For the hold stage alone, \(H_{\mathrm{ZOH}}(z)=(1-z^{-N})/(1-z^{-1})\),
whose impulse response is rectangular. For the complete cross-domain
path, \(h\) denotes the full effective
impulse response.
The root cause in one line: \(S_x\)
is normalized on \(T_{r0}\) while \(S_y\) is normalized on \(T_{v0} = T_{r0}/N\). The \(1/N\) reconciles the two
normalizations.
Assume real-valued \(h\) and
zero-mean white input:
# ============================================================ # DCO OUTPUT TIMESTAMPS # # The DLF output is held for N DCO cycles. # ============================================================
# DCO period error due to loop control dTctrl = (KT * u)
# Total DCO period error for every fast-clock cycle dT = np.repeat(dTctrl, N)
|Error/Jr| : 1.583866e-02 Error transfer gain : -36.006 dB ============================================================
!!DPLL time-domain model
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]
—, “Contributions to the Theory and Development of Low-Jitter
Bang-Bang Integrated Frequency Synthesizers.” University College Dublin.
School of Electrical and Electronic Engineering, 2022. [http://hdl.handle.net/10197/13372]
The paper defines the BPD input as
\[
\boxed{\Delta t[k]=t_r[k]-t_d[k]}
\]
where \(t_r[k]\) is the
reference-edge timestamp and \(t_d[k]\)
is the divider-output timestamp.
The signal chain is essentially \[
\epsilon[k] \rightarrow \underbrace{\beta\epsilon[k]+\psi[k]}_{u[k]}
\rightarrow \underbrace{K_T u[k]}_{\text{DCO period change}} \rightarrow
T_v.
\]
A useful distinction is that \(K_T\)
is not the usual DCO frequency gain \(K_{\mathrm{DCO}}\) in Hz/code.
This paper models the DCO in the period domain, so its
gain is period/code. Around the nominal operating point, \(f=\frac{1}{T}\)
hence for a small period change,
\[
\Delta f \approx -\frac{\Delta T}{T_0^2}.
\]
Therefore the corresponding frequency gain would be approximately
%% Reference absolute jitter jr = sigma_ref * randn(Nsim+1,1);
%% DCO cycle-period errors at the fast clock rate % % Tv(:,k) holds the N zero-mean period-noise samples in reference % interval k. Their sum is the Wv[k] term in the reference-rate % recursion. Keeping the individual samples makes it possible to % construct the path-consistent DCO timestamps tv[h] from Eq. (4). % if sigma_Tv == 0 Tv = []; Wv = zeros(Nsim,1); else Tv = sigma_Tv*randn(N,Nsim); Wv = sum(Tv,1).'; end
%% ------------------------------------------------------------ % DCO-output timestamps, Eq. (4) %% ------------------------------------------------------------ % The DLF output is zero-order held for N DCO cycles. Add that % control contribution to the SAME fast-rate noise samples whose % block sums drove the recursion above. Accumulate the period error % first so nominal-period roundoff cannot mask femtosecond jitter. dTctrl = (KT*u).'; ifisempty(Tv) Tv = repmat(dTctrl,N,1); else for m = 1:N Tv(m,:) = Tv(m,:) + dTctrl; end end % Reuse Tv for the accumulated timing error to limit the peak to % roughly two full DCO-rate traces during the leading-zero prepend. clear Wv u dTctrl Tv = cumsum(Tv(:)); % t_v[h] - h*Tv0, h = 1,...,N*Nsim tv = [0; Tv]; % include t_v[0] clear Tv
% Form literal edge timestamps without cumulatively adding Tv0. % Chunking avoids another full-size temporary vector. Ndco = N*Nsim; edge_chunk = 1e6; for h0 = 0:edge_chunk:Ndco h1 = min(h0+edge_chunk-1,Ndco); h = (h0:h1).'; idx = h+1; tv(idx) = tv(idx) + h*Tv0; end
for k = 1:length(sigma_sim) fprintf('(%c) %8.2f\n', ... 'a'+k-1, sigma_sim(k)/1e-15); end
There are two different random sequences: \[
\boxed{j_r[k] = \text{absolute reference edge jitter}}
\]
versus
\[
\boxed{\delta T_r[k]=j_r[k+1]-j_r[k] =\text{reference period jitter}}.
\]
Our simulation generates
1
jr = sigma_ref * randn(...);
because the paper assumes white absolute reference
jitter. The paper explicitly calls \(\sigma_{t_r}^2\) the absolute jitter
variance of the reference.
Then the model naturally converts that absolute jitter into
reference-period variation using
1
jr(k+1) - jr(k)
There is also a subtle but important consequence. If \(j_r[k]\sim\mathcal N(0,\sigma_{t_r}^2)\) is
i.i.d., then \(\operatorname{Var}\{j_r[k+1]-j_r[k]\} =
2\sigma_{t_r}^2.\)
and the DPLL recursion evolves from one edge interval to the
next, which is why the difference appears.
\(\boxed{\sigma_{\Delta t}}\) at the
BPD input, not directly the RMS DCO-output jitter. To
obtain actual DCO-output jitter, we should also simulate/store \(t_v[h]\), rather than only the
reference-rate recursion for \(\Delta
t[k]\).
causality z-1 in
linear model
\(\textcolor{red}{z^{-1}}\) makes
the loop causal, and it
represents the one-reference-cycle latency that is physically
unavoidable in a digital PLL
With the indexing used in this slide,
\[
\boxed{\Delta t[k]=t_r[k]-t_v[k-1]}
\]
so in the \(z\)-domain,
\[
\Delta T(z)=T_r(z)-z^{-1}T_v(z)
\]
That is exactly the \(z^{-1}\) shown
in the feedback path.
S. Levantino, "Digital phase-locked loops," 2018 IEEE Custom
Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018
—, "Advanced digital phase-locked loops," Proceedings of the IEEE
2013 Custom Integrated Circuits Conference, San Jose, CA, USA,
2013, pp. 1-95 [https://sci-hub.jp/10.1109/CICC.2013.6658505]
N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its
Validity Limits Applied to Jitter Transfer and Jitter Generation," in
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55,
no. 11, pp. 3663-3675, Dec. 2008 [https://sci-hub.st/10.1109/TCSI.2008.925948]
Model at DCO Rate
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]
tr[h] in Fig. 5 is up-sampled and
zero-padded from tr[k] in Fig. 2. — zero-padded
transform of a signal in the slow domain \[
\boxed{\Delta t[h] = \left\{ \begin{array}{cl}
t_r[h]-t_d[h] & \text{when } h=0,\pm N,\pm 2N,... \\
0 & \text{otherwise}
\end{array} \right.}
\]
Taking the \(\mathcal{Z}\)-transform
of the discrete-time accumulator
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]
M. Zanuso, D. Tasca, S. Levantino, A. Donadel, C. Samori and A. L.
Lacaita, "Noise Analysis and Minimization in Bang-Bang Digital PLLs," in
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56,
no. 11, pp. 835-839, Nov. 2009 [https://sci-hub.st/10.1109/TCSII.2009.2032470]
TODO 📅
reference
Wang, Xu and Michael Peter Kennedy. “Jitter and Spur Minimization in
Fractional-N Digital Frequency Synthesizers - Modeling, Simulation,
Analysis, and Design Methodologies.” Analog Circuits and Signal
Processing (2026).
Brandonisio, F., & Kennedy, M. P. (2014). Noise-Shaping
All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and
Design. Springer.
Staszewski, Robert Bogdan and Poras T. Balsara. “All-digital
frequency synthesizer in deep-submicron CMOS.” (2006).
Michael H. Perrott, ISSCC 2008 Tutorial on Digital Phase-Locked
Loops
D. Pfaff, R. Abbott, X. -J. Wang, S. Moazzeni, R. Mason and R. R.
smith, "A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter
for Wireline Applications in 7-nm FinFET CMOS," in IEEE Journal of
Solid-State Circuits, vol. 55, no. 3, pp. 580-591, March 2020 [https://sci-hub.ru/10.1109/JSSC.2019.2946134]
N. Da Dalt, "Markov Chains-Based Derivation of the Phase Detector
Gain in Bang-Bang PLLs," in IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 53, no. 11, pp. 1195-1199, Nov. 2006 [https://sci-hub.st/10.1109/TCSII.2006.883197]
—, "A design-oriented study of the nonlinear dynamics of digital
bang-bang PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005 [https://sci-hub.se/10.1109/TCSI.2004.840089]
—, "Theory and Implementation of Digital Bang-Bang Frequency
Synthesizers for High Speed Serial Data Communications", PhD
Dissertation, RWTH Aachen University, Aachen, North Rhine-Westphalia,
Germany, 2007 [pdf]
Vladimir Dmitriev-Zdorov, Mentor Graphics, DesignCon 2014,
Computation of Time Domain Impedance Profile from S-Parameters:
Challenges and Methods [link]
# Pseudo code, laying out the essential steps only # Trace data is in x_values sampling_interval = np.mean(np.diff(x_values)) # First derivative diff_gamma_values = np.gradient(gamma_values) # FFT fourier_data = fft(diff_gama_values) # Get the frequencies corresponding to the FFT result frequencies = np.fft.fftfreq(len(diff_gama_values), d=sampling_interval) # Calculate the magnitude of the complex Fourier transform data magnitude = np.abs(fourier_data) # Return loss magnitude = 20 * np.log10(magnitude) # Plot (frequency, magnitude)
In principle, both methods should yield identical impedance profiles.
In practice, differences in S-parameter quality, bandwidth, and
simulation setup can lead to noticeable discrepancies. The poor quality
of the S-parameter data and improper simulation parameters caused the
two traces to differ
Non-causal data — Early arrival, pre-ringing
\[
\boxed{S(t) = \int_{-\infty}^{t} h(\tau) d\tau, \text{ with } S(\infty)
= H(0)}
\] pure phase manipulation (linear phase or nonlinear phase)
preserves the total area, and the TDR settles to the same final
impedance on the flat sections
Bogatin, Eric. 2020. Bogatin’s Practical Guide to Transmission
Line Design and Characterization for Signal Integrity Applications /
.Eric Bogatin. Artech House.
keysight, Signal Integrity Characterization Techniques [pdf]
Tim Wang-Lee, DesignCon 2026 KEF: Mastering TDR and De-embedding
Through Simulation and Measurement [link]
Noise generated earlier
travels farther; noise generated later travels less. The pulses
overlap, so adding more coupled sections increases their summed
amplitude
Each short section contributes in proportion to its length and the
edge slope: \[
dV_F\propto dx\,\frac{\Delta V}{t_r} \quad\Longrightarrow\quad
\boxed{V_{F,\text{peak}}\propto \ell\,\frac{\Delta V}{t_r}}
\]
Here, \(\ell\) means the
length over which the traces run alongside each other.
For comparison, backward noise arrives at \(x/v+x/v=2x/v\), so contributions from different locations
spread out in time. That explains why extending a sufficiently
long coupled line mainly increases the backward pulse’s duration
Wavelength vs. Frequency
Ali Sheikholeslami, ESSERC 2026 Circuit Insights: Fundamentals of
Circuit Design at High Frequencies
relative
dielectric constant vs permittivity
The relative dielectric constant characterizes some of the electrical
properties of an insulator
skin effect
& Dielectric loss
Return Path
ISSCC2002. Special Topic Evening Discussion Sessions SE1: Inductance:
Implications and Solutions for High-Speed Digital Circuits [vSE1_Blaauw],
[vSE1_Gauthier],
[vSE1_Morton,
[vSE1_Restle]]
Current return paths are frequency dependent \(Z = R +j\omega L\)
Low frequency
\(R\) dominates - current use as
many returns as possible to have parallel resistances
High frequency
\(j\omega L\) dominates - current
use the closest possible return path to form the smallest
possible loop inductance
Very high frequency
The current would be confined to the nearest possible
return only at ultra-high frequencies (skin effect)
EMX simulation
setup:
frequency sweep:
Cadence October 2020, Analysis of a Figure-Eight Inductor with
EMX RAK
RLGC can be extracted from measurements of a
transmission line's input impedance under open-circuit
and short-circuit terminations at a specific
frequency
# input data, must be 2-port S2P data sub = rf.Network(args.s2p, z0=args.z0_ohm)
# physical length must be supplied by user length = args.l_um*1e-6
# target frequency for pi model extraction f_target = args.f_ghz*1e9
assert f_target < freq.stop
# get index for exctraction f = freq.f ftarget_index = rf.find_nearest_index(freq.f, f_target) omega = 2*np.pi*f[ftarget_index]
z11=sub.z[0::,0,0] # z11, the open impedance y11=sub.y[0::,0,0] # 1/y11, the short impedance Zline = np.sqrt(z11/y11) # characteristic impedance of the line
R = (gamma_ftarget*Zline_ftarget).real L = (gamma_ftarget*Zline_ftarget).imag / omega G = (gamma_ftarget/Zline_ftarget).real C = (gamma_ftarget/Zline_ftarget).imag / omega
Raymond Y. Chen, Raymond Y. Chen. Fundamentals of S Fundamentals of
S-Parameter Parameter Modeling for Power Distribution Modeling for Power
Distribution System (PDS) and SSO Analysis System (PDS) and SSO Analysis
[https://ibis.org/summits/jun05/chen.pdf]
J. H. Mikkelsen, O. K. Jensen and T. Larsen, "Crosstalk coupling
effects of CMOS co-planar spiral inductors," Proceedings of the IEEE
2004 Custom Integrated Circuits Conference [https://sci-hub.jp/10.1109/CICC.2004.1358825]
P. Guan et al., "8-Shaped Inductors: An Essential Addition to RFIC
Designers' Toolbox," in IEEE Open Journal of the Solid-State Circuits
Society, vol. 4, pp. 131-146, 2024 [pdf]
Field picture
Partial-inductance picture
Transformer
Quantity
Symbol
Meaning
Formula
Magnetic flux
\(\Phi\)
Magnetic field \(\mathbf{B}\)
passing through area \(\mathbf{S}\)
\(\Phi = \int_S \mathbf{B}\cdot
d\mathbf{S}\)
Flux linkage
\(\lambda\)
Flux linked with coil turns\(N\)
\(\lambda = N\Phi\)
Induced EMF
\(\mathcal{E}\)
Voltage generated by changing flux linkage
\(\mathcal{E} =
-\mathrm{d}\lambda/\mathrm{d}t\)
Self-inductance
\(L\)
Flux linkage caused by own current
\(L = \lambda/i\)
Mutual inductance
\(M\)
Flux linkage caused by another coil's current
\(M = \lambda_{21}/i_1\)
Coupling coefficient
\(k\)
Magnetic coupling strength between inductors
\(k = M/\sqrt{L_1L_2}\)
ideal transformer
For an ideal N:1 transformer, \[
\boxed{V_1 = N V_2} \qquad \boxed{I_1 = -\frac{I_2}{N}}
\] The minus sign comes from power conservation\[
V_1 I_1 + V_2 I_2 = 0
\] so \[
N V_2 I_1 + V_2 I_2 = 0
\] therefore \[
I_1 = -\frac{I_2}{N}
\]
So Fig. 2.3 has exactly the same two-port equations as the original
coupled inductors
Electromotive Force (EMF)
\(\mathcal{E}\)
back emf
mutual inductance
\[
M_{12}=M_{21}=M \qquad \frac{N_1\Phi_{12}}{i_2}=\frac{N_2\Phi_{21}}{i_1}
=
M
\]
Important: this does not mean\[
\Phi_{12} = \Phi_{21}
\]
\(k\) vs. \(M\)
Coupling coefficient \(k\) is based on flux
linkage ratios, not directly magnetic flux ratios
Bogatin, E. (2018). Signal and power integrity, simplified.
Prentice Hall. [pdf]
Paul, Clayton R. Inductance: Loop and Partial. Hoboken, N.J.
: [Piscataway, N.J.]: Wiley ; IEEE, 2010. [pdf]
Spartaco Caniggia. Signal Integrity and Radiated Emission of
High‐Speed Digital Systems. Wiley 2008
Luong, H. C., & Yin, J. (2016). Transformer-based design
techniques for oscillators and frequency dividers. Springer
International Publishing
ISSCC2002. Special Topic Evening Discussion Sessions SE1: Inductance:
Implications and Solutions for High-Speed Digital Circuits [vSE1_Blaauw],
[vSE1_Gauthier],
[vSE1_Morton,
[vSE1_Restle]]
Y. Massoud and Y. Ismail, "Gasping the impact of on-chip inductance,"
in IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14-21, July
2001 [https://sci-hub.se/10.1109/101.950046]
magnetic field (magnetic flux density, \(B\)), is the tesla
(symbol: \(T\)), defined as one
weber per square meter (\(Wb/m^2\))
Magnetic flux \(\Phi_B\) measures
the total magnetic field (\(B\))
passing through a given surface area (\(A\)), representing the number of field
lines penetrating that area. Measured in Webers (\(Wb\)),
Vector Calculus
3Blue1Brown, Divergence and curl: The language of Maxwell's
equations, fluid flow, and more [https://youtu.be/rB83DpBJQsE]
Electric Fields in Matter &
Magnetic Fields in Matter
TODO 📅
Electric Fields
Electric
field intensity \(\mathbf E\) &
Electric flux density \(\mathbf
D\)
\[
\boxed{
\underbrace{\varepsilon_0\mathbf E}_{\text{contains free + bound charge
effects}}
+
\underbrace{\mathbf P}_{\text{cancels bound-charge divergence}}
=
\underbrace{\mathbf D}_{\text{free-charge Gauss law}}
}.
\] Start from Gauss’s law for the actual electric field: \[
\nabla\cdot(\varepsilon_0\mathbf E)
=
\rho_{\text{free}}+\rho_{\text{bound}}.
\] Polarization satisfies \[
\rho_{\text{bound}}=-\nabla\cdot\mathbf P.
\] Therefore, \[
\nabla\cdot(\varepsilon_0\mathbf E)
=
\rho_{\text{free}}-\nabla\cdot\mathbf P.
\] Move the polarization term to the left: \[
\nabla\cdot(\varepsilon_0\mathbf E+\mathbf P)
=
\rho_{\text{free}}.
\] Define \[
\mathbf D=\varepsilon_0\mathbf E+\mathbf P.
\]
Electric field intensity \(\mathbf E\)
Gauss's law for \(\mathbf E\) is
\[
\boxed{
\nabla\cdot\mathbf E
=
\frac{\rho_{\text{total}}}{\varepsilon_0}
}
\] where \[
\rho_{\text{total}}
=
\rho_{\text{free}}+\rho_{\text{bound}}.
\] Therefore, \(\mathbf E\) is
determined by all charges:
externally supplied free charges,
polarization-induced bound charges.
In integral form, \[
\oint_S \mathbf E\cdot d\mathbf S
=
\frac{Q_{\text{total,enclosed}}}{\varepsilon_0}.
\]
Electric flux density \(\mathbf
D\)
Gauss's law for \(\mathbf D\) is
\[
\boxed{
\nabla\cdot\mathbf D=\rho_{\text{free}}
}
\] or \[
\boxed{
\oint_S\mathbf D\cdot d\mathbf S
=
Q_{\text{free,enclosed}}
}
\] Thus, \(\mathbf D\) is
constructed so that dielectric bound charge is absorbed into the
constitutive relation \[
\mathbf D=\varepsilon_0\mathbf E+\mathbf P.
\] It therefore relates directly only to free charge
Gauss's law for
\(\mathbf{E}\) & Gauss's law for
\(\mathbf{D}\)
\[
\boxed{
\begin{aligned}
\nabla\cdot\mathbf E
&=\frac{\rho_{\text{total}}}{\varepsilon_0},
\\[4pt]
\nabla\cdot\mathbf D
&=\rho_{\text{free}}.
\end{aligned}
}
\]
So when a textbook writes \[
\oint_S\mathbf D\cdot d\mathbf S
=
\int_V\rho_v\,dV,
\] the symbol \(\rho_v\)
normally means \[
\boxed{\rho_v=\rho_{v,\text{free}}}.
\] But when it writes \[
\oint_S\mathbf E\cdot d\mathbf S
=
\frac{1}{\varepsilon_0}\int_V\rho_v\,dV,
\] then \(\rho_v\) means the
total volume-charge density, unless the context
explicitly assumes vacuum or no polarization
Magnetostatics
Magnetostatics is the study of magnetic
fields in systems where the currents are steady (not
changing with time)
Relationship between
\(\mathbf B\) and \(\mathbf H\)
The central distinction is \[
\boxed{
\mathbf H\text{ tracks the free-current excitation, while }
\mathbf B\text{ is the resulting total magnetic flux density.}
}
\]
The general macroscopic relation is \[
\boxed{
\mathbf B=\mu_0\left(\mathbf H+\mathbf M\right)
}
\] where
\(\mathbf M\) is the magnetization
density of the material,
\(\mu_0\mathbf H\) represents the
part separated from material magnetization,
\(\mu_0\mathbf M\) is the
contribution caused by magnetic dipoles inside the material.
Therefore, \[
\boxed{
\mathbf H=\frac{\mathbf B}{\mu_0}-\mathbf M
}.
\] In vacuum
There is no material magnetization: \[
\mathbf M=0.
\] Hence, \[
\boxed{\mathbf B=\mu_0\mathbf H}.
\] In a linear, isotropic material
If \[
\mathbf M=\chi_m\mathbf H,
\] then \[
\mathbf B
=
\mu_0(1+\chi_m)\mathbf H.
\] Define \[
\mu_r=1+\chi_m,
\qquad
\mu=\mu_0\mu_r.
\] Then \[
\boxed{\mathbf B=\mu\mathbf H}.
\]
Suppose a coil carries a free current \(I\).
The free current produces an \(\mathbf
H\) field. If a magnetic material is placed inside the coil, the
material becomes magnetized: \[
I_{\mathrm{free}}
\longrightarrow
\mathbf H
\longrightarrow
\mathbf M.
\] The resulting total magnetic flux density is \[
\mathbf B=\mu_0(\mathbf H+\mathbf M).
\] Therefore: \[
\boxed{
\mathbf H
\text{ is related to the applied free current}
}
\] while \[
\boxed{
\mathbf B
\text{ includes both the applied field and the material response}.
}
\] For the same coil current, \(\mathbf
H\) may remain approximately the same, but inserting a
high-permeability core can greatly increase \(\mathbf B\).
Magnetic field intensity
\(\mathbf H\)
It is introduced to describe magnetic fields in matter while
separating the material’s magnetization from externally supplied, or
free, currents.
The Maxwell–Ampère law is \[
\boxed{
\nabla\times\mathbf H
=
\mathbf J_{\mathrm{free}}
+
\frac{\partial\mathbf D}{\partial t}
}
\] or, in integral form, \[
\boxed{
\oint_C\mathbf H\cdot d\mathbf l
=
I_{\mathrm{free}}
+
\int_S\frac{\partial\mathbf D}{\partial t}\cdot d\mathbf S
}.
\] Thus, the circulation of \(\mathbf
H\) is associated with free current.
Magnetic Flux Density \(\mathbf B\)
\(\mathbf B\) determines the
magnetic force on a moving charge.
It also defines magnetic flux: \[
\boxed{\Phi_B=\int_S\mathbf B\cdot d\mathbf S}
\] and appears in Faraday's law: \[
\oint_C\mathbf E\cdot d\mathbf l
=
-\frac{d}{dt}
\int_S\mathbf B\cdot d\mathbf S.
\] Gauss's law for magnetism is \[
\boxed{\nabla\cdot\mathbf B=0}
\] or \[
\boxed{\oint_S\mathbf B\cdot d\mathbf S=0}.
\] This is universally valid because magnetic monopoles have not
been observed.
If \[
\mathbf B=\mu\mathbf H,
\qquad
\mathbf D=\varepsilon\mathbf E,
\] with constant \(\mu\) and
\(\varepsilon\), then \[
\boxed{
\oint_C\mathbf B\cdot d\mathbf l
=
\mu I_{\mathrm{free}}
+
\mu\varepsilon
\int_S
\frac{\partial\mathbf E}{\partial t}\cdot d\mathbf S
}
\]
Gauss’s law for magnetism
The universally valid equation is \[
\boxed{\oint_S \mathbf B\cdot d\mathbf S=0}
\] or \[
\nabla\cdot\mathbf B=0.
\] This expresses that magnetic field lines have no beginning or
end—there are no observed magnetic monopoles
\[
\boxed{
\oint_S\mathbf B\cdot d\mathbf S=0
\text{ always, while }
\oint_S\mathbf H\cdot d\mathbf S=0
\text{ only under additional conditions.}
}
\] i.e. \(\mathbf B=\mu\mathbf
H\)
A. Sheikholeslami, "Current Without Electrons [Circuit Intuitions],"
in IEEE Solid-State Circuits Magazine, vol. 17, no. 4, pp. 8-10, Fall
2025
—, "Current Without Electric Field [Circuit Intuitions]," in IEEE
Solid-State Circuits Magazine, vol. 18, no. 1, pp. 8-12, winter
2026
energy and information are carried by electric and magnetic fields
(\(E\) and \(H\)) rather than by electron drift
proximity effect & skin
effect
Skin effect concentrates current near the
surface of a single conductor, while
proximity effect concentrates current in specific
regions of multiple conductors due to their
interaction
Skin effect is caused by the conductor's
own magnetic field, while proximity effect is
caused by the magnetic field of a nearby
conductor
proximity effect is a redistribution of
electric current occurring in nearby parallel
electrical conductors carrying alternating current
(AC), caused by magnetic effects (eddy
currents)
skin effect is the tendency of
AC current flow near the surface (or "skin")
of a conductor, rather than throughout its cross-section, due to the
magnetic field generated by the current
itself
Cause of skin effect
A main current \(I\) flowing through
a conductor induces a magnetic field \(H\). If the current increases, as in this
figure, the resulting increase in \(H\)
induces separate, circulating eddy currents\(I_W\) which partially cancel the
current flow in the center and reinforce it near the skin
Eddy current
By Lenz's
law, an eddy current creates a magnetic field that
opposes the change in the magnetic field that
created it, and thus eddy currents react back
on the source of the magnetic field
reference
Griffiths, David J. Introduction to Electrodynamics. Fifth
edition. Cambridge University Press, 2024. [pdf]
David Smith, Electromagnetic Theory for Complete Idiot, 2021
import numpy as np import matplotlib.pyplot as plt from scipy import signal
# Parameters: 4th order filter with 1kHz cutoff order = 4 w_cutoff = 2 * np.pi * 1000 w = np.logspace(2, 5, 1000) # Frequency range from 100Hz to 100kHz
# Generate Butterworth coefficients and frequency response b_but, a_but = signal.butter(order, w_cutoff, analog=True) w_but, h_but = signal.freqs(b_but, a_but, worN=w)
% Parameters wc = 100; % Cutoff frequency in rad/s orders = [1, 2, 6]; % Orders to compare w = logspace(0, 3, 1000); % Frequency range (1 to 1000 rad/s)
for n = orders % 1. Design Analog Filter (the 's' flag is critical) [b, a] = butter(n, wc, 's'); % 2. Calculate Complex Frequency Response h = freqs(b, a, w); % 3. Calculate Group Delay % For analog filters, we manually differentiate phase: gd = -d(phi)/dw phase = unwrap(angle(h)); gd = -diff(phase) ./ diff(w); % --- Plot Magnitude (dB) --- subplot(3,1,1); semilogx(w, 20*log10(abs(h)), 'LineWidth', 2, 'DisplayName', ['n=' num2str(n)]); hold on; % --- Plot Phase (Degrees) --- subplot(3,1,2); semilogx(w, phase * 180/pi, 'LineWidth', 2); hold on; % --- Plot Group Delay --- subplot(3,1,3); semilogx(w(1:end-1), gd, 'LineWidth', 2); hold on; end
Bessel filter is often called Bessel–Thomson
filter or simply Thomson filter
besself: Bessel analog filter design
[b,a] = besself(n, Wo)
the transfer function coefficients of an \(n\)th-order lowpass analog Bessel filter,
where Wo is the angular frequency up to which the filter's
group delay is approximately constant. Larger values of n
produce a group delay that better approximates a constant up to
Wo.
C. K. Singh and G. C. Temes, "R-C Ladder Design: A Tutorial [CAS
Education]," in IEEE Circuits and Systems Magazine, vol. 24,
no. 4, pp. 65-69, Fourthquarter 2024 [https://sci-net.xyz/10.1109/MCAS.2024.3462661]
Bode's noise theorem holds only for linear, passive networks
in thermal equilibrium, meaning every lossy element is at the
same temperature T and the only noise is the thermal noise of that
loss.
A short circuit is the limit of a capacitor with
infinite capacitance, since its impedance go to 0 only
when capacitance go to infinity.
For 1st RC filter, \(C_\infty=C\),
and \(C_0\) (the capacitance "seen" at
the output) is \(C\) in parallel with a
short, which is infinite, i.e. \(C_0=C+\infty=\infty\)\[
V_n^2=kT(\frac{1}{C} - \frac{1}{\infty})=\frac{kT}{C}
\]
x(t) ──┬── R ──┬── y(t) │ │ │ C │ │ └───────┴── gnd
Three discretizations of the same continuous prototype, all valid
first-order LPFs but with different sample-domain behavior \(\alpha = \frac{T}{T+\tau}\):
Form
Difference equation
Transfer function
Notes
Backward Euler (above)
\(y_n = (1-\alpha) y_{n-1} + \alpha\,
x_n\)
\(\dfrac{\alpha}{1 - (1-\alpha)
z^{-1}}\)
Implicit; needs \(x_n\) before
computing \(y_n\)
Delayed leaky integrator
\(y_n = (1-\alpha) y_{n-1} + \alpha\,
x_{n-1}\)
\(\dfrac{\alpha z^{-1}}{1 - (1-\alpha)
z^{-1}}\)
One extra sample of delay; same magnitude response
Pole magnitude \(|1-\alpha| < 1\)
always — backward Euler is unconditionally stable,
unlike forward Euler (\(\alpha =
T/\tau\)), which goes unstable when \(T
> 2\tau\)
All four collapse to the same continuous-time filter as \(T \to 0\), but they're not interchangeable
at finite \(T\) — the delayed leaky
integrator in particular adds one sample of group delay that the others
don't.
Boris Murmann. EE315A VLSI Signal Conditioning Circuits
Bill Redman-White, ISSCC 2009 Tutorial: T1 : Continuous-Time
Filters
B. Nikolic, "Tutorial: Filtering in RF Transceivers," 2014 IEEE
International Solid-State Circuits Conference Digest of Technical Papers
(ISSCC), San Francisco, CA, USA, 2014
W. Sansen, "Short Course: Power Limits for Amplifiers and Filters,"
2012 IEEE International Solid-State Circuits Conference, San
Francisco, CA, USA, 2012
Antonio Liscidini, 2018 New Trends in Analog Filters
M. Babaie, "Tutorial: Role of Current-Mode Passive Mixers and N-Path
Filters in RF Receivers," 2023 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2023
