KNOW-HOW

Jitter and Edge phase noise

[https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/56929/how-to-derive-edge-phase-noise-from-output-noise-in-sampled-pnoise-simulation/1388888]

Phase Noise Aliasing & Integration Limits

These two types of measurements deliver the same rms jitter of \(f_{CK}\)

• both rising and falling: integrated from \(-f_{CK}\) to \(+f_{CK}\)
• only the rising (or falling) edges: integrated from \(-f_{CK}/2\) to \(+f_{CK}/2\)

temporal autocorrelation and Wiener-Khinchin theorem is more appropriate to arise rms value

Y. Zhao and B. Razavi, "Phase Noise Integration Limits for Jitter Calculation,"[https://www.seas.ucla.edu/brweb/papers/Conferences/YZ_ISCAS_22.pdf]

time-average noise (phase-noise) & sampled noise (edge-phase noise or jitter) spectrum

Time-average noise analysis

\(S_{\Delta f}(f)\) between \([\Delta f, F_0/2]\) may be less than that of other harmonic window

Sampled noise analysis

correlation

VCO Phase Noise

pnoise - timeaverage

1. Direct Plot/Pnoise/Phase Noise or

   

2. manually calculate by definition

   

3. output noise with unit dBc

   Direct Plot/Pnoise/Output Noise Units:dBc/Hz and Noise convention: SSB

   

The above method 2 and 3 only apply to timeaveage pnoise simulation,

pnoise - sampled(jitter)/Edge Crossing

Direct Plot/Pnoise/Edge Phase Noise or

Another way, the following equation can also be used for sampled(jitter)/Edge Crossing

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PhaseNoise(dBc/Hz) = dB20( OutputNoise(V/sqrt(Hz)) / slopeCrossing / Tper*twoPi ) - dB10(2)

where dB10(2) is used to obtain SSB from DSB

Output Noise of sampled(jitter) pnoise

The last section's Output Noise (V**2/Hz) can be obtained by transient noise simulation

The idea is that sample waveform with ideal clock, subtract DC offset, then fft(psd)

• samplesRaw = sample(wv)
• samplePost = samplesRaw - average(samplesRaw)
• Output Noise (V**2/Hz) = psd(samplePost)

Expression:

The computation cost is typically very high, and the accuracy is lesser as compared to PSS/Pnoise

Pnoise Sampled(jitter): Sampled Phase Option

• Identical to noisetype=timedomain in old GUI
• Use model:
  • Sampleds Per Period: number of ponits
  • Add Specific Points: specific time point, still time points

pss beat freq = 5GHz

pnoise sweeptype: absolute, from 100k to 2.5GHz

Transient noise

phase noise from transient noise analysis

1. The Phase Noise function is now available in the Direct Plot form (Results-Direct Plot-Main Form) after Transient Analysis is run
   • Absolute jitter Method
   • Direct Power Spectral Density Method
2. PN phase noise function
   • Absolute jitter Method
   • Direct Power Spectral Density Method

Absolute jitter Method: Phase noise is defined as the power spectral density of the absolute jitter of an input waveform

and absolute jitter method is the default method

In below discussion, we only think about the absolute jitter method

PSD and Phase Noise

• phase noise is single-sideband
• psd is double-sideband
• Then the ratio is 2

By PSS_Pnoise

jee

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rfEdgePhaseNoise(?result "pnoise_sample_pm0" ?eventList 'nil) + 10 * log10(2)

convert single-sideband phase noise to psd by multiplying 2 or 10 * log10(2)

By trannoise PN function

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PN(clip(VT("/Out1") 2.60417e-08 0.000400052) "rising" 1.65 ?Tnom (1 / 3.84e+07) ?windowName "Rectangular" ?smooth 1 ?windowSize 15000 ?detrending "None" ?cohGain 1 ?methodType "absJitter")

double-sideband psd

By trannoise psd and abs_jitter function

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dB10(psd(abs_jitter(clip(VT("/Out1") 2.60417e-08 0.000400052) "rising" 1.65 ?Tnom (1 / 3.84e+07)) 2.60417e-08 0.000400052 15360 ?windowName "Rectangular" ?smooth 1 ?windowSize 15000 ?detrending "None" ?cohGain 1))

double-sideband psd

abs_jitter Y-Unit default is rad

Comparison

PN's result is same with psd's

RMS value

• build the abs_jitter function with seconds as the Y axis and add the stddev function to determine the Jee jitter value
• or integrate psd

The RMS \(x_{\text{RMS}}\) of a discrete domain signal \(x(n)\) is given by \[ x_{\text{RMS}}=\sqrt{\frac{1}{N}\sum_{n=0}^{N-1}|x(n)|^2} \] Inserting Parseval's theorem given by \[ \sum_{n=0}^{N-1}|x(n)|^2=\frac{1}{N}\sum_{n=0}^{N-1}|X(k)|^2 \] allows for computing the RMS from the spectrum \(X(k)\) as \[ x_{\text{RMS}}=\sqrt{\frac{1}{N^2}\sum_{n=0}^{N-1}|X(k)|^2} \]

Remarks

Cadence Spectre's PN function may call abs_jitter and psd function under the hood.

reference

Article (11514536) Title: How to obtain a phase noise plot from a transient noise analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nb1CEAQ

Article (20500632) Title: How to simulate Random and Deterministic Jitters URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fiXeEAI

Cadence, Application Note: Understanding the relations between time-average noise (phase-noise) and sampled noise (edge-phase noise or jitter) in Pnoise analysis

Tutorial on Scaling of the Discrete Fourier Transform and the Implied Physical Units of the Spectra of Time-Discrete Signals Jens Ahrens, Carl Andersson, Patrik Höstmad, Wolfgang Kropp URL: https://appliedacousticschalmers.github.io/scaling-of-the-dft/AES2020_eBrief/

PSRR (Power Supply Rejection Ratio)

A good PSRR is important when an LDO is used as a sub-regulator in cascade with a switching regulator

The LDO would need to have a sufficiently high rejection at the switching frequency of the switching converter to filter out the ripples at that frequency

PMOS LDO

A large output capacitor solves the sudden load change problem, but the stability decreases because the large output capacitor forces the output pole toward the origin with the role of dominant pole

DC output impedance

The output impedance of the LDO at DC is known as its load regulation

DC output impedance of NMOS and PMOS LDO is the same for the same error amplifier gain

\[ R_{\text{out}} = \frac{1}{\beta A_{o1} g_{m2}} \]

The NMOS LDO has a faster response to line transients than the PMOS LDO since it has better (smaller) PSRR

Power MOS gain affect on PMOS LDO

DC gain \[ A_{dc} = g_mR_\text{ota} A_2 \] 3dB bandwidth \[ \omega_p = \frac{1}{R_\text{ota}(C_g+A_2C_c)} \] and GBW \[ \omega_u = \frac{g_m}{\frac{C_g}{A_2}+C_c} \]

Feedforward Compensation with \(C_\text{FF}\)

• Improved Noise
• Improved Stability and Transient Response
• Improved PSRR

\[\begin{align} R_1 \parallel \frac{1}{sC_{FF}} &= \frac{R_1}{1+sR_1C_{FF}} \\ Z_o &= \left( R_1\parallel \frac{1}{sC_{FF}}+R_2\right)\parallel \frac{1}{sC_L} \\ &=\frac{R_1+R_2+sR_1R_2C_{FF}}{s^2R_1R_2C_{FF}C_L + s[(R_1+R_2)C_L+R_1C_{FF}]+1} \\ A_{V2} &= g_m Z_o \\ &= g_m \frac{R_1+R_2+sR_1R_2C_{FF}}{s^2R_1R_2C_{FF}C_L + s[(R_1+R_2)C_L+R_1C_{FF}]+1} \\ \beta &= \frac{R_2}{\frac{R_1}{1+sR_1C_{FF}}+R_2} \\ &= \frac{R_2(1+sR_1C_{FF})}{R_1+R_2+sR_1R_2C_{FF}} \\ A_{V2}\beta &= \frac{g_mR_2(1+sR_1C_{FF})}{s^2R_1R_2C_{FF}C_L+s[(R_1+R_2)C_L+R_1C_{FF}]+1} \end{align}\]

That is, adding a \(C_{FF}\) also introduces a zero (\(\omega_z\)) and pole (\(\omega_p\)) into the LDO feedback loop

\[\begin{align} \omega_{po} &= \frac{1}{(R_1+R_2)C_L} \\ \omega_z &= \frac{1}{R_1C_{FF}} \\ \omega_{p} &= \frac{1}{(R_1 \parallel R_2)C_{FF}} \end{align}\]

Application Report SBVA042–July 2014, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator [https://www.ti.com/lit/an/sbva042/sbva042.pdf]

LDO Basics: Noise – How a Feed-forward Capacitor Improves System Performance [https://www.ti.com/document-viewer/lit/html/SSZTA13]

LDO Basics: Noise – How a Noise-reduction Pin Improves System Performance [https://www.ti.com/document-viewer/lit/html/SSZTA40]

NMOS Slave LDO

\[\begin{align} \frac{V_g}{V_i} &=\frac{R||\frac{1}{s(C_g+C_{gs})}}{R||\frac{1}{s(C_g+C_{gs})}+\frac{1}{sC_{gd}}} \\ &= \frac{sRC_{gd}}{sR(C+C_{gd}+C_{gs})+1} \end{align}\] \[ \frac{V_g}{V_i} = -\frac{sC_{ds}+g_{ds}}{sC_{gs}+g_m} \]

That is, \[ \omega_{z,d} \simeq \frac{1}{R(\frac{g_m}{g_{ds}}C_{gd}+C)} \]

The calculating PSRR pole approach similar with zero, just \(V_o\) to \(V_i\) zero \[ \omega_{p,d} \simeq \frac{1}{R(\frac{C_s}{g_mR}+C)} \]

DC PSRR \[ \text{PSRR} = \frac{1}{g_mr_o} \]

PSRR @Vgate

KCL at output node

\[ g_m(-V_o\beta A_{E} - V_o) + \frac{V_i - V_o}{r_o} = \frac{V_o}{R_1+R_2} \]

Hence \[ \frac{V_o}{V_i} = \frac{1}{A_E\beta g_mr_o+g_mr_o +\frac{r_o}{R_1+R_2}+1} \approx \frac{1}{A_E\beta g_m r_o} \]

Through feedback loop, we derive \[ V_g = V_o \beta (-A_E) \approx \frac{V_i}{A_E\beta g_m r_o} \beta (-A_E) = -\frac{V_i}{g_mr_o} \]

That is \[ \frac{V_g}{V_i} \approx -\frac{1}{g_mr_o} \]

Due to closed loop, \(V_g\) and \(V_o\) is not source follower

High frequency PSRR

feedback resistor divider noise

assuming \(\text{LG} \gg 1\)

\[\begin{align} I_\text{t} &= \frac{V_\text{ref} - v_\text{n2}}{R_\text{2}} \\ V_\text{o} &= V_\text{ref} +v_\text{n1} + I_\text{t}R_\text{1} \\ \end{align}\]

Then \[ V_\text{o} = \frac{R_1+R_2}{R_2}V_\text{ref} + v_\text{n1} - \frac{R_1}{R_2}v_\text{n2} \] that is

\[ v_\text{no}^2 = v_\text{n1}^2 + \left(\frac{R_1}{R_2}\right)^2 v_\text{n2}^2 \]

\[ \text{vno1}^2= \text{vn1}^2+\text{vn2}^2/6^2=16.5758 + 99.45453/6^2 = 19.338425833 \]

reference

Hinojo, J.M., Martinez, C.I., & Torralba, A.J. (2018). Internally Compensated LDO Regulators for Modern System-on-Chip Design.

Chen, K.-H. (2016). Power Management Techniques for Integrated Circuit Design. Wiley-IEEE Press.

Morita, B.G. (2014). Understand Low-Dropout Regulator ( LDO ) Concepts to Achieve Optimal Designs.

H. -S. Kim, "Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable approaches that preserve performance," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 59-68, Spring 2023, doi: 10.1109/MSSC.2023.3262767.

Ali Sheikholeslami, Circuit Intuitions: Voltage Regulators IEEE Solid-State Circuits Magazine, Vol. 12, Issue 4, to appear, Fall 2020.

Operational Transconductance Amplifier II Multi-Stage Designs [https://people.eecs.berkeley.edu/~boser/courses/240B/lectures/M07%20OTA%20II.pdf]

Toshiba, Load Transient Response of LDO and Methods to Improve it Application Note [https://toshiba.semicon-storage.com/info/application_note_en_20210326_AKX00312.pdf?did=66268]

Carusone, Tony Chan, David Johns, and Kenneth Martin. Analog integrated circuit design. John wiley & sons, 2011. [https://mrce.in/ebooks/Analog%20Integrated%20Circuit%20Design%202nd%20Ed.pdf]

Pavan Kumar Hanumolu. CICC 2015. "Low Dropout Regulators" [https://uofi.app.box.com/v/CICC15-LDO]

Mingoo Seok. ISSCC 2020 T7: "Basics of Digital Low-Dropout (LDO) Integrated Voltage Regulator" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T7Visuals.pdf]

Yan Lu, ISSCC2021 T10: "Fundamentals of Fully Integrated Voltage Regulators" [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T10.pdf]

Hyun-Sik Kim, Low-Dropout (LDO) Voltage Regulators – From Basics to Recent Design Trends (presented in A-SSCC 2022) [pdf]

A. Raychowdhury. ISSCC 2024 T2: Fundamentals of Digital and Digitally-Assisted Linear Voltage Regulators

Voltage scattering

characteristic impedance (\(Z_0\))

TODO 📅

Remember, S-parameters don't mean much unless you know the value of the reference impedance (it's frequently called Z0).

simulator will read sp file's Z0 parameter

The default Z0 exported by EMX is 50

Voltage Transfer Function

Reflection Coefficients

Rational Fit

Matlab/rationalfit

To resolve the convergence problem of s-parameter in Spectre simulator - rationalfit and write Verilog-A

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filename  = 'touchstone/ISI.S4P';
s4p = read(rfdata.data, filename);
sdd_params = s2sdd(s2p.S_Parameters, 2);
sdd21 = squeeze(sdd_params(2, 1, :));   % s21
freq = s4p.Freq;

% rational fitting
weight = ones(size(sdd21));
weight(floor(end*3/4):end) = 0.2;
weight(2:10) = 0;

[hfit, errb] = rationalfit(freq, sdd21, 'IterationLimit', [4, 16], 'Delayfactor', 0.98, ...
    'Weight', weight, 'Tolerance', -38, 'NPoles', 32);
[sdd21_fit, ff] = freqresp(hfit, freq);

figure(1)
plot(freq/1e9, db(sdd21), 'b-'); hold on;
plot(ff/1e9, db(sdd21_fit), 'r-'); hold off; grid on;
legend('sdd21', 'sdd21\_fit');
xlabel('Freq (GHz)');
ylabel('magnitude (dB)');


ts = 1e-12;
n = 2^18;
trise = 4e-14;
[yout, tout] = stepresp(hfit, ts, n, trise);
figure(2)
plot(tout*1e12, yout, 'b-'); grid on;
xlabel('Time (ps)');
ylabel('V');
title('Step Response');


% write verilog-A
writeva(hfit, 'channel_32poles.va');

reference

microwaves101, S-parameters (https://www.microwaves101.com/encyclopedias/s-parameters)

Pupalaikis, P. (2020). S-Parameters for Signal Integrity. Cambridge: Cambridge University Press. doi:10.1017/9781108784863

Coelho, C. P., Phillips, J. R., & Silveira, L. M. (n.d.). Robust rational function approximation algorithm for model generation. Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). doi:10.1109/dac.1999.781313

Cadence IEEE IMS 2023, Introducing the Spectre S-Parameter Quality Checker and Rational Fit Model Generator [https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009lplhEAA]

The Complex Art Of Handling S-Parameters: The importance of extraction and fitting to circuit simulation involving S-parameters [https://semiengineering.com/the-complex-art-of-handling-s-parameters]

Dr. John Choma. EE 541, Fall 2006: Course Notes #2 Scattering Parameters: Concept, Theory, and Applications [https://www.ieee.li/pdf/essay/scattering_parameters_concept_theory_applications.pdf]

Dr. Ray Kwok . Network Techniques: Conversion between Filter Transfer Function and Filter Scattering (SMatrix) Parameters [https://www.sjsu.edu/people/raymond.kwok/docs/project172/FTF%20to%20S-Matrix%20Spring%202011.pdf]

Three fast time-domain system simulation techniques:

• single-bit response method
• double-edge response method
• multiple-edge response method

Single-Bit Response (SBR) Method

Overlapping portions of a pulse response from neighboring bits are referred to as intersymbol interference (ISI). A received waveform is formed by superimposing, in time, the pulse responses of each bit in the sequence, as illustrated in Figure 9, assuming symmetric positive and negative pulses are transmitted for 1s and 0s

To avoid spurious glitches between consecutive ones, rising and falling edge responses shall be symmetric. This is the limitation of SBR method.

Let \(p(t)\) be the SBR of the channel, \(t_s\) be the data sampling phase, \(T\) be the bit time, \(N_c\) is the number of UI in stored pulse response and \(b_m\) be the \(m\)th transmitted symbol. The voltage seen by the receiver's data sampler at the \(m\)th data sample is determined by \[ y_m = \sum_{k=m-N_c+1}^{m}b_kp(t_s+(m-k)T) \] where \(b_k \in [0, 1]\) and \(p(t) \ge 0\)

We always prepend \(Nc-1\) 0s in random bit stream for consistency.

For computation convenient, the pulse need to be positive. For differential signal and amplitude \(V_{peak}\), the peak to peak is \(-V_{peak}\) to \(+V_{peak}\). After pulse added by \(V_{peak}\), peak to peak is \(0\) to \(+2V_{peak}\).

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hold on;

yy_sum = zeros(OSR*Ns, Ns);
for idxBit = 1:Ns
    bs_split = zeros(1, Ns+Nc-1);
    bs_split(idxBit) = bs(idxBit);
    yy = zeros(OSR, Ns);
    for ii = Nc:Nc+Ns-1
        bb = bs_split(ii:-1:ii-Nc+1);
        yy(:,ii-Nc+1) = sum(bb.*yrps, 2);
    end
    yy_cont2 = reshape(yy, [], 1);
    h = plot(yy_cont2);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
    yy_sum(:, idxBit) = yy_cont2;
end
yy_sum = sum(yy_sum, 2);    % merge
plot(yy_sum, 'k--');
plot(yy_cont, 'm-.');
grid on;
legend('sum', 'syn');
title('merge all single bit');
ylabel('mag');
xlabel('Time (\times Ts)');

The pulse response contain rising and falling edge. The 1 bit first rise from -1 to 1, then fall to -1; The 0 bit just do nothing for synthesized waveform with the help of falling edge of 1 bit.

The DC shift help deal with continuous 0 bits.

another SBR example

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A = zeros(10,21);
n = [1:10];

% post cursor
for m = 1:3
    A(m, 11+n(m)) = 0.5;
    A(m, 11-n(m)) = 0.5;
end

% one
for m = 4:10
    A(m, 11) = 1;
end

% h0 or main cursor
h0 = zeros(1, 21);
h0(1, 1) = 0.5;
h0(1, 21) = 0.5;
out = h0;

for m = 1:10
    out = conv(out, A(m, :), "full");
end


stem(out)

Double-Edge Response (DER) Method

To handle the more general cases, with asymmetric rising and falling edges, the system response can be constructed in terms of edge transitions instead of bit responses.

The DER method decomposes the input data pattern, in terms of rising and falling edge transitions. The system response can be calculated by superimposing the shifted versions of the rising and falling edge responses : \[ y_m = \sum_{k=m-N_c+1}^{m}(b_k-b_{k-1})s_k(t_s+(m-k)T) + y_{int} \] where

\[\begin{align} s_i(t) &= r(t) -V_{low} \quad \text{if} \: (b_i\gt b_{i-1}) \\ &= V_{high}-f(t) \quad \text{otherwise} \end{align}\]

\(r(t)\) and \(f(t)\) are the rising and falling edge responses,respectively. \(V_{high}\) and \(V_{low}\) are the steady state DC levels, in response to a constant stream of ones and zeros, respectively. \(y_{int}\) is the initial DC state (either \(V_{high}\) or \(V_{low}\) ).

We always prepend \(Nc\) 0s in random bit stream for consistency.

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figure(1)
subplot(3, 1, 1)
plot(yrc);
hold on;
plot(yfc);
hold off;
legend('rising', 'falling')
grid on;
ylabel('mag');
xlabel('Time (\times Ts)');
title('step response');

subplot(3, 1, 2)
stem(bs, 'k'); grid on;
hold on;
stem((idxPreRspStart:idxPreRspEnd), bs(idxPreRspStart:idxPreRspEnd), "filled", 'r');
stem(idxPreRspStart, bs(idxPreRspStart), 'go');
stem(idxCurData, bs(idxCurData), "filled", 'm');
stem((idxPreRspStart:idxPreRspEnd)+0.5, 0.1.*bd(idxPreRspStart:idxPreRspEnd), 'bd-.');
hold off;
legend('', 'Nc bits', 'y_{int}', 'Current bit', 'Edge Transitions');
ylabel('mag');
xlabel('Time (\times UI)');
title('input stream');

subplot(3, 1, 3)
yy_cont = reshape(yy, [], 1);   % continuous version
plot(yy_cont); grid on;
title('continuous yout')
ylabel('mag');
xlabel('Time (\times Ts)');

figure(2)
hold on;
for idx = idxPreRspStart+1-Nc:idxCurData+32-Nc
    ys = yy(:, idx);
    tt = ((idx-1)*OSR+1:idx*OSR);
    h = plot(tt(:), ys(:), 'LineWidth',3);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
end
plot(yy_cont, 'm--', 'LineWidth',1);
hold off;
legend('syn')
ylabel('mag');
xlabel('Time (\times Ts)');
title('synthesize with step response');
grid on;

Reference

T. C. Carusone, "Introduction to Digital I/O: Constraining I/O Power Consumption in High-Performance Systems," in IEEE Solid-State Circuits Magazine, vol. 7, no. 4, pp. 14-22, Fall 2015

Oh, Kyung Suk Dan, and Xing Chao Chuck Yuan. High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting. Prentice Hall, 2011.

Ren, Jihong and Kyung Suk Oh. “Multiple Edge Responses for Fast and Accurate System Simulations.” IEEE Transactions on Advanced Packaging 31 (2008): 741-748.

Shi, Rui. “Off-chip wire distribution and signal analysis.” (2008).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

Matlab - pulse2stateye

Due to this function only output PDF of eye, postprocessing is needed which cumulative sum PDF.

Probability Density Function(PDF) plot

Bit Error Rate(BER) plot

pulse response

DC shift don't affect pulse2stateye function normally

Both pulse [0 0 0 0 .. 0 1 0 0 0 0 0 ...] and [1 1 1 1 ... 1 0 1 1 1 1 ...] can be fed into

pulse2stateye function

CAUTION: the 0 don't mean common voltage but bit 0 , which is -Vpeak in differential link

postprocessing function

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% REF: https://www.mathworks.com/help/serdes/ref/pulse2stateye.html
load('PulseResponseReflective100ps.mat');
modulation = 2;
pulsewave = zeros(size(pulse, 1), 1);
pulsewave = pulse(:, 1);
pulsewave(:,1) = pulsewave - pulsewave(1);  % DC shift, although `pulse2stateye` shift internally

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
%stateye(1:200, 1:200) = 10000;
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')

[ysize, xsize] = size(stateye);
ymid = floor((ysize+1)/2);
upperEyePDF = stateye(ymid:end,:);
lowerEyePDF = stateye(ymid:-1:1,:); % upside down

upperEyeCDF = cumsum(upperEyePDF, 1);
lowerEyeCDF = cumsum(lowerEyePDF, 1);


berlist = [1e-12, 1e-6, 0.01];
lenBer = length(berlist);
upperBERIdx = zeros(lenBer, xsize);
lowerBERIdx = zeros(lenBer, xsize);

for i = 1:lenBer
    for j = 1:xsize
        upperBERIdx(i, j) = find(upperEyeCDF(:, j) >= berlist(i), 1);
        lowerBERIdx(i, j) = find(lowerEyeCDF(:, j) >= berlist(i), 1);
    end
end

% shift idx to algin original stateye
upperBERIdx = ymid - 1 + upperBERIdx;
lowerBERIdx = ymid + 1 - lowerBERIdx;

upperBERVal = vh(upperBERIdx);
lowerBERVal = vh(lowerBERIdx);

tticks = th*SymbolTime*1e12;
figure(2);
lgd = cell(lenBer*2,1) ;
hold on;
for i = 1:lenBer% REF: https://www.mathworks.com/help/serdes/ref/pulse2stateye.html
load('PulseResponseReflective100ps.mat');
modulation = 2;
pulsewave = zeros(size(pulse, 1), 1);
pulsewave = pulse(:, 1);    % remove crosstalk pulse responses

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')

[ysize, xsize] = size(stateye);
ymid = floor((ysize+1)/2);
upperEyePDF = stateye(ymid:end,:);
lowerEyePDF = stateye(ymid:-1:1,:); % upside down

upperEyeCDF = cumsum(upperEyePDF, 1);
lowerEyeCDF = cumsum(lowerEyePDF, 1);


berlist = [1e-12, 1e-6, 0.01];
lenBer = length(berlist);
upperBERIdx = zeros(lenBer, xsize);
lowerBERIdx = zeros(lenBer, xsize);

for i = 1:lenBer
    for j = 1:xsize
        upperBERIdx(i, j) = find(upperEyeCDF(:, j) >= berlist(i), 1);
        lowerBERIdx(i, j) = find(lowerEyeCDF(:, j) >= berlist(i), 1);
    end
end

% shift idx to algin original stateye
upperBERIdx = ymid - 1 + upperBERIdx;
lowerBERIdx = ymid + 1 - lowerBERIdx;

upperBERVal = vh(upperBERIdx);
lowerBERVal = vh(lowerBERIdx);

tticks = th*SymbolTime*1e12;
figure(2);
lgd = cell(lenBer*2,1) ;
hold on;
for i = 1:lenBer
    plot(tticks, upperBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2-1} = strcat('BER=',num2str(berlist(i)));
    plot(tticks, lowerBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2} = "";
end
hold off;
legend(lgd)
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye BER')

figure(3)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave, 'k', tt*1e9, pulsewave-pulsewave(1), 'r--');
legend('original', 'dc shift');
xlim([0 10]);
ylim([-0.65 0.65])
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;
    plot(tticks, upperBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2-1} = strcat('BER=',num2str(berlist(i)));
    plot(tticks, lowerBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2} = "";
end
hold off;
legend(lgd)
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye BER')

figure(3)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave);
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;

pulse without ISI

Vp2p = 1V

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modulation = 2;
SamplesPerSymbol = 32;
pulsewave = zeros(SamplesPerSymbol*16, 1);
pulsewave(3*SamplesPerSymbol:4*SamplesPerSymbol-1, 1) = 1;

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')


figure(2)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave, 'k', tt*1e9, pulsewave-pulsewave(1), 'r--');
legend('original', 'dc shift');
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;

HSPICE - snpsSimADE

use StatEye Analysis in HSPICE

create netlist with hspiceD in Virtuoso

modify netlist

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P1 vi 0  port=1  Z0=0 LFSR (1 0 0 100p 100p 1G 1 [5,2])
P2 vo 0  port=2  Z0=1G
.stateye T=1ns trf=100p incident_port=1 probe_port=2
.probe stateye eye(2) berC(2) eyeBW(2)
.print stateye eye(2) berC(2) eyeBW(2)

Note bothZ0=0 and Z0=1G are used to remove port's effect, which is used as ideal voltage source and voltage monitor

The .probe stateye command generates netlist.stet# and netlist.stev# for following purposes:

• netlist.stet#: eye(t,v), eyeBW(t,v), eyeV(t), ber(t,v) and bathtubV(t)
• netlist.stet#: eye(t,v), eyeBW(t,v), eyeV(t), ber(t,v) and bathtubV(t)

setup

.cdsinit

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load( strcat( getShellEnvVar("HSPICE_HOME") "/hspice/interface/snpsSimADE.ile" ))

environment variable

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export CDS_LOAD_ENV=CSF
export SNPSSIMADE_LOAD_MODE=HSPICE

references

Sanders, Anthony, Michael Resso and John D'Ambrosia. “Channel Compliance Testing Utilizing Novel Statistical Eye Methodology.” (2004).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

HSPICE® User Guide: Signal Integrity Modeling and Analysis, Version Q-2020.03, March 2020

IA Title: Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]

Chris Li Ph.D. student at the University of Toronto [pystateye repo]

Jitter measurements can be classified into three categories: cycle-to-cycle jitter, period jitter, and long-term jitter

Jitter is a key performance parameter. Need to know what matters in each case:

• PJ for digital timing
• LTJ for data converters and serial data
• Phase noise for communications (not all bandwidths matter)

The above Cycle-Cycle Jitter equation is wrong, \(\tau_1\) and \(\tau_2\) are not independent

Short Term Jitter

Period jitter, Jper is the short term variation in clock period compared to the average (mean) clock period.

Cycle-to-Cycle, Jcc is the time difference of two adjacent clock periods

Long Term Jitter (LTJ)

measuring LTJ

Jitter Calculation Examples

Jcc vs Jper

Estimating the RMS cycle-to-cycle jitter if all you have available is the RMS period jitter.

• Cycle-to-cycle jitter - The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as \(J_{CC}\), may be specified as either an RMS or peak-to-peak quantity.
• Period jitter - The short-term variation in clock period over all measured clock cycles, compared to the average clock period. This jitter measure, abbreviated here as \(J_{PER}\), may be specified as either an RMS or peak-to-peak quantity.

Let the variable below represent the variance of a single edge’s timing jitter, i.e. the difference in time of a jittery edge versus an ideal edge, \(\sigma^2_j\)

If each edge’s jitter is independent then the variance of the period jitter can be written as \[\begin{align} \sigma^2_\text{jper} &= (\sigma_\text{j(n+1)}-\sigma_\text{j(n)})^2 \\ &= \sigma_\text{j(n+1)}^2-2\sigma_\text{j(n+1)}\sigma_\text{j(n)})+\sigma_\text{j(n)})^2\\ &= \sigma_\text{j(n+1)}^2+\sigma_\text{j(n)})^2 \\ &=2\sigma^2_j \end{align}\]

In every cycle-to-cycle measurement we use one "interior" clock edge twice and therefore we must account for this

\[\begin{align} \sigma^2_\text{jcc} &= (\sigma_\text{jper(n+1)}-\sigma_\text{jper(n)})^2 \\ &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \end{align}\]

Since each edge's jitter is assumed to be independent and have the same statistical properties we can drop the cross correlation terms and write:

\[\begin{align} \sigma^2_\text{jcc} &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \\ &=\sigma_\text{j(n+2)}^2+4\sigma_\text{j(n+1)}^2+\sigma_\text{j(n)}^2 \\ &=6\sigma_\text{j}^2 \end{align}\]

The ratio of the variances is therefore \[ \frac{\sigma^2_\text{jcc}}{\sigma^2_\text{jper}} = \frac{6\sigma_\text{j}^2} {2\sigma_\text{j}^2}=3 \] Then \[ \sigma_\text{jcc} = \sqrt{3}\sigma_\text{per} \]

[Timing 101 #8: The Case of the Cycle-to-Cycle Jitter Rule of Thumb, Silicon Labs]

Cadence Sampled Phase Noise

How to derive edge phase noise from Output Noise in sampled Pnoise simulation, [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/56929/how-to-derive-edge-phase-noise-from-output-noise-in-sampled-pnoise-simulation]

[Shawn Logan, Summary of Study of Cadence Sampled Phase Noise and Jitter Definitions with a Comparison to Conventional Time Interval Error (TIE) for a Driven Circuit]

General relationships between variance of jitter and phase noise

Understanding jitter and phase noise : a circuits and systems perspective

references

AN10007 Clock Jitter Definitions and Measurement Methods, SiTime [pdf]

SERDES Design and Simulation Using the Analog FastSPICE Platform, Silicon Creations [pdf]

Flexible clocking solutions in advanced processes from 180nm to 5nm, Silicon Creations [pdf]

One-size-fits-all PLLs for Advanced Samsung Foundry Processes, Silicon Creations [pdf]

Circuit Design and Verification of 7nm LowPower, Low-Jitter PLLs, Silicon Creations, [pdf]

Lecture 10: Jitter, ECEN720: High-Speed Links Circuits and Systems Spring 2023 [pdf]

loop inductance

由法拉第定律所導出的total loop inductance是迴路整體的效應，沒辦法區分出電源與地路徑上各別的電感，即難以分析 電感對power bounce或ground bounce分別的影響，所以有了partial inductance的定義

partial inductance

The first problem with using loop inductance to model the conductors of a loop is that at different frequencies, the return path

reference

Paul, Clayton R. Inductance: Loop and Partial. Hoboken, N.J. : [Piscataway, N.J.]: Wiley ; IEEE, 2010.

Spartaco Caniggia. Signal Integrity and Radiated Emission of High‐Speed Digital Systems. Wiley 2008

Clayton R. Paul, Partial Inductance [https://ewh.ieee.org/soc/emcs/acstrial/newsletters/summer10/PP_PartialInductance.pdf]

Yuriy Shlepnev. How Interconnects Work: Characteristic Impedance and Reflections [https://www.linkedin.com/pulse/how-interconnects-work-characteristic-impedance-yuriy-shlepnev/]

-. How Interconnects Work: Bandwidth for Modeling and Measurements [https://www.linkedin.com/pulse/how-interconnects-work-bandwidth-modeling-yuriy-shlepnev/?trackingId=874kpm3XuNyV9D0eP6IioA%3D%3D]

Eric Bogatin. Pop Quiz: When is an Interconnect Not a Transmission Line? [https://www.signalintegrityjournal.com/blogs/4-eric-bogatin-signal-integrity-journal-technical-editor/post/265-pop-quiz-when-is-an-interconnect-not-a-transmission-line]

TeledyneLeCroy/SignalIntegrity Python tools for signal integrity applications [SignalIntegrityApp]

A Look at Transmission-Line Losses [http://blog.teledynelecroy.com/2018/06/a-look-at-transmission-line-losses.html]

How Much Transmission-Line Loss is Too Much? [http://blog.teledynelecroy.com/2018/06/how-much-transmission-line-loss-is-too.html]

Y. Massoud and Y. Ismail, "Gasping the impact of on-chip inductance," in IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14-21, July 2001

Randy Wolff. Signal Loop Inductance in [Pin] and [Package Model] [https://ibis.org/summits/feb10/wolff.pdf]

Raymond Y. Chen, Raymond Y. Chen. Fundamentals of S Fundamentals of S-Parameter Parameter Modeling for Power Distribution Modeling for Power Distribution System (PDS) and SSO Analysis System (PDS) and SSO Analysis [https://ibis.org/summits/jun05/chen.pdf]

ANSYS Q3D Getting Started LE05. Module 5: Q3D Inductance Matrix Reduction [https://innovationspace.ansys.com/courses/wp-content/uploads/sites/5/2021/07/Q3D_GS_2020R1_EN_LE05_Ind_Matrix.pdf]

Assuming Target \(T\) ( for example, the total resistance) is function of \(x_1,x_2,...,x_N\), then total variation can be expressed as

\[\begin{align} dT &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}dx_n \\ &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}x_n\cdot \frac{dx_n}{x_n} \end{align}\]

Then, we obtain relative variation \[\begin{align} \frac{dT}{T} &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}\frac{x_n}{T}\cdot \frac{dx_n}{x_n} \\ &= \sum_{n=1}^N S_{x_n}^T \cdot \frac{dx_n}{x_n} \end{align}\]

⭐ where \(S_{x_n}^T=\frac{\partial T}{\partial x_n}\frac{x_n}{T}\) is relative sensitivity

relative sensitivity connect \(\frac{dx_n}{x_n}\) with total relative variation \(\frac{dT}{T}\)

And \(dT\) can be expressed as \[ dT =\sum_{n=1}^N S_{x_n}^T T\cdot \frac{dx_n}{x_n} = \sum_{n=1}^N x_n'\cdot \frac{dx_n}{x_n} \] ⭐ where \(x_n'= S_{x_n}^T T\) is the contribution of \(x_n\) in \(T\)

⭐ For parallel or series resistors, it can prove \(\sum_{n=1}^N S_{x_n}^T = 1\) and \(\sum_{n=1}^N x_n'=T\)

Here \(T= R_1 \parallel R_2 = \frac{R_1R_2}{R_1+R_2}\), and \(T|_{R_1=8000, R_2=2000} = 1600\)

We obtain relative sensitivity: \[\begin{align} S_{R_1}^T & = \frac{R_2}{R_1+R_2} \\ S_{R_2}^T & = \frac{R_1}{R_1+R_2} \end{align}\]

The contribution of \(R_1\) and \(R_2\) to \(T\) \[\begin{align} R_1' &= S_{R_1}^T T | _{R_1=8000, R_2=2000} = 320 \\ R_2' &= S_{R_2}^T T | _{R_1=8000, R_2=2000} = 1280 \end{align}\]

Normalized sensitivity captures relative sensitivity

change in objective per change in design variable

reference

Olivier de Weck, Karen Willcox. MIT, Gradient Calculation and Sensitivity Analysis [pdf]

Karti Mayaram, ECE 521 Fall 2016 Analog Circuit Simulation, Sensitivity and noise analyses [https://web.engr.oregonstate.edu/~karti/ece521/lec16_11_09.pdf]

Transit frequency \(f_T\)

aka cut-off frequency

Gate (thermal) noise

Two-Side Poly Contact & folding

Both scheme yield a total distributed resistance of \(R_G/4\) for gate noise calculation

folding

finger 0 \[\begin{align} \overline{i_{tot,0}^2} &= \left(\frac{g_m}{2} \right)^2(4kT\frac{R_G/2}{3}) \\ &= g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \end{align}\]

similarly finger 1 \[ \overline{i_{tot,1}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \] Assuming uncorrelated \[ \overline{i_{tot}^2} = \sum_{N=0}^1\overline{i_{tot,N}^2} =g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \cdot 2 = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2} \] Generally \[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2} \] where the gate is decomposed into \(N\) parallel fingers

two-side poly contact

We fracture Gate poly at the center point, then we obtain 2 segments, both have same \(\frac{g_m}{2}\) and \(R_G/2\).

The derivation procedure is same with folding structure, i.e. plug \(N=2\) into \(\overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2}\)

That is \[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{12}\right) \] The input referred noise of gate resistance \[ \overline{V_{nRG}^2} = 4kT\frac{R_G}{12} \]

four equal gate fingers

\[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{4^2} \] Then \[ \overline{V_{nRG}^2} = \frac{\overline{i_{tot}^2}}{g_m^2} =4kT\frac{R_G}{48} \]

Gate resistance handling by parasitic extraction tools

They fracture the poly line at the intersection with the active (diffusion) layer, breaking it into "gate poly"(poly over active) and "field poly" (poly outside active)

gploy, fpoly

Gate poly is also fractured at the center point. Gate instance pin of the MOSFET (SPICE model) is connected to the center point of the gate poly. Gate poly is described by two parasitic resistors, connecting the fracture points.

MOSFET extrinsic parasitic capacitance between gate poly and source / drain diffusion and contacts is calculated by parasitic extraction tools, and assigned to the nodes of the resistive networks.

Different extraction tools do this differently - some tools connect these parasitic capacitances to the center point of the gate poly, while some other tools connect them to the end points of the gate poly resistors.

\(\Delta\) gate model

This distributed network has a different AC and transient response than a simple lumped one-R and one-C circuit.

It was shown [B. Razavi] that such RC network behaves approximately the same as a network with one R and one C element, where C is the total capacitance, and R=1/3 * W/L rsh for single-side connected poly, and R=1/12 W/L * rsh for double-sided connected poly.

These coefficients - 1/3 and 1/12 - effectively enable an accurate reduced order model for the gate, reducing a large number of R and C elements to two (or three) resistors and one capacitor.

Gate Delta Model: where a gate is described by two positive and one negative resistors

only applicable to contacts on gate overhangs

invalid for self-aligned gate contacts, where gate contact land directly on top of gate, not gate overhang

1. 1-side gate contact \[ R_{eq,1side} =R_1 \parallel (R_2+R_1)= \frac{R_G}{6}\parallel (-\frac{R_G}{2}+\frac{R_G}{6})=\frac{R_G}{3} \]

2. 2-side contact \[ R_{eq,2side}= R_1 \parallel R_1 = \frac{R_G}{6}\parallel \frac{R_G}{6} = \frac{R_G}{12} \]

Some SPICE simulators have problems handling negative resistors, that's possibly why this model did not get a wide adoption. Some foundries and PDKs support delta gate model, while some others don't.

Vertical component of gate resistance

In "old" technologies (pre-16nm), gate resistance was dominated by lateral resistance. However, in advanced technologies, multiple interfaces between gate material layers lead to a large vertical gate resistance.

It's very easy to check this in DSPF file - if gate instance pin is connected directly to the center of the gate poly - vertical resistance is not accounted for. If it is connected by a positive resistor to the center of the gate poly - that resistors represents the vertical gate resistance.

decap

leakage current is determined by \(R_s + R_p\), and \(R_p \gg R_s\)

• low freq: \(Z=R_s + R_p\)
• high freq: \(Z=R_s\)

An example: \(R_s=200\space \Omega\), \(R_p = 8 \space M\Omega\) and \(C_\text{gate}=10\space fF\)

reference

⭐ B. Razavi, Y. Ran, and K. F. Lee, “Impact of Distributed Gate Resistance on the Performance of MOS Devices,” IEEE Trans. Circuits and Systems, Part I, pp. 750–754, Nov. 1994.

⭐ Maxim Ershov, Diakopto. "Gate Resistance in IC design flow", [link, pdf]

A.J.Sholten et al., "FinFET compact modelling for analogue and RF applications", IEDM'2010 [https://sci-hub.se/10.1109/IEDM.2010.5703322]

Saha, Samar K.. “FinFET Devices for VLSI Circuits and Systems.” (2020).

Harpe, Pieter J. A., Andrea Baschirotto and Kofi A. A. Makinwa. “Hybrid ADCs, Smart sensors for the IoT, and Sub-1V and Advanced node analog circuit design: Advances in Analog Circuit Design 2017.” (2018).

Chauhan, Yogesh Singh. FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard. London, UK: Academic Press, 2015.

A.J.Sholten et al., "FinFET compact modelling for analogue and RF applications", IEDM'2010, p.190.

W. Wu and M. Chan, “Gate resistance modeling of multifin MOS devices,” IEEE Electron Device Letters, vol. 27, no. 1, pp. 68-70, Jan. 2006.

A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

realtime vs time

• $realtime round the current time to timeprecision

• $time round the current time to integer

• %t will scale the rounded value to represent timeprecision,

  i.e. \([\$\text{realtime}, \$\text{time}]\cdot \$\text{timeunit} / \$\text{timeprecision}\)

https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94062 https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94096

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module tb;
  timeunit 10ns;
  timeprecision 1ps;

  initial begin
    $display("$realtime = %g", $realtime);
    $display("$time = %g", $time);
    // $realtime round to timeprecision
    // $time round to integer
    #1.10016
    $display("$realtime = %g", $realtime);
    $display("$time = %g", $time);

    // %t format will scale the rounded value to represent timeprecision
    // 1.1002*10e-9/1e-12 = 11002
    $display("$realtime %%t = %t", $realtime);
    $display("$time %%t = %t", $time);
  end
endmodule

output

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$realtime = 0
$time = 0
$realtime = 1.1002
$time = 1
$realtime %t =                11002
$time %t =                10000

timeunit, timeprecision

The time unit and time precision can be specified in the following two ways: - Using the compiler directive `timescale - Using the keywords timeunit and timeprecision

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module D (...);
  timeunit 100ps;
  timeprecision 10fs;
  ...
endmodule

module E (...);
  timeunit 100ps / 10fs; // timeunit with optional second argument
  ...
endmodule

The minimum of timeprecision determine %t output, the nearest timeunit and timeprecision determine the round of $realtime and $time. Of course, the simulator follow the time tick shown by $realtime.

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`timescale 1ns/1ns

// Due to minimum of timeprecision is 10ps
module rawplant;
  timeunit 1ns;
  timeprecision 100ps;

  task print;
    /*
    1ns: 1
    100ps:  6
    10ps: 6
    1ps: 6
    */
    #1.666
    $display("raw: $realtime = %g", $realtime);     // 1.7
    $display("raw: $time = %g", $time);             // 2
    $display("raw: $realtime %%t = %t", $realtime); // 1.7*1ns/10ps=170
    $display("raw: $time %%t = %t", $time);         // 2*1ns/10ps = 200
  endtask

endmodule

module fineplant;
  timeunit 100ps;
  timeprecision 10ps;

  task print;
    /*
    100ps: 2
    10ps: 6
    1ps: 6
    */
    #2.66
    $display("fine: $realtime = %g", $realtime);     // 2.7
    $display("fine: $time = %g", $time);             // 3
    $display("fine: $realtime %%t = %t", $realtime); // 2.7*100ps/10ps = 27
    $display("fine: $time %%t = %t", $time);         // 3*100ps/10ps = 30
  endtask

endmodule

module tb;
  rawplant rawblock();
  fineplant fineblock();

  initial begin
  fork
    rawblock.print();
    fineblock.print();
  join
  end
endmodule

output

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fine: $realtime = 2.7
fine: $time = 3
fine: $realtime %t =                   27
fine: $time %t =                   30
raw: $realtime = 1.7
raw: $time = 2
raw: $realtime %t =                  170
raw: $time %t =                  200

questasim cmd

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vlib work
vlog tb.v
vsim -c -do "run -all;exit" work.tb