KNOW-HOW

PSS and HB Overview

The steady-state response is the response that results after any transient effects have dissipated.

The large signal solution is the starting point for small-signal analyses, including periodic AC, periodic transfer function, periodic noise, periodic stability, and periodic scattering parameter analyses.

Designers refer periodic steady state analysis in time domain as "PSS" and corresponding frequency domain notation as "HB"

Harmonic Balance Analysis

The idea of harmonic balance is to find a set of port voltage waveforms (or, alternatively, the harmonic voltage components) that give the same currents in both the linear-network equations and nonlinear-network equations

that is, the currents satisfy Kirchoff's current law

Define an error function at each harmonic, \(f_k\), where \[ f_k = I_{\text{LIN}}(k\omega) + I_{\text{NL}}(k\omega) \] where \(k=0, 1, 2,...,K\)

Note that each \(f_k\) is implicitly a function of all voltage components \(V(k\omega)\)

Newton Solution of the Harmonic-Balance Equation

Iterative Process and Jacobian Formulation

The elements of the Jacobian are the derivatives \[ \frac{\partial F_{\text{n,k}}}{\partial _{V_\text{m,l}}} \] where \(n\) and \(m\) are the port indices \((1,N)\), and \(k\) and \(l\) are the harmonic indices \((0,...,K)\)

Selecting the Number of Harmonics and Time Samples

In theory, the waveforms generated in nonlinear analysis have an infinite number of harmonics, so a complete description of the operation of a nonlinear circuit would appear to require current and voltage vectors of infinite dimension.

Fortunately, the magnitudes of frequency components invariably decrease with frequency; otherwise the time wavefroms would represent infinite power.

Initial Estimate

One important property of Newton's method is that its speed and reliability of convergence depend strongly upon the initial estimate of the solution vector.

Shooting Newton

TODO 📅

Nonlinearity & Linear Time-Varying Nature

Nonlinearity Nature

The nonlinearity causes the signal to be replicated at multiples of the carrier, an effect referred to as harmonic distortion, and adds a skirt to the signal that increases its bandwidth, an effect referred to as intermodulation distortion

It is possible to eliminate the effect of harmonic distortion with a bandpass filter, however the frequency of the intermodulation distortion products overlaps the frequency of the desired signal, and so cannot be completely removed with filtering.

Time-Varying Linear Nature

linear with respect to \(v_{in}\) and time-varying

Given \(v_{in}(t)=m(t)\cos (\omega_c t)\) and LO signal of \(\cos(\omega_{LO} t)\), then \[ v_{out}(t) = \text{LPF}\{m(t)\cos(\omega_c t)\cdot \cos(\omega_{LO} t)\} \] and \[ v_{out}(t) = m(t)\cos((\omega_c - \omega_{LO})t) \]

A linear periodically-varying transfer function implements frequency translation

Periodic small signal analyses

Analysis in Simulator

1. LPV analyses start by performing a periodic analysis to compute the periodic operating point with only the large clock signal applied (the LO, the clock, the carrier, etc.).
2. The circuit is then linearized about this time-varying operating point (expand about the periodic equilibrium point with a Taylor series and discard all but the first-order term)
3. and the small information signal is applied. The response is calculated using linear time-varying analysis

Versions of this type of small-signal analysis exists for both harmonic balance and shooting methods

PAC is useful for predicting the output sidebands produced by a particular input signal

PXF is best at predicting the input images for a particular output

Conversion Matrix Analysis

Large-signal/small-signal analysis, or conversion matrix analysis, is useful for a large class of problems wherein a nonlinear device is driven, or "pumped" by a single large sinusoidal signal; another signal, much smaller, is applied; and we seek only the linear response to the small signal.

The most common application of this technique is in the design of mixers and in nonlinear noise analysis

1. First, analyzing the nonlinear device under large-signal excitation only, where the harmonic-balance method can be applied
2. Then, the nonlinear elements in the device's equivalent circuit are then linearized to create small-signal, linear, time-varying elements
3. Finally, a small-signal analysis is performed

Element Linearized

Below shows a nonlinear resistive element, which has the \(I/V\) relationship \(I=f(V)\). It is driven by a large-signal voltage

Assuming that \(V\) consists of the sum of a large-signal component \(V_0\) and a small-signal component \(v\), with Taylor series \[ f(V_0+v) = f(V_0)+\frac{d}{dV}f(V)|_{V=V_0}\cdot v+\frac{1}{2}\frac{d^2}{dV^2}f(V)|_{V=V_0}\cdot v^2+... \] The small-signal, incremental current is found by subtracting the large-signal component of the current \[ i(v)=I(V_0+v)-I(V_0) \] If \(v \ll V_0\), \(v^2\), \(v^3\),... are negligible. Then, \[ i(v) = \frac{d}{dV}f(V)|_{V=V_0}\cdot v \]

\(V_0\) need not be a DC quantity; it can be a time-varying large-signal voltage \(V_L(t)\) and that \(v=v(t)\), a function of time. Then \[ i(t)=g(t)v(t) \] where \(g(t)=\frac{d}{dV}f(V)|_{V=V_L(t)}\)

The time-varying conductance \(g(t)\), is the derivative of the element's \(I/V\) characteristic at the large-signal voltage

By an analogous derivation, one could have a current-controlled resistor with the \(V/I\) characteristic \(V = f_R(I)\) and obtain the small-signal \(v/i\) relation \[ v(t) = r(t)i(t) \] where \(r(t) = \frac{d}{dI}f_R(I)|_{I=I_L(t)}\)

A nonlinear element excited by two tones supports currents and voltages at mixing frequencies \(m\omega_1+n\omega_2\), where \(m\) and \(n\) are integers. If one of those tones, \(\omega_1\) has such a low level that it does not generate harmonics and the other is a large-signal sinusoid at \(\omega_p\), then the mixing frequencies are \(\omega=\pm\omega_1+n\omega_p\), which shown in below figure

A more compact representation of the mixing frequencies is \[ \omega_n=\omega_0+n\omega_p \] which includes only half of the mixing frequencies:

• the negative components of the lower sidebands (LSB)
• and the positive components of the upper sidebands (USB)

For real signal, positive- and negative-frequency components are complex conjugate pairs

Conversion Matrix as Bridge

The frequency-domain currents and voltages in a time-varying circuit element are related by a conversion matrix

The small-signal voltage and current can be expressed in the frequency notation as \[ v'(t) = \sum_{n=-\infty}^{\infty}V_ne^{j\omega_nt} \] and \[ i'(t) = \sum_{n=-\infty}^{\infty}I_ne^{j\omega_nt} \] where \(v'(t)\) and \(i'(t)\) are not Fourier series due to \(\omega_n=\omega_0+n\omega_p\)

The conductance waveform \(g(t)\) can be expressed by its Fourier series \[ g(t)=\sum_{n=-\infty}^{\infty}G_ne^{jn\omega_pt} \] Which is harmonics of large-signal \(\omega_p\)

Then the voltage and current are related by Ohm's law \[ i'(t)=g(t)v'(t) \] Then \[ \sum_{k=-\infty}^{\infty}I_ke^{j\omega_kt}=\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}G_nV_me^{j\omega_{m+n}t} \]

A linear periodically-varying transfer function implements frequency translation

Linear Time Varying

The response of a relaxed LTV system at a time \(t\) due to an impulse applied at a time \(t − \tau\) is denoted by \(h(t, \tau)\)

The first argument in the impulse response denotes the time of observation.

The second argument indicates that the system was excited by an impulse launched at a time \(\tau\) prior to the time of observation.

Thus, the response of an LTV system not only depends on how long before the observation time it was excited by the impulse but also on the observation instant.

The output \(y(t)\) of an initially relaxed LTV system with impulse response \(h(t, \tau)\) is given by the convolution integral \[ y(t) = \int_0^{\infty}h(t,\tau)x(t-\tau)d\tau \] Assuming \(x(t) = e^{j2\pi f t}\) \[ y(t) = \int_0^{\infty}h(t,\tau)e^{j2\pi f (t-\tau)}d\tau = e^{j2\pi f t}\int_0^{\infty}h(t,\tau)e^{-j2\pi f\tau}d\tau \] The (time-varying) frequency response can be interpreted as \[ H(j2\pi f, t) = \int_0^{\infty}h(t,\tau)e^{-j2\pi f\tau}d\tau \] Linear Periodically Time-Varying (LPTV) Systems, which is a special case of an LTV system whose impulse response satisfies \[ h(t, \tau) = h(t+T_s, \tau) \] In other words, the response to an impulse remains unchanged if the time at which the output is observed (\(t\)) and the time at which the impulse is applied (denoted by \(t_1\)) are both shifted by \(T_s\) \[ H(j2\pi f, t+T_s) = \int_0^{\infty}h(t+T_s,\tau)e^{-j2\pi f\tau}d\tau = \int_0^{\infty}h(t,\tau)e^{-j2\pi f\tau}d\tau = H(j2\pi f, t) \] \(H(j2\pi f, t)\) of an LPTV system is periodic with timeperiod \(T_s\), it can be expanded as a Fourier series in \(t\), resulting in \[ H(j2\pi f, t) = \sum_{k=-\infty}^{\infty} H_k(j2\pi f)e^{j2\pi f_s k t} \] The coefficients of the Fourier series \(H_k(j2\pi f)\) are given by \[ H_k(j2\pi f) = \frac{1}{T_s}\int_0^{T_s} H(j2\pi f, t) e^{-j2\pi k f_s t}dt \]

reference

K. S. Kundert, "Introduction to RF simulation and its application," in IEEE Journal of Solid-State Circuits, vol. 34, no. 9, pp. 1298-1319, Sept. 1999, doi: 10.1109/4.782091. [pdf]

Stephen Maas, Nonlinear Microwave and RF Circuits, Second Edition , Artech, 2003.

Karti Mayaram. ECE 521 Fall 2016 Analog Circuit Simulation: Simulation of Radio Frequency Integrated Circuits [pdf1, pdf2]

The Value Of RF Harmonic Balance Analyses For Analog Verification: Frequency domain periodic large and small signal analyses. [https://semiengineering.com/the-value-of-rf-harmonic-balance-analyses-for-analog-verification/]

Shanthi Pavan, "Demystifying Linear Time Varying Circuits"

S. Pavan and G. C. Temes, "Reciprocity and Inter-Reciprocity: A Tutorial— Part I: Linear Time-Invariant Networks," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3413-3421, Sept. 2023, doi: 10.1109/TCSI.2023.3276700.

S. Pavan and G. C. Temes, "Reciprocity and Inter-Reciprocity: A Tutorial—Part II: Linear Periodically Time-Varying Networks," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3422-3435, Sept. 2023, doi: 10.1109/TCSI.2023.3294298.

S. Pavan and R. S. Rajan, "Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 9, pp. 686-690, Sept. 2014, doi: 10.1109/TCSII.2014.2335393.

Prof. Shanthi Pavan. Introduction to Time - Varying Electrical Network. [https://youtube.com/playlist?list=PLyqSpQzTE6M8qllAtp9TTODxNfaoxRLp9]

Shanthi Pavan. EE5323: Advanced Electrical Networks (Jan-May. 2015) [https://www.ee.iitm.ac.in/vlsi/courses/ee5323/start]

R. S. Ashwin Kumar. EE698W: Analog circuits for signal processing [https://home.iitk.ac.in/~ashwinrs/2022_EE698W.html]

Piet Vanassche, Georges Gielen, and Willy Sansen. 2009. Systematic Modeling and Analysis of Telecom Frontends and their Building Blocks (1st. ed.). Springer Publishing Company, Incorporated.

Beffa, Federico. (2023). Weakly Nonlinear Systems. 10.1007/978-3-031-40681-2.

Wereley, Norman. (1990). Analysis and control of linear periodically time varying systems.

Hameed, S. (2017). Design and Analysis of Programmable Receiver Front-Ends Based on LPTV Circuits. UCLA. ProQuest ID: Hameed_ucla_0031D_15577. Merritt ID: ark:/13030/m5gb6zcz. Retrieved from https://escholarship.org/uc/item/51q2m7bx

Matt Allen. Introduction to Linear Time Periodic Systems. [https://youtu.be/OCOkEFDQKTI]

Fivel, Oren. "Analysis of Linear Time-Varying & Periodic Systems." arXiv preprint arXiv:2202.00498 (2022).

RF Harmonic Balance Analysis for Nonlinear Circuits [https://resources.pcb.cadence.com/blog/2019-rf-harmonic-balance-analysis-for-nonlinear-circuits]

Steer, Michael. Microwave and RF Design (Third Edition, 2019). NC State University, 2019.

Steer, Michael. Harmonic Balance Analysis of Nonlinear RF Circuits - Case Study Index: CS_AmpHB [link]

Vishal Saxena, "SpectreRF Periodic Analysis" URL:https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/SpectreRF%20Periodic%20Analysis.pdf

Josh Carnes,Peter Kurahashi. "Periodic Analyses of Sampled Systems" URL:https://slideplayer.com/slide/14865977/

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF. URL:https://designers-guide.org/analysis/sc-filters.pdf

Article (20482538) Title: Why is pnoise sampled(jitter) different than pnoise timeaverage on a driven circuit? URL:https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009EStcUAG

Article (20467468) Title: The mathematics behind choosing the upper frequency when simulating pnoise jitter on an oscillator URL:https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MnBUUA0

Andrew Beckett. "Simulating phase noise for PFD-CP". URL:https://groups.google.com/g/comp.cad.cadence/c/NPisXTElx6E/m/XjWxKbbfh2cJ

Dr. Yanghong Huang. MATH44041/64041: Applied Dynamical Systems [https://personalpages.manchester.ac.uk/staff/yanghong.huang/teaching/MATH4041/default.htm]

Jeffrey Wong. Math 563, Spring 2020 Applied computational analysis [https://services.math.duke.edu/~jtwong/math563-2020/main.html]

Jeffrey Wong. Math 353, Fall 2020 Ordinary and Partial Differential Equations [https://services.math.duke.edu/~jtwong/math353-2020/main.html]

Tip of the Week: Please explain in more practical (less theoretical) terms the concept of "oscillator line width." [https://community.cadence.com/cadence_blogs_8/b/rf/posts/please-explain-in-more-practical-less-theoretical-terms-the-concept-of-quot-oscillator-line-width-quot]

Rubiola, E. (2008). Phase Noise and Frequency Stability in Oscillators (The Cambridge RF and Microwave Engineering Series). Cambridge: Cambridge University Press. doi:10.1017/CBO9780511812798

Dr. Ulrich L. Rohde, Noise Analysis, Then and Today [https://www.microwavejournal.com/articles/29151-noise-analysis-then-and-today]

Nicola Da Dalt and Ali Sheikholeslami. 2018. Understanding Jitter and Phase Noise: A Circuits and Systems Perspective (1st. ed.). Cambridge University Press, USA.

Kester, Walt. (2005). Converting Oscillator Phase Noise to Time Jitter. [https://www.analog.com/media/en/training-seminars/tutorials/MT-008.pdf]

Drakhlis, B.. (2001). Calculate oscillator jitter by using phase-noise analysis: Part 2 of two parts. Microwaves and Rf. 40. 109-119.

Explanation for sampled PXF analysis. [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/45055/explanation-for-sampled-pxf-analysis/1376140#1376140]

模拟放大器的低噪声设计技术2-3实践 아날로그 증폭기의 저잡음 설계 기법2-3실습 [https://youtu.be/vXLDfEWR31k?si=p2gbwaKoTxtfvrTc]

2.2 How POP Really Works [https://www.simplistechnologies.com/documentation/simplis/ast_02/topics/2_2_how_pop_really_works.htm]

Jaeha Kim. Lecture 11. Mismatch Simulation using PNOISE [https://ocw.snu.ac.kr/sites/default/files/NOTE/7037.pdf]

Hueber, G., & Staszewski, R. B. (Eds.) (2010). Multi-Mode/Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends. John Wiley & Sons. https://doi.org/10.1002/9780470634455

B. Boser,A. Niknejad ,S.Gambin 2011 EECS 240 Topic 6: Noise Analysis [https://mixsignal.files.wordpress.com/2013/06/t06noiseanalysis_simone-1.pdf]

Jitter and Edge phase noise

[https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/56929/how-to-derive-edge-phase-noise-from-output-noise-in-sampled-pnoise-simulation/1388888]

Phase Noise Aliasing & Integration Limits

These two types of measurements deliver the same rms jitter of \(f_{CK}\)

• both rising and falling: integrated from \(-f_{CK}\) to \(+f_{CK}\)
• only the rising (or falling) edges: integrated from \(-f_{CK}/2\) to \(+f_{CK}/2\)

temporal autocorrelation and Wiener-Khinchin theorem is more appropriate to arise rms value

Y. Zhao and B. Razavi, "Phase Noise Integration Limits for Jitter Calculation,"[https://www.seas.ucla.edu/brweb/papers/Conferences/YZ_ISCAS_22.pdf]

G. Giust, “Phase Noise Aliases as TIE Jitter,” Signal Integrity Journal, July 23, 2018 [https://www.signalintegrityjournal.com/articles/912-phase-noise-aliases-as-tie-jitter]

Reference-Clock Phase Noise in PLL

TODO 📅

phase noise in a 100 MHz input clock signal gets filtered by an example PLL with a closed-loop bandwidth of 1 MHz

Gary Giust. How to Evaluate Reference-Clock Phase Noise in High-Speed Serial Links [expanded version], [compact version]

time-average noise (phase-noise) & sampled noise (edge-phase noise or jitter) spectrum

Time-average noise analysis

\(S_{\Delta f}(f)\) between \([\Delta f, F_0/2]\) may be less than that of other harmonic window

Sampled noise analysis

correlation

VCO Phase Noise

pnoise - timeaverage

1. Direct Plot/Pnoise/Phase Noise or

   

2. manually calculate by definition

   

3. output noise with unit dBc

   Direct Plot/Pnoise/Output Noise Units:dBc/Hz and Noise convention: SSB

   

The above method 2 and 3 only apply to timeaveage pnoise simulation,

pnoise - sampled(jitter)/Edge Crossing

Direct Plot/Pnoise/Edge Phase Noise or

Another way, the following equation can also be used for sampled(jitter)/Edge Crossing

1

PhaseNoise(dBc/Hz) = dB20( OutputNoise(V/sqrt(Hz)) / slopeCrossing / Tper*twoPi ) - dB10(2)

where dB10(2) is used to obtain SSB from DSB

Output Noise of sampled(jitter) pnoise

The last section's Output Noise (V**2/Hz) can be obtained by transient noise simulation

The idea is that sample waveform with ideal clock, subtract DC offset, then fft(psd)

• samplesRaw = sample(wv)
• samplePost = samplesRaw - average(samplesRaw)
• Output Noise (V**2/Hz) = psd(samplePost)

Expression:

The computation cost is typically very high, and the accuracy is lesser as compared to PSS/Pnoise

Pnoise Sampled(jitter): Sampled Phase Option

• Identical to noisetype=timedomain in old GUI
• Use model:
  • Sampleds Per Period: number of ponits
  • Add Specific Points: specific time point, still time points

pss beat freq = 5GHz

pnoise sweeptype: absolute, from 100k to 2.5GHz

Transient noise

phase noise from transient noise analysis

1. The Phase Noise function is now available in the Direct Plot form (Results-Direct Plot-Main Form) after Transient Analysis is run
   • Absolute jitter Method
   • Direct Power Spectral Density Method
2. PN phase noise function
   • Absolute jitter Method
   • Direct Power Spectral Density Method

Absolute jitter Method: Phase noise is defined as the power spectral density of the absolute jitter of an input waveform

and absolute jitter method is the default method

In below discussion, we only think about the absolute jitter method

PSD and Phase Noise

• phase noise is single-sideband
• psd is double-sideband
• Then the ratio is 2

By PSS_Pnoise

jee

1

rfEdgePhaseNoise(?result "pnoise_sample_pm0" ?eventList 'nil) + 10 * log10(2)

convert single-sideband phase noise to psd by multiplying 2 or 10 * log10(2)

By trannoise PN function

1

PN(clip(VT("/Out1") 2.60417e-08 0.000400052) "rising" 1.65 ?Tnom (1 / 3.84e+07) ?windowName "Rectangular" ?smooth 1 ?windowSize 15000 ?detrending "None" ?cohGain 1 ?methodType "absJitter")

double-sideband psd

By trannoise psd and abs_jitter function

1

dB10(psd(abs_jitter(clip(VT("/Out1") 2.60417e-08 0.000400052) "rising" 1.65 ?Tnom (1 / 3.84e+07)) 2.60417e-08 0.000400052 15360 ?windowName "Rectangular" ?smooth 1 ?windowSize 15000 ?detrending "None" ?cohGain 1))

double-sideband psd

abs_jitter Y-Unit default is rad

Comparison

PN's result is same with psd's

RMS value

• build the abs_jitter function with seconds as the Y axis and add the stddev function to determine the Jee jitter value
• or integrate psd

The RMS \(x_{\text{RMS}}\) of a discrete domain signal \(x(n)\) is given by \[ x_{\text{RMS}}=\sqrt{\frac{1}{N}\sum_{n=0}^{N-1}|x(n)|^2} \] Inserting Parseval's theorem given by \[ \sum_{n=0}^{N-1}|x(n)|^2=\frac{1}{N}\sum_{n=0}^{N-1}|X(k)|^2 \] allows for computing the RMS from the spectrum \(X(k)\) as \[ x_{\text{RMS}}=\sqrt{\frac{1}{N^2}\sum_{n=0}^{N-1}|X(k)|^2} \]

Remarks

Cadence Spectre's PN function may call abs_jitter and psd function under the hood.

reference

Article (11514536) Title: How to obtain a phase noise plot from a transient noise analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nb1CEAQ

Article (20500632) Title: How to simulate Random and Deterministic Jitters URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fiXeEAI

Cadence, Application Note: Understanding the relations between time-average noise (phase-noise) and sampled noise (edge-phase noise or jitter) in Pnoise analysis

Tutorial on Scaling of the Discrete Fourier Transform and the Implied Physical Units of the Spectra of Time-Discrete Signals Jens Ahrens, Carl Andersson, Patrik Höstmad, Wolfgang Kropp URL: https://appliedacousticschalmers.github.io/scaling-of-the-dft/AES2020_eBrief/

PSRR (Power Supply Rejection Ratio)

A good PSRR is important when an LDO is used as a sub-regulator in cascade with a switching regulator

The LDO would need to have a sufficiently high rejection at the switching frequency of the switching converter to filter out the ripples at that frequency

PMOS LDO

A large output capacitor solves the sudden load change problem, but the stability decreases because the large output capacitor forces the output pole toward the origin with the role of dominant pole

DC output impedance

The output impedance of the LDO at DC is known as its load regulation

DC output impedance of NMOS and PMOS LDO is the same for the same error amplifier gain

\[ R_{\text{out}} = \frac{1}{\beta A_{o1} g_{m2}} \]

The NMOS LDO has a faster response to line transients than the PMOS LDO since it has better (smaller) PSRR

Power MOS gain affect on PMOS LDO

DC gain \[ A_{dc} = g_mR_\text{ota} A_2 \] 3dB bandwidth \[ \omega_p = \frac{1}{R_\text{ota}(C_g+A_2C_c)} \] and GBW \[ \omega_u = \frac{g_m}{\frac{C_g}{A_2}+C_c} \]

Feedforward Compensation with \(C_\text{FF}\)

• Improved Noise
• Improved Stability and Transient Response
• Improved PSRR

\[\begin{align} R_1 \parallel \frac{1}{sC_{FF}} &= \frac{R_1}{1+sR_1C_{FF}} \\ Z_o &= \left( R_1\parallel \frac{1}{sC_{FF}}+R_2\right)\parallel \frac{1}{sC_L} \\ &=\frac{R_1+R_2+sR_1R_2C_{FF}}{s^2R_1R_2C_{FF}C_L + s[(R_1+R_2)C_L+R_1C_{FF}]+1} \\ A_{V2} &= g_m Z_o \\ &= g_m \frac{R_1+R_2+sR_1R_2C_{FF}}{s^2R_1R_2C_{FF}C_L + s[(R_1+R_2)C_L+R_1C_{FF}]+1} \\ \beta &= \frac{R_2}{\frac{R_1}{1+sR_1C_{FF}}+R_2} \\ &= \frac{R_2(1+sR_1C_{FF})}{R_1+R_2+sR_1R_2C_{FF}} \\ A_{V2}\beta &= \frac{g_mR_2(1+sR_1C_{FF})}{s^2R_1R_2C_{FF}C_L+s[(R_1+R_2)C_L+R_1C_{FF}]+1} \end{align}\]

That is, adding a \(C_{FF}\) also introduces a zero (\(\omega_z\)) and pole (\(\omega_p\)) into the LDO feedback loop

\[\begin{align} \omega_{po} &= \frac{1}{(R_1+R_2)C_L} \\ \omega_z &= \frac{1}{R_1C_{FF}} \\ \omega_{p} &= \frac{1}{(R_1 \parallel R_2)C_{FF}} \end{align}\]

Application Report SBVA042–July 2014, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator [https://www.ti.com/lit/an/sbva042/sbva042.pdf]

LDO Basics: Noise – How a Feed-forward Capacitor Improves System Performance [https://www.ti.com/document-viewer/lit/html/SSZTA13]

LDO Basics: Noise – How a Noise-reduction Pin Improves System Performance [https://www.ti.com/document-viewer/lit/html/SSZTA40]

NMOS Slave LDO

\[\begin{align} \frac{V_g}{V_i} &=\frac{R||\frac{1}{s(C_g+C_{gs})}}{R||\frac{1}{s(C_g+C_{gs})}+\frac{1}{sC_{gd}}} \\ &= \frac{sRC_{gd}}{sR(C+C_{gd}+C_{gs})+1} \end{align}\] \[ \frac{V_g}{V_i} = -\frac{sC_{ds}+g_{ds}}{sC_{gs}+g_m} \]

That is, \[ \omega_{z,d} \simeq \frac{1}{R(\frac{g_m}{g_{ds}}C_{gd}+C)} \]

The calculating PSRR pole approach similar with zero, just \(V_o\) to \(V_i\) zero \[ \omega_{p,d} \simeq \frac{1}{R(\frac{C_s}{g_mR}+C)} \]

DC PSRR \[ \text{PSRR} = \frac{1}{g_mr_o} \]

PSRR @Vgate

KCL at output node

\[ g_m(-V_o\beta A_{E} - V_o) + \frac{V_i - V_o}{r_o} = \frac{V_o}{R_1+R_2} \]

Hence \[ \frac{V_o}{V_i} = \frac{1}{A_E\beta g_mr_o+g_mr_o +\frac{r_o}{R_1+R_2}+1} \approx \frac{1}{A_E\beta g_m r_o} \]

Through feedback loop, we derive \[ V_g = V_o \beta (-A_E) \approx \frac{V_i}{A_E\beta g_m r_o} \beta (-A_E) = -\frac{V_i}{g_mr_o} \]

That is \[ \frac{V_g}{V_i} \approx -\frac{1}{g_mr_o} \]

Due to closed loop, \(V_g\) and \(V_o\) is not source follower

High frequency PSRR

feedback resistor divider noise

assuming \(\text{LG} \gg 1\)

\[\begin{align} I_\text{t} &= \frac{V_\text{ref} - v_\text{n2}}{R_\text{2}} \\ V_\text{o} &= V_\text{ref} +v_\text{n1} + I_\text{t}R_\text{1} \\ \end{align}\]

Then \[ V_\text{o} = \frac{R_1+R_2}{R_2}V_\text{ref} + v_\text{n1} - \frac{R_1}{R_2}v_\text{n2} \] that is

\[ v_\text{no}^2 = v_\text{n1}^2 + \left(\frac{R_1}{R_2}\right)^2 v_\text{n2}^2 \]

\[ \text{vno1}^2= \text{vn1}^2+\text{vn2}^2/6^2=16.5758 + 99.45453/6^2 = 19.338425833 \]

reference

Hinojo, J.M., Martinez, C.I., & Torralba, A.J. (2018). Internally Compensated LDO Regulators for Modern System-on-Chip Design.

Chen, K.-H. (2016). Power Management Techniques for Integrated Circuit Design. Wiley-IEEE Press.

Morita, B.G. (2014). Understand Low-Dropout Regulator ( LDO ) Concepts to Achieve Optimal Designs.

H. -S. Kim, "Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable approaches that preserve performance," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 59-68, Spring 2023, doi: 10.1109/MSSC.2023.3262767.

Ali Sheikholeslami, Circuit Intuitions: Voltage Regulators IEEE Solid-State Circuits Magazine, Vol. 12, Issue 4, to appear, Fall 2020.

Operational Transconductance Amplifier II Multi-Stage Designs [https://people.eecs.berkeley.edu/~boser/courses/240B/lectures/M07%20OTA%20II.pdf]

Toshiba, Load Transient Response of LDO and Methods to Improve it Application Note [https://toshiba.semicon-storage.com/info/application_note_en_20210326_AKX00312.pdf?did=66268]

Carusone, Tony Chan, David Johns, and Kenneth Martin. Analog integrated circuit design. John wiley & sons, 2011. [https://mrce.in/ebooks/Analog%20Integrated%20Circuit%20Design%202nd%20Ed.pdf]

Pavan Kumar Hanumolu. CICC 2015. "Low Dropout Regulators" [https://uofi.app.box.com/v/CICC15-LDO]

Mingoo Seok. ISSCC 2020 T7: "Basics of Digital Low-Dropout (LDO) Integrated Voltage Regulator" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T7Visuals.pdf]

Yan Lu, ISSCC2021 T10: "Fundamentals of Fully Integrated Voltage Regulators" [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T10.pdf]

Hyun-Sik Kim, Low-Dropout (LDO) Voltage Regulators – From Basics to Recent Design Trends (presented in A-SSCC 2022) [pdf]

A. Raychowdhury. ISSCC 2024 T2: Fundamentals of Digital and Digitally-Assisted Linear Voltage Regulators

Missing Term in KVL

Prof. Kolb/Whites. EE 382 Applied Electromagnetics Lecture 8: Maxwell's Equations and Electrical CIrcuits [http://montoya.sdsmt.edu/ee382/lectures/382Lecture8.pdf]

Transmission-line

Telegrapher’s equations

EECS 723- Microwave Engineering Spring 2009. 2.1 -The Lumped Element Circuit Model for Transmission Lines [https://www.ittc.ku.edu/~jstiles/723/handouts/2_1_Lumped_Element_Circuit_Model_package.pdf]

[https://www.ittc.ku.edu/~jstiles/723/handouts/section_2_1_The_Lumped_Element_Circuit_Model_package.pdf]

[https://www.ittc.ku.edu/~jstiles/723/handouts/section_2_1_The_Lumped_Element_Circuit_Model_present.pdf]

Transmission Line Wave Equation

Characteristic Impedance (\(Z_0\))

Remember, S-parameters don't mean much unless you know the value of the reference impedance (it's frequently called Z0).

simulator will read sp file's Z0 parameter

The default Z0 exported by EMX is 50

Input impedance (Line Impedance)

Reflection Coefficient

TODO 📅

Steady -State Solution (DC voltage division)

Sam Palermo. [https://people.engr.tamu.edu/spalermo/ecen689/lecture3_ee689_tlines.pdf]

Kyoung-Jae Chung. Special Topics in Radiation Engineering (High-voltage pulsed power engineering) [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lecture_03_Transmission%20line%20theory.pdf]

David R. Jackson. [https://courses.egr.uh.edu/ECE/ECE3317/SectionJackson/Class%20Notes/Notes%208%203317%20Transmission%20Lines%20(Bounce%20Diagram).pdf]

Shouri Chatterjee [https://web.iitd.ac.in/~shouri/ell112/material/txline.pdf]

How can I go from transmission line model to lumped elements model? [https://physics.stackexchange.com/a/386603]

Input impedance

E157 Introduction to Radio Frequency Circuit Design [https://pages.hmc.edu/mspencer/e157/fa24/]

Eric Bogatin. Pop Quiz: When is an Interconnect Not a Transmission Line? [https://www.signalintegrityjournal.com/blogs/4-eric-bogatin-signal-integrity-journal-technical-editor/post/265-pop-quiz-when-is-an-interconnect-not-a-transmission-line]

Shen Lin. On-Chip Inductance and Coupling Effects [http://eda.ee.ucla.edu/pub/asic.pdf]

A. Deutsch et al., "When are transmission-line effects important for on-chip interconnections?," in IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 10, pp. 1836-1846, Oct. 1997

Ho, Ron. “Chip Wires: Scaling and Efficiency.” (2003). [https://www-vlsi.stanford.edu/people/alum/pdf/0303_Ho_Wires.pdf]

—. ISSCC 2007 T3: Dealing with Issues in VLSI Interconnect Scaling, by Ron Ho

Tony Chan Carusone. ISSCC 2017 T6: Signal Integrity Analysis for Gb/s Links

Byungsub Kim ISSCC 2022 T11: "Basics of Equalization Techniques: Channels, Equalization, and Circuits"

Voltage scattering

transmitted voltage \[ V= \frac{2Z_l}{Z_l+R_0}\frac{V_s}{2}= \frac{Z_l}{Z_l+R_0}\cdot V_s \]

Voltage Transfer Function

Reflection Coefficients

Rational Fit

Matlab/rationalfit

To resolve the convergence problem of s-parameter in Spectre simulator - rationalfit and write Verilog-A

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filename  = 'touchstone/ISI.S4P';
s4p = read(rfdata.data, filename);
sdd_params = s2sdd(s2p.S_Parameters, 2);
sdd21 = squeeze(sdd_params(2, 1, :));   % s21
freq = s4p.Freq;

% rational fitting
weight = ones(size(sdd21));
weight(floor(end*3/4):end) = 0.2;
weight(2:10) = 0;

[hfit, errb] = rationalfit(freq, sdd21, 'IterationLimit', [4, 16], 'Delayfactor', 0.98, ...
    'Weight', weight, 'Tolerance', -38, 'NPoles', 32);
[sdd21_fit, ff] = freqresp(hfit, freq);

figure(1)
plot(freq/1e9, db(sdd21), 'b-'); hold on;
plot(ff/1e9, db(sdd21_fit), 'r-'); hold off; grid on;
legend('sdd21', 'sdd21\_fit');
xlabel('Freq (GHz)');
ylabel('magnitude (dB)');


ts = 1e-12;
n = 2^18;
trise = 4e-14;
[yout, tout] = stepresp(hfit, ts, n, trise);
figure(2)
plot(tout*1e12, yout, 'b-'); grid on;
xlabel('Time (ps)');
ylabel('V');
title('Step Response');


% write verilog-A
writeva(hfit, 'channel_32poles.va');

Using S Parameters to Estimate Q

TODO 📅

Jeff Walling. ECE 5984 Using S Parameters to Estimate Q [https://youtu.be/PXgM6pGIRvk?si=YDeh-COQEBXKUiw-]

Simulating S-parameters in a time domain

reference

microwaves101, S-parameters (https://www.microwaves101.com/encyclopedias/s-parameters)

Pupalaikis, P. (2020). S-Parameters for Signal Integrity. Cambridge: Cambridge University Press. doi:10.1017/9781108784863

Coelho, C. P., Phillips, J. R., & Silveira, L. M. (n.d.). Robust rational function approximation algorithm for model generation. Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). doi:10.1109/dac.1999.781313

Cadence IEEE IMS 2023, Introducing the Spectre S-Parameter Quality Checker and Rational Fit Model Generator [https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009lplhEAA]

The Complex Art Of Handling S-Parameters: The importance of extraction and fitting to circuit simulation involving S-parameters [https://semiengineering.com/the-complex-art-of-handling-s-parameters]

Dr. John Choma. EE 541, Fall 2006: Course Notes #2 Scattering Parameters: Concept, Theory, and Applications [https://www.ieee.li/pdf/essay/scattering_parameters_concept_theory_applications.pdf]

Dr. Ray Kwok . Network Techniques: Conversion between Filter Transfer Function and Filter Scattering (SMatrix) Parameters [https://www.sjsu.edu/people/raymond.kwok/docs/project172/FTF%20to%20S-Matrix%20Spring%202011.pdf]

Three fast time-domain system simulation techniques:

• single-bit response method
• double-edge response method
• multiple-edge response method

Single-Bit Response (SBR) Method

Overlapping portions of a pulse response from neighboring bits are referred to as intersymbol interference (ISI). A received waveform is formed by superimposing, in time, the pulse responses of each bit in the sequence, as illustrated in Figure 9, assuming symmetric positive and negative pulses are transmitted for 1s and 0s

To avoid spurious glitches between consecutive ones, rising and falling edge responses shall be symmetric. This is the limitation of SBR method.

Let \(p(t)\) be the SBR of the channel, \(t_s\) be the data sampling phase, \(T\) be the bit time, \(N_c\) is the number of UI in stored pulse response and \(b_m\) be the \(m\)th transmitted symbol. The voltage seen by the receiver's data sampler at the \(m\)th data sample is determined by \[ y_m = \sum_{k=m-N_c+1}^{m}b_kp(t_s+(m-k)T) \] where \(b_k \in [0, 1]\) and \(p(t) \ge 0\)

We always prepend \(Nc-1\) 0s in random bit stream for consistency.

For computation convenient, the pulse need to be positive. For differential signal and amplitude \(V_{peak}\), the peak to peak is \(-V_{peak}\) to \(+V_{peak}\). After pulse added by \(V_{peak}\), peak to peak is \(0\) to \(+2V_{peak}\).

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hold on;

yy_sum = zeros(OSR*Ns, Ns);
for idxBit = 1:Ns
    bs_split = zeros(1, Ns+Nc-1);
    bs_split(idxBit) = bs(idxBit);
    yy = zeros(OSR, Ns);
    for ii = Nc:Nc+Ns-1
        bb = bs_split(ii:-1:ii-Nc+1);
        yy(:,ii-Nc+1) = sum(bb.*yrps, 2);
    end
    yy_cont2 = reshape(yy, [], 1);
    h = plot(yy_cont2);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
    yy_sum(:, idxBit) = yy_cont2;
end
yy_sum = sum(yy_sum, 2);    % merge
plot(yy_sum, 'k--');
plot(yy_cont, 'm-.');
grid on;
legend('sum', 'syn');
title('merge all single bit');
ylabel('mag');
xlabel('Time (\times Ts)');

The pulse response contain rising and falling edge. The 1 bit first rise from -1 to 1, then fall to -1; The 0 bit just do nothing for synthesized waveform with the help of falling edge of 1 bit.

The DC shift help deal with continuous 0 bits.

another SBR example

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A = zeros(10,21);
n = [1:10];

% post cursor
for m = 1:3
    A(m, 11+n(m)) = 0.5;
    A(m, 11-n(m)) = 0.5;
end

% one
for m = 4:10
    A(m, 11) = 1;
end

% h0 or main cursor
h0 = zeros(1, 21);
h0(1, 1) = 0.5;
h0(1, 21) = 0.5;
out = h0;

for m = 1:10
    out = conv(out, A(m, :), "full");
end


stem(out)

Double-Edge Response (DER) Method

To handle the more general cases, with asymmetric rising and falling edges, the system response can be constructed in terms of edge transitions instead of bit responses.

The DER method decomposes the input data pattern, in terms of rising and falling edge transitions. The system response can be calculated by superimposing the shifted versions of the rising and falling edge responses : \[ y_m = \sum_{k=m-N_c+1}^{m}(b_k-b_{k-1})s_k(t_s+(m-k)T) + y_{int} \] where

\[\begin{align} s_i(t) &= r(t) -V_{low} \quad \text{if} \: (b_i\gt b_{i-1}) \\ &= V_{high}-f(t) \quad \text{otherwise} \end{align}\]

\(r(t)\) and \(f(t)\) are the rising and falling edge responses,respectively. \(V_{high}\) and \(V_{low}\) are the steady state DC levels, in response to a constant stream of ones and zeros, respectively. \(y_{int}\) is the initial DC state (either \(V_{high}\) or \(V_{low}\) ).

We always prepend \(Nc\) 0s in random bit stream for consistency.

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figure(1)
subplot(3, 1, 1)
plot(yrc);
hold on;
plot(yfc);
hold off;
legend('rising', 'falling')
grid on;
ylabel('mag');
xlabel('Time (\times Ts)');
title('step response');

subplot(3, 1, 2)
stem(bs, 'k'); grid on;
hold on;
stem((idxPreRspStart:idxPreRspEnd), bs(idxPreRspStart:idxPreRspEnd), "filled", 'r');
stem(idxPreRspStart, bs(idxPreRspStart), 'go');
stem(idxCurData, bs(idxCurData), "filled", 'm');
stem((idxPreRspStart:idxPreRspEnd)+0.5, 0.1.*bd(idxPreRspStart:idxPreRspEnd), 'bd-.');
hold off;
legend('', 'Nc bits', 'y_{int}', 'Current bit', 'Edge Transitions');
ylabel('mag');
xlabel('Time (\times UI)');
title('input stream');

subplot(3, 1, 3)
yy_cont = reshape(yy, [], 1);   % continuous version
plot(yy_cont); grid on;
title('continuous yout')
ylabel('mag');
xlabel('Time (\times Ts)');

figure(2)
hold on;
for idx = idxPreRspStart+1-Nc:idxCurData+32-Nc
    ys = yy(:, idx);
    tt = ((idx-1)*OSR+1:idx*OSR);
    h = plot(tt(:), ys(:), 'LineWidth',3);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
end
plot(yy_cont, 'm--', 'LineWidth',1);
hold off;
legend('syn')
ylabel('mag');
xlabel('Time (\times Ts)');
title('synthesize with step response');
grid on;

Reference

T. C. Carusone, "Introduction to Digital I/O: Constraining I/O Power Consumption in High-Performance Systems," in IEEE Solid-State Circuits Magazine, vol. 7, no. 4, pp. 14-22, Fall 2015

Oh, Kyung Suk Dan, and Xing Chao Chuck Yuan. High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting. Prentice Hall, 2011.

Ren, Jihong and Kyung Suk Oh. “Multiple Edge Responses for Fast and Accurate System Simulations.” IEEE Transactions on Advanced Packaging 31 (2008): 741-748.

Shi, Rui. “Off-chip wire distribution and signal analysis.” (2008).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

Jitter measurements can be classified into three categories: cycle-to-cycle jitter, period jitter, and long-term jitter

Jitter is a key performance parameter. Need to know what matters in each case:

• PJ for digital timing
• LTJ for data converters and serial data
• Phase noise for communications (not all bandwidths matter)

The above Cycle-Cycle Jitter equation is wrong, \(\tau_1\) and \(\tau_2\) are not independent

Short Term Jitter

Period jitter, Jper is the short term variation in clock period compared to the average (mean) clock period.

Cycle-to-Cycle, Jcc is the time difference of two adjacent clock periods

Long Term Jitter (LTJ)

measuring LTJ

Jitter Calculation Examples

Jcc vs Jper

Estimating the RMS cycle-to-cycle jitter if all you have available is the RMS period jitter.

• Cycle-to-cycle jitter - The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as \(J_{CC}\), may be specified as either an RMS or peak-to-peak quantity.
• Period jitter - The short-term variation in clock period over all measured clock cycles, compared to the average clock period. This jitter measure, abbreviated here as \(J_{PER}\), may be specified as either an RMS or peak-to-peak quantity.

Let the variable below represent the variance of a single edge’s timing jitter, i.e. the difference in time of a jittery edge versus an ideal edge, \(\sigma^2_j\)

If each edge’s jitter is independent then the variance of the period jitter can be written as \[\begin{align} \sigma^2_\text{jper} &= (\sigma_\text{j(n+1)}-\sigma_\text{j(n)})^2 \\ &= \sigma_\text{j(n+1)}^2-2\sigma_\text{j(n+1)}\sigma_\text{j(n)})+\sigma_\text{j(n)})^2\\ &= \sigma_\text{j(n+1)}^2+\sigma_\text{j(n)})^2 \\ &=2\sigma^2_j \end{align}\]

In every cycle-to-cycle measurement we use one "interior" clock edge twice and therefore we must account for this

\[\begin{align} \sigma^2_\text{jcc} &= (\sigma_\text{jper(n+1)}-\sigma_\text{jper(n)})^2 \\ &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \end{align}\]

Since each edge's jitter is assumed to be independent and have the same statistical properties we can drop the cross correlation terms and write:

\[\begin{align} \sigma^2_\text{jcc} &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \\ &=\sigma_\text{j(n+2)}^2+4\sigma_\text{j(n+1)}^2+\sigma_\text{j(n)}^2 \\ &=6\sigma_\text{j}^2 \end{align}\]

The ratio of the variances is therefore \[ \frac{\sigma^2_\text{jcc}}{\sigma^2_\text{jper}} = \frac{6\sigma_\text{j}^2} {2\sigma_\text{j}^2}=3 \] Then \[ \sigma_\text{jcc} = \sqrt{3}\sigma_\text{per} \]

[Timing 101 #8: The Case of the Cycle-to-Cycle Jitter Rule of Thumb, Silicon Labs]

Cadence Sampled Phase Noise

How to derive edge phase noise from Output Noise in sampled Pnoise simulation, [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/56929/how-to-derive-edge-phase-noise-from-output-noise-in-sampled-pnoise-simulation]

[Shawn Logan, Summary of Study of Cadence Sampled Phase Noise and Jitter Definitions with a Comparison to Conventional Time Interval Error (TIE) for a Driven Circuit]

General relationships between variance of jitter and phase noise

Understanding jitter and phase noise : a circuits and systems perspective

references

AN10007 Clock Jitter Definitions and Measurement Methods, SiTime [pdf]

SERDES Design and Simulation Using the Analog FastSPICE Platform, Silicon Creations [pdf]

Flexible clocking solutions in advanced processes from 180nm to 5nm, Silicon Creations [pdf]

One-size-fits-all PLLs for Advanced Samsung Foundry Processes, Silicon Creations [pdf]

Circuit Design and Verification of 7nm LowPower, Low-Jitter PLLs, Silicon Creations, [pdf]

Lecture 10: Jitter, ECEN720: High-Speed Links Circuits and Systems Spring 2023 [pdf]

Loop Inductance is the sum of partial self-inductance and partial-mutual inductance

Magnetic Vector Potential (磁矢势)

Youjin Deng. 5-3 静磁场的基本规律 [http://staff.ustc.edu.cn/~yjdeng/EM2022/pdf/5-2(2022).pdf]

磁场不能用标量势描述

Partial Inductance

self partial inductance

mutual partial inductance

Ex. two-wire

[https://www.oldfriend.url.tw/Q3D/ansys_ch_Partial_Loop_Inductance.html]

Current Return Path

Current return paths are frequency dependent \(Z = R +j\omega L\)

• Low frequency
  • \(R\) dominates - current use as many returns as possible to have parallel resistances
• High frequency
  • \(j\omega L\)​ dominates - current use the closest possible return path to form the smallest possible loop inductance
• Very high frequency
  • The current would be confined to the nearest possible return only at ultra-high frequencies (skin effect)

EMX simulation

setup:

frequency sweep:

Cadence October 2020, Analysis of a Figure-Eight Inductor with EMX RAK

proximity effect & skin effect

• Skin effect concentrates current near the surface of a single conductor, while proximity effect concentrates current in specific regions of multiple conductors due to their interaction
• Skin effect is caused by the conductor's own magnetic field, while proximity effect is caused by the magnetic field of a nearby conductor

proximity effect is a redistribution of electric current occurring in nearby parallel electrical conductors carrying alternating current (AC), caused by magnetic effects (eddy currents)

skin effect is the tendency of AC current flow near the surface (or "skin") of a conductor, rather than throughout its cross-section, due to the magnetic field generated by the current itself

Cause of skin effect

A main current \(I\) flowing through a conductor induces a magnetic field \(H\). If the current increases, as in this figure, the resulting increase in \(H\) induces separate, circulating eddy currents \(I_W\) which partially cancel the current flow in the center and reinforce it near the skin

Eddy current

By Lenz's law, an eddy current creates a magnetic field that opposes the change in the magnetic field that created it, and thus eddy currents react back on the source of the magnetic field

Electromagnetic coupling

Electric field coupling (also called capacitive coupling) occurs when energy is coupled from one circuit to another through an electric field

Magnetic field coupling (also called inductive coupling) occurs when energy is coupled from one circuit to another through a magnetic field

For instance

• magnetic coupling between multiple inductors
• capacitive coupling between multiple transmission lines

Grounding

TODO 📅

Chapter 11 Layout and grounding [http://ieb-srv1.upc.es/gieb/tecniques/doc/EMC/pdfs/ScienceDirect_articles_27Jul2018_12-16-10.699/Chapter-11---Layout-and-grounding_2007_EMC-for-Product-Designers.pdf]

Decoupling Capacitor

reference

ISSCC2002. Special Topic Evening Discussion Sessions SE1: Inductance: Implications and Solutions for High-Speed Digital Circuits [vSE1_Blaauw], [vSE1_Gauthier], [vSE1_Morton, [vSE1_Restle]]

Y. Massoud and Y. Ismail, "Gasping the impact of on-chip inductance," in IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14-21, July 2001 [https://sci-hub.se/10.1109/101.950046]

Clayton R. Paul, Partial Inductance [https://ewh.ieee.org/soc/emcs/acstrial/newsletters/summer10/PP_PartialInductance.pdf]

Cheung-Wei Lam. Common Misconceptions about Inductance & Current Return Path [https://ewh.ieee.org/r6/scv/emc/archive/022010Lam.pdf]

Randy Wolff. Signal Loop Inductance in [Pin] and [Package Model] [https://ibis.org/summits/feb10/wolff.pdf]

ANSYS Q3D Getting Started LE05. Module 5: Q3D Inductance Matrix Reduction [https://innovationspace.ansys.com/courses/wp-content/uploads/sites/5/2021/07/Q3D_GS_2020R1_EN_LE05_Ind_Matrix.pdf]

Paul, Clayton R. Inductance: Loop and Partial. Hoboken, N.J. : [Piscataway, N.J.]: Wiley ; IEEE, 2010.

Spartaco Caniggia. Signal Integrity and Radiated Emission of High‐Speed Digital Systems. Wiley 2008

Yuriy Shlepnev. How Interconnects Work: Characteristic Impedance and Reflections [https://www.linkedin.com/pulse/how-interconnects-work-characteristic-impedance-yuriy-shlepnev/]

-. How Interconnects Work: Bandwidth for Modeling and Measurements [https://www.linkedin.com/pulse/how-interconnects-work-bandwidth-modeling-yuriy-shlepnev/?trackingId=874kpm3XuNyV9D0eP6IioA%3D%3D]

Eric Bogatin. Pop Quiz: When is an Interconnect Not a Transmission Line? [https://www.signalintegrityjournal.com/blogs/4-eric-bogatin-signal-integrity-journal-technical-editor/post/265-pop-quiz-when-is-an-interconnect-not-a-transmission-line]

TeledyneLeCroy/SignalIntegrity Python tools for signal integrity applications [SignalIntegrityApp]

A Look at Transmission-Line Losses [http://blog.teledynelecroy.com/2018/06/a-look-at-transmission-line-losses.html]

How Much Transmission-Line Loss is Too Much? [http://blog.teledynelecroy.com/2018/06/how-much-transmission-line-loss-is-too.html]

Raymond Y. Chen, Raymond Y. Chen. Fundamentals of S Fundamentals of S-Parameter Parameter Modeling for Power Distribution Modeling for Power Distribution System (PDS) and SSO Analysis System (PDS) and SSO Analysis [https://ibis.org/summits/jun05/chen.pdf]

Assuming Target \(T\) ( for example, the total resistance) is function of \(x_1,x_2,...,x_N\), then total variation can be expressed as

\[\begin{align} dT &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}dx_n \\ &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}x_n\cdot \frac{dx_n}{x_n} \end{align}\]

Then, we obtain relative variation \[\begin{align} \frac{dT}{T} &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}\frac{x_n}{T}\cdot \frac{dx_n}{x_n} \\ &= \sum_{n=1}^N S_{x_n}^T \cdot \frac{dx_n}{x_n} \end{align}\]

⭐ where \(S_{x_n}^T=\frac{\partial T}{\partial x_n}\frac{x_n}{T}\) is relative sensitivity

relative sensitivity connect \(\frac{dx_n}{x_n}\) with total relative variation \(\frac{dT}{T}\)

And \(dT\) can be expressed as \[ dT =\sum_{n=1}^N S_{x_n}^T T\cdot \frac{dx_n}{x_n} = \sum_{n=1}^N x_n'\cdot \frac{dx_n}{x_n} \] ⭐ where \(x_n'= S_{x_n}^T T\) is the contribution of \(x_n\) in \(T\)

⭐ For parallel or series resistors, it can prove \(\sum_{n=1}^N S_{x_n}^T = 1\) and \(\sum_{n=1}^N x_n'=T\)

Here \(T= R_1 \parallel R_2 = \frac{R_1R_2}{R_1+R_2}\), and \(T|_{R_1=8000, R_2=2000} = 1600\)

We obtain relative sensitivity: \[\begin{align} S_{R_1}^T & = \frac{R_2}{R_1+R_2} \\ S_{R_2}^T & = \frac{R_1}{R_1+R_2} \end{align}\]

The contribution of \(R_1\) and \(R_2\) to \(T\) \[\begin{align} R_1' &= S_{R_1}^T T | _{R_1=8000, R_2=2000} = 320 \\ R_2' &= S_{R_2}^T T | _{R_1=8000, R_2=2000} = 1280 \end{align}\]

Normalized sensitivity captures relative sensitivity

change in objective per change in design variable

reference

Olivier de Weck, Karen Willcox. MIT, Gradient Calculation and Sensitivity Analysis [pdf]

Karti Mayaram, ECE 521 Fall 2016 Analog Circuit Simulation, Sensitivity and noise analyses [https://web.engr.oregonstate.edu/~karti/ece521/lec16_11_09.pdf]

Transit frequency \(f_T\)

aka cut-off frequency

Gate (thermal) noise

Two-Side Poly Contact & folding

Both scheme yield a total distributed resistance of \(R_G/4\) for gate noise calculation

folding

finger 0 \[\begin{align} \overline{i_{tot,0}^2} &= \left(\frac{g_m}{2} \right)^2(4kT\frac{R_G/2}{3}) \\ &= g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \end{align}\]

similarly finger 1 \[ \overline{i_{tot,1}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \] Assuming uncorrelated \[ \overline{i_{tot}^2} = \sum_{N=0}^1\overline{i_{tot,N}^2} =g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \cdot 2 = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2} \] Generally \[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2} \] where the gate is decomposed into \(N\) parallel fingers

two-side poly contact

We fracture Gate poly at the center point, then we obtain 2 segments, both have same \(\frac{g_m}{2}\) and \(R_G/2\).

The derivation procedure is same with folding structure, i.e. plug \(N=2\) into \(\overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2}\)

That is \[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{12}\right) \] The input referred noise of gate resistance \[ \overline{V_{nRG}^2} = 4kT\frac{R_G}{12} \]

four equal gate fingers

\[ \overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{4^2} \] Then \[ \overline{V_{nRG}^2} = \frac{\overline{i_{tot}^2}}{g_m^2} =4kT\frac{R_G}{48} \]

Gate resistance handling by parasitic extraction tools

They fracture the poly line at the intersection with the active (diffusion) layer, breaking it into "gate poly"(poly over active) and "field poly" (poly outside active)

gploy, fpoly

Gate poly is also fractured at the center point. Gate instance pin of the MOSFET (SPICE model) is connected to the center point of the gate poly. Gate poly is described by two parasitic resistors, connecting the fracture points.

MOSFET extrinsic parasitic capacitance between gate poly and source / drain diffusion and contacts is calculated by parasitic extraction tools, and assigned to the nodes of the resistive networks.

Different extraction tools do this differently - some tools connect these parasitic capacitances to the center point of the gate poly, while some other tools connect them to the end points of the gate poly resistors.

\(\Delta\) gate model

This distributed network has a different AC and transient response than a simple lumped one-R and one-C circuit.

It was shown [B. Razavi] that such RC network behaves approximately the same as a network with one R and one C element, where C is the total capacitance, and R=1/3 * W/L rsh for single-side connected poly, and R=1/12 W/L * rsh for double-sided connected poly.

These coefficients - 1/3 and 1/12 - effectively enable an accurate reduced order model for the gate, reducing a large number of R and C elements to two (or three) resistors and one capacitor.

Gate Delta Model: where a gate is described by two positive and one negative resistors

only applicable to contacts on gate overhangs

invalid for self-aligned gate contacts, where gate contact land directly on top of gate, not gate overhang

1. 1-side gate contact \[ R_{eq,1side} =R_1 \parallel (R_2+R_1)= \frac{R_G}{6}\parallel (-\frac{R_G}{2}+\frac{R_G}{6})=\frac{R_G}{3} \]

2. 2-side contact \[ R_{eq,2side}= R_1 \parallel R_1 = \frac{R_G}{6}\parallel \frac{R_G}{6} = \frac{R_G}{12} \]

Some SPICE simulators have problems handling negative resistors, that's possibly why this model did not get a wide adoption. Some foundries and PDKs support delta gate model, while some others don't.

Vertical component of gate resistance

In "old" technologies (pre-16nm), gate resistance was dominated by lateral resistance. However, in advanced technologies, multiple interfaces between gate material layers lead to a large vertical gate resistance.

It's very easy to check this in DSPF file - if gate instance pin is connected directly to the center of the gate poly - vertical resistance is not accounted for. If it is connected by a positive resistor to the center of the gate poly - that resistors represents the vertical gate resistance.

decap

leakage current is determined by \(R_s + R_p\), and \(R_p \gg R_s\)

• low freq: \(Z=R_s + R_p\)
• high freq: \(Z=R_s\)

An example: \(R_s=200\space \Omega\), \(R_p = 8 \space M\Omega\) and \(C_\text{gate}=10\space fF\)

reference

⭐ B. Razavi, Y. Ran, and K. F. Lee, “Impact of Distributed Gate Resistance on the Performance of MOS Devices,” IEEE Trans. Circuits and Systems, Part I, pp. 750–754, Nov. 1994.

⭐ Maxim Ershov, Diakopto. "Gate Resistance in IC design flow", [link, pdf]

A.J.Sholten et al., "FinFET compact modelling for analogue and RF applications", IEDM'2010 [https://sci-hub.se/10.1109/IEDM.2010.5703322]

Saha, Samar K.. “FinFET Devices for VLSI Circuits and Systems.” (2020).

Harpe, Pieter J. A., Andrea Baschirotto and Kofi A. A. Makinwa. “Hybrid ADCs, Smart sensors for the IoT, and Sub-1V and Advanced node analog circuit design: Advances in Analog Circuit Design 2017.” (2018).

Chauhan, Yogesh Singh. FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard. London, UK: Academic Press, 2015.

A.J.Sholten et al., "FinFET compact modelling for analogue and RF applications", IEDM'2010, p.190.

W. Wu and M. Chan, “Gate resistance modeling of multifin MOS devices,” IEEE Electron Device Letters, vol. 27, no. 1, pp. 68-70, Jan. 2006.

A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

realtime vs time

• $realtime round the current time to timeprecision

• $time round the current time to integer

• %t will scale the rounded value to represent timeprecision,

  i.e. \([\$\text{realtime}, \$\text{time}]\cdot \$\text{timeunit} / \$\text{timeprecision}\)

https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94062 https://verificationacademy.com/forums/systemverilog/time-vs-realtime#answer-94096

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module tb;
  timeunit 10ns;
  timeprecision 1ps;

  initial begin
    $display("$realtime = %g", $realtime);
    $display("$time = %g", $time);
    // $realtime round to timeprecision
    // $time round to integer
    #1.10016
    $display("$realtime = %g", $realtime);
    $display("$time = %g", $time);

    // %t format will scale the rounded value to represent timeprecision
    // 1.1002*10e-9/1e-12 = 11002
    $display("$realtime %%t = %t", $realtime);
    $display("$time %%t = %t", $time);
  end
endmodule

output

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$realtime = 0
$time = 0
$realtime = 1.1002
$time = 1
$realtime %t =                11002
$time %t =                10000

timeunit, timeprecision

The time unit and time precision can be specified in the following two ways: - Using the compiler directive `timescale - Using the keywords timeunit and timeprecision

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module D (...);
  timeunit 100ps;
  timeprecision 10fs;
  ...
endmodule

module E (...);
  timeunit 100ps / 10fs; // timeunit with optional second argument
  ...
endmodule

The minimum of timeprecision determine %t output, the nearest timeunit and timeprecision determine the round of $realtime and $time. Of course, the simulator follow the time tick shown by $realtime.

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`timescale 1ns/1ns

// Due to minimum of timeprecision is 10ps
module rawplant;
  timeunit 1ns;
  timeprecision 100ps;

  task print;
    /*
    1ns: 1
    100ps:  6
    10ps: 6
    1ps: 6
    */
    #1.666
    $display("raw: $realtime = %g", $realtime);     // 1.7
    $display("raw: $time = %g", $time);             // 2
    $display("raw: $realtime %%t = %t", $realtime); // 1.7*1ns/10ps=170
    $display("raw: $time %%t = %t", $time);         // 2*1ns/10ps = 200
  endtask

endmodule

module fineplant;
  timeunit 100ps;
  timeprecision 10ps;

  task print;
    /*
    100ps: 2
    10ps: 6
    1ps: 6
    */
    #2.66
    $display("fine: $realtime = %g", $realtime);     // 2.7
    $display("fine: $time = %g", $time);             // 3
    $display("fine: $realtime %%t = %t", $realtime); // 2.7*100ps/10ps = 27
    $display("fine: $time %%t = %t", $time);         // 3*100ps/10ps = 30
  endtask

endmodule

module tb;
  rawplant rawblock();
  fineplant fineblock();

  initial begin
  fork
    rawblock.print();
    fineblock.print();
  join
  end
endmodule

output

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fine: $realtime = 2.7
fine: $time = 3
fine: $realtime %t =                   27
fine: $time %t =                   30
raw: $realtime = 1.7
raw: $time = 2
raw: $realtime %t =                  170
raw: $time %t =                  200

questasim cmd

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vlib work
vlog tb.v
vsim -c -do "run -all;exit" work.tb