Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing,
3rd edition [pdf]
R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th
ed., Wiley, 2013 [pdf]
John G. Proakis and Masoud Salehi, Fundamentals of communication
systems 2nd ed [pdf]
Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System
Perspectives and Circuit Design Aspects. John Wiley & Sons
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007
Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers,
oscillators, samplers, and logic: an introduction to cyclostationary
noise." Proceedings of the IEEE 2000 Custom Integrated Circuits
Conference. [pdf, slides]
note result browser show noise contribution, which is
same with noise summary
res isnoisy
differential R/C simulation
The left testbench is better choice for differential R/C extraction.
because the right testbench may have uncontrolled AC common
stimulus, which is undesired
ACMatch analysis linearizes the circuit about the DC operating point
and computes the variations of AC responses
due to statistical parameters defined in statistics blocks.
Only mismatch parameters are considered. The analysis skips the
process parameters.
//Curve parameters real gm; real A; real factor; real Vop; real vcp;
integer light_i; integer en; analog begin
@(initial_step) begin en = 0; A = 1; Vop = 1; factor = 10; end //Enable digitalization @(cross(V(EN)-vthreshold,1)) begin if(V(EN)>=vthreshold) en = 1; else en = 0; end case(light): 0: begin A = 0; Vop = 0; end 1: begin A = -1.2; Vop = 1.71; end 2: begin A = -0.8; Vop = 1.64; end 3: begin A = -0.4; Vop = 1.50; end 4: begin A = 0.1; Vop = 1.43; end 5: begin A = 0.7; Vop = 1.36; end 6: begin A = 1.1; Vop = 1.22; end default: begin A = -1.2; Vop = 1.71; end endcase
//gm = A + atan(factor*(Vop-V(Vsolar))); //Transconductance
alias bk hiSetBindKey when ( isCallable('schGetEnv') bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")") bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")") bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")") bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()") bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)") ) unalias bk
leBindKeys.il
layout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
alias bk hiSetBindKey when ( isCallable('leGetEnv) bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" ) ; M1-VIA1-M2 bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" ) ; M2-VIA2-M3 bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" ) ; M3-VIA3-M4 bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" ) ; M4-VIA4-M5 ; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" ) ; all visiable bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" ) ) unalias bk
Design Variable in vpwlf
PWL File as Design Var? parameter in vpwlf cell
is convenient for sweep simulation or corner simulation, wherein there
are multiple pwl files .
The file path should be surrounded with
double-quotes to be protected from evaluation.
save option
Using Spectre Save Effectively RAK
none:
Does not save any data (currently does save one node chosen at
random)
selected:
Saves only signals specified with save statements. The default
setting.
lvlpub:
Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.
lvl:
Saves all signals up to nestlvl deep in the subcircuit hierarchy.
This option is relevant for subcircuits.
allpub:
Saves only signals that are normally useful.
all:
Saves all signals.
Signals that are "normally useful" include the shared node voltages
and currents through voltage sources and iprobes, and exclude the
internal nodes on devices (the internal collector, base, emitter on a
BJT, the internal drain, source on a FET, and so on). It also excludes
currents through inductors, controlled sources, transmission lines,
transformers, etc.
If you use lvl or all instead of
lvlpub or allpub, you will also get
internal node voltages and currents through other components that happen
to compute current.
Thus, using *pub excludes internal nodes on devices
(the internal collector, base, emitter on a BJT, the internal drain and
source on a FET, etc). It also excludes the currents through inductors,
controlled sources, transmission lines, transformers, etc.
nestlvl
This variable is used to save groups of signals as results and when
signals are saved in subcircuits. The nestlvl parameter also specifies
how many levels deep into the subcircuit hierarchy you want to save
signals.
virtuoso "dlopen failed
to open 'libdl.so'"
1
$ sudo yum install glibc-devel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST. Dependencies resolved. ========================================================================================================================================= Package Architecture Version Repository Size ========================================================================================================================================= Installing: glibc-devel x86_64 2.28-189.5.el8_6 baseos 78 k Installing dependencies: glibc-headers x86_64 2.28-189.5.el8_6 baseos 482 k kernel-headers x86_64 4.18.0-372.26.1.el8_6 baseos 9.4 M libxcrypt-devel x86_64 4.1.1-6.el8 baseos 24 k
* DSPF files to use with Corner Definitions * This is an example file showing how to define different dspf files for different corners * using model files for individual components as the * building blocks. simulator lang=spectre library dspf_files_corners
section rcworst_25 dspf_include "DSPF_RC_WORSE25.spf" end section rcworst_25
section rcworst_125 dspf_include "DSPF_RC_WORSE125.spf" end section rcworst_125
endlibrary dspf_files_corners
Add the file created above ‘myDSPF_File.scs’ in
‘Add/Edit Model Files’ of Corners setup form
split pins in dspf_emir
dspf extract using starrc
multiple label and rectangle in vssa net
general dspf
SHORT_PINS: YES
other pin are short together
dspf for emir analysis
It seems that dspf_emir don't contain the
rectangle pin information.
only label is necessary
setup
spectre result
netlist type
dspf option
emir analysis
dspf
/
disable
✓
dspf_emir
/
disable
✗
dspf_emir
shortPins="yes"
disable
✓
dspf_emir
shortPins="no"
disable
✗
dspf_emir
/
enable
✓
dspf_emir
shortPins="yes"
enable
✓
dspf_emir
shortPins=”no”
enable
✓
shortPins="yes" is preferred default option for
dspf_emir, which has split pins
DSPF Syntax
::=*|P ?
describes pins in the net. Multiple pin descriptions can be listed in
one line.
::=( {}?)
represents the name of the pin. represents the type
of the pin. It can be any of the following: I (Input), O (Output),
B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
represents the capacitance value associated with the pin.
is optional. It represents the location of the pin. Multiple pin
locations are allowed
split pins
1 2 3 4 5
*|P (avss_1 O 0 207.7555 59.9170) *|P (avss_10 O 0 181.1610 151.1130) *|P (avss_11 O 0 186.6330 151.1130) *|P (avss_12 O 0 192.1050 151.1130) *|P (avss_13 O 0 197.5770 151.1130)
reference
Article (20467964) Title: Difference in result on running Spectre APS
with EMIR and without EMIR analysis
StarRC User Guide and Command Reference Version O-2018.06, June
2018
DSPF Options
Case Sensitivity
netlist format
default option
Spectre netlist
case sensitive
dspf format
case insensitive
For a dspf format, it will be treated as a spice
netlist format, which is by default case insensitive
Pay attention to VerilogIn block, which may contain upper
case / lower case net name, e.g NET1 and net1.
The extracted DSPF using extraction tool also contain NET1 and net1,
which shall not be shorted together.
Port Order
If you use .dspf_include, the following rules apply:
The subcircuit description is taken from the DSPF file even if the
same subcircuit description is available in the schematic netlist.
Depending on the port_order option, the port order of
the subcircuit definition is taken from the pre-layout schematic netlist
or from the DSPF file subcircuit definition, as shown below.
port_order=sch – (Default). The port order is taken
from schematic subcircuit definition. The same port number and names are
required. If the schematic subcircuit definition is not available, a
warning is issued in the log file, and DSPF port order is used.
port_order=spf – The port order is taken from the DSPF
subcircuit definition.
SPICE_SUBCKT_FILE of StarRC
The StarRC tool reads the files specified by the
SPICE_SUBCKT_FILE command to obtain port ordering
information. The files control the port ordering of the top
cell as well. The port order and the port list members read from the
.subckt for a skip cell are preserved in the output
netlist.
The file usually is the cdl netlist of extracted cell, this
way, port order is not problem
CDF termOrder
DSPF same order
DSPF
input.scs
different order
manual change DSPF's pin order shown as below
port_order=sch
dspf port is mapping to schematic by name, and the
simulation result is right
port_order=spf
dspf pin order is retained, and no mapping between
spectre netlist and dspf.
The simulation result is wrong
bus_delim="_ <>"
The way this works is that the first part of bus_delim is
the "schematic" delimiter (i.e. what's in the spectre netlist), and the
other part is the DSPF delimiter
reference
Article (20502176) Title: How does Spectre understand case-sensitive
net names when using various post-layout netlists such as dspf,
av_extracted view, or smart view?
Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit
Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1
StarRC™ User Guide and Command Reference Version O-2018.06, June
2018
Virtual Connectivity
Normally, if the layout connectivity extractor finds disjoint,
unconnected geometries with the same net name text attached, the
extractor will view this as an open circuit.
Virtual connection results in the extraction of a single net from
two or more disjoint physical nets when the physical net segments share
the same name.
Virtual connectivity is triggered by the rule file VIRTUAL
CONNECT COLON and VIRTUAL CONNECT NAME
specification statements.
Virtual connectivity can also be specified through the Calibre
Interactive GUI.
Virtual connectivity is of primary interest in
LVS applications
connect all nets by name:
VIRTUAL CONNECT NAME "?"
VIRTUAL CONNECT COLON
Virtual Connect Colon is used to virtually connect
nets that share a common prefix before a colon, like
VDD:1, VDD:2, and so forth.
If you specify YES, then the connectivity extractor first
strips off all characters from the first colon to the end of
the label names.
Next, the extractor forms a virtual connection between any two labels
that have the same name and that originally contained a
colon.
Colons can appear anywhere in the name with the exception that a
colon at the beginning of a name is treated as a regular character (that
is, it has no special effect).
up to the first colon character encountered
The colon is discarded in the extracted net
name
VIRTUAL CONNECT NAME
Virtual Connect Name virtually connects nets that
share the same name
Each name is a net name and can be optionally enclosed in quotes.
The connectivity extractor forms a virtual connection between
any two labels having the same name such that
the label name appears in a Virtual Connect Name
specification statement in the rule file.
VIRTUAL CONNECT NAME ? == Connect all nets by name
Note that if Virtual Connect Colon YES is also
specified, then Virtual Connect Name operates on names
after all colon suffixes have been stripped off.
Calibre Interactive stores a list of your most recently opened
runsets in your home directory as .cgidrcdb or
.cgilvsdb for Calibre Interactive DRC or LVS,
respectively.
When invoked, the Calibre DRC and LVS windows automatically load the
runset used when the last session was closed.
Runsets are ASCII files that set up Calibre Interactive for a Calibre
run. They contain only information that differs from the default
configuration of Calibre Interactive. There is a one-to-one
correspondence between entry lines in the runset file and fields and
button items in the Calibre Interactive user interface. Here is as
example of a DRC runset:
The runset filename opened at startup (if no runset is specified on
the command line) can also be specified by setting the
MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC,
and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable
for LVS. If these environment variables are set, they take precedence
over all other runset opening behavior options.
On the transient options form, there's a field called "infotimes" -
specify the times at which you want it to output the dc operating point
data. You can then annotate the "transient operating points" from any of
these times after the simulation, or access them via the results
browser.
Or you could get the operating point data to be continuously saved
during the transient for selected devices - if so, create a file called
(say) "save.scs" (make sure it has a ".scs" suffix), and put: save
M1:oppoint or save M*:oppoint sigtype=dev in this file, and then
reference the file via Setup->Model Libraries or as a "definition
file" on Setup->Simulation Files. With this approach you can then
find the operating point data for the selected devices in the results
browser and plot it versus time (be cautious of saving too much though
because this can generate a lot of data if you're not careful)
<divider> represents the hierarchical pathname
divider. The default hierarchical character is forward slash
(/).
*|DELIMITER <delimiter>
<delimiter> represents the delimiter character
used to concatenate an instance name and pin name to form an instance
pin name.
It is also represents the delimiter character used to concatenate a
net name and subnode number to form a subnode name. The default
character is colon (:)
*|BUSBIT <left_busbit_char><right_busbit_char>
<left_busbit_char> and
<right_busbit_char> are used at the end of an
identifier of an array to select a single object of the array.
Objects which may be indexed include nets, primary pins, and
instance pins
*|NET <netName> <netCap>
<netName> represents the name of a net. It can be
a user-provided net name, the name of the driving pin, or the name of
the driving instance pin.
<netCap> represents the total
capacitance value in farads associated with the net. This may be
comprised of capacitances to ground and capacitances to nearby
wires.
*|P <pinName> <pinType> <pinCap> {<coord>}
<pinName> represents the name of the pin.
<pinType> represents the type of the pin. It can
be any of the following: I (Input), O (Output), B (Bidirectional), X
(don’t care), S (Switch), and J (Jumper).
<pinCap> represents the capacitance value
associated with the pin.
<coord> is optional. It represents the location
of the pin. Multiple pin locations are allowed.
*|S <subNodeName> {<coord>}
subnodes in the net
<subNodeName> represents the name of the subnode.
A subnode name is obtained by concatenating the net name and a subnode
number using the delimiter specified in the DELIMITER statement. The
default delimiter is colon (:).
<instPinName> represents the name of the instance
pin. An instance pin name is obtained by concatenating the
<instName> and the <pinName> with
a delimiting character which is specified by the DELIMITER
statement
<instName> represents the name of the
instance
*|DeviceFingerDelim "@"
MOS finger delimiter
For example, M8's finger is 4, then split into 4 Devices
in DSPF
MM8, MM8@2, MM8@3,
MM8@4
its drain terminal will be
MM8:d, MM8@2:d, MM8@3:d,
MM8@4:d
DSPF Syntax
DSPF has two sections:
a net section
The net section consists of a series of net description blocks. Each
net description block corresponds to a net in the physical design. A net
description block begins with a net statement followed by pins, instance
pins, subnodes, and parasitic resistor/capacitor
(R/C) components that characterize the
electrical behavior of the net.
an instance section
The instance section consists of a series of SPICE instance
statements. SPICE instance statements begin with an
X.
Each file consists of hierarchical cells and interconnects only.
The DSPF format is as generic and as much like SPICE as possible.
While native SPICE statements describe the R/C sections, some non-native
SPICE statements complete the net descriptions. These non-native SPICE
statements start with the notation "*|" to differentiate them from
native SPICE statements. For native SPICE statements, a continuation
line begins with the conventional "+" sign in the first column.
The native SPICE statements used by the DSPF format are listed
below:
.SUBCKT represents a subcircuit statement.
.ENDS represents the end of a subcircuit
statement.
R represents a resistor element.
C represents a capacitor element.
E represents a voltage-controlled voltage sources
element.
X represents an instance of a cell;
* represents a comment line unless it is
*| or *+.
.END is an optional statement that represents the end
of a simulation session
spectre netlist
hier_delimiter="."
Used to set hierarchical delimiter. Length of
hier_delimiter should not be longer than 1, except the
leader escape character
This option maps the bus delimiter between schematic netlist and
parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus
delimiter in the schematic netlist, and optionally the bus delimiter in
the parasitic file. By default, the bus delimiter of the parasitic file
is taken from the parasitic file header (i.e. |BUSBIT [],
|BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not
defined in the parasitic file header, you need to specify it by using
the spfbusdelim option in schematic netlist.
Exampel
spfbusdelim=<> - A<1> in the schematic netlist is mapped
to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is
"_".
spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1]
in the DSPF file (the bus delimiter in DSPF header will be
ignored).
How to Save Net voltage in
DSPF
!!! follow the name of net section in DSPF - prepend to top-level
devices in the schematic with X
Assume node n1...n4 are named as below in DSPF file (prefix
X)
n1
XXosc/zip:1
n2
XXosc/zip:2
n3
XXosc/zip:3
n4
XXosc/zip:4
To save these nodes, you can add follow code in Definition
Files
saveopt.scs
1 2 3 4
save Xwrapper.Xvco.XXosc\/zip\:1 save Xwrapper.Xvco.XXosc\/zip\:2 save Xwrapper.Xvco.XXosc\/zip\:3 save Xwrapper.Xvco.XXosc\/zip\:4
Escape character \ is used for hierarchical pathname
divider / and subnode :
By the way, . is hierarchical delimiter of
Spectre
Calibre always prepend one X to instance name of
schematic in generated DSPF file
The DSPF design is flatten, the DIVIDER character
indicate the hierarchy
1
save Xwrapper.Xvco.XXosc\/zip
The above save voltage, however I'm NOT sure which node it save.
To avoid this unsure problem, the MOS terminal may be better choice
to save.
But keep in mind
OD resistance is lumped in the FEOL model
M0OD and above layer resistances are extracted by RC tool
How to Save Current in DSPF
!!! follow the name of instance section of DSPF - prepend to
top-level devices in the schematic with XX
MOS in schematic: Xsupply.M4
MOS related information in DSPF (prefix XX in instance
section):
1 2 3 4 5 6 7 8 9
... // net section *|I XXsupply/MM4:d XXsupply/MM4 d B 0.0
<instName> in
*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}
which has prefix X corresponding to schematic is
NOT the instance name in DSPF. The instance name is in
instance section and has prefix XX
!!! Only work for MOS terminal current. Fail to apply to block
pin
Thinking about voltage
and current save
MOS device always prepend with M
To save net voltage, take account of the prefix
X of top-level device
To save MOS terminal, take account of the prefix
XX of top-level device
Post-layout netlists are created by layout extraction tools - Mentor
Calibre
Differences
Between DSPF and Schematic Names
MOS Terminal Mismatch ( ‘s’ vs ‘1’)
Schematic: number '1' ,'2', '3','4'
DSPF: 'd', 'g', 's','b'
.simrc file
If DSPF files show such differences, you can set options in the
.simrc file to update the save statement in the
netlist so that the device names match with those in the DSPF
file
Additionally, dspf_include reads all the DSPF lines
starting with * (|NET, |I, *|P,*|S), while
include considers all related lines as comments.
Only verified to DSPF output of Mentor Calibre
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
; ensure that the netlist is recreated each time nlReNetlistAll=t
The net name is x1/x1:DRN. During the simulation, the following
warning is reported:
Warning from spectre during initial setup.
1 2
WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name. WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.
How can I save this net for plotting and measurements?
Solution
The colon (:) in the save statement specifies terminal
current. So, the save statement used above is for terminal
current and, hence, the warning messages are reported.
1
save xpi1.x1\/x1:DRN
You need to modify the save statement as below:
1
save xpi1.x1\/x1\:DRN
Now, run the simulation and the issue will be resolved.
DSPF r vs rcc
rcc
c
only c dspf give the lumped
capacitance
EMIR via Voltus-Fi
general terminology
DC related
Imax in T*'s DRC document is the maximum allowed
DC current, which depends on Length and Width
only
Iavg is the average value of the current, which is
the effective DC current. Therefore, Iavg
rules are identical to Imax
rules \[
I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau}
\] Similarly, Iabsavg rules are
identical to Imax rules, too \[
I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau}
\]
rms
Irms is the root-mean-square of the current through
a metal line, which depends w(in um), the drawn
width of the metal line and \(\Delta
T\), the temperature rise due to Joule heating. \[
I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2}
\]
peak current
Ipeak in T*'s DRC document is the current at which a
metal line undergoes excessive Joule heating and can begin to melt.
Ipeak is corresponding to
EM Current Analysis: max in Voltus-Fi Analysis Setup \[
I_{\text{peak}}=\max(|I(t)|)
\] The limit for the peak current is \[
I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r
} }
\] where r is the duty ratio
The relationship between Ipeak and
Ipeak_DC is merged in DRC document so that there is
only Ipeak equation in document
\(I_{\text{peak,limit}}\) depends on
\(t_D\), r, width and length
\[
r=\frac{t_D}{\tau}
\]
where \(t_D\) is equivalent duration
\[
t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}}
\] or \[
r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}}
\]
where the drawn width is 1um, r is 0.1
\[
9.37*(1-0.004)/\sqrt0.1 = 29.512
\]
acpeak/pwc
It's same with max EM Current Analysis in
Voltus-Fi
dynamicACPeak
This option affect how duty ratio r is computed in max
and acpeak/pwc EM current Analysis
When the dynamicACPeak variable is set to
true or multiPeak\[
r=\frac{T_d}{T_{\text{total}}}
\]
where \(T_{\text{total}} = \text{EMIR time
window}\)
\(T_d\) = the time duration in
microsecond of the total "On Time" period based on IPWC
Pulse-Wise Constant EM current calculation (IPWC)
where Tau is \(T_d\) in above formula
!!! It seems that t*'s PDK don't support
dynamicACPeak=true
IR drop filter layers
EM techfile (qrcTechFile) may take diffusion contact
(n_odtap, p_odtap in DSPF file) into account during IR
drop analysis. And these segment often dominate IR drop, but we as IC
designer can NOT improve them. In general, the IR drop to M1 layer is
enough and feasible.
Regular
analysis statements in emir configuration
1 2
net name=[I0.vdd I0.vss] analysis=[vmax vavg] net name=[I0.*] analysis =[imax ivavg irms]
emirreport command
Creating reports for specific nets after simulation using
emirreport
Create a new config file as shown below:
1 2 3
** test.conf** net name=[I1.VDD I1.VSS] analysis=[iavg] net name=[I1.VBIAS] analysis=[imax]
Run emirreport on the command line using the
emirdatabase (emir*.bin) and test.conf
created above in
input.emir0_bin: The first EMIR Analysis which is DC or
Transient, which depends on Analyses order
input_tran.emir0_bin: EMIR Analysis in Transient
simulation
input_dcOp.emir0_bin: EMIR Analysis in DC
simulation
For example
Two results are generated input.emir0_bin and
input_dcOp.emir0_bin and their reports respectly
Fix Electromigration
Type
wider wire
downsize drivers
decrease fanout
RJ JMAX
✓
✓
JAVG
JABSAVG
JACPEAK
JACRMS
✓
✓
✓
Iavg
The average value of the current, which is the effective DC
current
Irms
Irms rule relates to the heat or Joule-heating of metal
lines
Ipeak
The main goal of the Ipeak limits is to ensure that no thermal
breakdown could occur on single overshoot events. If the signal may not
have a high current density but if it has a very large peak current
density, then, local melting will happen and cause failures
QA
Q. Why “length” column in EM results form doesn’t show extracted
length, it shows “NA”.
A. Voltus-Fi reports the “length” column only when length rules are
present in the emDataFile.
Seeing different port currents with and without emir simulations
for same dspf included in EMIR Direct method using dspf_include.
Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the
regular spectre flow. Islands patching is only performed in EMIR
only
Setting temperature for EM analysis
By Default, Voltus-FI and VPS pick up the current density limit for
temperature at which simulation has been performed.
By the way, Design Variables - temperature will
override the temperature in Setup toolbar which is gray in ADE
Explorer
AC Peak EM analysis - Voltus-Fi
The available options within the EM current analysis section in the
EMIR Analysis Setup form are:
max / avg / avgabs / rms.
In order to enable the AC Peak based information when
loading the EM results, both max and avg should be
selected when setting up the EMIR Analysis Setup.
With this configuration, the AC Peak option becomes available and can
be used.
How to print average, rms, and peak current of device
tap in Spectre/Voltus FI EMIR analysis
The following option enables you to save the average, rms, and peak
tap currents in the emir0bin file and report it in the
input.rpt_tapi file.
1
solver report_tapi=true
Add this option in emir.conf to enable the reporting
of tap current after the Spectre EMIR simulation. The input.rpt_tapi
file will be saved in the psf/raw directory.
Note: This feature is supported in SPECTRE20.1 ISR14
and later versions.
emir.conf file
emir.conf file is generated automaticaly after configure
EM/IR Analysis in ADE, which is in netlist
directory.
Setting default path for EM rules file in APS EMIR analysis
set the following environment variable in your terminal
1
setenv EMDATAFILE < path to EM rules file>
or set in .cdsinit
1
setShellEnvVar("EMDATAFILE=<path to EM rules file>")
Print node names and length associated with parasitic resistors
in EM report file
export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME
Printing the parasitic resistor length in the EM report
1
emirutil reportLength=true
Printing nodes that are associated with the parasitic
resistor
1
emirutil reportNodeName=true
Once these are enabled, you will have the Length,
Node_1, and Node_2 columns printed in
the EM report file, as shown below:
Is it possible to run RMS IR Drop analysis using Voltus-Fi?
Typically, in a simulation, Power/Ground nets are always biased with
a constant DC source. Hence, at present, Voltus-Fi only
supports Average and Maximum (Peak) IR Drop
analysis.
For a net to have data for IR analysis(vmax/vavg), the net/node must
be connected to a DC vsource or a vsource which is constant
within the emir time window.
Can we change the time window of EM computation after the
simulation completed ?
It is not possible to modify the EM time window without re-running
the full simulation.
However you can specify several time window in the emir conf file for
instance for 2 time window [0 to 10n] and [10n 20n]
1
time window=[0 10n 10n 20n]
In that case it will create 2 emir_bin files and
then 2 different em report files according to the 2 different time
windows.
How to print segment_W values being used to compute EM limits
You can use the following option to print segment_W to
the report:
1
emirutil reportSegmentWidth=[true]
This would print a Segment_w column in the report
containing the segment width values used for computing the limit:
Pass/Fail %
Resistor
layer
Current
Width
PathLength
I limit
X1
Y1
X2
Y2
J/JMAX
Res
ViaArea
No of needed vias
width/#via
J limit
Segment_w
(mA)
(um)
(um)
(um)
(um)
(um)
(um)
(nm^2)
(um/#)
(A/um)
pass-100.0
Rj3292
Met1
9.02376e-12
0.1
42.72
1.10067
0.350
11.568
0.350
11.376
8.19843e-12
0.7382
NA
NA
0.0001
0.0110067
0.1
pathLength vs Length in EM report file
Length: parasitic resistor length, which is set by
emirutil reportLength=true
pathlength: Blech length is also known as "Short length" or "Path
length", and can be explained as : The longest and continuous
centerline path from edge to edge among the connected wire
shapes on the same metal layer.
For all resistors falling on this shape, same
pathLength is reported.
After the longest path in shape has been determined the tool applies
the same blech length to all the resistor falling on that shape.
This resistor length is NOT used in EM analysis
because EM rules consider Blech length of the resistor.
where W is the wire width and L is the Blech length.
By default the tool will sum all branches of a given
metal layer. In other words the path length that will be used
to look up the EM density limit is :
To enable EMIR in PSS, you have to enable DC and/or Tran simulation
simultaneously. Two or more binary results file should be generated and
select the file based file name or configure text file in
psf directory.
(given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)
StarRC
NETLIST_CONNECT_OPENS
Connector resistors - non-physical
resistors (well or substrate layer, that is not extracted for
resistance)
A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts
of electromigration awareness," 2013 18th Asia and South Pacific Design
Automation Conference (ASP-DAC), 2013, pp. 527-532, doi:
10.1109/ASPDAC.2013.6509650.
Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling
of electromigration in SRAMs.” (2014).
N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical
approach to static signal electromigration analysis," Proceedings 1998
Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998,
pp. 572-577, doi: 10.1109/DAC.1998.724536.
Blaauw, David & Oh, Chanhee & Zolotov, Vladimir &
Dasgupta, Aurobindo. (2003). Static electromigration analysis for
on-chip signal interconnects. Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on. 22. 39 - 48.
10.1109/TCAD.2002.805728.
A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC
Oscillator," in IEEE Open Journal of the Solid-State Circuits
Society, vol. 5, pp. 45-59, 2025, doi: 10.1109/OJSSCS.2024 [pdf]
where \(X_{I,AM,USB}(t)=\cos(\omega_m
t)\) and \(X_{Q,AM,USB}(t)=\sin(\omega_m t)\); \(X_{I,AM,USB}(t)=\cos(\omega_m t)\) and
\(X_{Q,AM,USB}(t)=-\sin(\omega_m
t)\);
\(X_{I,AM,USB} = X_{I,AM,LSB}\) and
\(X_{Q,AM,USB} = -X_{Q,AM,LSB}\)
where \(X_{I,PM,USB}(t)=\cos(\omega_m
t)\) and \(X_{Q,PM,USB}(t)=\sin(\omega_m t)\); \(X_{I,PM,USB}(t)=-\cos(\omega_m t)\) and
\(X_{Q,PM,USB}(t)=\sin(\omega_m
t)\);
\(X_{I,PM,USB} = -X_{I,PM,LSB}\) and
\(X_{Q,PM,USB} = X_{Q,PM,LSB}\)
The spectrum of the narrowband FM signal is very similar to that of
an amplitude modulation (AM) signal but has the phase
reversal for the other sideband component
Assume the modulation frequency of PM and AM are
same, \(\omega_m\)
Therefore, sideband is asymmetric if \(\omega_{pm} = \omega_{am}\)same
Hegazi, Emad, Asad Abidi, and Jacob Rael. The Designer's Guide to
High-purity Oscillators. [New York]: Kluwer Academic Publishers,
2005. [pdf]
PSD of Narrowband FM Signal
Chembiyan T. Jitter and Phase Noise in Phase Locked Loops [link]
\[
y(t) = A\cos(2\pi f_0t+\phi_n(t)) \approx A \cos(2\pi f_0 t) - A \phi_n
(t)\sin(2\pi f_0 t)
\]
\[
R_x(\tau) = \frac{A^2}{2}\cos(2\pi f_0\tau)
+ \frac{A^2}{2}R_\phi(\tau)\cos(2\pi f_0\tau)
\] The PSD of the signal \(x(t)\) is given by \[
S_x(f) = \mathcal{F}\{R_x(\tau)\} =
\frac{P_c}{2}\left[\delta(f+f_0)+\delta(f-f_0)\right]+\frac{P_c}{2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right]
\] where \(P_c = A^2/2\) is the
carrier power of the signal
Phase Noise and Frequency Noise are not two different noise sources,
they are artifacts of the same noise, it is just a matter of what units
you want to use
If the narrowband noise \(n(t)\) is
Gaussian and its power spectral density \(S_N
(t )\) is symmetric about the mid-band frequency
\(f_c\), then the in-phase
component\(n_I(t)\) and
quadrature component\(n_Q(t)\) are statistically
independent
For AM & pacphase=90deg, complex
exponentials with frequency \(\omega_m\)\[
\alpha_+(t) = je^{j\omega_m t} = e^{j(\omega_mt+\pi/2)}
\] where \(A_+=j\)
Then, the complex exponentials with frequency \(-\omega_m\) shall be \[
\alpha_-(t) = [\alpha_+(t)]^* = -je^{-j\omega_m t} =
e^{-j(\omega_mt+\pi/2)}
\] where \(A_-=A_+^* =-j\)
Bob Nelson. Phase Noise 101: Basics, Applications and Measurements
[[https://www.qsl.net/ab4oj/test/docs/20180720_KEE7_PhaseNoise.pdf])https://www.qsl.net/ab4oj/test/docs/20180720_KEE7_PhaseNoise.pdf]
The three most widely adopted techniques are direct
spectrum, phase detector, and
two-channel cross-correlation.
While the direct spectrum technique measures phase noise with the
existence of the carrier signal, the other two remove the carrier
(demodulation) before phase noise is measured.
Though direct spectrum technique method may not be useful
for measuring very close-in phase noise to a drifting carrier,
it is convenient for qualitative quick evaluation on sources with
relatively high noise
1 2 3 4 5 6 7 8 9
import numpy as np
# at 5KHz n_pm = -140# dBc n_am = -142# dBc
# calculate the total noise by PM + AM n_tot = 10*np.log10(10**(n_pm / 10) + 10**(n_am / 10)) print(n_tot) # -137.8755739720566
J. -H. Seol, K. Choo, D. Blaauw, D. Sylvester and T. Jang, "Reference
Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur," in
IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp.
2993-3007, Oct. 2021 [https://sci-hub.se/10.1109/JSSC.2021.3089930]
K. J. Wang, A. Swaminathan and I. Galton, "Spurious Tone Suppression
Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL," in
IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp.
2787-2797, Dec. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005716]
Frequency Divider
Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF,
Analog and Mixed Signal Circuits and Systems. Aalborg: River
Publishers, 2017
Large values of N lowers the loop BW which is bad for jitter
MMD (Multimodulus Divider)
TODO 📅
Noise in dividers (jitter
generation)
S. Levantino, L. Romano, S. Pellerano, C. Samori and A. L. Lacaita,
"Phase noise in digital frequency dividers," in IEEE Journal of
Solid-State Circuits, vol. 39, no. 5, pp. 775-784, May 2004 [https://sci-hub.se/10.1109/JSSC.2004.826338]
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007.
W. F. Egan, "Modeling phase noise in frequency dividers," in IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol.
37, no. 4, pp. 307-315, July 1990 [https://sci-hub.se/10.1109/58.56498]
Multiplying the frequency of a signal by a factor of N using an
ideal frequency multiplier increases the phase noise of
the multiplied signal by \(20\log(N)\)
dB.
Similarly dividing a signal frequency by \(N\) reduces the phase noise of the output
signal by \(20\log(N)\) dB
The sideband offset from the carrier in the frequency
multiplied/divided signal is the same as for the original signal.
\(20\log (N)\)
Rule
If the carrier frequency of a clock is divided down by a factor of
\(N\) then we expect the phase noise to
decrease by \(20\log(N)\).The primary
assumption here is a noiseless conventional digital
divider.
The \(20\log(N)\) rule only applies
to phase noise and not integrated phase noise or phase
jitter. Phase jitter should generally measure about the
same.
What About Phase Jitter?
We integrate SSB phase noise L(f) [dBc/Hz] to
obtain rms phase jitter in seconds as follows for “brick wall”
integration from f1 to f2 offset frequencies in Hz and where f0 is the
carrier or clock frequency.
Note that the rms phase jitter in seconds is inversely proportional
to f0. When frequency is divided down, the phase noise, L(f),
goes down by a factor of 20log(N). However, since the frequency goes
down by N also, the phase jitter expressed in units of time is
constant.
Therefore, phase noise curves, related by 20log(N), with the same
phase noise shape over the jitter bandwidth, are expected to
yield the same phase jitter in seconds.
\[
f = \frac{d(\omega_0 t + A\sin\omega_mt)}{2\pi dt}=\frac{\omega_0 +
A\cdot 2\pi f_m \cos\omega_m t}{2\pi}
\] therefore \[
\Delta f_{pk} = Af_m
\] and \[
P_{spur} = 10\log\left(\frac{\Delta f_{pk}}{2f_m}\right)^2=
10\log\left(\frac{A}{2}\right)^2
\]
Reference Spur
spurs are carrier or clock frequency spectral
imperfections measured in the frequency domain just like phase noise.
However, unlike phase noise they are discrete frequency
components.
Spurs are deterministic
Spur power is independent of bandwidth
Spurs contribute bounded peak jitter in the time domain
Sources of Spurs:
External (coupling from other noisy block) Supply, substrate, bond
wires, etc.
Internal (int-N/fractional-N operation)
Frac spur: Fractional divider (multi-modulus and
frequency accumulation)
the frequency resolution, is equal to the reference
frequency, meaning that only integer multiples of the reference
frequency can be synthesized
Stability requirements limit the loop bandwidth to about
one tenth of the reference frequency; therefore
decreasing the reference frequency increases the settling time as
the loop bandwidth also has to be decreased
a reduced loop bandwidth allows less suppression of the VCO’s
inherent phase noise
Another drawback of the integer-N PLL is the trade-off
between phase noise and settling time when the divider ratio
becomes large (The contributions to the output phase noise of
almost all PLL building blocks, except the VCO, are multiplied
by the division ratio)
if a small reference frequency is chosen, the reference spur
in the output phase noise is located at a smaller offset
frequency
Fractional-N
Dither Feedback Divider Ratio by a delta-sigma
modulator
Frequency Accumulation
Switched Capacitor Banks
Q: why \(R_b\) ?
A: TODO 📅
Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in
RF/millimeter-wave oscillators for 5G communications." PhD diss.,
2019.
S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough
analysis of the tank quality factor in LC oscillators with switched
capacitor banks," Proceedings of 2010 IEEE International Symposium
on Circuits and Systems, Paris, France, 2010, pp. 1903-1906
False locking
TODO 📅
divider failure
even-stage ring oscillator ( multipath ring oscillators)
DLL: harmonic locking, stuck locking
clock edge impact
ck1 is div2 of ck0
edge of ck0 is affected differently by ck1
edge of ck1 is affected equally by ck0
Why Type 2 PLL ?
Type: # of integrators within the loop
Order: # of poles in the closed-loop
transfer function
Type \(\leq\) Order
That is, to have a wide bandwidth, a high loop gain is required
More importantly, the type 1 PLL has the problem of a
static phase error for the change of an input
frequency
A step response test is an easy way to determine the
bandwidth.
Sum a small step into the control voltage of your oscillator
(VCO or NCO), and measure the 90% to 10% fall time of the
corrected response at the output of the loop filter as shown in this
block diagram
a first order loop \[
BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}
\] Where \(BW\) is the 3 dB
bandwidth in Hz and \(𝑡\) is the
10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7
this relationship is closer to: \[
BW = \frac{0.33}{t}\space\space\space\space \text{(second order system,
damping factor = 0.7)}
\]
Pulse Code Modulation (PCM) is a method for digitally representing
analog signals by sampling their amplitude at regular intervals and then
encoding these samples into binary numbers
Energy/bit (pJ/b)
1mW/Gbps = 1pJ/bit
Joules are a unit of work or energy.
Watts are a unit of power which is the rate at
which energy is generated or consumed.
modulation depth
The modulation index (or
modulation depth) of a modulation scheme
describes by how much the modulated variable of the carrier signal
varies around its unmodulated level
The Nyquist rate is the minimum sample rate required
to accurately measure a signal's highest frequency. It's equal to
twice the highest frequency of the
signal
Nyquist frequency
The Nyquist frequency is the highest frequency that can be
represented without aliasing in a discrete signal. It's
equal to half the sampling frequency
Oversampling Ratio (OSR) is defined as the ratio of
the Nyquist frequency\(f_s/2\) to the signal bandwidth\(B\) given by \(\text{OSR}=f_s/2B\)
Summation & Integration
impulse response
Transform
ROC
Summation
\(u(t)\)
\(\frac{1}{s}\)
\(\mathfrak{Re}\{s\}\gt 0\)
Integration
\(u[n]\)
\(\frac{1}{1-z^{-1}}\)
\(|z| \gt 1\)
both are NOT stable
sinc function
where \(W\) is sampling frequency in
Hz
sinc function is square integrable but notabsolutely integrable
Zero-order hold (ZOH)
\[
h_{ZOH}(t) = \text{rect}(\frac{t}{T} - \frac{1}{2}) = \left\{
\begin{array}{cl}
1 & : \ 0 \leq t \lt T \\
0 & : \ \text{otherwise}
\end{array} \right.
\] The effective frequency response is the continuous Fourier
transform of the impulse response \[
H_{ZOH}(f) = \mathcal{F}\{h_{ZOH}(t)\} = T\frac{1-e^{j2\pi fT}}{j2\pi
fT}=Te^{-j\pi fT}\text{sinc}(fT)
\] where \(\text{sinc}(x)\) is
the normalized sinc function \(\frac{\sin(\pi
x)}{\pi x}\)
The Laplace transform transfer function of the ZOH is found by
substituting \(s=j2\pi f\)\[
H_{ZOH}(s) = \mathcal{L}\{h_{ZOH}(t)\}=\frac{1-e^{-sT}}{s}
\]
The probability distribution of the sum of two or more
independent random variables is the
convolution of their individual distributions.
Thermal noise
Thermal noise in an ideal resistor is approximately
white, meaning that its power spectral density is
nearly constant throughout the frequency spectrum.
When limited to a finite bandwidth and viewed in the time
domain, thermal noise has a nearly Gaussian amplitude
distribution
System Type
Control of Steady-State Error to Polynomial Inputs: System Type
control systems are assigned a type number according
to the maximum degree of the input polynominal for which the
steady-state error is a finite constant. i.e.
Type 0: Finite error to a step (position error)
Type 1: Finite error to a ramp (velocity error)
Type 2: Finite error to a parabola (acceleration error)
The open-loop transfer function can be expressed as \[
T(s) = \frac{K_n(s)}{s^n}
\]
where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),
The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform
is \[
R(s) = \frac{1}{s^{k+1}}
\]
Then the equation for the error is simply \[
E(s) = \frac{1}{1+T(s)}R(s)
\]
Application of the Final Value Theorem to the error formula
gives the result
\(H(j\omega)\) is obtained as below
\[
H(j\omega) = \frac{1}{1+j\omega}
\]
Different Variants of
the PSD Definition
In the practice of engineering, it has become customary to use
slightly different variants of the PSD definition, depending on the
particular application or research field.
Two-Sided PSD, \(S_x(f)\)
this is a synonym of the PSD defined as the Fourier Transform of the
autocorrelation.
One-Sided PSD, \(S'_x(f)\)
this is a variant derived from the two-sided PSD by
considering only the positive frequency semi-axis.
To conserve the total power, the value of the
one-sided PSD is twice that of the two-sided PSD \[
S'_x(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_x(f) & : \ f = 0 \\
2S_x(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the one-sided PSD definition makes sense only if the
two-sided is an even function of \(f\)
If \(S'_x(f)\) is even
symmetrical around a positive frequency \(f_0\), then two additional definitions can
be adopted:
Single-Sideband PSD, \(S_{SSB,x}(f)\)
This is obtained from \(S'_x(f)\) by moving the origin of the
frequency axis to \(f_0\)\[
S_{SSB,x}(f) =S'_x(f+f_0)
\] This concept is particularly useful for describing phase or
amplitude modulation schemes in wireless communications, where \(f_0\) is the carrier frequency.
Note that there is no difference in the values of the one-sided
versus the SSB PSD; it is just a pure translation on the frequency
axis.
Double-Sideband PSD, \(S_{DSB,x}(f)\)
this is a variant of the SSB PSD obtained by considering only the
positive frequency semi-axis.
As in the case of the one-sided PSD, to conserve total power, the
value of the DSB PSD is twice that of the SSB \[
S_{DSB,x}(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_{SSB,x}(f) & : \ f = 0 \\
2S_{SSB,x}(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the DSB definition makes sense only if the SSB PSD is even
symmetrical around zero
Poles and Zeros of
transfer function
poles
\[
H(s) = \frac{1}{1+s/\omega_0}
\]
magnitude and phase at \(\omega_0\)
and \(-\omega_0\)\[\begin{align}
H(j\omega_0) &= \frac{1}{1+j} = \frac{1}{\sqrt{2}}e^{-j\pi/4} \\
H(-j\omega_0) &= \frac{1}{1-j} = \frac{1}{\sqrt{2}}e^{j\pi/4}
\end{align}\]
subplot(5,1,2) n=100; %number of Histrogram bins [f,x]=hist(X,n); bar(x,f/trapz(x,f)); hold on; %Theoretical PDF of Gaussian Random Variable g=(1/(sqrt(2*pi)*sigma))*exp(-((x-mu).^2)/(2*sigma^2)); plot(x,g, LineWidth=3);hold off; grid on; title('Theoretical PDF and Simulated Histogram of White Gaussian Noise'); legend('Histogram','Theoretical PDF'); xlabel('Bins'); ylabel('PDF f_x(x)');
%Alternative method %[Rxx,lags] =xcorr(X,'biased'); %The argument 'biased' is used for proper scaling by 1/L %Normalize auto-correlation with sample length for proper scaling
plot(lags,Rxx, LineWidth=4); title('Auto-correlation Function of white noise'); xlabel('Lags') ylabel('Correlation') grid on; hold on;
subplot(5,1,4) [pxx_norm, f] = pwelch(X, 1024,[],[],1, 'centered'); plot(f, 10*log10(pxx_norm)) axis([-0.50.5010]); grid on; ylabel('PSD (dB/Hz)'); xlabel('Normalized Frequency'); title('Power spectral density of white noise with inbuilt pwelch');
subplot(5,1,5) %Verifying the constant PSD of White Gaussian Noise Process %with arbitrary mean and standard deviation sigma
mu=0; %Mean of each realization of Noise Process sigma=2; %Sigma of each realization of Noise Process
L = 1000; %Number of Random Signal realizations to average N = 1024; %Sample length for each realization set as power of 2 for FFT
%Generating the Random Process - White Gaussian Noise process MU=mu*ones(1,N); %Vector of mean for all realizations Cxx=(sigma^2)*diag(ones(N,1)); %Covariance Matrix for the Random Process R = chol(Cxx); %Cholesky of Covariance Matrix %Generating a Multivariate Gaussian Distribution with given mean vector and %Covariance Matrix Cxx z = repmat(MU,L,1) + randn(L,N)*R; %By default, FFT is done across each column - Normal command fft(z) %Finding the FFT of the Multivariate Distribution across each row %Command - fft(z,[],2) Z = 1/sqrt(N)*fft(z,[],2); % Scaling by sqrt(N); Pzavg = mean(Z.*conj(Z)); % Computing the **mean power** from fft
normFreq= [-N/2:N/2-1]/N; Pzavg=fftshift(Pzavg); %Shift zero-frequency component to center of spectrum plot(normFreq,10*log10(Pzavg),'r'); axis([-0.50.5010]); grid on; ylabel('PSD (dB/Hz)'); xlabel('Normalized Frequency'); title('Power spectral density of white noise');
white noise doesn't mean it has a
Gaussian/normal distribution
The only criteria for a (discrete) signal to be
"white" is for each sample to be independently
taken from the same probability distribution
By understanding input signal's statistical nature, we can gather
more insights about certain requirements for our circuits than just from
frequency domain
that total power will always be the same
for any sampling rate used (as long as the
histogram of those samples is still \(\sigma_x\)). Thus the power spectral
density will be \(\sigma_x^2/f_s\).
How to generate white noise signal from a given PSD?
[https://www.mathworks.com/matlabcentral/answers/1968-how-to-generate-white-noise-signal-from-a-given-psd#answer_1498849]
Nx = 2^16; % number of samples to synthesize B = [0.049922035-0.0959935370.050612699-0.004408786]; A = [1-2.4949560022.017265875-0.522189400]; nT60 = round(log(1000)/(1-max(abs(roots(A))))); % T60 est. v = randn(1,Nx+nT60); % Gaussian white noise: N(0,1) x = filter(B,A,v); % Apply 1/F roll-off to PSD x = x(nT60+1:end); % Skip transient response %{ octave:1> sum(B)/sum(A) ans = 1.0991 %}
The process of generating coloured noise is relatively simple:
Start with a representation of white noise signal in the frequency
domain
Shape the signal in the frequency domain according
to the PSD you'd like to achieve
Take the inverse Fourier transform of the shaped signal
Sampling shaping transfer function (not scaled by \(1/T_s\)) make sense in time domain
convolution between sampled noise and sampled impulse response of
filter
Autoregressive (AR) modeling in signal processing represents a signal
as a linear combination of its own previous values plus a white noise
error term, effectively acting as an all-pole IIR filter
% IIR FILTER PARAMETERS (USED TO GENERATE COLOURED NOISE) a = 0.99; B = sqrt(1-a^2); % INPUT COEFFICIENTS IN THE DIFFERENCE EQUATION A = [1 -a]; % OUTPUT COEFFICIENTS IN THE DIFFERENCE EQUATION
The aliasing of the noise, or noise
folding, plays an important role in switched-capacitor as it
does in all switched-capacitor filters
Assume for the moment that the switch is always closed (that
there is no hold phase), the single-sided noise density would be
\(v_s[n]\) is the sampled version of
\(v_{RC}(t)\), i.e. \(v_s[n]= v_{RC}(nT_C)\)\[
S_s(e^{j\omega}) = \frac{1}{T_C}
\sum_{k=-\infty}^{\infty}S_{RC}(j(\frac{\omega}{T_C}-\frac{2\pi
k}{T_C})) \cdot d\omega
\] where \(\omega \in [-\pi,
\pi]\), furthermore \(\frac{d\omega}{T_C}= d\Omega\)\[
S_s(j\Omega) = \sum_{k=-\infty}^{\infty}S_{RC}(j(\Omega-k\Omega_s))
\cdot d\Omega
\]
The noise in \(S_{RC}\) is a
stationary process and so is uncorrelated over \(f\) allowing the \(N\) rectangles to be combined by simply
summing their noise powers
Matt Pharr, Wenzel Jakob, and Greg Humphreys. 2016. Physically Based
Rendering: From Theory to Implementation (3rd. ed.). Morgan Kaufmann
Publishers Inc., San Francisco, CA, USA.
R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for
Signal Processing. Wiley-Interscience, 1986
Unlike the quantization noise and the thermal noise, the impact of
the clock jitter on the ADC performance depends on the input signal
properties like its PSD
The error between the ideal sampled signal and the
sampling with clock jitter can be treated as noise and it results
in the degradation of the SNR of the ADC
K. Tyagi and B. Razavi, "Performance Bounds of ADC-Based Receivers
Due to Clock Jitter," in IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 70, no. 5, pp. 1749-1753, May 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/KT_TCAS_2023.pdf]
N. Da Dalt, M. Harteneck, C. Sandner and A. Wiesbauer, "On the jitter
requirements of the sampling clock for analog-to-digital converters," in
IEEE Transactions on Circuits and Systems I: Fundamental Theory and
Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002 [https://sci-hub.se/10.1109/TCSI.2002.802353]
M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of
high-speed sampling systems," in IEEE Journal of Solid-State Circuits,
vol. 25, no. 1, pp. 220-224, Feb. 1990 [https://sci-hub.se/10.1109/4.50307]
In both DAC or ADC cases, doubling the timing jitter doubles the
noise level
Also, doubling the frequency or amplitude doubles the jitter induced
noise - SNR is not improved
Boris Murmann ISSCC 2022 SC1: Introduction to ADCs/DACs: Metrics,
Topologies, Trade Space, and Applications [pdf]
S. Kim, K. -Y. Lee and M. Lee, "Modeling Random Clock Jitter Effect
of High-Speed Current-Steering NRZ and RZ DAC," in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp.
2832-2841, Sept. 2018 [https://sci-hub.se/10.1109/TCSI.2018.2821198]
Martin Clara. High-Performance D/A-Converters - Application to
Digital Transceivers, 2013 [pdf]
Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data
Converters. July, 2006 [pdf]
Chembian Thambidurai, "Power Spectral Density of Pulsed Noise
Signals" [link]
White Noise Modulation
Noisy Resistor & Clocked Switch
\[
v_t (t) = v_i(t)\cdot m_t(t)
\]
where \(v_i(t)\) is input
white noise, whose autocorrelation is \(A\delta(\tau)\), and \(m_t(t)\) is periodically operating switch,
then autocorrelation of \(v_t(t)\)\[\begin{align}
R_t (t_1, t_2) &= E[v_t(t_1)\cdot v_t(t_2)] \\
&= R_i(t_1, t_2)\cdot m_t(t_1)m_t(t_2)
\end{align}\]
Then \[\begin{align}
R_t(t, t-\tau) &= R_i(\tau)\cdot m_t(t)m_t(t-\tau) \\
& = A\delta(\tau) \cdot m_t(t)m_t(t-\tau) \\
& = A\delta(\tau) \cdot m_t(t)
\end{align}\] Because \(m_t(t)=m_t(t+T)\), \(R_t(t, t-\tau)\) is is periodic in the
variable \(t\) with period \(T\)
The time-averaged ACF is denoted as \(\tilde{R_t}(\tau)\)
\[
\tilde{R}_{t}(\tau) = m\cdot A\delta(\tau)
\] That is, \[
S_t(f) = m\cdot S_{A}(f)
\]
Much like sinusoidal-steady-state signal analysis,
steady-state noise analysis methods assume an input
\(x(t)\) of infinite
duration, which is a Wide-Sense Stationary (WSS) random
process
Frequency-domain Analysis
Time-domain Analysis
The output \(y(t)\) of a linear
time-invariant (LTI) system \(h(t)\)\[\begin{align}
R_{yy}(\tau) &= R_{xx}(\tau)*[h(\tau)*h(-\tau)] \\
&= S_{xx}(0)\delta(\tau) * [h(\tau)*h(-\tau)] \\
&= S_{xx}(0)[h(\tau)*h(-\tau)] \\
&= S_{xx}(0) \int_\alpha h(\alpha)h(\alpha-\tau)d\alpha
\end{align}\]
with WSS white noise input \(x(t)\),
\(R_{xx}(\tau)=S_{xx}(0)\delta(\tau)\),
therefore
Assuming the noise applied duration is much less than the time
constant, the output voltage does not reach steady-state and WSS
noise analysis does not apply
Time-domain Analysis
The step noise input\(x(t) = \nu(t)u(t)\) where an underlying
WSS process\(\nu(t)\)\[
R_{xx}(t_1,t_2) = E[x(t_1)x(t_2)] = R_{\nu\nu}(t_1,
t_2)u(t_1)u(t_2)=R_{\nu\nu}(t_1, t_2) \tag{3.28}
\]
That is \[
\sigma^2_y (t)= R_{yy}(t_1,t_2)|_{t_1=t_2=t}=S_{xx}(0)\int_{-\infty}^t
|h(\tau)|^2d\tau \tag{3.33}
\]
\(t\), the upper limit of
integration is just intuitive, which lacks strict derivation
Because stable systems have impulse responses that decay to
zero as time goes to infinity, the output
noise variance approaches the WSS result as time approaches
infinity
Because the definition of the PSD assumes that the variance of the
noise process is independent of time, the PSD of a non-stationary
process is not very meaningful
Input Referred Noise
Noise Voltage to Timing Jitter Conversion & noise
gain
Suppose \(t_i \gg \tau_0\)\[
\overline{v_n^2}(t_i) = 4kTR_n\frac{1}{4\tau_o}
\coth(\frac{t_i}{2\tau_o}) \approx 4kTR_n\frac{1}{4\tau_o}
= \frac{G_n}{G_m}\frac{kT}{C}\frac{1}{A_0}
\] As expected, the input referred noise voltage is \(kT/C\) noise
Pharr, Matt; Humphreys, Greg. (28 June 2010). Physically Based
Rendering: From Theory to Implementation. Morgan Kaufmann. ISBN
978-0-12-375079-2. Chapter
7 (Sampling and reconstruction)
Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing,
3rd edition
Mathuranathan Viswanathan. Digital Modulations using Matlab: Build
Simulation Models from Scratch
we get \(C_\text{out,eq}=
(1+\frac{1}{A_v})C_c\approx C_c\)
Pole Splitting
Generic circuit in textbook
In addition to lowering the required capacitor value, Miller
compensation entails a very important property: it moves the output pole
away from the origin. This effect is called pole
splitting
The 1st stage is replaced with Thevenin equivalent circuit , \(V_i \approx V_i \cdot g_{m1}R_{o1}\)
\[\begin{align}
\frac{V_i-V_{o1}}{R_{o1}} &= V_{o1}\cdot sC_{o1}+(V_{o1}-V_o)\cdot
sC_c \\
V_{o1} &= \frac{V_i+sR_{o1}C_cV_o}{1+sR_{o1}(C_{o1}+C_c)}
\end{align}\]\[
(V_{o1}-V_o)sC_c=g_{m2}V_{o1}+V_o(\frac{1}{R_{o2}+sC_L})
\] substitute \(V_{o1}\), we
get
\(s^3\) terms in denominator \[
H_3 = s^3\cdot(R_{o1}R_{o2}R_c+R_{o1}R_{o2}R_{sw} +R_{o1}R_cR_{sw})\cdot
C_{o1}C_cC_L
\]\(s^2\) terms in denominator
\[\begin{align}
H_2
&=s^2\cdot(R_{o1}R_{o2}C_{o1}C_c+R_{o1}R_{o2}C_{o1}C_L+R_{o2}R_cC_cC_L+R_{o1}R_{o2}C_cC_L+R_{o1}R_cC_{o1}C_c\\
&+R_{o2}R_{sw}C_cC_L+R_{o1}R_{sw}C_cC_L\cdot
g_{m2}R_{o2}+R_{o1}R_{sw}C_{o1}C_L+R_{sw}R_cC_cC_L+R_{o1}R_{sw}C_cC_L)
\end{align}\]
\(s^1\) term in denominator \[
H_1=s(R_{o1}\cdot
g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_cC_c+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L+R_{sw}C_L)
\]\(s^0\) term in denominator
\[
H_0=1
\] set \(R_c=0\) and \(R_{sw}=0\), the \(H_*\) reduced to \[\begin{align}
H_3 &= 0 \\
H_2 &=s^2R_{o1}R_{o2}(C_{o1}C_c+C_{o1}C_L+C_cC_L) \\
H_1&=s(R_{o1}\cdot
g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L) \\
H_0&=1
\end{align}\] That is \[
H=s^2R_{o1}R_{o2}(C_{o1}C_c+C_{o1}C_L+C_cC_L)+s(R_{o1}\cdot
g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L)+1
\]
which is same with our previous analysis of Generic circuit in
textbook
And we know \[
\frac{V_o}{V_{o2}}=\frac{1}{1+sR_{sw}C_L}
\] Finally, we get \(\frac{V_o}{V_i}\)\[\begin{align}
\frac{V_o}{V_i} &= \frac{V_{o2}}{V_i} \cdot \frac{V_o}{V_{o2}} \\
&= -g_{m2}R_{o2}\frac{\left[ sC_c(R_c-1/g_{m2})+1
\right](sR_{sw}C_L+1)}{H_3+H_2+H_1+1} \cdot \frac{1}{1+sR_{sw}C_L} \\
&= -g_{m2}R_{o2}\frac{ sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1}
\end{align}\]
The loop transfer function is \[
\frac{V_o}{V_i} =-g_{m1}R_{o1}g_{m2}R_{o2}\frac{
sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1}
\]
The poles can be deduced \[\begin{align}
\omega_1 &= \frac{1}{R_{o1}\cdot g_{m2}R_{o2}C_c} \\
\omega_2 &= \frac{1}{1+g_{m2}R_{sw}}\cdot \frac{g_{m2}}{C_L} \\
&= \frac{1}{(g_{m2}^{-1}+R_{sw})C_L}
\end{align}\]
The pole \(\omega_2=\frac{1}{g_{m2}^{-1}C_L}\) is
changed to \(\omega_2=\frac{1}{(g_{m2}^{-1}+R_{sw})C_L}\)
In order to cancel \(\omega_2\) with
\(\omega_z\), \(R_c\) shall be increased
Following demonstrate how derive \(f_{nd}\) from Razavi's equation. We copy
\(\omega_2\) here \[
\omega_2 = \frac{R_{o1}C_c\cdot
g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)}
\] which can be reduced as below
The benefits of Ahuja compensation over Miller compensation
are severa
better PSRR
higher unity-gain bandwidth using smaller compensation
capacitor
ability to cope better with heavy capacitive and resistive
loads
Of course, , if the capacitance at the gate of \(M_1\) is taken into account, pole splitting
is less pronounced.
including \(r_\text{o2}\)
\[
\frac{V_{out}}{I_{in}} \approx
\frac{-g_{m1}R_SR_L(g_{m2}+C_Cs)}{\frac{R_S+r_\text{o2}}{r_\text{o2}}R_LC_LC_Cs^2+g_{m1}g_{m2}R_LR_SC_Cs+g_{m2}}
\] The poles as
and zero is not affected, which is \(\omega_z =\frac{g_{m2}}{C_C}\)
the above model simulation result is shown below
the zero is located between two poles
take into the capacitance at the gate of \(M_1\) and all other second-order effect
intuitive analysis of zero
miller compensation
zero in the right half plane \[
g_\text{m1}V_P = sC_c V_P
\]
cascode compensation
zero in the left half plane \[
g_\text{m2}V_X = - sC_c V_X
\]
Mitigate Impact of Zero
dominant pole\[
\omega_\text{p,d} = \frac {1} {R_\text{eq}g_\text{m9}R_{L}C_{c}}
\]first nondominant pole\[
\omega_\text{p,nd} = \frac {g_\text{m4}R_\text{eq}g_\text{m9}} {C_L}
\]zero\[
\omega_\text{z} = (g_\text{m4}R_\text{eq})(\frac {g_\text{m9}} {C_c})
\] a much greater magnitude than \(g_\text{m9}/C_C\)
ahuja variations
Pole-Zero Compensation
Pole-Zero Compensation is also known as
Lead Compensation, Parallel
Compensation
Note: The dominant pole is at output of the first
stage, i.e. \(\frac{1}{R_{EQ}C_{EQ}}\).
Pole & Zero in transfer
function
Design with operational amplifiers and analog integrated circuits /
Sergio Franco, San Francisco State University. – Fourth edition
\[
Y = \frac{1}{R_1} + sC_1+\frac{1}{R_c+1/SC_c}
\]
\[\begin{align}
Z &= \frac{1}{\frac{1}{R_1} + sC_1+\frac{1}{R_c+1/SC_c}} \\
&= \frac{R_1(1+sR_cC_c)}{s^2R_1C_1R_cC_c+s(R_1C_c+R_1C_1+R_cC_c)+1}
\end{align}\] If \(p_{1c} \ll
p_{3c}\), two real roots can be found \[\begin{align}
p_{1c} &= \frac{1}{R_1C_c+R_1C_1+R_cC_c} \\
p_{3c} &= \frac{R_1C_c+R_1C_1+R_cC_c}{R_1C_1R_cC_c}
\end{align}\]
The additional zero is \[
z_c = \frac{1}{R_cC_c}
\] Given \(R_c \ll R\) and \(C_c \gg C\)\[\begin{align}
p_{1c} &\simeq \frac{1}{R_1(C_c+C_1)} \simeq \frac{1}{R_1C_c}\\
p_{3c} &= \frac{1}{R_cC_1}+\frac{1}{R_cC_c}+\frac{1}{R_1C_1} \simeq
\frac{1}{R_cC_1}
\end{align}\]
The output pole is unchanged, which is \[
p_2 = \frac{1}{R_LC_L}
\] We usually cancel\(p_2\) with \(z_c\), i.e. \[
R_cC_c=R_LC_L
\]
Phase margin
unity-gain frequency \(\omega_t\)\[
\omega_t = A_\text{DC}\cdot P_{1c} =\frac{g_{m1}g_{m2}R_L}{C_c}
\]
PM=45\(^o\)\[
p_{3c} = \omega_t
\] Then, \(C_c\) and \(R_c\) can be obtained
for the unity-gain frequency \(\omega_t\) we find \[
\omega_t = \sqrt{\frac{1}{2}\cdot \frac{g_{m1}g_{m2}}{C_1C_L}}
\] The parallel compensation shows a remarkably good result. The
new 0 dB frequency lies only a factor \(\sqrt{2}\) lower than the theoretical
maximum
To increase \(\phi_m\), we need to
raise\(C_c\) a bit
while lowering\(R_c\)
in proportion in order to maintain pole-zero cancellation. This causes
\(p_{1c}\) and \(p_{3c}\) to split a bit further apart.
The denominator part of \(H_{closed}(s)\) is \[
D(s) =
\frac{s^2}{(A_0+1)\omega_{p1}\omega_{p2}}+\frac{\frac{1}{\omega_{p1}} +
\frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}}{A_0+1}s+1
\]
Thus, the two poles of the closed-loop transfer function of system
are \[\begin{align}
\omega_{pA} &= \frac{A_0+1}{\frac{1}{\omega_{p1}} +
\frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}}
= \frac{(A_0+1)\omega_{p1} \omega_{p2}}{\omega_{p1} + \omega_{p2} +
\frac{A_0}{\omega_z}\omega_{p1} \omega_{p2}}\\
\omega_{pB} &= \omega_{p1} + \omega_{p2} +
\frac{A_0}{\omega_z}\omega_{p1} \omega_{p2}
\end{align}\]
non-dominant pole \(\omega_{p2}\) and zero \(\omega_z\) are in UGB
\[\begin{align}
\omega_{pA} &\approx \omega_{p2}\\
\omega_{pB} &\approx (1+A_0)\omega_{p1}
\end{align}\] Then, closed-loop transfer function is \[
H_{closed}(s) \approx
\frac{\frac{A_0}{A_0+1}\left(1+\frac{s}{\omega_z}\right)}{\left(1+\frac{s}{(1+A_0)\omega_{p1}}\right)\left(
1+\frac{s}{\omega_{p2}} \right)}
\]
Consider the Laplace transform function of step response, \(X(s)=\frac{1}{s}\)\[
Y(s)=\frac{1}{s}\times H_{closed}(s)
\] Thus, the small-signal step response of the
closed-loop amplifier is \[
y(t)=\frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t}
\right]u(t)
\] Since, \(\omega_{p2}\ll
(1+A_0)\omega_{p1}\). rewrite the \(y(t)\)\[
y(t)\approx
\frac{A_0}{A_0+1}\left[1-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t}
\right]u(t)
\]
rio = 1; wpx =rio*wpz; wzx =wpz/rio; wp1x = 1*wp1; Ho = A0*(1+s/wzx)/(1+s/wp1x)/(1+s/wp2)/(1+s/wpx); Hc = Ho/(1+Ho); [mag_1p0, phase_1p0, wout_1p0] = bode(Ho, wi); [vo_1p0, to_1p0] = step(Hc, ti);
rio = 1.25; wpx =rio*wpz; wzx =wpz/rio; wp1x = 0.65*wp1; Ho = A0*(1+s/wzx)/(1+s/wp1x)/(1+s/wp2)/(1+s/wpx); Hc = Ho/(1+Ho); [mag_10p0, phase_10p0, wout_10p0] = bode(Ho, wi); [vo_10p0, to_10p0] = step(Hc, ti);
subplot(2,2,1) semilogx(wout_0p1(:)/2/pi, 20*log10(mag_0p1(:)),'b-',LineWidth=2); hold on semilogx(wout_1p0(:)/2/pi, 20*log10(mag_1p0(:)),'r-',LineWidth=2); semilogx(wout_10p0(:)/2/pi, 20*log10(mag_10p0(:)),'g-',LineWidth=2); grid on; xlabel('Hz'); ylabel('Mag (dB)'); legend('\omega_{p2}<\omega_{z}', '\omega_{p2}=\omega_{z}', '\omega_{p2}>\omega_{z}')
subplot(2,2,3) semilogx(wout_0p1(:)/2/pi, phase_0p1(:),'b-',LineWidth=2); hold on semilogx(wout_1p0(:)/2/pi, phase_1p0(:),'r-',LineWidth=2); semilogx(wout_10p0(:)/2/pi, phase_10p0(:),'g-',LineWidth=2); grid on; xlabel('Hz'); ylabel('Phase') legend('\omega_{p2}<\omega_{z}', '\omega_{p2}=\omega_{z}', '\omega_{p2}>\omega_{z}')
subplot(2,2,[24]) plot(to_0p1(:), vo_0p1(:),'b-',LineWidth=2); hold on plot(to_1p0(:), vo_1p0(:),'r-',LineWidth=2); plot(to_10p0(:), vo_10p0(:),'g-',LineWidth=2); grid on; xlabel('time'); ylabel('V') legend('\omega_{p2}<\omega_{z}', '\omega_{p2}=\omega_{z}', '\omega_{p2}>\omega_{z}')
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no. 6, pp. 969-982, Dec. 1982, [https://sci-hub.se/10.1109/JSSC.1982.1051851]
Damping Factor (\(\zeta\)) is
defined for close loop system
We can analyze open loop system in a better perspective because it is
simpler. So, we always use the loop gain analysis to find the phase
margin and see whether the system is stable or not.
The zeros in the right half of the complex plane are called
nonminimum phase zeros. Systems with
nonminimum phase zeros are called nonminimum phase
systems
Zero close to the real pole attenuates the effect of that
pole on the system response
Zeros Tend to Increase the Overshoot of the
System
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
zeta=0.4 omega_n=3 k=1 s=tf('s') W1=1/(s^2+2*zeta*s+1) W2=(1/(k*zeta))*s*W1 W3=W1+W2 figure(1) hold on step(W1,'r') step(W2,'k') step(W3,'b') grid
Nonminimum Phase Zeros – Effect on the Transient
Response
1 2 3 4 5 6 7 8 9 10 11 12 13
zeta=0.4 omega_n=3 k=1 s=tf('s') S1=1/(s^2+2*zeta*s+1) S2=(1/(k*zeta))*s*S1 S=S1-S2 figure(1) hold on step(S1,'r') step(-S2,'k') step(S,'b') grid
Let \(s=j\omega\) and omit factor,
\[
A_\text{dB}(\omega) = 10\log[1+(\frac{\omega}{\omega _z})^2] -
10\log[1+\frac{\omega^4}{\omega_n^4}+\frac{2\omega^2(2\zeta ^2
-1)}{\omega_n^2}]
\] peaking frequency \(\omega_\text{peak}\) can be obtained via
\(\frac{d A_\text{dB}(\omega)}{d\omega} =
0\)\[
\omega_\text{peak} = \omega_z \sqrt{\sqrt{(\frac{\omega_n}{\omega_z})^4
- 2(\frac{\omega_n}{\omega_z})^2(2\zeta ^2-1)+1} - 1}
\]
minimum-phase
system vs Non-minimum phase system
a linear, time-invariant system is said to be minimum-phase if
the system and its inverse are causal and
stable
Systems that are causal and stable whose inverses are
causal and unstable are known
as non-minimum-phase systems
Settling Time
One Pole
we have \[
\tau \approx \left(1 + \frac{R_1}{R_2}\right)\frac{1}{A_0\omega_0}=
\frac{1}{\beta \omega_\text{ugb}}
\]
Two Poles
with open-loop transfer function \(A_{OL}=\frac{A_0}{(1+s/\omega_1)(1+s/\omega_2)}\)
and assuming \(\omega_1\) is dominant
pole, then yield closed-loop transfer function
That is \(\omega_n =
\sqrt{\omega_u\omega_2}\), \(\zeta =
\frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\) , where \(\omega_u\approx \beta A_0 \omega_1\) is the
unity gain bandwidth
Rise Time (0% to
100% )
\[
t_r = \frac{\pi - \beta}{\omega_d}=\frac{\pi -
\arctan\frac{\omega_n\sqrt{1-\zeta^2}}{\zeta\omega_n}}{\omega_n\sqrt{1-\zeta^2}}\approx\frac{\pi
-
\arctan\frac{\sqrt{1-\zeta^2}}{\zeta}}{\sqrt{\omega_u\omega_2}\sqrt{1-\zeta^2}}=\frac{\pi
- \arctan\frac{\sqrt{1-\zeta^2}}{\zeta}}{\omega_u\sqrt{k(1-\zeta^2)}}
\] where \(k =
\frac{\omega_2}{\omega_u}\), is the function of PM
Gene F. Franklin, Feedback Control of Dynamic Systems, 8th
Edition
As we know \[
\zeta \omega_n=\frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\cdot
\sqrt{\omega_u\omega_2}=\frac{1}{2}\omega_2
\]
Then \[
t_s = \frac{9.2}{\omega_2}
\]
For \(\text{PM}=70^o\), \(\omega_2 = 2.75\omega_u\), that is \[
t_s \approx \frac{3.35}{\omega_u}
\]
For \(\text{PM}=45^o\), \(\omega_2 = \omega_u\), that is \[
t_s \approx \frac{9.2}{\omega_u}
\]
Above equation is valid only for underdamped, \(\zeta=\frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\lt
1\), that is \(\omega_2\lt
4\omega_u\)
2 Stage RC filter
High Pass Filter
Since \(1/sC_1+R_1 \gg R_0\)\[
\frac{V_m}{V_i}(s) \approx \frac{R_0}{R_0 + 1/sC_0} =
\frac{sR_0C_0}{1+sR_0C_0}
\]step response of \(V_m\)\[
V_m(t) = e^{-t/R_0C_0}
\] where \(\tau = R_0C_0\)
And \(V_o(s)\) can be expressed as
\[\begin{align}
\frac{V_o}{V_i}(s) & \approx \frac{sR_0C_0}{1+sR_0C_0} \cdot
\frac{sR_1C_1}{1+sR_1C_1} \\
&= \frac{sR_0C_0R_1C_1}{R_0C_0-R_1C_1}\left(\frac{1}{1+sR_1C_1} -
\frac{1}{1+sR_0C_0}\right)
\end{align}\]
Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018.
Feedback Control of Dynamic Systems (8th Edition) (8th. ed.).
Pearson. [pdf]
Katsuhiko Ogata, Modern Control Engineering, 5th edition [pdf]
C. T. Chuang, "Analysis of the settling behavior of an operational
amplifier," in IEEE Journal of Solid-State Circuits, vol. 17,
no. 1, pp. 74-80, Feb. 1982 [https://sci-hub.se/10.1109/JSSC.1982.1051689]
Often, AC-driven circuits can be mistaken as non-linear as the basis
that determines the linearity of a circuit is the relationship between
the voltage and current.
While an AC signal varies with time, it still exhibits a linear
relationship across elements like resistors, capacitors, and inductors.
Therefore, AC driven circuits are linear.
Phasor
Phasor concept has no real physical significance. It is just a
convenient mathematical tool.
Phasor analysis determines the steady-state response to a linear
circuit driven by sinusoidal sources with frequency \(f\)
If your circuit includes transistors or other nonlinear components,
all is not lost. There is an extension of phasor analysis to nonlinear
circuits called small-signal analysis in which you linearize the
components before performing phasor analysis - AC analyses of SPICE
A sinusoid is characterized by 3 numbers, its amplitude, its phase,
and its frequency. For example \[
v(t) = A\cos(\omega t + \phi) \tag{1}
\] In a circuit there will be many signals but in the case of
phasor analysis they will all have the same frequency. For this reason,
the signals are characterized using only their amplitude and
phase.
The combination of an amplitude and
phase to describe a signal is the
phasor for that signal.
Thus, the phasor for the signal in \((1)\) is \(A\angle \phi\)
In general, phasors are functions of frequency
Often it is preferable to represent a phasor using complex
numbers rather than using amplitude and phase. In this case we
represent the signal as: \[
v(t) = \Re\{Ve^{j\omega t} \} \tag{2}
\] where \(V=Ae^{j\phi}\) is the
phasor.
\((1)\) and \((2)\) are the same
Phasor Model of a Resistor
A linear resistor is defined by the equation \(v = Ri\)
Now, assume that the resistor current is described with the
phasor\(I\). Then \[
i(t) = \Re\{Ie^{j\omega t}\}
\]\(R\) is a real constant, and
so the voltage can be computed to be \[
v(t) = R\Re\{Ie^{j\omega t}\} = \Re\{RIe^{j\omega t}\} =
\Re\{Ve^{j\omega t}\}
\] where \(V\) is the phasor
representation for \(v\), i.e. \[
V = RI
\]
Thus, given the phasor for the current we can directly
compute the phasor for the voltage across the
resistor.
Similarly, given the phasor for the voltage across a
resistor we can compute the phasor for the current through the
resistor using \(I =
\frac{V}{R}\)
Phasor Model of a Capacitor
A linear capacitor is defined by the equation \(i=C\frac{dv}{dt}\)
Now, assume that the voltage across the capacitor is described with
the phasor\(V\). Then \[
v(t) = \Re\{ V e^{j\omega t}\}
\]\(C\) is a real constant
\[
i(t) = C\Re\{\frac{d}{dt}V e^{j\omega t}\} = \Re\{j\omega C V e^{j\omega
t}\}
\] The phasor representation for \(i\) is \(i(t) =
\Re\{Ie^{j\omega t}\}\), that is \(I =
j\omega C V\)
Thus, given the phasor for the voltage across a
capacitor we can directly compute the phasor for the current
through the capacitor.
Similarly, given the phasor for the current through a
capacitor we can compute the phasor for the voltage across the
capacitor using \(V=\frac{I}{j\omega
C}\)
Phasor Model of an Inductor
A linear inductor is defined by the equation \(v=L\frac{di}{dt}\)
Now, assume that the inductor current is described with the
phasor\(I\). Then \[
i(t) = \Re\{ I e^{j\omega t}\}
\]\(L\) is a real constant, and
so the voltage can be computed to be \[
v(t) = L\Re\{\frac{d}{dt}I e^{j\omega t}\} = \Re\{j\omega L I e^{j\omega
t}\}
\] The phasor representation for \(v\) is \(v(t) =
\Re\{Ve^{j\omega t}\}\), that is \(V =
j\omega L I\)
Thus, given the phasor for the current we can directly
compute the phasor for the voltage across the
inductor.
Similarly, given the phasor for the voltage across an inductor we
can compute the phasor for the current through the inductor using \(I=\frac{V}{j\omega L}\)
Impedance and Admittance
Impedance and admittance are generalizations of resistance and
conductance.
They differ from resistance and conductance in that they are complex
and they vary with frequency.
Impedance is defined to be the ratio of the phasor for the
voltage across the component and the current through the component:
\[
Z = \frac{V}{I}
\]
Impedance is a complex value. The real part of the impedance is
referred to as the resistance and the imaginary part is referred to as
the reactance
For a linear component, admittance is defined to be the ratio of the
phasor for the current through the component and the voltage
across the component: \[
Y = \frac{I}{V}
\]
Admittance is a complex value. The real part of the admittance is
referred to as the conductance and the imaginary part is referred to as
the susceptance.
Response to Complex
Exponentials
The response of an LTI system to a complex
exponential input is the same complex
exponential with only a change in amplitude
where \(h(n)\) is the impulse
response of a discrete-time LTI system
convolution sum is used here
The signals of the form \(e^{st}\)
in continuous time and \(z^{n}\) in
discrete time, where \(s\) and \(z\) are complex numbers are
referred to as an eigenfunction of the system, and the
amplitude factor\(H(s)\),
\(H(z)\) is referred to as the system's
eigenvalue
Laplace transform
One of the important applications of the Laplace transform is in the
analysis and characterization of LTI systems, which
stems directly from the convolution property\[
Y(s) = H(s)X(s)
\] where \(X(s)\), \(Y(s)\), and \(H(s)\) are the Laplace transforms
of the input, output, and impulse response of the system,
respectively
From the response of LTI systems to complex exponentials, if the
input to an LTI system is \(x(t) =
e^{st}\), with \(s\) the ROC of
\(H(s)\), then the output will be \(y(t)=H(s)e^{st}\); i.e., \(e^{st}\) is an eigenfunction of
the system with eigenvalue equal to the Laplace
transform of the impulse response.
s-Domain Element Models
Sinusoidal Steady-State
Analysis
Here Sinusoidal means that source excitations have
the form \(V_s\cos(\omega t +\theta)\)
or \(V_s\sin(\omega t+\theta)\)
Steady state mean that all transient behavior of the
stable circuit has died out, i.e., decayed to zero
\(s\)-domain and phasor-domain
Phasor analysis is a technique to find the steady-state
response when the system input is a sinusoid. That is, phasor
analysis is sinusoidal analysis.
Phasor analysis is a powerful technique with which to find the
steady-state portion of the complete response.
Phasor analysis does not find the transient response.
Phasor analysis does not find the complete response.
The beauty of the phasor-domain circuit is that it is described by
algebraic KVL and KCL equations with time-invariant sources, not
differential equations of time
The difference here is that Laplace analysis can also give
us the transient response
The zero-state response is given by \(\mathscr{L^1}[H(s)F(s)]\), for the
arbitrary \(s\)-domain input \(F(s)\)
where \(Z_L(s) = sL\), the inductor
with zero initial current \(i_L(0)=0\)
and \(Z_C(s)=1/sC\) with zero initial
voltage \(v_C(0)=0\)
transient response & steady-state
response
natural response & forced
response
Transfer Functions
and Frequency Response
transfer function
The transfer function\(H(s)\) is the ratio of the Laplace
transform of the output of the system to its input assuming
all zero initial conditions.
frequency response
An immediate consequence of convolution is that an input of
the form \(e^{st}\) results in an
output \[
y(t) = H(s)e^{st}
\] where the specific constant \(s\) may be complex, expressed as \(s = \sigma + j\omega\)
A very common way to use the exponential response of LTIs is
in finding the frequency response i.e. response
to a sinusoid
First, we express the sinusoid as a sum of two
exponential expressions (Euler’s relation): \[
\cos(\omega t) = \frac{1}{2}(e^{j\omega t}+e^{-j\omega t})
\] If we let \(s=j\omega\), then
\(H(-j\omega)=H^*(j\omega)\), in polar
form \(H(j\omega)=Me^{j\phi}\) and
\(H(-j\omega)=Me^{-j\phi}\). \[\begin{align}
y_+(t) & = H(s)e^{st}|_{s=j\omega} = H(j\omega)e^{j\omega t} = M
e^{j(\omega t + \phi)} \\
y_-(t) & = H(s)e^{st}|_{s=-j\omega} = H(-j\omega)e^{-j\omega t} = M
e^{-j(\omega t + \phi)}
\end{align}\]
By superposition, the response to the sum of these two
exponentials, which make up the cosine signal, is the sum of the
responses \[\begin{align}
y(t) &= \frac{1}{2}[H(j\omega)e^{j\omega t} + H(-j\omega)e^{-j\omega
t}] \\
&= \frac{M}{2}[e^{j(\omega t + \phi)} + e^{-j(\omega t + \phi)}] \\
&= M\cos(\omega t + \phi)
\end{align}\]
where \(M = |H(j\omega|\) and \(\phi = \angle H(j\omega)\)
This means if a system represented by the transfer function \(H(s)\) has a sinusoidal input, the
output will be sinusoidal at the same frequency with magnitude
\(M\) and will be shifted in phase by
the angle \(\phi\)
Laplace transform vs.
Fourier transform
Laplace transforms such as \(Y(s)=H(s)U(s)\) can be used to study the
complete response characteristics of systems, including
the transient response—that is, the time response to an
initial condition or suddenly applied signal
This is in contrast to the use of Fourier transforms, which
only take into account the steady-state response
Given a general linear system with transfer function \(H(s)\) and an input signal \(u(t)\), the procedure for determining \(y(t)\) using the Laplace transform
is given by the following steps:
FSM and Shift Register of DR and IR works at the
posedge of the clock
TMS, TDI, TDO and Hold Register of DR and IR changes value at the
negedge of the clock
capture IR 01, the fixed is for easier fault
detection
After power-up, they may not be in sync, but there is a trick. Look
at the state machine and notice that no matter what state you are, if
TMS stays at "1" for five clocks, a TAP controller goes back to
the state "Test-Logic Reset". That's used to synchronize the TAP
controllers.
It is important to note that in a typical Boundary-Scan test, the
time between launching a signal from driver (at the falling edge of test
clock (TCK) in the Update-DR or Update-IR TAP
Controller state) and capturing that signal (at the rising edge of TCK
in the Caputre-DR TAP Controller state) is no less
tha 2.5 TCK cycles
Further, the time between successive launches on a driver is governed
- not only by the TCk rate - but by the amount of serial data shifting
needed to load the next pattern data in the concatenated Boundary-Scan
Registers of the Boundary-Scan chain
Thus the effective test data rate of a driver could be thousands of
the times lower than the TCK rate
For DC-coupled interconnect, this time is of no concern
For AC-coupled interconnect, the signal may easily decay partially
or completely before it can be captured
If only partial decay occurs before capture, that decay will very
likely be completed before the driver produces the next edge
AC-coupling
In general, AC-coupling can distort a signal transmitted across a
channel depending on its frequency.
Figure 5
The high frequency signal is relatively unaffected by the
coupling
The low frequency signal is severely impacted
it decays to \(V_T\) after a few
time constants
its amplitude is double the input amplitude > transient response,
before AC-coupling capacitor: \(-A_p \to
A_p\); after AC-coupling capacitor \(V_T \to V_T+2A_p\) > A key item to note
is that the transitions in the original signal are preserved, although
their start and end points are offset > > compared to where they
were in the high frequency
Test signal implementation
The test data is either the content of the Boundary-Scan Register
Update latch (U) when executing the (DC) EXTEST instruction, or an
"AC Signal" when an AC testing instruction is
loaded into the device.
The AC signal is a test waveform suited for transmission through
AC-coupling
Test signal reception
When an AC testing instruction is loaded, a specialized
test receiver detects transitoins of the AC signal seen at the input and
determines if this represents a logic '0' or '1'
When EXTEST is loaded, the input signal level is detected
and sent to the output of the test receiver to the Boundary-Scan
Register cell
When testing for a shorted capacitor, the test software must
ensure that enough time has passed for the signal to decay before
entering Capture-DR, either by stopping TCk or by spending
additional TCK cycles in the Run-Test/Idle TAP Controller
state
EXTEST_PULSE & EXTEST_TRAIN
The two new AC-test instructions provided by this standard differ
primarily in the number and timing of transitions to provide flexibility
in dealing with the specific dynamic behavior of the channels being
tested
AC Test Signal essentially modulates test data so
that it will propagate through AC-coupled channels, for devices that
contatin AC pins
Tools should use the EXTEST_PULSE instruction unless
there is a specific requirement for the EXTEST_TRAIN
instruction
EXTEST_PULSE
Generate two additional driver transitions and
allows a tester to vary the time between them dependent
on how many TCK cycles the TAP is left in the Run-Test/Idle TAP
Controller state.
This is intended to allow any undesired transient condition to decay
to a DC steady-state value when that will make the
final transition more reliably detectable
The duration in the Run-Test/Idle TAP Controller state
should be at least three times the high-pass coupling
time constant. This allows the first additional transition to
decay away to the DC steady-state value for the
channel, and ensures that the full amplitude of the final
transition is added to or subtracted from that steady-state
value
This establishes a known initial condition for the final
transition and permits reliable specification of the detection
threshold of the test receiver
EXTEST_TRAIN
Generate multiple additional transitions, the
number dependent on how long the TAP is left in the
Run-Test/Idle TAP Controller state
This is intended to allow any undesired transient condition to decay
to an AC steady-state value when that will make the
final transition more reliably detectable
IEEE Std 1149.6-2003
This standard is built on top of IEEE Std 1149.1 using the same Test
Access Port structure and Boundary-Scan architecture.
It adds the concept of a "test receiver" to input pins that are
expected to handle differential and/or AC-coupling
It adds two new instructions that cause drivers to emit AC waveforms
that are processed by test receivers.
JTAG Instruction
Implementation
AC mode hysteresis, detect transistion
DC mode threshold is determined by jtag initial value
reference
IEEE Std 1149.1-2001, IEEE Standard Test Access Port and
Boundary-Scan Architecture, IEEE, 2001
IEEE Std 1149.6-2003, IEEE Standard for BoundaryScan Testing of
Advanced Digital Networks, IEEE, 2003
B. Eklow, K. P. Parker and C. F. Barnhart, "IEEE 1149.6: a
boundary-scan standard for advanced digital networks," in IEEE Design
& Test of Computers, vol. 20, no. 5, pp. 76-83, Sept.-Oct. 2003,
doi: 10.1109/MDT.2003.1232259.
