KNOW-HOW

CML vs. SST based driver

Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

SST Driver

sharing termination in SST transmitter

Sharing termination keep a constant current through leg, which improve TX speed in this way. On the other hand, the sharing termination facilitate drain/source sharing technique in layout.

pull-up and pull-down resistor

Original stacked structure

Pro's:

​ smaller static current when both pull up and pull down path is on

Con's:

​ slowly switching due to parasitic capacitance behind pull-up and pull-down resistor

with single shared linearization resistor

Pro's:

​ The parasitic capacitance behind the resistor still exists but is now always driven high or low actively

Con's:

​ more static current

VM Driver Equalization - differential ended termination

\[ V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1} \]

where \(D_n \in \{-1, 1\}\)

\[ V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \] With \(R_u=(L+M+N)R_T\)

Normalize above equation, obtain \[ V_{\text{rx,norm}} = \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \]

Where precursor \(R_L = L\times R_T\), main cursor \(R_M = M\times R_T\) and post cursor \(R_N = N\times R_T\)

Equation-1

\(D_{n-1}D_nD_{n+1}=1,-1,-1\)

\[\begin{align} R_1 &= R_N \\ &= \frac{R_u}{N} \\ R_2 &= R_L\parallel R_M \\ &= \frac{R_u}{L+M} \end{align}\]

We obtain \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \]

Equation-2

\(D_{n-1}D_nD_{n+1}=-1,1,-1\)

with \(R_1=R_T\) and \(R_2=+\infty\), we obtain \[ V_M = \frac{1}{2} \]

Equation-3

\(D_{n-1}D_nD_{n+1}=-1,-1,1\)

\[\begin{align} R_1 &= R_L \\ &= \frac{R_u}{L} \\ R_2 &= R_N\parallel R_M \\ &= \frac{R_u}{N+M} \end{align}\]

We obtain \[ V_N = \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

We define \[\begin{align} l &= \frac{L}{L+M+N} \\ m &= \frac{M}{L+M+N} \\ n &= \frac{N}{L+M+N} \end{align}\]

where \(l+m+n=1\)

Due to Eq1 ~ Eq3 \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = \frac{1}{2}(n-l-m) \\ -C_{-1}+C_0-C_1 & = \frac{1}{2} \\ -C_{-1}-C_0+C_1 & = \frac{1}{2}(l-n-m) \end{array} \right. \] After scaling, we get \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = -l-m+n \\ -C_{-1}+C_0-C_1 & = l+m+n \\ -C_{-1}-C_0+C_1 & = l-m-n \end{array} \right. \] Then, the relationship between FIR coefficients and legs is clear, i.e. \[\begin{align} C_{-1} &= -\frac{L}{L+M+N} \\ C_{0} &= \frac{M}{L+M+N} \\ C_{1} &= -\frac{N}{L+M+N} \end{align}\]

For example, \(C_{-1}=-0.1\), \(C_0=0.7\) and \(C_1=-0.2\) \[ H(z) = -0.1+0.7z^{-1}-0.2z^{-2} \]

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w = [-0.1, 0.7, -0.2];
Fs = 32e9;
[mag, w] = freqz(w, 1, [], Fs);
plot(w/1e9, abs(mag));
xlabel('Freq(GHz)');
ylabel('mag');
grid on;

VM Driver Equalization - single ended termination

Equation-1

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\ V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N} \end{align}\] So \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \] which is same with differential ended termination

Equation-2

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \\ V_{\text{rxm}} &= 0 \end{align}\] So \[ V_{M}= \frac{1}{2} \] which is same with differential ended termination

Equation-3

\[ V_{N}= \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

Same with differential ended termination driver.

Basic Feed Forward Equalization Theory

Pre-cursor FFE can compensate phase distortion through the channel

Single-ended termination

Differential termination

reference

J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012, doi: 10.1109/JSSC.2012.2216414.

Jhwan Kim, CICC 2022, ES4-4: Transmitter Design for High-speed Serial Data Communications

Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

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@(posedge clk iff(vld));
do_something;

is equivalent to

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forever begin
	@(posedge clk);
    if(vld) break;
end
do_something;

iff is more efficient than if because the expression is recalculated when vld transition rather than clk.

One example, detecting the negative edge of rtr_io.cb.frameo_n[da]

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wait(rtr_io.cb.frameo_n[da] !== 0);
@(rtr_io.cb iff(rtr_io.cb.frameo_n[da] === 0 )); 
$display("[DEBUG HGUO] %0t, rtr_io.cb.frameo_n[da] negedge", $realtime);

[DEBUG HGUO] 6887250.0ns, rtr_io.cb.frameo_n[da] negedge

reference

system verilog中的iff, URL: https://www.francisz.cn/2019/07/18/sv-iff/

Linear Time-varying System Theory

We define the ISF of the sampler as the sensitivity of its final output voltage to the impulse arriving at its input at different times, the ISF essentially describes the aperture of the sampler.

An ideal sampler would have the perfect aperture, i.e. sampling the input voltage at exactly one point in time; thus, its ISF would be a Dirac delta function, \(\delta(t-t_s)\) where \(t_s\) is when sampling occurs.

A realistic sampler would rather capture a weighted-average of the input voltage over a certain time window. This weighting function is called the sampling aperture and is equivalent to the ISF

A time-varying impulse response \(h(t, \tau)\) is defined as the circuit response at time \(t\) responding to an impulse arriving at time \(\tau\).

In general, the ISF can be regarded as the time-varying impulse response evaluated at one particular observation time \(t=t_0\).

The system output \(y(t)\) is related to the input \(x(t)\) as: \[ y(t) = \int_{-\infty}^{\infty}h(t, \tau)\cdot x(\tau)d\tau \] Note that in a linear time-invariant (LTI) system, \(h(t,\tau)=h(t-\tau)\) and the above equation reduces to a convolution.

If \(X(j\omega)\) is the Fourier transform of the input signal \(x(t)\), i.e. \[ x(t) = \frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega t}d\omega \] Then \[\begin{align} y(t) &= \int_{-\infty}^{\infty}h(t,\tau)\left[\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega\tau }d\omega \right]\cdot d\tau \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{j\omega\tau}d\tau\right]\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\right]\cdot e^{j\omega t}\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot H(j\omega;t)\cdot e^{j\omega t}\cdot d\omega \end{align}\]

where \(H(j\omega;t)\) is time-varying transfer function, defined as the Fourier transform of the time-varying impulse response. \[ H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \] And it follows that: \[ Y(j\omega)=H(j\omega;t)\cdot X(j\omega) \] And

\[\begin{align} x(\tau) & \overset{FT}{\longrightarrow} X(j\omega) \\ h(t,\tau) & \overset{FT}{\longrightarrow} H(j\omega;t) \end{align}\]

For linear, periodically time-varying (LPTV) systems, \(h(t, \tau) = h(t+T, \tau+T)\) and \(H(j\omega; t) = H(j\omega; t+T)\) where \(T\) is the period of the time-varying dynamics of the system.

We prove \(H(j\omega; t) = H(j\omega; t+T)\):

\[\begin{align} \because H(j\omega;t)&=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ \therefore H(j\omega;t+T) &= \int_{-\infty}^{\infty}h(t+T,\tau)\cdot e^{-j\omega(t+T-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t+T-(\tau+T))}d(\tau+T) \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= H(j\omega;t) \end{align}\]

PSS + PAC Method

Since \(H(j\omega;t)\) is periodic in \(T\), The time-varying transfer function \(H(j\omega;t)\) can be expressed in a Fourier series: \[ H(j\omega;t)=\sum_{m=-\infty}^{\infty}H_m(j\omega) \cdot e^{jm\omega_c t} \] where \(\omega_c\) is the fundamental frequency of the periodic system. \(H_m(j\omega)\) represent the frequency response of the system at the (m-th) harmonic output sideband to a unit \(j\omega\) sinusoid.

The above equation link time-varying transfer function \(H(j\omega;t)\) with PAC simulation output

The response to a periodic impulse train, that is: \[ x(t)=\sum_{m=-\infty}^{\infty}\delta(t-\tau-nkT) \] The idea is that if the impulse response of the system settles to zero long before the next impulse arrives, then the system response to this impulse train would be approximately equal to the periodic repetition of the true impulse response, i.e.: \[ y(t) \cong \sum_{m=-\infty}^{\infty}h(t;\tau+nkT) \] and \(y(t)\) would be approximately equal to \(h(t;\tau)\) for \(\tau \leq t \le t+kT\)

Without loss of generality and for computation convenience, we set \(k=1\) thereafter.

The Fourier transform \(X(j\omega)\) of the T-periodic impulse train is: \[ X(j\omega)=\omega_c\sum_{n=-\infty}^{\infty}\delta(\omega-n\omega_c)\cdot e^{-j\omega\tau} \] Then the response \(y(t)\) is: \[ y(t)=\frac{1}{T}\sum_{n=-\infty}^{\infty}H(jn\omega_c;t)\cdot e^{jn\omega_c\cdot(t-\tau)} \] The expression for the approximate time-varying impulse response: \[ h(t,\tau) = \left\{ \begin{array}{cl} \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct+jn\omega_c\cdot (t-\tau)} & : \ \tau \leq t \lt \tau+T \\ 0 & : \ \text{elsewhere} \end{array} \right. \] Finally, the ISF \(\Gamma(\tau)\) is equal to \(h(t,\tau)\) when \(t=t_0\) and \(t_0 \gt \tau\) \[ \Gamma(\tau)\cong \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct_0+jn\omega_c\cdot (t_0-\tau)} \] In practice, the summations are carried out over finite ranges of n and m, for example, -50~50.

For each combination of n and m, the PAC analysis needs to be performed to compute \(H_m(jn\omega_c)\), the m-th harmonic response to the excitation at \(n\omega_c\)

The detailed procedure for characterizing the ISF of this sampler is outlined as follows:

• First, apply the proper input voltages that place the sampler in a metastable state and perform the periodic steady-state (PSS) analysis.

• Second, perform the PAC analysis.

• Third, based on the simulated PAC response, pick a time point \(t_0\) at which the ISF is to be computed and derive the ISF

One possible candidate for the ISF measurement point \(t_0\) is the time at which the output voltage is amplified to the largest value. PAC response of the sampler to a small signal DC input, that is, the time-varying transfer function evaluated at \(\omega=0\) \[ H(0;t)=\sum_{m=-\infty}^{\infty}H_m(0) \cdot e^{jm\omega_c t} \]

The total area under the ISF is the sampling gain, which is equal to the time-varying gain measured at \(t_0\) to a small signal DC input (\(\omega=0\))

Because we have \(H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\), i.e. Fourier transform \[ H(0;t)=\int_{-\infty}^{\infty}h(t,\tau)d\tau = \int_{-\infty}^{\infty}\Gamma(\tau)d\tau \]

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time-varying gain at t0 H(0;t0): 19.486305
The total area under the ISF: 19.990230

Align pss_td.pss with ISF

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****************************************************
Periodic Steady-State Analysis `pss': fund = 500 MHz
****************************************************
Trying `homotopy = gmin' for initial conditions.
DC simulation time: CPU = 4.237 ms, elapsed = 4.27389 ms.

===============================
`pss': time = (0 s -> 102.6 ns)
===============================

Opening the PSF file ../psf/pss.tran.pss ...
...
Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 102.6 ns
    period = 2 ns
    maxperiods = 20
    step = 102.6 ps
...

tstab = 102.6 ns can be observed in pss simulation log

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tstab = 102.6e-9;
tshift = mod(tstab, Tc);
tt_shift = tt - tshift;
tt_shift_start_indx = find(tt_shift>=0, 1);
isf_shift = circshift(isf_re, -tt_shift_start_indx);

Align pss_fd.pss with ISF

Since both are frequency originated, time-shift is NOT needed

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function wv = wv_fd(fname,tt)
fd = csvread(fname, 1, 0);
DC = fd(1, 2);
w = 2*pi*fd(2:end, 1);
coef = fd(2:end, 2) + 1i*fd(2:end, 3);
exp_sup = 1i*w.*tt;
wv = sum(real(coef .* exp(exp_sup)), 1) + DC;
end

PSS + PAC Setup

• clock frequency should be low enough to assure system response settle to zero.
• Beat Frequency os PSS should be clock frequency
• For PAC setup,
  • the Sweeptype is absolute
  • Input Frequency Sweep Range(Hz) should be large enough.
  • Sweep Type should be Linear and Step Size should equal PSS Beat Frequency(Hz)
  • SideBands should large enough, like 50 (i.e. 50*2 +1, positive, negative and 0)
  • Specialized Analyses should be None

one example: clock, i.e. beat frequency = 8G PAC: input frequency sweep from -400G to 400G and step is 8G, which is beat frequency, here K=1 Eq.(9) of paper

freqaxis=out: freqaxis of PAC not only affect "Direct Plot"'s output but also simuation data i.e. the phase shift(imaginary part).

matlab matrix nonconjugate transpose:

transpose, .' cf. https://www.mathworks.com/help/matlab/ref/transpose.html

tstab in PSS

Using shooting PSS, the steady waveform starts from tstab+n*tperiod.

• pss_td.pss is one period waveform starting from tstab+n*tperiod
• pss_fd.pss is the complex fourier series coefficient of expanded to left and right pss_td.pss waveform (tstab+n*tperiod : tstab+(n+1)*tperiod)

We have to left-shift mod(tstab, tperiod) pss_fd.pss in order to align it with of pss_tb.pss

simulation log

The below stop = 1.3 ns is actual tstab time, though Stop Time(tstab) field of pss form is filled with 0.3n

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**************************************************
Periodic Steady-State Analysis `pss': fund = 1 GHz
**************************************************
DC simulation time: CPU = 208 us, elapsed = 211.954 us.

=============================
`pss': time = (0 s -> 1.3 ns)
=============================

Opening the PSF file ../psf/pss.tran.pss ...

Output and IC/nodeset summary:
                 save   1       (current)
                 save   2       (voltage)

Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 1.3 ns
    period = 1 ns
    maxperiods = 20
    step = 1.3 ps
    maxstep = 40 ps
    ic = all
    useprevic = no
	...

    pss: time = 64.01 ps    (4.92 %), step = 31.63 ps     (2.43 %)
	...
    pss: time = 1.224 ns    (94.2 %), step = 40 ps        (3.08 %)
    pss: time = 1.3 ns       (100 %), step = 35.99 ps     (2.77 %)
...

PSS simulation result

Align pss_tb and pss_fd

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clear;
clc;

freq = 1e9;
tstab = 1.3e-9;
Tp  = 1e-9;

load('pss_td.matlab')
t = pss_td(:, 1);
ytd = pss_td(:, 2);
plot(t*1e9, ytd, 'k', 'LineWidth',6)
hold on;

% time domian from pss frequency domain information
coff_real = -0.155222;
coff_imag = -0.0247045;
wc = 2*pi*freq;
tfd = (0:1e-11:2e-9);
yfd = coff_real*cos(wc*tfd) - coff_imag*sin(wc*tfd);
plot(tfd*1e9, yfd, 'b')

% actual pss_td.pss one-period waveform
tfd_td = (tstab:1e-11:2e-9);
yfd_td = coff_real*cos(wc*tfd_td) - coff_imag*sin(wc*tfd_td);
plot(tfd_td*1e9, yfd_td, '--b', 'LineWidth', 4)

% align pss_fd with pss_tb by left shift mod(tstab, Tp) pss_fd
tshift = mod(tstab, Tp);
tfd_shift = tfd - tshift;
tfd_shift_start_indx = find(tfd_shift>=0, 1);
tfd_shift = tfd_shift(1, tfd_shift_start_indx:end);
yfd_shift = yfd(1, tfd_shift_start_indx:end);
plot(tfd_shift*1e9, yfd_shift, '-magenta', 'LineWidth', 2)
grid on;

xlabel('t (ps)');
ylabel('V(t)');
legend('Using pss\_td', 'Using pss\_fd', 'pss\_tb one period clip', 'Using pss\_fd with time shift', 'location', 'east');

Transient Method

TODO 📅

reference

J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 386-391, doi: 10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]

M. Jeeradit et al., "Characterizing sampling aperture of clocked comparators," 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2008, pp. 68-69 [https://people.engr.tamu.edu/spalermo/ecen689/sampling_aperature_comparators_vlsi_2008.pdf]

T. Toifl et al., "A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 954-965, April 2006 [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=4d1f0442be77425ed34b9dcfd48fbfff954a707b]

Sam Palermo, ECEN 720 High-Speed Links: Circuits and Systems [Lecture 6: RX Circuits], [Lab4 - Receiver Circuits]

Latchup

TODO 📅

Silicon Controlled Rectifiers (SCR)

TODO 📅

ESD design window

[https://monthly-pulse.com/2021/06/02/the-esd-design-window-concept/]

[https://www.researching.cn/ArticlePdf/m00098/2020/41/12/122403.pdf]

• Transparency
  • Trigger voltage Vt1
  • Holding/clamping voltage Vh
• Robustness
  • failure current level It2
• Effectiveness
  • maximum voltage of the clamp device: Vmax

Secondary protection

1. Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors.
2. ESD current through this clamp will build-up voltage across the isolation resistance, while protecting the circuit.
3. The higher voltage at the IN pad will then trigger the primary protection (red current path)

Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors

Extended ESD design window example. The failure voltage of a thin gate oxide in advanced CMOS is about 4V. The primary ESD solution (red IV curve) introduces too much voltage. Thanks to an isolation resistance between primary and secondary local clamp device (green IV curve) additional margin is created.

[https://monthly-pulse.com/2022/03/29/introduction-esd-protection-concepts-for-i-os/]

Gated diode & STI diode

M. Simicic, G. Hellings, S. -H. Chen, N. Horiguchi and D. Linten, "ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology," 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, Germany, 2018

TLP/vf-TLP

TRANSMISSION LINE PULSE TESTING: THE INDISPENSABLE TOOL FOR ESD CHARACTERIZATION OF DEVICES, CIRCUITS AND SYSTEMS [https://www.esda.org/assets/News/1708-ESD-firstDraft.pdf]

[https://monthly-pulse.com/2021/06/08/transmission-line-pulse-tlp-test-system/]

Jon Barth "TLP and VFTLP Testing of Integrated Circuit ESD Protection" [https://barthelectronics.com/wp-content/uploads/2016/09/TLP-and-VFTLP-Test-of-Integrated-Circuit-ESD-Protection.pdf]

Horst A. Gieser(IZM), "ESD- Testing: HBM to very fast TLP" [https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf]

Vt1: trigger voltage

Vhold: holding voltage

soft failure current: Isoft

hard failure current: It2

TLP vs ESD

• ESD tests simulate real world events (HBM, MM, CDM)
• TLP does not simulate any real-world event
• ESD tests record failure level (Qualification)
• TLP tests record failure level and device behavior (Characterization)

TLP is not a qualification test, but a characterization method, which describes the resistance of a device for a given stimulus, aka. Device Characterization

Unlike ESD waveforms, TLP does not mimic any real world event

TLP and Curve Tracing

• Curve Tracing is DC; TLP is a short pulse
  • Shorter pulse - Reduced duty cycle, less heating, which means higher voltage before failure
  • Controlled Impedance - Allows device behavior to be observed
• Both measure resistance of device with increasing voltage

Device Characterization with TLP

• Turn-on time
• Snapback voltage
• Performance changes with rise time

VF-TLP and CDM differences

Question:

How well will VF-TLP results predict CDM testing performance?

Answer:

VF-TLP can be a guide to CDM failure levels, and provide a lot of understanding of a circuit's operation during CDM stressing, but simple correlations between VF-TLP failure current level and CDM withstand voltage levels are difficult to establish.

I.V and Leakage Evolution Plots

DC leakage current data combined with the I-V data provides electrical indications of where damage begins, and how rapidly it can evolve from soft to hard failures

Henry, Leo & Barth, Jon & Richner, John & Verhaege, Koen. (2000). Transmission Line Pulse Testing of the ESD Protection Structures in ICs - A Failure Analyst's Perspective. 203-213. 10.31399/asm.cp.istfa2000p0203. [https://barthelectronics.com/pdf_files/2000%20ISTFA%20TLP%20Testing%20of%20the%20ESD%20Protection%20Structure.pdf]

Henry, L.G. & Barth, Jon & Verhaege, K. & Richner, J.. (2001). Transmission-line pulse ESD testing of ICs: A new beginning. Compliance Engineering. 18. 46+53. [https://barthelectronics.com/pdf_files/CE%20TLP%20Article%20March-April%202001.pdf]

Snapback

Unfortunately, this protection concept is not effective anymore in advanced FinFET technology. Our analysis showed that both core and IO transistors are damaged at the onset of snapback in several FinFET processes.

Lesson 2 - ESD Clamps [https://aicdesign.org/wp-content/uploads/2021/05/Lesson02_ESD_Clamps210315.pdf]

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis - Device Level [https://www.esdemc.com/public/docs/TechnicalSlides/ESDEMC_TS001.pdf]

Safe operating area (SOA)

power clamp

Thanks to the device scaling the area is actually reasonable. However, the leakage becomes the main bottleneck.

high current diode

both diode are reverse-biased in normal operation, the PN Junction capacitance is proportional to forward-bias voltage

HIA_DIO can be used for logic or high speed circuits ESD protection

HIA: high current application purpose (High Amp)

There is no process difference between HIA_DIO and regular diode

• diode is drain/source originated, which is different from MOS (Gate originated)

• The perimeter of diode in DRC is different from that in PERC deck, where PERC excludes the the left and right edge of OD

g after the rule numbers: DFM recommendations and guidelines

^U: the rule is not checked by the DRC

MOS

l in netlist has different definition for MOS and diode.

MOS: length of channel

diode: Gate space

HIA = High Amp

lateral diode: perimeter is key DRC rule for ESD diode

HIA diode process is same with regular junction diode

Dual Stacked Diodes

PS: I/O to GND positively

NS: I/O to GND negatively

PD: I/O to VDD positively

ND: I/O to VDD negatively

Dual diode should be used with power clamp for PS and ND path

PMOS power clamp

Gate grounded N-MOS (ggNMOS)

[https://monthly-pulse.com/2022/02/02/time-to-say-farewell-to-the-snapback-ggnmos-for-esd-protection/]

[https://monthly-pulse.com/2023/01/26/ggnmos-grounded-gated-nmos/]

Influence of the pulse rise time on ggNMOS. (left side) A fast ESD pulse can couple the bulk of the NMOS to a higher potential for a short period, reducing the trigger voltage. (right side) A clear Vt1 reduction is visible, while the remaining part of the IV curve remains the same.

resistance between gate and source that designers typically use to reduce the Vt1 trigger voltage of a ggNMOS ESD protection

The drain (D) is connected to an I/O pad and the gate (G) is grounded.

To ensure “zero” leakage of the ESD protection structure under normal operations.

To to protect gate of core device, tie-high and tie-low shall be used when used as secondary ESD protection.

Positive ESD transient at I/O pad

1. DB junction is reverse-biased all the way to its breakdown.
2. Avalance multiplication takes place and generates electron-hole pairs
3. Hole current flows into the ground via the B-region and build up a potential, VR, across the lateral parasitic resistance R
4. As VR increases, the BS junction turns on, eventually triggers the parasitic lateral NPN transistor Q (DBS)

Negative ESD transient at I/O pad

The forward-biased parasitic diode, BD, will shunt the transient

ggNMOS is commonly used in the GPIO provided by foundry, which alleviate the ESD design burden of customer.

These GPIO is self-protective thanks to the ggNMOS.

Reference

Introduction to Transmission Line Pulse (TLP), URL: https://tools.thermofisher.com/content/sfs/brochures/TLP%20Presentation%20May%202009.pdf

VF-TLP and CDM differences, URL: https://www.grundtech.com/app-note-vf-tlp-cdm-differences

ESD-Testing: HBM to very fast TLP URL: https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1-6, doi: 10.1109/CICC48029.2020.9075899.

KOEN DECOCK IEEE-SSCSLEUVEN "ON-CHIP ESD PROTECTION: BASIC CONCEPTS AND ADVANCED APPLICATIONS" [https://monthly-pulse.com/wp-content/uploads/2021/11/2021-11-sofics_presentation_ieee_final.pdf]

Yuanzhong Zhou, D. Connerney, R. Carroll and T. Luk, "Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models," Sixth international symposium on quality electronic design (isqed'05), 2005, pp. 476-481, doi: 10.1109/ISQED.2005.81.

Charged Device Model (CDM) Qualification Issues - Expanded [https://www.jedec.org/sites/default/files/IndustryCouncil_CDM_October2021_JEDECversion_September2022_rev1.pdf]

Wang, Albert ZH. On-chip ESD protection for integrated circuits: an IC design perspective. Vol. 663. Springer Science & Business Media, 2002.

Wang, Albert. Practical ESD Protection Design. John Wiley & Sons, 2021.

Ker, Ming-Dou, and Sheng-Fu Hsu. Transient-induced latchup in CMOS integrated circuits. John Wiley & Sons, 2009.

Milin Zhang, "Low Power Circuit Design Using Advanced CMOS Technology" River Publishers 2018

It depends on the simulator:

• QuestaSim, Xcelium: You have to import pkg or `include file in top testbench
• VCS: VCS automatically search testcase in other Compilation Units

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// test_pkg.sv
package sim_pkg;
	import uvm_pkg::*;
	`include "uvm_macros.svh"

	class my_test extends uvm_test;
		`uvm_component_utils(my_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of my_test", UVM_LOW)
		endtask : run_phase
	endclass : my_test

	class its_test extends uvm_test;
		`uvm_component_utils(its_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of its_test", UVM_LOW)
		endtask : run_phase
	endclass : its_test

endpackage : sim_pkg

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// tb_top.sv
module tb_top;
	import uvm_pkg::*;
	//import sim_pkg::*;

	initial begin
		run_test();
	end
endmodule

Xcelium log:

UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. UVM_INFO /home/EDA/Cadence/XCELIUM2109/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 0: reporter [UVM/REPORT/CATCHER]

QuestaSim log:

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) # UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. # UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. # UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]

solution:

uncomment //import sim_pkg::*; in tb_top.sv

FSDB

$fsdbDumpfile

It specifies the FSDB file name created by the Novas object files for FSDB dumping. If it is not specified, then the default FSDB file name is "novas.fsdb".

This command is valid only before executing $fsdbDumpvars and is ignored if specified after $fsdbDumpvars

$fsdbSuppress

The fsdbSuppressutility is used to skip dumping of few instances, scopes, modules and signals. The fsdbSuppressutility is a system task like other fsdb tasks.

For $fsdbSuppress() to be effective, it needs to be specified/called before $fsdbDumpvars

$fsdbAutoSwitchDumpfile

Automatically switch to a new dump file when the working FSDB file reaches the specified size or the specified wall time period.

After the dumping is finished, a virtual FSDB file (*.vf) is automatically created and list all of the generated FSDB files with the correct sequence. Only the virtual FSDB file, rather than all of the FSDB files, needs to be loaded to view the simulation results

When specified in the design to switch based on file size:

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$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"]);

When specified in the design to switch based on time period

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$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"], “+by_period”);

“+by_period”

$fsdbDumpvars

This command dumps the change in signal value to the FSDB file.

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$fsdbDumpvars([ depth, | "level=",depth_var, ],[instance | "instance=",instance_var])

For VCS users, to include memory, MDA, packed array and structure information in the generated FSDB file, the -debug_access option must be included when VCS is invoked to compile the design

• depth

  Specify how many sub-scope levels under the given scope you want to dump.

  • Specify this argument as 1 to dump the signals under the given scope
  • Specify this argument as 0 to dump all signals under the given scope and its descendant scopes.

  0: all signals in all scopes.

  1: all signals in current scope.

  2: all signals in the current scope and all scopes one level below.

  n: all signals in the current scope and all scopes n-1 levels below.

  	tb.clk	tb.u_div2.div2	tb.u_div2.u_div2neg.div2neg
  $fsdbDumpvars(0)	✓	✓	✓
  $fsdbDumpvars(1)	✓	✗	✗
  $fsdbDumpvars(2)	✓	✓	✗
  $fsdbDumpvars(1, tb.u_div2)	✗	✓	✗
  $fsdbDumpvars(0, tb.u_div2)	✗	✓	✓

  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

  module tb; reg clk; divider2 u_div2(clk); initial begin clk = 1'b0; forever #5 clk = ~clk; end initial begin #100; $finish(); end initial begin #10; $fsdbDumpfile("tb.fsdb"); //$fsdbDumpvars(0); // same with $fsdbDumpvars(0, tb) //$fsdbDumpvars(1); // same with $fsdbDumpvars(1, tb) //$fsdbDumpvars(2); // same with $fsdbDumpvars(2, tb) //$fsdbDumpvars(1, tb.u_div2); $fsdbDumpvars(0, tb.u_div2); #80 $finish(); end endmodule module divider2 ( input clk ); reg div2; divider2neg u_div2neg(div2); always@(posedge clk) begin div2 = ~div2; end initial begin div2 = 1'b0; end endmodule module divider2neg ( input clk ); reg div2neg; always@(negedge clk) begin div2neg = ~div2neg; end initial begin div2neg= 1'b0; end endmodule

  compile

  1	vcs -full64 -kdb -debug_access+all tb.v

  simulate

  1

  ./simv

  load fsdb

  1	verdi -ssf tb.fsdb

  

$fsdbDumpon, $fsdbDumpoff

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$fsdbDumpon(["+fsdbfile+filename"])

$fsdbDumpoff(["+fsdbfile+filename"])

These FSDB dumping commands turn dumping on and off. fsdbDumpon/fsdbDumpoff has the highest priority and overrides all other FSDB dumping commands.

fsdbDumpon/fsdbDumpoff is not restricted to only fsdbDumpvars. If there is more than one FSDB file open for dumping at one simulation run, fsdbDumpon/fsdbDumpoff may only affect a specific FSDB file by specifying the specific file name.

• +fsdbfile+filename: Specify the FSDB file name. If not specified, the default FSDB file name is "novas.fsdb"

$fsdbDumpFinish

This command closes all FSDB files in the current simulation and stops dumping of signals. Although all FSDB files are closed automatically at the end of simulation, this dumping command can be invoked to explicitly close the FSDB files during the simulation

VCD

$dumpfile

The declaration onf $dumpfile must come before the $dumpvars or any other system tasks that specifies dump.

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$dumpfile("test.vcd");

argument is necessary, there is no default value

$dumpvars

The $dumpvars is used to specify which variables are to be dumped ( in the file mentioned by $dumpfile). The simplest way to use it is without any argument.

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$dumpvars(<levels> <, <module_or_variable>>* );

$dumplimit

It is possible that you inadvertantly generate huge file in Gigabytes ( for examples while dumping a Gigahertz clock for one second). To reduce such occurrences, we may use $dumplimit. It usage is

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$dumplimit(<filesize>);

$dumpoff and $dumpon

During the simulation if you are bothered about about only during a certain interval then you can use $dumpoff and $dumpon. The following example shows its usage. It will dump the changes for first 100 units of time and then between 10200 and 10400 units of time.

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initial
    $monitor($time, " reset=%b,clk_out=%b",reset,clk_out);
    initial begin
            $dumpfile("clkdiv2n_tb.vcd");
            $dumpvars(0,clkdiv2n_tb);
            #100;
            $dumpoff;
            #10200;
            $dumpon;
            #10400;
            $dumpoff;
    end

demo

stimulus.v

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`timescale 1ns / 1ps
module stimulus;
	// Inputs
	reg x;
	reg y;
	// Outputs
	wire z;
	// Instantiate the Unit Under Test (UUT)
	comparator uut (
		.x(x),
		.y(y),
		.z(z)
	);

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0);
		// Initialize Inputs
		x = 0;
		y = 0;

		#20 x = 1;
		#20 y = 1;
		#20 y = 0;
		#20 x = 1;
		#40 ;

	end

	initial begin
		$monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,z, );
	end

endmodule

comparator.v

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module comparator(
	input x,
	input y,
	output z
);

	assign z = (~x & ~y) |(x & y);

endmodule

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$ xrun stimulus.v comparator.v -access +rwc
$ simvision test.vcd

reference

$dumpvars and $dumpfile Verilog, http://www.referencedesigner.com/tutorials/verilog/verilog_62.php

plusargs are command-line switches supported by the simulator. As per SystemVerilog LRM arguments beginning with the + character will be available using the $test$plusargs and $value$plusargs PLI APIs.

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$test$plusargs (user_string)

$value$plusargs (user_string, variable)

Example

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// tb.v
module tb;
        int a;
        initial begin
                if($test$plusargs("RUNSIM")) begin
                        $display("There is RUNSIM plusargs");
                end else begin
                        $display("There is NO $test$plusargs");
                end
                if($value$plusargs("SEED=%d",a)) begin
                        $display("SEED=%d",a);
                end else begin
                        $display("There is NO $value$plusargs");
                end
        end
endmodule

• compile

  1 2	$ vlib work $ vlog -sv tb.v

• simulate (QuestaSim)

  • without plusargs

    1	$ vsim work.tb -c -do "run; exit"

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    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is NO $test$plusargs # There is NO $value$plusargs # exit # End time: 13:04:23 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

  • with plusargs

    1	$ vsim work.tb -c -do "run; exit" +SEED=31 +RUNSIM

    +SEED=31 +RUNSIM

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    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is RUNSIM plusargs # SEED= 31 # exit # End time: 13:04:55 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

reference

systemverilog-command-line-input URL: https://www.chipverify.com/systemverilog/systemverilog-command-line-input

PLUSARGS IN SYSTEMVERILOG URL:https://www.theartofverification.com/plusargs-in-systemverilog/

unsigned + unsigned = unsigned

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function [7:0] satadd_uuu8b;   // unsigned + unsigned = unsigned
    input [7:0] a;
    input [7:0] b;

    reg [8:0] t;   // extend 1b
    begin
        t = {1'b0, a} + {1'b0, b};
        satop_uuu16b = t[8] ? {8{1'b1}} : t[7:0];
    end
endfunction

1'b1: overflow

signed + signed = signed

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function [7:0] satadd_sss8b;    // signed + signed = signed
    input signed    [7:0] a;
    input signed    [7:0] b;

    reg signed [8:0] t; // extend 1b
    begin
        t = a + b;  // extend sign bit automatically
        satadd_sss8b =  (t[8:7] == 2'b01) ? {1'b0, 7{1'b1}} : // up sat
                        (t[8:7] == 2'b10) ? {1'b1, 7{1'b0}} : // dn sat
                                            t[7:0];
    end
endfunction

2'b01: overflow

2'b10: underflow

signed + unsigned = unsigned

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function [7:0] satadd_suu8b;    // signed + unsigned = unsigned
    input signed    [7:0] a;
    input           [7:0] b;

    reg signed [8:0] t; // extend 1b
    begin
        t = {a[7], a} + {1'b0, b};
        satadd_ssu8b =  (t[8:7] == 2'b10) ? {8{1'b1}} : // up saturate for unsigned
                        (t[8:7] == 2'b11) ? {8{1'b0}} : // dn saturate for unsigned
                                            t[7:0];
    end
endfunction

signed + unsigned = signed

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function signed [7:0] satop_sus8b;    //signed +/- unsigned = signed
    input signed    [7:0] a;
    input           [7:0] b;
    input plus;

    reg signed [8:0] t;    // extend 1b
    begin
        if(plus) begin
            t = {a[7], a} + {1'b0, b};
            satop_sus8b = (t[8:7]==2'b01) ? {1'b0, {7{1'b1}}}   // up saturate for signed
                                             : t[7:0];
        end else begin
            t = {a[7], a} - {1'b0, b};
            satop_sus8b = (t[8:7]==2'b10) ? {1'b1, {7{1'b0}}}   // dn saturate for signed
                                             : t[7:0];
        end
    end
endfunction

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain (AON).

To prevent corruption of always-on domain, we clamp the nets crossing the power domains to a value depending upon the design.

A simple circuit having a switchable (or gated) power domain

The circuit shown in Figure 1, after isolation cells are inserted

Always-On Buffer

reference

Isolation cells and Level Shifter cells URL: https://vlsitutorials.com/isolation-cells-level-shifter-cells-low-power-vlsi/

Jitter separation lets you learn if the components of jitter are random or deterministic. That is, if they are caused by crosstalk, channel loss, or some other phenomenon. The identification of jitter and noise sources is critical when debugging failure sources in the transmission of high-speed serial signals

• Tail Fit Method
• Spectral method

Jitter Components

dual-Dirac model

Spectral method

power spectral density (PSD) represents jitter spectrum and peaks in the spectrum can be interpreted as PJ or DDJ, while the average noise floor is the power of RJ

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S1 = sum(win);
S2 = sum(win.^2);
N = length(win);
spec_nospur2 = (spec_nospur*S1).^2/N/S2;    % To obtain linear spectrum for rj
rj_utj = sqrt(sum(spec_nospur2))*1e12;

spec = 1*ones(length(spec_nospur), 1)*1e-21;
spec(index) = specx(index);
% insert fft nyquist frequency component between positive frequency and
% negative frequency component
% DC;posFreq;nyqFreq;negFreq
spec_ifft = [spec;specnyq;conj(spec(end:-1:2))]';
sfactor = sum(win)/sqrt(2);
spec_ifft = spec_ifft*sfactor;
sig_rec = real(ifft(spec_ifft));
sig_rec = sig_rec(:);
sig_rec_utj = sig_rec./win(1:end);

Tail Fit Method

Tail fitting algorithm based on the Gaussian tail model by using probability distribution of collected jitter value

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bin_sig = bin_sig*1e12;

x = qfuncinv(cdf_sig);

% coef(1)*bin_sig + coef(2) = x
% which x is norm(0, 1)
% bin_sig = (x - coef(2))/coef(1)
% Then bin is norm(-coef(2)/coef(1), 1/coef(1))
coef = polyfit(bin_sig, x, 1);
sigma = 1/coef(1);
mu = -coef(2)*sigma;

fprintf('sigma=%.3fps, mu=%.3fps\n', sigma, mu);

Least Squares (LS) method

It is known that TIE jitter is a linear equation, shown in below formula \[ x[n] = d_n \times \left[ \Delta t_{pj}[n]+\Delta t_{DCD}[n] +\Delta t_{ISI}[n]+\Delta t_{RJ}[n]\right] \] LS can be used to estimate the PJ, DCD, RJ , and ISI parameters \([a,b,J_{DCD},J_0, J_1...J_{(2^k-1)}]\)

Jitter modeling

Periodic Jitter (PJ)

PJ is a repeating jitter \[ \Delta t_{PJ}[n]=A\sin(2\pi f_0\cdot nT_s + \theta)=a \sin(2\pi f_0 \cdot nT_s)+b\cos(2\pi f_0 \cdot nT_s) \] where \(f_0\) represents the fundamental frequency of PJ; \(A\) is the amplitude of PJ; \(T_s\) is the data stream period, and \(\theta\) is the initial phase of PJ

In the spectrum, the frequency of maximum amount of the jitter is PJ frequency \(f_0\).

Duty Cycle Distortion (DCD)

DCD is viewed as a series of adjacent positive and negative impulses \[ \Delta t_{DCD}[n] = J_{DCD}\times (-1)^n = [-J_{DCD},J_{DCD},-J_{DCD},J_{DCD},...] \] Where \(J_{DCD}\) is the DCD amplitude.

Random Jitter (RJ)

RJ is created by unbounded jitter sources, such as Gaussian white noise. The statistical PDF for RJ is enerally treated as a Gaussian distribution \[ f_{RJ}(\Delta t) = \frac{1}{\sqrt{2\pi\sigma}}\exp(-\frac{(\Delta t)^2}{2\sigma^2}) \]

Remarks

Periodic Jitter Generator and Insertion

Analysis and Estimation of Jitter Sub-Components: Classification and Segregation of Jitter Components

Reference

Mike Li. 2007. Jitter, noise, and signal integrity at high-speed (First. ed.). Prentice Hall Press, USA.

余宥浚 Jacky Yu, Keysight Taiwan AEO, Advanced Jitter and Eye-Diagram Analysis

Y. Duan and D. Chen, "Accurate jitter decomposition in high-speed links," 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, pp. 1-6, doi: 10.1109/VTS.2017.7928918.

Y. Duan's phd thesis URL: https://dr.lib.iastate.edu/handle/20.500.12876/30459

Y. Duan and D. Chen, "Fast and Accurate Decomposition of Deterministic Jitter Components in High-Speed Links," in IEEE Transactions on Electromagnetic Compatibility, vol. 61, no. 1, pp. 217-225, Feb. 2019, doi: 10.1109/TEMC.2018.2797122.

"Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-Scale", Whitepaper: Keysight Technologies, U.S.A., Dec. 2017

Sharma, Vijender Kumar and Sujay Deb. "Analysis and Estimation of Jitter Sub-Components." (2014).

Qingqi Dou and J. A. Abraham, "Jitter decomposition in ring oscillators," Asia and South Pacific Conference on Design Automation, 2006

E. Balestrieri, L. De Vito, F. Lamonaca, F. Picariello, S. Rapuano and I. Tudosa, "The jitter measurement ways: The jitter decomposition," in IEEE Instrumentation & Measurement Magazine, vol. 23, no. 7, pp. 3-12, Oct. 2020, doi: 10.1109/MIM.2020.9234759.

McClure, Mark Scott. "Digital jitter measurement and separation." PhD diss., 2005.

Ren, Nan, Zaiming Fu, Shengcu Lei, Hanglin Liu, and Shulin Tian. "Jitter generation model based on timing modulation and cross point calibration for jitter decomposition." Metrology and Measurement Systems 28, no. 1 (2021).

M. P. Li, J. Wilstrup, R. Jessen and D. Petrich, "A new method for jitter decomposition through its distribution tail fitting," International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, pp. 788-794, doi: 10.1109/TEST.1999.805809.

K. Bidaj, J. -B. Begueret and J. Deroo, "RJ/DJ jitter decomposition technique for high speed links," 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) [https://sci-hub.se/10.1109/ICECS.2016.7841269]