KNOW-HOW

Gain-boosted cascode

TODO 📅

Zero-Value Time Constant Analysis

TODO 📅

Transmission Gate

Equivalent Resistance is defined by large signal

[https://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/TGlecture.pdf]

CMRR (Common-Mode Properties)

MOS Thermal Noise

Michael H. Perrott. Analysis and Design of Analog Integrated Circuits Lecture 14 Noise Spectral Analysis for Circuit Elements [https://www.cppsim.com/CircuitLectures/Lecture14.pdf]

Legacy Long-Channel Model

\[ \color{red} \overline{i^2_d} \propto \gamma \propto \eta \propto \frac{1}{V_{DS}} \]

[https://www.eecg.toronto.edu/~johns/ece512/lecture_notes/04_noise_2_per_page.pdf]

[https://people.engr.tamu.edu/spalermo/ecen474/lecture12_ee474_noise.pdf]

Short-Channel Effects

Gildenblat, G. S. (2010). Compact modeling : principles, techniques and applications. Springer.

VDS Effect On Channel Noise

\[ \color{red} \overline{i^2_d} \propto V_{DS} \]

K. Ohmori and S. Amakawa, "Direct White Noise Characterization of Short-Channel MOSFETs," in IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1478-1482, April 2021 [pdf, slides]

X. Ding, G. Niu, A. Zhang, W. Cai and K. Imura, "Experimental Extraction of Thermal Noise γ Factors in a 14-nm RF FinFET technology," 2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, 2021[https://sci-hub.se/10.1109/SiRF51851.2021.9383331]

NF50

TODO 📅

\(\gamma\) vs VDS, VGS in simulation

N28

fix VDS, sweep VGS

fix VGS, sweep VDS

MOS Flicker Noise

T. Noulis, "CMOS process transient noise simulation analysis and benchmarking," 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Bremen, Germany, 2016 [https://sci-hub.ru/10.1109/PATMOS.2016.7833428] Dr. Thomas Gneiting, AdMOS GmbH. Flicker Noise Extraction for Scalable MOS Simulation Models [https://www.mos-ak.org/premstaetten/papers/MOS-AK_T.Gneiting.pdf]

Noise analysis ON,IN cfg	input noise, noise gain, output noise
		i: Id o: Vg
		i: V5 o: Id
		i: V1 o: Id

Above simulation demonstrate that flicker noise is represented by a drain-source current in BSIM model, however modeled as a voltage source in series with the gate is just for calculating convenience

Sam Palermo. Lecture 12: Noise. ECEN474: (Analog) VLSI Circuit Design Fall 2012 [https://people.engr.tamu.edu/spalermo/ecen474/lecture12_ee474_noise.pdf]

p23 TODO 📅

Notice, input referred noise unit follow output noise's unit

陈铖颖，杨丽琼，王统. CMOS模拟集成电路设计与仿真实例：基于CadenceADE. 电子工业出版社，2013

MOS Shot Noise

Gate-Referred Noise Lemma

inverter capacitance simulation

inverter input

R-C, series equivalent circuit

inverter output

R-C, parallel equivalent circuit

AC simulation

@vi = 0

sweep vi from 0 to 800mV (vdd)

SP simulation

EEStream. Cadence - How to find device capacitance - DC simulation, SP simulation and Large-signal SP simulation [https://www.youtube.com/watch?v=M3zP6eJnONk]

50-ohm?

Why is 50-ohm characteristic impedance standardized in RF and Microwave systems? [link]

[https://www.microwaves101.com/encyclopedias/why-fifty-ohms]

It was a compromise made and a tradeoff between power handling (red curve) and losses (blue curve)

Gm Rout Lemma

\[ A_V = -G_m R_{out} \]

Relative Sensitivity

Olivier de Weck, Karen Willcox. MIT, Gradient Calculation and Sensitivity Analysis [pdf]

Karti Mayaram, ECE 521 Fall 2016 Analog Circuit Simulation, Sensitivity and noise analyses [https://web.engr.oregonstate.edu/~karti/ece521/lec16_11_09.pdf]

Assuming Target \(T\) ( for example, the total resistance) is function of \(x_1,x_2,...,x_N\), then total variation can be expressed as

\[\begin{align} dT &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}dx_n \\ &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}x_n\cdot \frac{dx_n}{x_n} \end{align}\]

Then, we obtain relative variation \[\begin{align} \frac{dT}{T} &= \sum_{n=1}^N\frac{\partial T}{\partial x_n}\frac{x_n}{T}\cdot \frac{dx_n}{x_n} \\ &= \sum_{n=1}^N S_{x_n}^T \cdot \frac{dx_n}{x_n} \end{align}\]

⭐ where \(S_{x_n}^T=\frac{\partial T}{\partial x_n}\frac{x_n}{T}\) is relative sensitivity

relative sensitivity connect \(\frac{dx_n}{x_n}\) with total relative variation \(\frac{dT}{T}\)

And \(dT\) can be expressed as \[ dT =\sum_{n=1}^N S_{x_n}^T T\cdot \frac{dx_n}{x_n} = \sum_{n=1}^N x_n'\cdot \frac{dx_n}{x_n} \] ⭐ where \(x_n'= S_{x_n}^T T\) is the contribution of \(x_n\) in \(T\)

⭐ For parallel or series resistors, it can prove \(\sum_{n=1}^N S_{x_n}^T = 1\) and \(\sum_{n=1}^N x_n'=T\)

Here \(T= R_1 \parallel R_2 = \frac{R_1R_2}{R_1+R_2}\), and \(T|_{R_1=8000, R_2=2000} = 1600\)

We obtain relative sensitivity: \[\begin{align} S_{R_1}^T & = \frac{R_2}{R_1+R_2} \\ S_{R_2}^T & = \frac{R_1}{R_1+R_2} \end{align}\]

The contribution of \(R_1\) and \(R_2\) to \(T\) \[\begin{align} R_1' &= S_{R_1}^T T | _{R_1=8000, R_2=2000} = 320 \\ R_2' &= S_{R_2}^T T | _{R_1=8000, R_2=2000} = 1280 \end{align}\]

Normalized sensitivity captures relative sensitivity

change in objective per change in design variable

Device Current Components

common gate amplifiers

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_analog-analogdesign-rfdesign-activity-7126946716938878976-GeW6?utm_source=share&utm_medium=member_desktop]

Level Shifter

TIA

\[\begin{align} I_{in} &= \frac{V_i}{R_S} + \frac{V_i - V_o}{R_F} \\ \frac{V_i - V_o}{R_F} &= g_m V_i \end{align}\]

Then

\[\begin{align} V_o &= \frac{I_{in}R_F}{\frac{R_S+R_F}{R_S}\frac{1}{1-g_mR_F}- 1} \\ V_i &= \frac{I_{in}R_F}{\frac{R_F}{R_S}+g_mR_F} \end{align}\] If \(R_S \gg R_F\) \[\begin{align} V_o &= \frac{I_{in}}{g_m}(1-g_mR_F) \\ V_i &= \frac{I_{in}}{g_m} \end{align}\]

linearity

TIA stage allows for improved gain with better linearity, as mostly signal current passes through \(R_F\) TODO 📅 ??? Quantitative analysis

Switched-Capacitor Resistor

\[ R_{eq} = \frac{1}{f_sC} \]

[https://youtu.be/SL3-9ZMwdJQ?si=m_FSjnFQH4wjbZKH&t=1339]

Channel-Length Modulation & Pinched off

• \(\lambda \propto \frac{1}{L_g}\)
• \(\lambda \propto \frac{1}{V_{DS}}\)

• If \(V_{DS}\) is slightly greater than \(V_{GS} - V_{TH}\), then the inversion layer stops at \(x \leq L\), and we say the channel is "pinched off"
• Upon passing the pinchoff point, the electrons simply shoot through the depletion region near the drain junction and arrive at the drain terminal

\(L^{'}\) is the function of \(V_{DS}\)

with \(\frac{1}{L^{'}} = \frac{1}{L-\Delta L}=\frac{L+\Delta L}{L^2-\Delta L^2}\approx \frac{1}{L}\left(1+\frac{\Delta L}{L}\right)\), we have \[ I_D \approx \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(1+\frac{\Delta L}{L}\right)(V_{GS}-V_{TH})^2 = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2 (1+\lambda V_{DS}) \] assuming \(\frac{\Delta L}{L} = \lambda V_{DS}\)

\(\lambda\) represents the relative variation in length for a given increment in \(V_{DS}\). Thus, for longer channels, \(\lambda\) is smaller

In reality, however, \(r_O\) varies with \(V_{DS}\). As \(V_{DS}\) increases and the pinch-off point moves toward the source, the rate at which the depletion region around the source becomes wider decreases, resulting in a higher incremental output impedance.

Early Voltage indicator

\[ g_m r_o = \frac{g_m}{I_D}I_D \cdot \frac{V_A}{I_D} = \frac{g_m}{I_D} \cdot V_A \]

$g_m r_o $ is the indicator of \(V_A\), if \(\frac{g_m}{I_D}\) is same

Cgd of Common-Source Stage

Miller effect of Cgd during layout

Nonlinearity of Differential Circuits

\[ \cos^3\omega t = \frac{3\cos \omega t + \cos(3\omega t)}{4} \]

Zero in differential pair with active current mirror

Noting the circuit consists of a "slow path" (M1, M3, M4) in parallel with a "fast path" (M2)

• "slow path" \[ H_\text{slow}(s) = \frac{A_0}{(1+s/\omega _{pE})(1+s/\omega _{pO})} \]

• "fast path" \[ H_\text{fast}(s) = \frac{A_0}{1+s/\omega _{pO}} \]

Then \[\begin{align} \frac{V_\text{out}}{V_\text{in}} &= H_\text{slow}(s) + H_\text{fast}(s) \\ &= \frac{A_0}{1+s/\omega _{pO}}\left(\frac{1}{1+s/\omega _{pE}} + 1 \right) \\ &= \frac{A_0(1+s/2\omega _{pE})}{(1+s/\omega _{pO})(1+s/\omega _{pE})} \end{align}\]

That is, the system exhibits a zero at \(2\omega_{pE}\)

signals traveling through two paths within an amplifier may cancel each other at one frequency, creating a zero in the transfer function

\[ \omega_z = \frac{(A_1+A_2)\omega_{p1}\omega_{p2}}{A_1\omega_{p1}+A_2\omega_{p2}} \] noting \(\omega_{p1}\lt \omega_z \lt \omega_{p2}\)

"Zero" by Inspection

a method to predict the existence of "zero" by inspection, based on the concept of "Analog Phase Interpolation"

TODO 📅

Debashis Dhar, How to Recognize "Zero" by Inspection (Utilizing Analog Phase Interpolation) [https://www.linkedin.com/posts/debashis-dhar-12487024_how-to-recognize-zero-by-inspection-activity-7163364364329160704-9qOq?utm_source=share&utm_medium=member_desktop]

Random offset

The dependence of offset voltage and current mismatches upon the overdrive voltage is similar to our observations for corresponding noise quantities

differential pair

In reality, since mismatches are independent statistical variables

Above shows that the input transistors must be designed for high gain (\(g_mr_o = \frac{2}{V_{OV}\lambda}\)), which means they must be designed for small \(V_{GS}-V_{TH}\).

It is desirable to minimize \(V_{GS}-V_{TH}\) by lowering the tail current or increasing the transistor widths

For \(\frac{\Delta K}{K}\)

\[\begin{align} v_{os} g_m &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} 2K\frac{W}{L}(V_{GS}-V_{TH}) &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} &= \frac{V_{GS}-V_{TH}}{2} \frac{\Delta K}{K} \end{align}\]

The derivation for \(\frac{\Delta W/L}{W/L}\) is same with \(\frac{\Delta K}{K}\)

alternative derivation

\[\begin{align} \Delta V_\beta \cdot g_m &= \frac{\partial I_D}{\partial \beta} \Delta \beta \\ &= I_D \frac{\Delta \beta}{\beta} \end{align}\]

That is \(\Delta V_\beta = \frac{I_D}{g_m}\frac{\Delta \beta}{\beta}\)

\[ \Delta V_R \cdot g_m R = I_D \cdot \Delta R \]

That is \(\Delta V_R = \frac{I_D}{ g_m} \cdot \frac{\Delta R}{R}\)

[https://electronicengineering.phd.upc.edu/en/courses-and-seminars/courses-materials/2008-2009/slides-makinwa-1]

current mirror

To minimize current mismatch, the overdrive voltage must be maximized, a trend opposite to that in differential pair.

This is because as \(V_{GS}-V_{TH}\) increases, threshold mismatch has a lesser effect on the device currents

\(\Delta I_D= g_m \Delta V_{TH} = \frac{2I_D}{V_{OV}}\Delta V_{TH}\)

Effect of Feedback on Noise

Feedback does not improve the noise performance of circuits.

The input-referred noise voltage and current remain the same if the feedback network introduces no noise.

RC charge & discharge

• charge: \[ V_o(t) = V_{X}(1-e^{-\frac{t}{\tau}}) + V_{o,0}\cdot e^{\frac{-t}{\tau}} \]

• discharge: \[ V_o(t) = V_{o,0}\cdot e^{-\frac{t}{\tau}} + V_{o,\infty}\cdot(1-e^{-\frac{t}{\tau}}) \]

1. \(e^{-\frac{t}{\tau}}\) item determine the initial state
2. \((1-e^{-\frac{t}{\tau}})\) item determine the final state

AC coupling

\(V_m=\frac{1}{4},\space \frac{3}{4}\) and its common voltage \(\frac{1}{2}\)

\(V_o=-\frac{1}{4},\space \frac{1}{4}\) and its common voltage \(0\)

\[ \tau = 200 \text{nF} \times (50+50)\text{ohm} = 20 \mu s \]

high level envelope:

Current mirror with source degeneration

Razavi 2nd, problem 14.15

STB and PSTB in Spectre/RF

F. Wiedmann, "Loop gain simulation, [https://sites.google.com/site/frankwiedmann/loopgain]

M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17, no. 1, pp. 31-41, Jan. 2001, doi: 10.1109/101.900125.

Open loop gain analysis and "STB" method [https://www.linkedin.com/pulse/open-loop-gain-analysis-stb-method-jean-francois-debroux]

刘堃. Middlebrook环路测量方法讨论，STB原理 [https://bbs.eetop.cn/thread-985438-1-1.html]

STB analysis

Spectre stb's "loopgain" is negative of "T" in paper \[ T = \frac{2(AD-BC) - A + D}{2(AD-BC)-A+D-1} \]

AC simulation testbench, shown as below,

1. \(I_{inj}\) = 0, \(V_{inj}\) = 1

   B = if, D = ve

2. \(I_{inj}\) = 1, \(V_{inj}\) = 0

   A = if, C = ve

PSTB analysis

Spectre pstb is similar to stb, just set pac as 1 instead of ac in current source and voltage source.

This analysis just use harmonic 0 transfer function in pac analysis, which has limitation.

Thevenin and Norton Equivalent Circuits

戴维南定理

等效电阻的计算方法

使用外加电源法时， 全部独立电源需要置零

诺顿定理

Miller's Approximation: right-half-plane zero

A quick inspection of this circuit reveals that a zero lies at a frequency where the current through \(C_{12}\) becomes equal to \(g_2V_1\).

When this occurs, the current through the parallel combination of \(C_2\) and \(R_2\) becomes zero, creating a zero in the transfer function.

In other words, we can write

\[\begin{align} g_2V_1 &= V_1sC_{12} \\ s &= \frac{g_2}{C_{12}} \end{align}\]

Nonoverlapping clock

Classical

DWC

C2PHIa is important to ensure nonoverlapping and DelayA2B is due to level shifter

Single ended Amplifier Offset Voltage

unity gain buffer

\[\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \end{align}\]

Then, we get \[ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) \] Due to \(V_o=V_m\) and \(V_o'=V_m'\) \[ V_{os}=(1/A+1)\Delta{V_m} \] or \[ V_{os}=(1/A+1)\Delta{V_o} \] if \(A \gg 1\) \[ V_{os}=\Delta{V_o} \]

non-inverting amplifier

\[\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \\ V_m &= \beta V_o \\ V_m' &= \beta V_o' \end{align}\]

we get \[ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) \] or \[ V_{os}=\frac{\Delta V_o}{A}+\beta \Delta V_o \] if \(A \gg 1\) \[ V_{os}=\beta \Delta V_o \] or \[ V_{os}=\Delta V_m \]

Lecture 22 Variability and Mismatch of Dr. Hesham A. Omran's Analog IC Design

URL: https://www.master-micro.com/professional-courses/analog-ic-design/course-resources

Gotcha MOS ron

There is discrepancy between model operating point and \(V_{ds}/I_{ds}\)

I believe that the equation \(V_{ds}/I_{ds}\) is more appropriate where mos is used as switch, though \(V_{ds}=0\) is an outlier.

Schmitt Inverter

gm/ID Intuition

small gm/ID for High ro, or high Early voltage \(V_A\)

Transit Frequency \(f_T\)

Defined as the frequency at which the small-signal current gain of a device is unity

mag(Ids@ft) = Ig(1mA)

Aditya Varma Muppala. MMIC 08: High Frequency Device Characterization in Cadence - Fmax, Ft, NFmin vs Jd [https://youtu.be/kgEypIA8eus?si=sd4581x2hOuhsJ3P]

MOSFET ZTC Condition Analysis

M. Coelho et al., "Is There a ZTC Biasing Point in the Leading-Edge FET Intrinsic Gain gmrDS?," 2025 9th International Young Engineers Forum on Electrical and Computer Engineering (YEF-ECE), Caparica / Lisbon, Portugal, 2025

zero temperature coefficient (ZTC)

MOM cap of wo_mx

Monte Carlo model:

• \(C_{pa}=C_{pa1}\), \(C_{pb}=C_{pb1}\) for each iteration during Process Variation
• different variation is applied to \(C_{ab}\) and \(C_{a1b1}\) each iteration during Mismatch Variation, though \(C_{pa}\), \(C_{pb}\), \(C_{pa1}\) and \(C_{pb1}\) remain constant

Miller multiplication of Capacitor

Positive Cap

Negative Cap

gain has limited bandwidth

\(V_o = V_i |A|e^{j\theta}\), and \(A_r = |A|\cos\theta\), \(A_i = |A|\sin\theta\)

Then \(I_i = (V_i - V_o)sC_f= V_i(1-|A|e^{j\theta})sC_f\), impedance is shown as below

\[\begin{align} Z &= \frac{V_i}{I_i} \\ &= \frac{1}{(1-|A|e^{j\theta})j\omega C_f} \\ &= -\frac{j}{\omega C_f\frac{1+|A|^2-2|A|\cos\theta}{1-|A|\cos\theta}} + \frac{|A|\sin\theta}{\omega C_f (1+|A|^2-2|A|\cos\theta)} \\ \end{align}\]

\(C_\text{eq}\) and \(R_\text{eq}\) are obtained \[\begin{align} C_\text{eq} &= \frac{1+|A|^2-2A_r}{1-A_r}\cdot C_f \\ R_\text{eq} &= \frac{A_i}{1+|A|^2-2A_r}\cdot \frac{1}{\omega C_f} \end{align}\]

D/S small signal model

The Drain and Source of MOS are determined in DC operating point, i.e. large signal.

That is, top of \(M_2\) is drain and bottom is source, \[\begin{align} R_\text{eq2} &= \frac{r_\text{o2}+R_L}{1+g_\text{m2}r_\text{o2}} \\ & \simeq \frac{1}{g_\text{m2}} \end{align}\]

PMOS small signal model polarity

The small-signal models of NMOS and PMOS transistors are identical

A negative \(\Delta V_\text{GS}\) leads to a negative \(\Delta I_D\).

Recall that \(I_D\), in the direction shown here, is negative because the actual current of holes flows from the source to the drain.

Conversely, a positive \(\Delta V_\text{GS}\) produces a positive \(\Delta I_D\), as is the case for an NMOS device.

Leakage in MOS

• Subthreshold leakage
  • Drain-Induced Barrier Lowering (DIBL)
• Reverse-bias Source/Drain junction leakages
• Gate leakage
• two other leakage mechanisms
  • Gate Induced Drain Leakage (GIDL)
  • Punchthrough

W. M. Elgharbawy and M. A. Bayoumi, "Leakage sources and possible solutions in nanometer CMOS technologies," in IEEE Circuits and Systems Magazine, vol. 5, no. 4, pp. 6-17, Fourth Quarter 2005, doi: 10.1109/MCAS.2005.1550165.

X. Qi et al., "Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries," in IEEE Circuits and Devices Magazine, vol. 22, no. 5, pp. 39-47, Sept.-Oct. 2006, doi: 10.1109/MCD.2006.272999.

P. Monsurró, S. Pennisi, G. Scotti and A. Trifiletti, "Exploiting the Body of MOS Devices for High Performance Analog Design," in IEEE Circuits and Systems Magazine, vol. 11, no. 4, pp. 8-23, Fourthquarter 2011, doi: 10.1109/MCAS.2011.942751.

Andrea Baschirotto, ISSCC2015 "ADC Design in Scaled Technologies"

Joachim Assenmacher Infineon Technologies, "BSIM4 Modeling and Parameter Extraction" [https://ewh.ieee.org/r5/denver/sscs/References/2003_03_Assenmacher.pdf]

Stefan Rusu, Intel ISSCC 2008 Tutorial: "Leakage Reduction Techniques" [https://www.nishanchettri.com/isscc-slides/2008%20ISSCC/Tutorials/T06_Pres.pdf]

Drain-Induced Barrier Lowering (DIBL)

As a result of DIBL, threshold voltage is reduced with shorter channel lengths and, consequently, the subthreshold leakage current is increased

impact on output impedance

The principal impact of DIBL on circuit design is the degraded output impedance.

In short-channel devices, as \(V_{DS}\) increases further, drain-induced barrier lowering becomes significant, reducing the threshold voltage and increasing the drain current

Impact Ionization and GIDL are different, however both increase drain current, which flowing from the drain into the substrate

Gate induced drain leakage (GIDL)

The large current flows from the drain to bulk and this drain leakage current is named gate-induced drain leakage (GIDL) since it is due to a gate-induced high electric field present in the gate-to-drain overlap region

gate-induced drain leakage (GIDL) increases exponentially due to the reduced gate oxide thickness

Chauhan, Yogesh Singh, et al. FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press, 2015.

\[ \frac{g_m}{I_D} = \frac{2}{V_{GS}-V_{TH}} \] Decrease of gm/Id results from decrease in VT.

GIDL (Gate induced drain leakage) as at weak inversion may results in a weak lateral electric field causing leakage current between drain and bulk, which degrade the efficiency of the transistor (gm/ID).

[https://www.linkedin.com/posts/master-micro_mastermicro-mastermicro-adt-activity-7214549962833989632-ZoV_?utm_source=share&utm_medium=member_desktop]

Voltage Dependence

Temperature Dependence

In advanced node, gate leakage is also a strong function of temperature

signal detection circuit

phase I

\[\begin{align} Q_a &= (V_{a0} - 0.5*(V_{ip} + V_{im}))*C + (V_{a0} - V_{th})*C \\ Q_b &= (V_{b0} - 0.5*(V_{ip} + V_{im}))*C + V_{b0}*C \end{align}\]

Phase II

\[\begin{align} Q_a &= (V_{a} - V_{ip})*C + (V_{a} - V_{b})*0.5C \\ Q_b &= (V_{b} - V_{im})*C + (V_{b} - V_{a})*0.5C \end{align}\]

With the law of charge conservation, we get

\[\begin{equation} V_a - V_b = (V_{a0} - V_{b0}) + 0.5*(V_{ip} - V_{im} - V_{th}) \end{equation}\]

REF: D. A. Yokoyama-Martin et al., "A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS," IEEE Custom Integrated Circuits Conference 2006, 2006, pp. 401-404, doi: 10.1109/CICC.2006.320970.

Power/Ground and I/O Pins

Power / Ground Pin Information

In both digital and analog I/O, power and ground pins appear at the sub-circuit definiton, allowing user to use the I/O in voltage islands. They follow certain naming conventions.

1. digital I/O sub-circuit

• VDD: pre-driver core voltage (supplied by PVDD1CDGM)
• VSS: pre-driver ground and also global ground (supplied by PVDD1CDGM)
• VDDPST: I/O post-driver voltage, i.e. 1.8V (supplied by PVDD2CDGM or PVDD2POCM)
• VSSPOST: I/O post-driver ground (supplied by PVDD2CDGM or PVDD2POCM)
• POCCTRL: POCCTRL signal (supplied by PVDD2POCM)

2. analog I/O placed in a core voltage domain, the convention is

• TACVDD: analog core voltage (supplied by PVDD3ACM)
• TACVSS: analog core ground (supplied by PVDD3ACM)
• VSS: global core ground

3. analog I/O placed in an I/O voltage domain, the convention is:

• TAVDD: analog I/O voltage, i.e. 1.8V (supplied by PVDD3AM)
• TAVSS: analog I/O ground (supplied by PVDD3AM)
• VSS: global core ground

Power/Ground Combo Cells

Note for the retention mode

1. At initial state, IRTE must be 0 when VDD is off.
2. IRTE must be kept >= 10us after VDD turns on again (from the retention mode to the normal operation mode).
3. IRTE can be switched only when both VDD and VDDPST are on.

When the rention function is needed, IRTE signal must come from an "always-on" core power domain. If you don't need the rention function, it is required to tie IRTE to ground. In other words, no matter the rention feature is needed or not, it is required to have PCBRTE in each domain.

Note: PCBRTE does not need PAD connection.

Internal Pins

There are 3 internal global pins, i.e. ESD, POCCTRL, RTE, in all digital domain cells.

In real application,

• ESD pin is an internal signal and active in ESD event happening
• POCCTRL is an internal signal and active in Power-on-control event.

However, these special events (i.e. ESD event and Power-on-control event) are not modeled in NLDM kit (.lib), only normal function is covered, so ESD and POCCTRL pins are simply defined as ground in NLDM kit (.lib).

These 3 global pins will be connected automatically after cell-to-cell abutting in physical layout.

Power-Up sequence in Digital Domain

Power up the I/O power (VDDPST) first, then the core power (VDD)

1. PVDDD2POCM cell would generate Power-On-Control signal (POCCTRL) to have the post-driver NMOS and PMOS off, so that the crowbar current would not occur in the post-driver fingers when the I/O voltage is on while the core voltage remains off. As such, I/O cell would be in the Hi-Z state. when POCCTRL is on, the pll-up/down resistor is disabled and C is 0.
2. The POCCTRL signal is transmitted to I/O cells through cell abutment. There is no need to have routing for POCCTTRL nor give a control signal to the POCCTRL pin any of I/O cells. Note that the POCCTRL signal would be cut if inserting a power-cut (PRCUT) cell.

Power-Down sequence in Digital Domain

It's the reverse of power-up sequence.

Use model in Innovus

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set init_gnd_net "vss_core vss DUMMY_ESD DUMMY_POCCTRL"

addInst -moduleBased u_io -ori R270 -physical -status fixed -loc 135 994 -inst u_io/VDDIO_1 -cell PVDD2CDGM_H

addNet u_io_RTE
attachTerm FILLER_6 RTE u_io_RTE
attachTerm VDDIO_1 RTE u_right_RTE
setAttribute -skip_routing true -net u_io_RTE

clearGlobalNets
globalNetConnect DUMMY_POCCTRL -type pgpin -pin POCCTRL -singleInstance u_io/VDDDIO_1 -override
globalNetConnect DUMMY_ESD -type pgpin -pin ESD -singleInstance u_io/VDDDIO_1 -override

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set pins [get_object_name [get_ports *]]
foreach pin $pins {
	set netPtr [dbGetNetByName $pin]
	if { $netPtr == "0x0" } {
		puts "INFO: can't find the port: $pin"
	} else {
		setAttribute -net $pin -skip_routing true
	}
}

foreach net [get_object_name [get_nets -of_objects [get_pins */RTE -hierarchical]]] {
	setAttribute -net $net -skip_routing true
	dbSet [dbGetNetByName $net].dontTouch true
}

reference

The Analog Designer's Toolbox (ADT) | Invited Talk by IEEE Santa Clara Valley Section CAS Society, https://youtu.be/FT6kKC5OdE0

ESSCIRC2023 Circuit Insights Ali Sheikholeslami [https://youtu.be/2xFIZM5_FPw?si=XWwSzDgKWZGB0rX1]

Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 3 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 4, pp. 7-8, Fall 2018.

—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 2 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 3, pp. 7-8, Summer 2018.

—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 1 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 2, pp. 7-8, Spring 2018.

—, Circuit Intuitions: Miller's Approximation IEEE Solid-State Circuits Magazine, Vol. 7, Issue 4, pp. 7-8, Fall 2015.

—, Circuit Intuitions: Miller's Theorem IEEE Solid-State Circuits Magazine, Vol. 7, Issue 3, pp. 8-10, Summer 2015.

Shanthi Pavan, "Demystifying Linear Time Varying Circuits"

ecircuitcenter. Switched-Capacitor Resistor [http://www.ecircuitcenter.com/Circuits/SWCap/SWCap.htm]

Jørgen Andreas Michaelsen. INF4420 Switched-Capacitor Circuits. [https://www.uio.no/studier/emner/matnat/ifi/INF4420/v13/undervisningsmateriale/inf4420_v13_07_switchedcapacitor_print.pdf]

chembiyan T. OC Lecture 10: A very basic introduction to switched capacitor circuits [https://youtu.be/SaYtemYp4rQ?si=q2qovTKJrLy65pnu

Robert Bogdan Staszewski, Poras T. Balsara. "All‐Digital Frequency Synthesizer in Deep‐Submicron CMOS"

Mayank Parasrampuria, Sandeep Jain, Burn-in 101 [link]

Kevin Zheng. Circuit Artists [https://circuit-artists.com/posts/]

Terminology

The most accurate method to calculate the degradation of transistors is the SPICE-level simulation of the whole netlist with application programming interface (API) and industry-standard stress process models

​ MOSRA: MOSFET reliability analysis Synopsys

​ RelXpert: Cadence

​ TMI: TSMC Model Interface, TSMC

​ OMI: Open Model Interface, Si2 standard,

The Silicon Integration Initiative (Si2) Compact Model Coalition has released the Open Model Interface, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions.OMI allows circuit designers to simulate and analyze such important physical effects as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014.

• TDDB: Time-Dependent Dielectric Breakdown
• HCI: Hot Carrier injection
• BTI: Bias Temperature Instability
  • NBTI: Negative Bias Temperature Instability
  • PBTI: Positive Bias Temperature Instability
• SHE: Self-Heating Effect

Aging & SHE in FinFET

SHE

Self-Heating & EM

Heat Sink (HS)

1. guard ring

   closer OD help reduce dT

2. extended gate

3. source/drain metal stack

Bias Temperature Instability (BTI)

BTI occurs predominantly in PMOS (or p-type or p channel) transistors and causes an increase in the transistor's absolute threshold voltage.

Stress in the case of NBTI means that the PMOS transistor is in inversion; that means that its gate to body potential is substantially below 0 V for analogue circuits or at VGB = −VDD for digital circuits

Higher voltages and higher temperatures both have an exponential impact onto the degradation, induced by NBTI.

NBTI will be accelaerated with thinner gate oxide, at a high temperature and at a high electric field across the oxide region.

During recovery phase where the gate voltage of pMOS is high and stress is removed, the H atoms in the gate oxiede diffuse back to Si-SiO2 interface and the recombination of Si-H bonds reduces the threshold voltage of pMOS.

The net result is an increase in the magnitude of the device threshold voltage |Vt|, and a degradation of the channel carrier mobility.

Caution: The aging model provided by fab may NOT contain recovry effect

PBTI

Hot Carrier Degradation (HCI)

Short-channel MOSFETs may exprience high lateral electric fields if the drain-source voltage is large. while the average velocity of carriers saturate at high fields, the instantaneous velocity and hence the kinetic energy of the carriers continue to increase, especially as they accelerate toward the drain. These are called hot carriers.

In nanometer technologies, hot carrier effects have subsided. This is because the energy required to create an electron-hole pair, \(E_g \simeq 1.12 eV\), is simply not available if the supply voltage is around 1V.

\[ F_E= E \cdot q \]

\[\begin{align} E_k &= F_E \cdot s \\ &= E \cdot q \cdot s \end{align}\]

Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, degrading the current-voltage characteristics of the MOSFET.

The channel hot-electron (CHE) effect is caused by electons flowing in the channel region, from the source to the drain. This effect is more pronounced at large drain-to-source voltage, at which the lateral electric field in the drain end of the channel accelerates the electrons.

Four different hot carrier injectoin mechanisms can be distinguished: - channel hot electron (CHE) injection - drain avalanche hot carrier (DAHC) injection - secondary generated hot electron (SGHE) injection - substrate hot electron (SHE) injection

HCI is more of a drain-localized mechanism, and is primarily a carrier mobility degradation (and a Vt degradation if the device is operated bi-directionally).

For smaller transistor dimensions, CHE dominates the hot carrier degradation effect

The hot-carrier induced damage in nMOS transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both.

The damage caused by hot-carrier injection affects the transistor characteristics by causing a degradation in transconductance, a shift in the threshold voltage, and a general decrease in the drain current capability.

HCI seems to have just a weak temperature dependency. Unlike BTI, it seems to be no or just little recovery. As holes are much "cooler" (i.e. heavier) than electrons, the channel hot carrier effect in nMOS devices is shown to be more significant than in pMOS devices.

Degradation saturation effect

HCI model can reproduce the saturation effect if stress time is long enough

Gate Oxide Integrity (GOI)

Time dependent dielectric breakdown (TDDB)

Scaling drive more concerns in TDDB

M. A. Alam, ECE 695A Reliability Physics of Nanotransistors [link], [https://nanohub.org/resources/17208/download/2013.03.01-ECE695A-L21.pdf]

K. Yang, R. Zhang, T. Liu, D. -H. Kim and L. Milor, "Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology," 2018 Conference on Design of Circuits and Integrated Systems (DCIS), Lyon, France, 2018 [https://par.nsf.gov/servlets/purl/10104486]

waveform-dependent nature

The figure below illustrates the waveform-dependent nature of these mechanisms – as described earlier, BTI and HCI depend upon the region of active device operation. The slew rate of the circuit inputs and output will have a significant impact upon these mechanisms, especially HCI.

• Negative bias temperature instability (NBTI). This is caused by constant electric fields degrading the dielectric, which in turn causes the threshold voltage of the transistor to degrade. That leads to lower switching speeds. This effect depends on the activity level of the circuits, with heavier impact on parts of the design that don’t switch as often, such as gated clocks, control logic, and reset, programming and test circuitry.
• Hot carrier injection (HCI). This is caused by fast-moving electrons inserting themselves into the gate and degrading performance. It primarily occurs on higher-voltage modes and fast switching signals.

• longer channel length help both BTI and HCI
• larger \(V_{ds}\) help BTI, but hurt HCI
• lower temperature help BTI of core device, but hurt that of IO device for 7nm FinFET

MOSRA

MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age analysis

TMI

BTI recovery effect NOT included for N7

Stochastic Nature of Reliability Mechanisms

A fraction of devices will fail

Circuit Simulations

Heat transfer, thermal resistance

Burn-in & High-temperature operating life (HTOL)

• HTOL:
  • characterization test
  • characterize the life expectancy
• Burn-in:
  • production test
  • weed out defective products

HTOL and Burn-in Testing capture the two ends of the reliability characterization graph known as the "bathtub curve"

[https://arworld.us/the-importance-of-htol-and-burn-in-testing-methods/]

reference

Phillip Allen. Reliability of Analog Circuits [https://aicdesign.org/wp-content/uploads/2021/04/Reliability_Theory210224-1.pdf]

M. A. Alam. ECE 695A Reliability Physics of Nanotransistors [https://nanohub.org/groups/ece695alam]

Tanya Nigam and Andreas Kerber. Global Foundaries. CICC2014 Session 15 - Challenges for Analog Nanoscale Technologies: Reliability challenges and modeling of HK MG Technologies

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out - Analog/Custom Design (Analog/Custom design) - Cadence Blogs - Cadence Community https://shar.es/afd31p

S. Liao, C. Huang, and A. C. J. X. T. Guo, "New Generation Reliability Model," Dec 2016. [Online]. Available: http://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf. [Accessed Aug 2018]

Tianlei Guo, Jushan Xie, "A Complete Reliability Solution: Reliability Modeling, Applications, and Integration in Analog Design Environment" [https://mos-ak.org/beijing_2018/presentations/Tianlei_Guo_MOS-AK_Beijing_2018.pdf]

FinFET Reliability Analysis with Device Self-Heating via @DanielNenni https://semiwiki.com/eda/synopsys/5085-finfet-reliability-analysis-with-device-self-heating/

Chris Changze Liu 刘长泽,Hisilicon, Huawei, "Reliability Challenges in Advanced Technology Node" https://www.tek.com.cn/sites/default/files/2018-09/reliability-challenges-in-advanced-technology-node.pdf

Ben Kaczer, imec. FEOL reliability: from essentials to advanced and emerging devices and circuits. 2016 IRPS Tutorial

Ben Kaczer, imec. Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation. 2016 IEDM 2016 [link]

Kang, Sung-Mo Steve, Yusuf Leblebici and Chulwoo Kim. “CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition.” (2014).

Behzad Razavi. "Design of Analog CMOS Integrated Circuits" (2016)

Basel Halak. Ageing of Integrated Circuits : Causes, Effects and Mitigation Techniques. Cham, Switzerland: Springer, 2020. ‌

Elie Maricau, and Georges Gielen. Analog IC Reliability in Nanometer CMOS. Springer Science & Business Media, 2013. ‌

Transistor Aging Intensifies At 10/7nm And Below https://semiengineering.com/transistor-aging-intensifies-10nm/

Modeling Effects of Dynamic BTI Degradation on Analog and Mixed-Signal CMOS Circuits. MOS-AK/GSA Workshop, April 11-12, 2013, Munich https://www.mos-ak.org/munich_2013/presentations/05_Leonhard_Heiss_MOS-AK_Munich_2013.pdf

Challenges and Solutions in Modeling and Simulation of Device Self-heating, Reliability Aging and Statistical Variability Effects https://www.mos-ak.org/beijing_2018/presentations/Dehuang_Wu_MOS-AK_Beijing_2018.pdf

New Generation Reliability Model https://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf

FinFET SPICE Modeling: Synopsys Solutions to Simulation Challenges of Advanced Technology Nodes https://www.mos-ak.org/washington_dc_2015/presentations/T03_Joddy_Wang_MOS-AK_Washington_DC_2015.pdf

A. Zhang et al., "Reliability variability simulation methodology for IC design: An EDA perspective," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2015, pp. 11.5.1-11.5.4, doi: 10.1109/IEDM.2015.7409677.

W. -K. Lee et al., "Unifying self-heating and aging simulations with TMI2," 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan, 2014, pp. 333-336, doi: 10.1109/SISPAD.2014.6931631.

Aging and Self-Heating in FinFETs - Breakfast Bytes - Cadence Blogs - Cadence Community https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/aging-and-self-heating

Article (20482350) Title: Measure the Impact of Aging in Spectre Technology URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESBFUA4

Karimi, Naghmeh, Thorben Moos and Amir Moradi. “Exploring the Effect of Device Aging on Static Power Analysis Attacks.” IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (2019): 233-256.[link]

Self-Heating Issues Spread https://semiengineering.com/self-heating-issues-spread/

Y. Zhao and Y. Qu, "Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 829-836, 2019, doi: 10.1109/JEDS.2019.2911085.

Wafer Acceptance Test (WAT)

温德通. 集成电路制造工艺与工程应用. 机械工业出版社 2018

Wafer acceptance testing (WAT) also known as Process Control Monitoring (PCM)

Vtgm & Vtlin

Parameter Definition:

\[\begin{align} I_{\text{D,lin}} &= I_D \mid _{V_G=V_{DD},V_D=0.05V} \\ I_{\text{D,sat}} &= I_D \mid _{V_G=V_D=V_{DD}} \\ V_{\text{t,lin}} &= V_G \mid _{I_D=I_{\text{thx}}\cdot \frac{W}{L}@\{V_D=0.05V\}} \end{align}\]

\(I_{\text{thx}}\) could be different for technologies. (For N16, \(I_{\text{thx}}=10\)nA)

[Inspect 4. Extracting Standard Parameters]

Constant Current Threshold Voltage	gm-Maximum Method

IC-CAP 2011.01 - Target Modeling [https://edadownload.software.keysight.com/eedl/iccap/2011_01/pdf/target.pdf]

Short Lg Stackgate

TSMC. VLSI2025 JFS2-1: Analog Cells DTCO (Design and Technology Co-Optimization) and Their Impact on Advanced Node CMOS Analog/MixedSignal Circuits

smaller W*L*M, X*Y for same mismatch with short Lg stackgate

N7/N5 4-fin Grid Rule

Same Fin1/Fin3 or Fin2/Fin4 Fin Position

note W/L is different \(12/(135*2) \lt 6/(8*8)\)

Current Density (EM)

Interconnect Resistance Evolution

White Paper: Microelectronics/Semiconductor Research Community Virtual Workshop 2022 [https://nnci.net/sites/default/files/inline-files/Microelectronics%202022%20Workshop%20Report%20with%20Slides.pdf]

Copper Pillar Bump vs Solder bump

Cu-pillar bumping is a next-generation flip chip interconnection between chip & packages, especially for fine pitch applications

• On the wafer end, comparing to solder bump, cu-pillar bump provides the advantage of fine pitch; the die size can be reduced about 5~10%.

• On the package end, the substrate layer can be reduced from 6 layers to 4 layers by fine pitch and bump on trace process and using simplified substrate process.

Why Your Symmetric Layouts Are Showing Mismatches in SPICE Simulations

[https://www.ansys.com/blog/symmetric-layouts-showing-mismatches-spice-simulations]

The root cause of the delay mismatch is related to how parasitic extraction tools distribute coupling capacitances over the nodes of the resistive networks

The most likely reason for such asymmetry is the anisotropy of computational geometry algorithms used by extraction tools.

STRAP

A "strap" refers to a low-impedance connection

NWDMY = NWDMY1, NWDMY2

STRAP = NWSTRAP or PWSTRAP

NWSTRAP = {NP & OD} & {NW not {NW INTERACT NWDMY}}

PWSTRAP = {PP & OD} not NW

Calibre Rule::NOT

Calibre Rule::INTERACT

Antenna Effect

The antenna effect is a common name for the effects of charge accumulation in isolated nodes of an integrated circuit during its processing

This effect is also sometimes called "Plasma Induced Damage", "Process Induced Damage" (PID) or "charging effect"

This accumulation of charge is usually, and misleadingly, called the antenna effect.

antenna ratio

During manufacture, if part of the metal wiring is connected to the gate, but not a diffusion contact, this "floating" metal collects charge from the plasma.

Manufacturing rules for the antenna effect are usually expressed as the ratio of the area of floating metal (i.e. charge collection area) to the area of the gate.

To prevent the antenna effect from destroying your circuit you need to reduce the floating metal/gate area ratio or give the charge a safe way to dissipate to the ground before it can build up and cause damage

metal jumping (bridging, metal hopping)

Long metal can be taken to higher metal routing layer, which is known as metal jumping.

This metal jumping is usually done near the gate, which will mean that there is a full connection to the diffusion contact before the area of floating metal becomes too large

The jumper is constructed so that the long track is only connected to the gate once it has also been connected to a diffusion contact, which then allows the charge to dissipate through diffusion to the substrate

Diode Insertion

Diode helps dissipate charges accumulated on metal. Diode should be placed as near as possible to the gate of device on low level of metal.

In the reverse bias region, the reverse saturation current of Si and Ge diodes doubles for every \(10 ^oC\) rise in temperature

pulsic.com, Analog layout – Stop the antenna effect from destroying your circuit [link]

Prof. Adam Teman, Digital VLSI Design. Lecture-10-The-Manufacturing-Process [pdf]

Zongjian Chen, Processing and Reliability Issues That Impact Design Practice. [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/lect_15_2up.pdf]

Shallow Trench Isolation (STI)

Voltage-Dependent DRC

In T* DRC deck, it is based on the voltage recognition CAD layer and net connection to calculate the voltage difference between two neighboring nets by the following formula:

\[ \Delta V = \max(V_H(\text{net1})-V_L(\text{net2}), V_H(\text{net2})-V_L(\text{net1})) \]

where \[ V_H(\text{netx}) = \max(V(\text{netx})) \] and \[ V_L(\text{netx}) = \min(V(\text{netx})) \]

• The \(\Delta V\) will be 0 if two nets are connected as same potential
• If \(V_L \gt V_H\) on a net, DRC will report warning on this net

Voltage recognition CAD Layer

Automate those voltage-dependent DRC checks! - siemens

Two method

1. voltage text layer

   You place specific voltage text on specific drawing layer

2. voltage marker layer

   Each voltage marker layer represent different voltage for specific drawing layer

voltage text layer has higher priority than voltage marker layer and is recommended

voltage text layer

For example M3

where 63 is layer number, 110 ~ 113 is datatype

voltage marker layer

Different data type represent different voltage, like

Example

drain & source sharing

Planar process vs. FinFet process

Standard Cell Tapcell

Guard Ring in Custom block

Place well tie and substrate tie where they are needed. Redundant guard ring consume area and increase the routing of critical signal net.

Continuous OD

Performance & Matching

current mirror

split diffusion with dummy transistors

cascode structure

off transistor split diffusion

sharing source & drain

Stacked MOSFETs

LDE (Layout Dependent Effects)

Vladimír Stejskal, Jiří Slezák March, 2016. LOD Effect: Modeling and Implementation [https://www.mos-ak.org/dresden_2016/presentations/T5_Stejskal_MOS-AK_Dresden_2016.pdf]

John Faricelli – April 16, 2009. Layout-Dependent Proximity Effects in Deep Nanoscale CMOS [https://ewh.ieee.org/r5/denver/sscs/Presentations/2009_04_Faricelli.pdf]

吉富貞幸. 2021年7月29日. 高周波RFCMOS回路を実現する半導体素子のコンパクトモデリング技術 [https://kobaweb.ei.st.gunma-u.ac.jp/lecture/20210729_analog_KIOXIA_Yoshitomi.pdf]

Kanamoto, Toshiki, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe and Masanori Hashimoto. “Impact of well edge proximity effect on timing.” ESSDERC 2007 - 37th European Solid State Device Research Conference (2007)

J. V. Faricelli, "Layout-dependent proximity effects in deep nanoscale CMOS," IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, USA, 2010 [https://sci-hub.se/10.1109/CICC.2010.5617407]

Aleksandr Sidun, Layout-dependent effects (LOD, WPE, Latch-up, Electromigration, Antenna) [https://analoghub.ie/category/Layout/article/layoutDependentEffects]

Length of Diffusion (LOD)

Shallow Trench Isolation Stress

LOD key points:

• LOD is the result of the STI formation (Shallow trench isolation);
• STI becomes compressive as the wafer cools down;
• The width of STI (active to active spacing) has a strong impact on determining stress;
• LOD improves holes mobility and decreases electron mobility.

Stress has been more effective for PMOS

• This has caused beta (N/P) ratio to fall to about unity at 7nm

LOD effect can be prevented by distancing devices away from the WELL edge (guard ring). This is usually done by placing dummy devices around the circuit devices, in which case your circuit devices will also benefit from the equal edge effects (each device will have the same neighbours).

Well Proximity Effect (WPE)

Since the well implant dopant (acceptor or donor) is the same type as the channel implant dopant, the additional doping increases the absolute value of the threshold voltage (VT) of both NMOS and PMOS devices

Gate Cut Stress LDE

Metal Boundary Effect (MBE)

M. Hamaguchi et al., "New layout dependency in high-k/Metal Gate MOSFETs," 2011 International Electron Devices Meeting, Washington, DC, USA, 2011 [https://sci-hub.st/10.1109/IEDM.2011.6131614]

Alvin Loke. 2016 VLSI Circuits Short Courses – 2.2 Migrating Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm [pdf]

Gate = (ALD MG stack to set \(\Phi_M\))+(metal fill to reduce RG)

Matching

Aleksandr Sidun. Matching patterns in layout [https://analoghub.ie/category/Layout/article/layoutMatchingPatterns]

—. Matching in layout [https://analoghub.ie/category/Layout/article/layoutMatching]

Interdigitation

Interdigitation provides good matching properties against 1D-gradients and is suitable for the simple circuits

The main concept is that you should create an imaginary center line and place your devices symmetrically, relative to this line. The simplest example of that is so called "ABBA" pattern

Interdigitation reduces the device mismatch as it suffers equally from process variations in X dimension. This technique was used to layout current mirrors and resistors in PTAT and BGR circuits.

Common Centroid

Common Centroid provides better matching for 2D gradients, which is critical for the large arrays and advanced (below 28nm) nodes

The main idea behind common centroid is that we make our array symmetrical of the common centre. In other words, the array should be symmetrical in both X- and Y- axes

The common centroid technique describes that if there are n blocks which are to be matched then the blocks are arranged symmetrically around the common centre at equal distances from the centre. This technique offers best matching for devices as it helps in avoiding cross-chip gradients

Design with FinFETs

Mark Williams. Stacked MOSFETs in Analog Layout [https://community.cadence.com/cadence_blogs_8/b/cic/posts/stacked-mosfets-in-analog-layout]

Modeling Consideration

\[\begin{align} R_{d1} &\propto \frac{1}{N_{fins}} \\ R_{s1} &\propto \frac{1}{N_{fins}} \\ R_{g1} &\propto N_{fins} \\ C_{gd} &\propto N_{fins} \cdot N_{fingers} \cdot N_{multipler} \\ C_{gs} &= Cgd \\ C_{g1d} &\propto N_{fins} \\ C_{g1s} &= C_{g1d} \\ C_{g1d1} &\propto N_{fins} \\ C_{g1s1} &= C_{g1d1} \\ C_{g1d1} &\simeq 2\times C_{g1d} \end{align}\]

PODE & CPODE

The PODE devices is extracted as parasitic devices in post-layout netlist

DDB is the PODE (Poly on OD/Diffusion Edge) in TSMC 16FFC process.

SDB is the CPODE (Common Poly on Diffusion Edge) in TSMC 16FFC process.

PO on OD edge (PODE) is a must and to define GATE that abuts OD vertical edge

CPODE is used to connect two PODE cells together. It will isolate OD to save 1 poly pitch, via STI; Additional mask (12N) is required for manufacture

Leading Edge Logic Comparison March 9, 2018 [https://semiwiki.com/wp-content/uploads/2018/03/Leading-Edge-Logic.pdf]

What is CPODE, and why do we use it in VLSI layout? [https://semiconwiki.com/what-is-cpode-and-why-do-we-use-it-in-vlsi-layout/]

3T PODE device

US9053283B2: Methods for layout verification for polysilicon cell edge structures in finFET standard cells using filters [https://patentimages.storage.googleapis.com/36/2c/ff/ad3d4c232ecc8d/US9053283.pdf]

US8943455B2: Methods for layout verification for polysilicon cell edge structures in FinFET standard cells [https://patentimages.storage.googleapis.com/19/12/64/f2badfdc09a4a4/US8943455.pdf]

CNOD

continuous oxide diffusion (CNOD) design

In CNOD, the diffusion is not broken at all. The fabrication process continues normally, but when standard cells need to be separated, the gate between them is designated as a dummy gate. This dummy gate is then connected to a Gate Tie-Down Via to the power rail

This dummy gate tie-down method of CNOD achieves the same horizontal width savings as SDB, and has the advantage of keeping the transistor diffusion unbroken and thus can achieve more uniform strain and performance characteristics

The TRUTH of TSMC 5nm [https://www.angstronomics.com/p/the-truth-of-tsmc-5nm]

S. Badel et al., "Chip Variability Mitigation through Continuous Diffusion Enabled by EUV and Self-Aligned Gate Contact," 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, China, 2018 [https://sci-hub.st/10.1109/ICSICT.2018.8565694]

4T MPODE (with source/drain) may be formed in CNOD design layout

potential leakage: channel leakage (S to D); junction leakage (S/D to bulk)

CNOD (MPODE) is same with primitive MOS model; PODE is the primitive MOS, just S/D shorted together

Contacted-Poly-Pitch (CPP)

Wider Contacted-Poly-Pitch allows wider MD and VD size, which help reduce MEOL IRdrop

Naoto Horiguchi. Entering the Nanosheet Transistor Era [link]

SAC & SAGC

self-aligned diffusion contacts (SACs)

As shown in Fig. 35 in older planar technology nodes, gate pitch is so relaxed such that S/D contacts and gate contacts can easily be placed next to each other without causing any shorting risk (see Fig. 35(a)).

As the gate pitch scales, there’s no room to put gate contacts next to S/D contacts, and gatecontacts have been pushed away from the active region and are only placed on the STI region.

In addition, at tight gate pitch, even forming S/D contact without shorting to gate metal becomes very challenging.

The idea of self-aligned contacts (SAC) has been introduced to mitigate the issue of S/D contact to gate shorts.

As shown in Fig. 35(b), the gate metal is fully encapsulated by a dielectric spacer and gate cap, which protects the gate from shorting to the S/D contact.

A dielectric cap is added on top of the gate so that if the contact overlaps the gate, no short occurs.

MD layer represent SACs in PDK

self-aligned gate contacts (SAGCs)

Self-aligned gate contacts (SAGCs) have also been implemented and Denser standard cells can be achieved by eliminating the need to land contacts on the gate outside the active area.

SAGCs require the source/drain contacts to be capped with an insulator that is different from both contact and gate cap dielectrics to protect the source/drain contacts against a misaligned gate contact etch.

According to the DRC of T foundary, poly extension > 0 um and space between MP and OD > 0 um., which demonstrate self-aligned gate contact is not introduced.

Gate Resistance

Native NMOS Blocked Implant (NT_N)

Principles of VLSI Design CMOS Processing CMPE 413 [https://redirect.cs.umbc.edu/~cpatel2/links/315/lectures/chap3_lect09_processing2.pdf]

CMOS processing [http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf]

The Fabrication Process of CMOS Transistor [https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/#:~:text=latch%2Dup%20susceptibility.-,N%2D%20well%2F%20P%2D%20well%20Technology,well%20it%20is%20vice%2D%20verse.]

CMOS Processing Technology [link1, link2]

A native layer (NT_N) is usually added under inductors or transformers in the nanoscale CMOS to define the non-doped high-resistance region of substrate, which decreases eddy currents in the substrate thus maintaining high Q of the coils.

For T* PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy currents

OD inside NT_N only can be used for NT_N potential pickup purpose, such as the guarding-ring of MOM and inductor

Derived Geometries

NP: N+ Source/Drain Ion Implantation

PP: P+ Source/Drain Ion Implantation

OD: Gate Oxide and Diffustion

NW: N-WELL

PW: P-WELL

CMOS Processing Technology

Four main CMOS technologies:

• n-well process
• p-well process
• twin-tub process
• silicon on insulator

Triple well, Deep N-Well (optional):

• NWell: NMOS svt, lvt, ulvt ...
• PWell: PMOS svt, lvt, ulvt ...
• DNW: For isolating P-Well from the substrate

The NT_N drawn layer adds no process cost and no extra mask

The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.

The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.

Deep N-well

Chew, K.W., Zhang, J., Shao, K., Loh, W., & Chu, S.F. (2002). Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration. 32nd European Solid-State Device Research Conference, 251-254. URL:[slides, paper]

Mark Waller, Analog layout: Why wells, taps, and guard rings are crucial

KEITH SABINE Using Deep N Wells in Analog Design

Faricelli, J. (2010). Layout-dependent proximity effects in deep nanoscale CMOS. IEEE Custom Integrated Circuits Conference 2010, 1-8.

cmos_processing, URL:http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf

Kuo-Tsai LiPaul ChangAndy Chang, TSMC, US20120053923A1, "Methods of designing integrated circuits and systems thereof"

Substrate noise

A variety of techniques can be used to minimize this noise, for example by keeping analog devices surrounded by guard rings, or using a separate supply for the substrate/well taps.

However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

PMOS are less noisy than NMOS since PMOS has its nwell which isolates the substrate noise, but such is not valid for NMOS .

DNW

The N-channel devices built directly into the P-type substrate are not as effectively isolated as P-channel devices in their N-wells. This is because despite creating a P+ guard ring around the devices, there remains an electrical path below the guard ring for charge to flow.

To overcome this issue, a deep N-well can be used to more effectively isolate these N-channel devices.

pwdnw: PW/DNW diode

dnwpsub: DNW/PSUB diode

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

• the P-well is separated, allowing the voltage to be controlled
• because the circuit within the deep N-well is separated from the p-substrate in this structure, there is the benefit that this circuitry is less susceptible to noise that propagates through the p-substrate.

Decap

Kevin Zheng. The Unsung Heroes – Dummies, Decaps, and More [https://circuit-artists.com/the-unsung-heroes-dummies-decaps-and-more/]

The Difference Between MOM, MIM, and MOS Capacitors [https://www.ansys.com/blog/difference-between-mom-mim-mos-capacitor]

MIM/MOM capacitor extraction boosts analog and RF designs [https://www.eeworldonline.com/mim-mom-capacitor-extraction-boosts-analog-and-rf-designs/]

Metal Resistors In Wire Management

Kevin Zheng. Metal Resistors – Your Unexpected Friend In Wire Management [https://circuit-artists.com/metal-resistors-your-unexpected-friend-in-wire-management/]

reference

Mikael Sahrling, Layout Techniques for Integrated Circuit Designers 1st Edition , Artech House 2022

LAYOUT, EE6350 VLSI Design Lab SMART TEMPERATURE SENSOR URL: https://www.ee.columbia.edu/~kinget/EE6350_S16/06_TEMPSENS_Sukanya_Vani/layout.html

Stacked MOSFETs in analog layout https://pulsic.com/stacked-mosfets-in-analog-layout/

JED Hurwitz, ISSCC2011 "T4: Layout: The other half of Nanometer CMOS Analog Design" [slides, transcript]

Tom Quan, TSMC, Bob Lefferts, Fred Sendig, Synopsys, Custom Design with FinFETs - Best practices designing mixed-signal IP

Jacob, Ajey & Xie, Ruilong & Sung, Min & Liebmann, Lars & Lee, Rinus & Taylor, Bill. (2017). Scaling Challenges for Advanced CMOS Devices. International Journal of High Speed Electronics and Systems. 26. 1740001. 10.1142/S0129156417400018.

Joddy Wang, Synopsys "FinFET SPICE Modeling" Modeling of Systems and Parameter Extraction Working Group 8th International MOS-AK Workshop (co-located with the IEDM Conference and CMC Meeting) Washington DC, December 9 2015

A. L. S. Loke et al., "Analog/mixed-signal design challenges in 7-nm CMOS and beyond," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-8, doi: 10.1109/CICC.2018.8357060.[slides]

Prof. Adam Teman, Advanced Process Technologies, [pdf]

Luke Collins. FinFET variability issues challenge advantages of new process [link]

Loke, Alvin. (2020). FinFET technology considerations for circuit design (invited short course). BCICTS 2020 Monterey, CA

Alvin Leng Sun Loke, TSMC. Device and Physical Design Considerations for Circuits in FinFET Technology", ISSCC 2020

A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

A. L. S. Loke, Migrating Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm. 2016 Symposia on VLSI Technology and Circuits

Lattice Semiconductor, 16FFC Process Technology Introduction December 9th, 2021[pdf]

藍色天空. 匹配那些事儿… [https://www.kaixinspace.com/matching/]

Subthreshold Conduction

By square-law, the Eq \(g_m = \sqrt{2\mu C_{ox}\frac{W}{L}I_D}\), it is possible to obtain a higer transconductance by increasing \(W\) while maintaining \(I_D\) constant. However, if \(W\) increases while \(I_D\) remains constant, then \(V_{GS} \to V_{TH}\) and device enters the subthreshold region. \[ I_D = I_0\exp \frac{V_{GS}}{\xi V_T} \]

where \(I_0\) is proportional to \(W/L\), \(\xi \gt 1\) is a nonideality factor, and \(V_T = kT/q\)

As a result, the transconductance in subthreshold region is \[ g_m = \frac{I_D}{\xi V_T} \]

which is \(g_m \propto I_D\)

PTAT with subthreshold MOS

MOS working in the weak inversion region ("subthreshold conduction") have the similar characteristics to BJTs and diodes, since the effect of diffusion current becomes more significant than that of drift current

Hongprasit, Saweth, Worawat Sa-ngiamvibool and Apinan Aurasopon. "Design of Bandgap Core and Startup Circuits for All CMOS Bandgap Voltage Reference." Przegląd Elektrotechniczny (2012): 277-280.

Curvature Compensation

VBE

In advanced node, N4P, \(V_{BE}\) is about -1.45mV/K

Assuming \(I_C\) is constant

Assuming \(I_C\) is PTAT, \(I_C = (V_T \ln n) / R_3\)

The first-order linear temperature dependence term of \(V_{BE}\) can be eliminated with IPTAT. \(V_T(\eta - \theta)\ln)T/T_r\) is the high-order nonlinear temperature-dependent term of \(V_{BE}\), which requires high-order curvature compensation

G. Zhu, Y. Yang and Q. Zhang, "A 4.6-ppm/°C High-Order Curvature Compensated Bandgap Reference for BMIC," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 9, pp. 1492-1496, Sept. 2019 [https://sci-hub.se/10.1109/TCSII.2018.2889808]

X. Fu, D. M. Colombo, Y. Yin and K. El-Sankary, "Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference," in IEEE Access, vol. 10, pp. 110970-110982, 2022 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9923910]

Tutorials | 08012023 | 1.2.1 Bandgap Voltage Regular [https://youtu.be/dz067SOX0XQ&t=6362]

temperature coefficient

The parameter that shows the dependence of the reference voltage on temperature variation is called the temperature coefficient and is defined as: \[ TC_F=\frac{1}{V_{\text{REF}}}\left[ \frac{V_{\text{max}}-V_{\text{min}}}{T_{\text{max}}-T_{\text{min}}} \right]\times10^6\;ppm/^oC \]

Choice of n

classic bandgap reference

\[ V_{bg} = \frac{\Delta V_{be}}{R_1} (R_1+R_2) + V_{be2} = \frac{\Delta V_{be}}{R_1} R_2 + V_{be1} \]

\[ V_{bg} = \left(\frac{\Delta V_{be}}{R_1} + \frac{V_{be1}}{R_2}\right)R_3 = \left(\frac{\Delta V_{be}}{R_1} R_2 + V_{be1}\right)\frac{R_3}{R_2} \]

OTA offset effect

\[\begin{align} V_{be1} &= \frac{kT}{q}\ln(\frac{I_{e1}}{I_{ss}}) \\ V_{be2} &= \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \end{align}\]

Here, we assume \(I_e = I_c\)

Hence,

\[\begin{align} \Delta V_{be} &= \frac{kT}{q}\ln(n\frac{I_{e1}}{I_{e2}}) \\ &= \frac{kT}{q}\ln(n) + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \\ &= \Delta V_{be,0} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \end{align}\]

Therefore,

\[\begin{align} V_{bg} &= \frac{\Delta V_{be}+V_{os}}{R_2}(R_1+R_2) + V_{be2} \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}})+\frac{kT}{q}\ln(\frac{I_{e2}}{I_{e2,0}}) \end{align}\]

We omit the last part \[\begin{align} V_{bg} &\approx \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + V_{be2,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \\ &= V_{bg,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \end{align}\]

i.e. the bg variation due to OTA offset \[ \Delta V_{bg} \approx \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \]

• \(V_{os} \gt 0\)

  ​ \(I_{e1} \gt I_{e2}\): \(\Delta V_{bg} \gt \alpha V_{os}\)

• \(V_{os} \lt 0\)

  ​ \(I_{e1} \lt I_{e2}\): \(\Delta V_{bg} \lt \alpha V_{os}\)

OTA with chopper

\(I_{e1}\), \(I_{e2}\)

\[\begin{align} V_{ip} &= V_{im} + V_{os} \\ \frac{V_{bg}-V_{ip}}{R_2} &= I_{e2} \\ \frac{V_{bg}-V_{im}}{R_2} &= I_{e1} \\ V_{ip} &= I_{e2}R_1 + V_T\frac{I_{e2}}{nI_S} \\ V_{im} &= V_T\frac{I_{e1}}{I_S} \end{align}\] where \(V_T = \frac{kT}{q}\)

we obtain \[ I_{e1} = \frac{V_T\ln n}{R_1} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) - \frac{1}{R_1}\cdot V_T\ln\left(1- \frac{V_{os}}{R_2I_{e1}} \right) \]

we omit the last part \[\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) \\ I_{e2} &= I_{e1} - \frac{V_{os}}{R_2} = I_{e0} + \frac{V_{os}}{R_1} \end{align}\] where \(I_{e0} = \frac{\Delta V_{be}}{R_1}\), \(\Delta V_{be}=V_T\ln n\)

That is, both \(I_{e1}\) and \(I_{e2}\) are proportional to \(V_{os}\)

\(I_{e1}\) and \(I_{e2}\) can be expressed as \[\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) + \frac{V_{os}}{2R_2} \\ I_{e2} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) - \frac{V_{os}}{2R_2} \end{align}\] i.e., \(\Delta I_{e,cm} = V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right)\) and \(\Delta I_{e,dif} =\frac{V_{os}}{2R_2}\)

bandgap output voltage is

\[\begin{align} V_{bg} &= V_T \ln \frac{I_{e1}}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e0}R_2 + V_{os}\frac{R_1+R_2}{R_1} \\ &= I_{e0}R_2 + V_T \ln \frac{I_{e0}}{I_s} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \\ &= V_{bg0} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \end{align}\]

Therefore, the averaged output of bandgap

\[ V_{bg,avg} = V_{bg0} +\frac{1}{2}V_T\ln\left(1-\frac{V_{os}^2\left(\frac{1}{R_1} + \frac{1}{R_2} \right)^2}{I_{e0}^2} \right) \lt V_{bg0} \]

\(V_{bg,avg} \lt V_{bg0}\) due to nonlinearity of BJT

reference

ECEN 607 (ESS) Bandgap Reference: Basics URL:https://people.engr.tamu.edu/s-sanchez/607%20Lect%204%20Bandgap-2009.pdf

CICC 2023 Session 12: Forum: Recent Progress in LDOs and Voltage, Current, and Timing References

• Jae-Yoon Sim, POSTECH. 12-2: Design of Ultra-low-power Bandgap Reference Circuits
• Inhee Lee, University of Pittsburgh. 12-3: Sub-μW Non-Bandgap Voltage References

MOS capacitances

• oxide capacitance (aka gate-channel capacitance) between the gate and the channel \(C_1=WLC_{ox}\)
  • divided between \(C_{GS}\) and \(C_{GD}\)
• depletion capacitance between the channel and the substrate \(C_2\)
• overlap capacitance: direct overlap and fringing field
• junction capacitance between the source/drain areas and the substrate
  • The value of \(C_{SB}\) and \(C_{DB}\) is a function of the source and drain voltages with respect to the substrate

The gate-bulk capacitance is usually neglected in the triode and saturation regions because the inversion layer acts as a "shield" between the gate and the bulk.

classification with Intrinsic and Extrinsic MOS capacitor

[Circuit Insights - 11-CI: Fundamentals 4 Tsinghua Nan Sun]

FinFET Parasitic Fringing Capacitance

Temperature Dependence of Junction Diode CV

where TCJ and TCJSW are positive

https://cmosedu.com/cmos1/BSIM4_manual.pdf

Integrated varactors

D=S=B varactor

Inversion-mode (I-MOS)

Accumulation-mode (A-MOS)

NMOS in NWELL, aka NMOS in N-Well varactor

Notice: S/D and NWELL are connected togethor in layout

I-MOS vs . A-MOS

P. Andreani and S. Mattisson, "On the use of MOS varactors in RF VCOs," in IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000 [https://sci-hub.se/10.1109/4.845194]

varactor losses

channel resistance & gate resistance

PDK varactor

nmoscap: NMOS in N-Well varactor

• Base Band MOSCAP model (nmoscap) is built without effective series resistance (ESR) and effective series inductance (ESL) calibrations, which is for capacitance simulation only
• LC-Tank MOSCAP model (moscap_rf) is for frequency-dependent Q factor and capacitance simulations

MOS Device as Capacitor

Voltage dependence

• capacitance of MOS gate varies nonmonotonically with \(V_{GS}\)

• "accumulation-mode" varactor varies monotonically with \(V_{GS}\)

reference

Aditya Varma Muppala. MOS Varactors | Oscillators 15 | MMIC 27 [https://youtu.be/LYCLZPQvIz0?si=yoSBZSD2j_wEx0zZ]

R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs," in IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003, doi: 10.1109/JSSC.2003.814416.

T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee and S. S. Wong, "Analysis and optimization of accumulation-mode varactor for RF ICs," 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), 1998, pp. 32-33, doi: 10.1109/VLSIC.1998.687993. URL: http://www-smirc.stanford.edu/papers/VLSI98s-chet.pdf

R. Jacob Baker, 6.1 MOSFET Capacitance Overview/Review, CMOS Circuit Design, Layout, and Simulation, Fourth Edition

B. Razavi, Design of Analog CMOS Integrated Circuits 2nd

Bing Sheu, TSMC. "Circuit Design using FinFETs" [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T4.pdf]

Due to the fact that long-term drift of temperature sensors and bandgap references caused by package-induced stress is lower with PNP BJTs than with NPN BJTs, PNP BJTs have been used traditionally for temperature sensor design in CMOS

Calibration

TODO 📅

[https://ww1.microchip.com/downloads/en/Appnotes/Atmel-8108-Calibration-of-the-AVRs-Internal-Temperature-Reference_ApplicationNote_AVR122.pdf]

\(V_{BE}\) curvature

curvature results in results in non-linearity

Though it is assumed that \(V_{BE}\) is a linear function of temperature for first oder analysis.

In practice, \(V_{BE}\) is slightly nonlinear, the magnitude of this nonlinearity is referred to as curvature.

curvature depends on the temperature dependency of the saturation current (\(I_s\)), and on that of the collector current (\(I_c\)), it can be written as \[ V_{curv}(T)=\frac{k}{q}(\eta-\delta)(T-T_r-T\cdot \ln(\frac{T}{T_r})) \] where \(\eta\) = a constant depending on the doping level, CMOS substrate pnp transistors have a typically value of \(\eta \cong 4\)

\(\delta\) = order of the temperature dependence of collector current (\(I_c\))

PTAT \(I_c\) help reduce \(V_{curv}(T)\), \(\delta=1\)

Although the temperature dependence of the bias current \(I_b\) doesn’t impact the accuracy of \(V_{BE}\), it does impact the systematic nonlinearity or curvature of \(V_{BE}\), and hence the sensor's systematic error. The curvature in \(V_{BE}\) can be reduced by using a PTAT bias current.

PTAT bias current

\[ I_{bias} = \frac{0.7}{\beta \cdot R^2} \] in which \(\beta=\frac{\mu_{n}\cdot C_{ox}\cdot W}{L}\), where:

\(\mu_n\)=mobility,

\(C_{ox}\) = oxide capacitance density,

\(\frac{W}{L}\) = dimension ratio of unit NMOS used for \(M_1\) and \(M_2\)

\(\mu_n\) is complementary to the absolute temperature and resitor R is implemented using high-R flow in FinFET which has a low temperature dependency, the net temperature dependency of \(I_{bias}\) is proportional to the absolute temperature \[ I_{bias}\propto T \]

Kamath, Umanath Ramachandra. "BJT Based Precision Voltage Reference in FinFET Technology." (2021).

Errors due to V-I Finite Gain

Finite gain introduces errors both in the V-I converters, finite loop gain results in errors in the closed-loop transconductances.

\[\begin{align} (V_{i1} - V_{o1})\cdot A_{OL1} &= V_{o1} \\ V_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}V_{i1} \\ I_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}\frac{1}{R_1}V_{i1} \end{align}\] similarly, \[ I_{o2} = \frac{A_{OL2}}{1+A_{OL2}}\frac{1}{R_2}V_{i2} \]

Then, \(\alpha\) is obtained \[ \alpha = \frac{(1+A_{OL2})A_{OL1}}{A_{OL2}(1+A_{OL1})}\cdot\frac{R_2}{R_1} \] Since the loop gains in the two V-I converters cannot be expected to match, the resulting errors in both converters should be reduced to negligible levels.

First, assume \(A_{OL2}=\infty\) \[\begin{align} \Delta \alpha &= (1-\frac{A_{OL1}}{1+A_{OL1}})\cdot\frac{R_2}{R_1}\\ &=\frac{1}{1+A_{OL1}}\cdot\frac{R_2}{R_1}\\ &\cong \frac{1}{A_{OL1}}\cdot\frac{R_2}{R_1} \end{align}\]

We get \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL1}} \] Follow the same procedure, assume \(A_{OL1}=\infty\) \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL2}} \] The finite gain introduces an error inversely proportional to the loop gain \(A_{OL1}\),\(A_{OL2}\), the resulting errors in both converters should be reduced to negligible levels

Why is it named as "bandgap reference"

Let us write the output voltage as \[ V_{REF} = V_{BE} + V_T\cdot \ln n \] and hence \[ \frac{\partial V_{REF}}{\partial T} = \frac{\partial V_{BE}}{\partial T} + \frac{V_T}{T}\ln n \] Setting this to zero and substituting for \(\frac{\partial V_{BE}}{\partial T}\), we have \[ \frac{V_{BE}-(4+m)V_T-E_g/q}{T}=-\frac{V_T}{T}\ln n \] If \(V_T\ln n\) is found from this equation and inserted in \(V_{REF}\), we obtain \[ V_{REF}=\frac{E_g}{q} + (4+m)V_T \]

The term bandgap is used here because as \(T\to 0\), \(V_{REF} \to E_g/q\)

sinking PTAT-current generator without current mirrors

why without current mirror?

Bakker, Anton. (2000). High-Accuracy CMOS Smart Temperature Sensors. 10.1007/978-1-4757-3190-3. [https://repository.tudelft.nl/record/uuid:fd398056-48dd-4d84-8ae8-27a1b011d2c3]

Readout Circuit

ADC dynamic range

Take \(V_{PTAT}=\alpha \cdot \Delta V_{BE}\) as input and \(V_{REF}\) as reference. The output \(\mu\) of the ADC will then be \[ \mu =\frac{V_{PTAT}}{V_{VREF}}=\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] A final digital output \(D_{out}\) in degrees Celsius can be obtained by linear scaling: \[ D_{out}=A\cdot \mu + B \] where \(A\simeq 600K\) and \(B\simeq -273K\)

While the transfer is simple, it only uses about 30% of the of the ADC (the extremes of the operating range correspond to \(\mu \simeq 1/3\) and \(\mu \simeq 2/3\)). The ratio results in a rather inefficient use of the modulator's dynamic range.

For a first-order \(\Sigma\Delta\) modulator, this means that about 1.5 bits of resolution are lost

A more efficient transfer is \[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] With this more efficient combination, 90% of the dynamic range is used rather than 30%. Thus, the required resolution of the ADC is reduced by a factor of three.

Integrator Output Swing

\[ \mu =\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

\[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

In advanced process, like Finfet 16nm, 7nm, high resistance resistor has +/-15% variation and MOM capacitor has +/-30% variation.

Then, \(R_1\) and \(R_2\) not only determine the \(\alpha\) but also the integrator's output swing, so do \(V_{BE}\) and \(\Delta V_{BE}\), \(C_{int}\).

The integrator's output change per period

example

integrator, comparator offset

integrator offset

comparator offset

integrator design

application in sensor

Offset Errors

The offset of opamp \(A_3\) is much less critical:

1. It affects the integrated currents via the finite output impedances \(R_{out1,2}\) of the V-I converters, and is therefore attenuated by a factor \(R_{out1}/R_1\) when referred back to the input of the sinking V-I converter,

2. or by a factor \(R_{out2}/R_2\) when referred back to the input of the sourcing V-I converter.

Therefore, no special offset cancellation is needed for opamp \(A_3\).

The current change due to offset of \(A_3\): \[\begin{align} \frac{V_{BE,os}}{R_1} &= \frac{V_{ota,os}}{R_{out1}} \\ \frac{\Delta V_{BE,os}}{R_2} &= \frac{V_{ota,os}}{R_{out2}} \end{align}\] Then, the input referenced offset is: \[\begin{align} V_{BE,os} &=\frac{ V_{ota,os}}{R_{out1}/R_1} \\ \Delta V_{BE,os} &= \frac{ V_{ota,os}}{R_{out2}/R_2} \end{align}\]

Errors due to Finite Gain

Finite gain of opamp \(A_3\) results in a non-zero overdrive voltage at its input, which modulates the current Iint due to the finite output impedances of the V-I converters.

Assuming the opamp is implemented as a transconductance amplifier, there are two main causes of this non-zero overdrive voltage

1. The finite transconductance \(g_{m3}\) of the opamp, , which implies that an overdrive voltage is required to provide the feedback current

​ The change in the integrated current

​ \[\begin{align} ​ \Delta I_{int} &= \frac{V_{i,ota}}{R_{out}}\\ ​ &= \frac{I_{int}}{g_{m3}}\cdot \frac{1}{R_{out}} ​ \end{align}\]

2. The finite DC gain \(A_{0,3}\), which implies that an overdrive voltage is required to produce the output voltage \(V_{int}\)

reference

Micheal, A., P., Pertijs., Johan, H., Huijsing., Pertijs., Johan, H., Huijsing. (2006). Precision Temperature Sensors in CMOS Technology.

C. -H. Chang, J. -J. Horng, A. Kundu, C. -C. Chang and Y. -C. Peng, "An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, pp. 165-168, doi: 10.1109/ASSCC.2014.7008886.

EE247 - Analog Digital Interface Integrated Circuits - Fall 2009 Lecture 24- Oversampled ADCs

Hecht, Bruce. (2010). SSCS DL Kofi Makinwa Talks About Smart Sensor Design at SSCS-Boston [People]. Solid-State Circuits Magazine, IEEE. 2. 54 - 56. 10.1109/MSSC.2009.935278.

Linear Time-varying System Theory

We define the ISF of the sampler as the sensitivity of its final output voltage to the impulse arriving at its input at different times, the ISF essentially describes the aperture of the sampler.

An ideal sampler would have the perfect aperture, i.e. sampling the input voltage at exactly one point in time; thus, its ISF would be a Dirac delta function, \(\delta(t-t_s)\) where \(t_s\) is when sampling occurs.

A realistic sampler would rather capture a weighted-average of the input voltage over a certain time window. This weighting function is called the sampling aperture and is equivalent to the ISF

A time-varying impulse response \(h(t, \tau)\) is defined as the circuit response at time \(t\) responding to an impulse arriving at time \(\tau\).

In general, the ISF can be regarded as the time-varying impulse response evaluated at one particular observation time \(t=t_0\).

The system output \(y(t)\) is related to the input \(x(t)\) as: \[ y(t) = \int_{-\infty}^{\infty}h(t, \tau)\cdot x(\tau)d\tau \] Note that in a linear time-invariant (LTI) system, \(h(t,\tau)=h(t-\tau)\) and the above equation reduces to a convolution.

If \(X(j\omega)\) is the Fourier transform of the input signal \(x(t)\), i.e. \[ x(t) = \frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega t}d\omega \] Then \[\begin{align} y(t) &= \int_{-\infty}^{\infty}h(t,\tau)\left[\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega\tau }d\omega \right]\cdot d\tau \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{j\omega\tau}d\tau\right]\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\right]\cdot e^{j\omega t}\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot H(j\omega;t)\cdot e^{j\omega t}\cdot d\omega \end{align}\]

where \(H(j\omega;t)\) is time-varying transfer function, defined as the Fourier transform of the time-varying impulse response. \[ H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \] And it follows that: \[ Y(j\omega)=H(j\omega;t)\cdot X(j\omega) \] And

\[\begin{align} x(\tau) & \overset{FT}{\longrightarrow} X(j\omega) \\ h(t,\tau) & \overset{FT}{\longrightarrow} H(j\omega;t) \end{align}\]

For linear, periodically time-varying (LPTV) systems, \(h(t, \tau) = h(t+T, \tau+T)\) and \(H(j\omega; t) = H(j\omega; t+T)\) where \(T\) is the period of the time-varying dynamics of the system.

We prove \(H(j\omega; t) = H(j\omega; t+T)\):

\[\begin{align} \because H(j\omega;t)&=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ \therefore H(j\omega;t+T) &= \int_{-\infty}^{\infty}h(t+T,\tau)\cdot e^{-j\omega(t+T-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t+T-(\tau+T))}d(\tau+T) \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= H(j\omega;t) \end{align}\]

PSS + PAC Method

Since \(H(j\omega;t)\) is periodic in \(T\), The time-varying transfer function \(H(j\omega;t)\) can be expressed in a Fourier series: \[ H(j\omega;t)=\sum_{m=-\infty}^{\infty}H_m(j\omega) \cdot e^{jm\omega_c t} \] where \(\omega_c\) is the fundamental frequency of the periodic system. \(H_m(j\omega)\) represent the frequency response of the system at the (m-th) harmonic output sideband to a unit \(j\omega\) sinusoid.

The above equation link time-varying transfer function \(H(j\omega;t)\) with PAC simulation output

The response to a periodic impulse train, that is: \[ x(t)=\sum_{m=-\infty}^{\infty}\delta(t-\tau-nkT) \] The idea is that if the impulse response of the system settles to zero long before the next impulse arrives, then the system response to this impulse train would be approximately equal to the periodic repetition of the true impulse response, i.e.: \[ y(t) \cong \sum_{m=-\infty}^{\infty}h(t;\tau+nkT) \] and \(y(t)\) would be approximately equal to \(h(t;\tau)\) for \(\tau \leq t \le t+kT\)

Without loss of generality and for computation convenience, we set \(k=1\) thereafter.

The Fourier transform \(X(j\omega)\) of the T-periodic impulse train is: \[ X(j\omega)=\omega_c\sum_{n=-\infty}^{\infty}\delta(\omega-n\omega_c)\cdot e^{-j\omega\tau} \] Then the response \(y(t)\) is: \[ y(t)=\frac{1}{T}\sum_{n=-\infty}^{\infty}H(jn\omega_c;t)\cdot e^{jn\omega_c\cdot(t-\tau)} \] The expression for the approximate time-varying impulse response: \[ h(t,\tau) = \left\{ \begin{array}{cl} \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct+jn\omega_c\cdot (t-\tau)} & : \ \tau \leq t \lt \tau+T \\ 0 & : \ \text{elsewhere} \end{array} \right. \] Finally, the ISF \(\Gamma(\tau)\) is equal to \(h(t,\tau)\) when \(t=t_0\) and \(t_0 \gt \tau\) \[ \Gamma(\tau)\cong \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct_0+jn\omega_c\cdot (t_0-\tau)} \] In practice, the summations are carried out over finite ranges of n and m, for example, -50~50.

For each combination of n and m, the PAC analysis needs to be performed to compute \(H_m(jn\omega_c)\), the m-th harmonic response to the excitation at \(n\omega_c\)

The detailed procedure for characterizing the ISF of this sampler is outlined as follows:

• First, apply the proper input voltages that place the sampler in a metastable state and perform the periodic steady-state (PSS) analysis.

• Second, perform the PAC analysis.

• Third, based on the simulated PAC response, pick a time point \(t_0\) at which the ISF is to be computed and derive the ISF

One possible candidate for the ISF measurement point \(t_0\) is the time at which the output voltage is amplified to the largest value. PAC response of the sampler to a small signal DC input, that is, the time-varying transfer function evaluated at \(\omega=0\) \[ H(0;t)=\sum_{m=-\infty}^{\infty}H_m(0) \cdot e^{jm\omega_c t} \]

The total area under the ISF is the sampling gain, which is equal to the time-varying gain measured at \(t_0\) to a small signal DC input (\(\omega=0\))

Because we have \(H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\), i.e. Fourier transform \[ H(0;t)=\int_{-\infty}^{\infty}h(t,\tau)d\tau = \int_{-\infty}^{\infty}\Gamma(\tau)d\tau \]

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time-varying gain at t0 H(0;t0): 19.486305
The total area under the ISF: 19.990230

Align pss_td.pss with ISF

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****************************************************
Periodic Steady-State Analysis `pss': fund = 500 MHz
****************************************************
Trying `homotopy = gmin' for initial conditions.
DC simulation time: CPU = 4.237 ms, elapsed = 4.27389 ms.

===============================
`pss': time = (0 s -> 102.6 ns)
===============================

Opening the PSF file ../psf/pss.tran.pss ...
...
Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 102.6 ns
    period = 2 ns
    maxperiods = 20
    step = 102.6 ps
...

tstab = 102.6 ns can be observed in pss simulation log

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tstab = 102.6e-9;
tshift = mod(tstab, Tc);
tt_shift = tt - tshift;
tt_shift_start_indx = find(tt_shift>=0, 1);
isf_shift = circshift(isf_re, -tt_shift_start_indx);

Align pss_fd.pss with ISF

Since both are frequency originated, time-shift is NOT needed

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function wv = wv_fd(fname,tt)
fd = csvread(fname, 1, 0);
DC = fd(1, 2);
w = 2*pi*fd(2:end, 1);
coef = fd(2:end, 2) + 1i*fd(2:end, 3);
exp_sup = 1i*w.*tt;
wv = sum(real(coef .* exp(exp_sup)), 1) + DC;
end

PSS + PAC Setup

• clock frequency should be low enough to assure system response settle to zero.
• Beat Frequency os PSS should be clock frequency
• For PAC setup,
  • the Sweeptype is absolute
  • Input Frequency Sweep Range(Hz) should be large enough.
  • Sweep Type should be Linear and Step Size should equal PSS Beat Frequency(Hz)
  • SideBands should large enough, like 50 (i.e. 50*2 +1, positive, negative and 0)
  • Specialized Analyses should be None

one example: clock, i.e. beat frequency = 8G PAC: input frequency sweep from -400G to 400G and step is 8G, which is beat frequency, here K=1 Eq.(9) of paper

freqaxis=out: freqaxis of PAC not only affect "Direct Plot"'s output but also simuation data i.e. the phase shift(imaginary part).

matlab matrix nonconjugate transpose:

transpose, .' cf. https://www.mathworks.com/help/matlab/ref/transpose.html

tstab in PSS

Using shooting PSS, the steady waveform starts from tstab+n*tperiod.

• pss_td.pss is one period waveform starting from tstab+n*tperiod
• pss_fd.pss is the complex fourier series coefficient of expanded to left and right pss_td.pss waveform (tstab+n*tperiod : tstab+(n+1)*tperiod)

We have to left-shift mod(tstab, tperiod) pss_fd.pss in order to align it with of pss_tb.pss

simulation log

The below stop = 1.3 ns is actual tstab time, though Stop Time(tstab) field of pss form is filled with 0.3n

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**************************************************
Periodic Steady-State Analysis `pss': fund = 1 GHz
**************************************************
DC simulation time: CPU = 208 us, elapsed = 211.954 us.

=============================
`pss': time = (0 s -> 1.3 ns)
=============================

Opening the PSF file ../psf/pss.tran.pss ...

Output and IC/nodeset summary:
                 save   1       (current)
                 save   2       (voltage)

Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 1.3 ns
    period = 1 ns
    maxperiods = 20
    step = 1.3 ps
    maxstep = 40 ps
    ic = all
    useprevic = no
	...

    pss: time = 64.01 ps    (4.92 %), step = 31.63 ps     (2.43 %)
	...
    pss: time = 1.224 ns    (94.2 %), step = 40 ps        (3.08 %)
    pss: time = 1.3 ns       (100 %), step = 35.99 ps     (2.77 %)
...

PSS simulation result

Align pss_tb and pss_fd

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clear;
clc;

freq = 1e9;
tstab = 1.3e-9;
Tp  = 1e-9;

load('pss_td.matlab')
t = pss_td(:, 1);
ytd = pss_td(:, 2);
plot(t*1e9, ytd, 'k', 'LineWidth',6)
hold on;

% time domian from pss frequency domain information
coff_real = -0.155222;
coff_imag = -0.0247045;
wc = 2*pi*freq;
tfd = (0:1e-11:2e-9);
yfd = coff_real*cos(wc*tfd) - coff_imag*sin(wc*tfd);
plot(tfd*1e9, yfd, 'b')

% actual pss_td.pss one-period waveform
tfd_td = (tstab:1e-11:2e-9);
yfd_td = coff_real*cos(wc*tfd_td) - coff_imag*sin(wc*tfd_td);
plot(tfd_td*1e9, yfd_td, '--b', 'LineWidth', 4)

% align pss_fd with pss_tb by left shift mod(tstab, Tp) pss_fd
tshift = mod(tstab, Tp);
tfd_shift = tfd - tshift;
tfd_shift_start_indx = find(tfd_shift>=0, 1);
tfd_shift = tfd_shift(1, tfd_shift_start_indx:end);
yfd_shift = yfd(1, tfd_shift_start_indx:end);
plot(tfd_shift*1e9, yfd_shift, '-magenta', 'LineWidth', 2)
grid on;

xlabel('t (ps)');
ylabel('V(t)');
legend('Using pss\_td', 'Using pss\_fd', 'pss\_tb one period clip', 'Using pss\_fd with time shift', 'location', 'east');

Transient Method

TODO 📅

reference

J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 386-391, doi: 10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]

M. Jeeradit et al., "Characterizing sampling aperture of clocked comparators," 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2008, pp. 68-69 [https://people.engr.tamu.edu/spalermo/ecen689/sampling_aperature_comparators_vlsi_2008.pdf]

T. Toifl et al., "A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 954-965, April 2006 [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=4d1f0442be77425ed34b9dcfd48fbfff954a707b]

Sam Palermo, ECEN 720 High-Speed Links: Circuits and Systems [Lecture 6: RX Circuits], [Lab4 - Receiver Circuits]

CDM (Charged Device Model)

Jordan Davis, Samsung Electronics. Full-Chip CDM Analysis: Is Static Simulation Enough? [https://www.synopsys.com/content/dam/synopsys/implementation&signoff/electrical-layout-verification-documents/esd-workshop-2021-pres.pdf]

M. Etherton et al., "A new full-chip verification methodology to prevent CDM oxide failures," 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 2015 [pdf]

P.E. Allen 2021. Lesson 4 – ESD Input Circuit Protection [https://aicdesign.org/wp-content/uploads/2021/05/Lesson04_ESD_Input_Ckt_Protection210323.pdf]

M. Di, H. Wang, F. Zhang, C. Li, Z. Pan and A. Wang, "Does CDM ESD Protection Really Work?," 2019 IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, USA, 2019 [https://sci-hub.se/10.1109/WMED.2019.8714145]

On-Chip Decoupling Capacitors

Y. -C. Huang and M. -D. Ker, "Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits," in IEEE Journal of the Electron Devices Society, vol. 9, pp. 881-890, 2021 [pdf]

Y. -C. Huang and M. -D. Ker, "Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors," in IEEE Journal of the Electron Devices Society, vol. 11, pp. 84-94, 2023

NMOS capacitor with DNW owing to the parasitic junction that formed between P-substrate and the DNW to reduce the probability of ESD damage on the thin gate oxide layer of NMOS capacitor.

Therefore, it results in higher CDM ESD robustness than that of the other two designs with decoupling capacitors realized by of varactor and NMOS capacitor

Circuit-Level CDM Model

H. Wang, F. Zhang, C. Li, M. Di and A. Wang, "Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS," 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, China, 2018

—. (2018). A Chip-Level CDM ESD Protection Circuit Modeling and Simulation Method and Experimental Verification. UC Riverside [https://escholarship.org/content/qt1355v6vs/qt1355v6vs.pdf]

Today's cognition ondie CDM charge is stored in the substrate

The circuit model is divided into three parts:

• IC package

• substrate resistance & capacitance

• protection devices & circuit elements

all charges are considered be distributed to the surface of an IC die, i.e., Si substrate

The surface-stored charges are modeled using the capacitors at the surfaces of the IC substrate

A Vulnerable Circuit Topology — cascode topology

Parasitic Capacitance Path

Lin, Chun-Yu, Tang-Long Chang and Ming-Dou Ker. "Investigation on CDM ESD events at core circuits in a 65-nm CMOS process." Microelectron. Reliab. 52 (2012) [pdf]

CDM ESD issue due to the coupled current when I/O circuit is stressed by CDM ESD

negative CDM ESD event

positive CDM ESD event

CDM Failure Mechanisms

• reverse S/D junctions
• capacitively coupled through the gate

For a bare Si die, the charges induced by whatever procedures, are stored inside the IC die randomly, unpredictably and anywhere, e.g., in the substrate, along the metal rails or locally to transistors

M. Etherton et al., "A new full-chip verification methodology to prevent CDM oxide failures," 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 2015 [https://www.synopsys.com/content/dam/synopsys/implementation&signoff/electrical-layout-verification-documents/cdm-esd-paper.pdf]

Note that there is no notable CDM current flow in the signal route

Yorgos Christoforou. Why negative polarity CDM ESD leads more often to failure [https://ycindustrial.wordpress.com/2014/01/15/why-negative-polarity-cdm-esd-leads-more-often-to-to-failure/]

?? suppose that charged package and substrate are same electric potential

Misconception in CDM ESD Protection

Two players will affect the internal CDM discharging routing:

• the amount of electrostatic charge stored inside the IC
• more importantly, their internal distribution within a chip

Wang, Han, Feilong Zhang, Cheng Li, Mengfu Di and Albert Z. H. Wang. “Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS.” 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2018) [pdf]

It is generally believed that the induced electrostatic charges are stored on the package frame and/or on the supply buses in a lumped way

induced electrostatic charges are randomly distributed throughout a bare die of mixed-signal IC, anywhere and everywhere

Field Induced CDM (FICDM)

Field Induced CDM Explained [https://certus-semi.com/field-induced-cdm-explained/]

Confusion about the test procedure is understandable because the actual process is opposite from what is expected

• field induction does not place any charge on the device

• the "discharge" when the pogo pin first touches the DUT is when the DUT is actually charged

\(C_{DF}\) is the capacitance of the DUT to the field plate

\(C_{DG}\) is the capacitance of the DUT to the ground plane

\(C_{FG}\) is the capacitance of the field plate to the ground plane

\(C_{DF}\gg C_{DG}\) — the separation of the DUT from the field plate is always much less than the separation of the DUT from the ground plane

Assuming no initial charge on the DUT, with the switch S open the DC voltage between the DUT and the Field Plate is \[ V_{DF} = \frac{C_{DG}}{C_{DG} + C_{DF}}\cdot V_{HV} \approx 0 \]

• DUT potential will therefore closely track the power supply voltage
• The potential of the DUT relative to the ground plane can therefore be controlled without actually putting any net charge on the DUT

CDM Test Sequence

1. With the field plate at zero volts an uncharged DUT is placed on the field plate in the dead bug position and the ground plane is positioned with the pogo pin above the pin to be tested

2. The field plate is raised to a high potential, for example +500 V. The high value resistor ensures that the field plate changes potential relatively slowly. The slow change in potential ensures that the DUT is not damaged before the CDM event.

   The potential of the DUT will closely track the field plate, reaching in excess of 450 V, although there will be no net charge on the DUT

   Capacitive coupling elevates the potential of the integrated circuit to a voltage close to that of the field plate

3. After the voltage has stabilized the separation between the field plate and the ground plane is reduced until an arc forms between the pogo pin and the DUT pin and eventually the two pins touch.

   This is equivalent to closing the switch S in Figure 3

4. Closing S in the circuit diagram produces a very rapid grounding of the DUT and a redistribution of charge between the three capacitors

   At this point the DUT is charged and the potential between the field plate and the ground plane has fallen as the capacitor \(C_{FG}\) provides charge to the DUT

   During this redistribution of charge, which usually lasts under 2 ns, the high voltage power supply and the high value resistor can be ignored because of their slow response time

5. After the initial redistribution of charge the field plate will slowly return to the voltage on the high voltage power supply, while the DUT remains at zero potential, but in a charged state

6. With the pogo pin still touching the DUT pin the HV power supply voltage is set to zero. The field plate will slowly return to zero volts and the charge on the DUT will slowly bleed off through the pogo pin.

single & dual discharge method

single discharge procedure:

single positive or single negative CDM ESD pulse is applied to DUT for individual CDM discharge

the single discharge procedure involves only one CDM discharge to stress the DUT device

dual discharge procedure:

single positive and single negative CDM ESD pulses are applied to produce one pair of alternating polarity CDM discharges to zap the DUT

Static Induction

ESD Static Induction & Double Jeopardy Demonstration [https://youtu.be/RGN-PvAE-OI]

Electrostatic Equilibrium State

CDM Tester Model Using Spice

Robert Ashton. Simulating Small Device CDM Using Spice [https://incompliancemag.com/simulating-small-device-cdm-using-spice/]

TODO 📅

The value of CFG is also based on a parallel plate capacitor model with a peripheral capacitance term minus a capacitance representing a shielding of the Field Plate to ground plane capacitance due to the size of the device under test

Challenges of CDM Modeling for High-Speed Interface Devices [https://incompliancemag.com/challenges-of-cdm-modeling-for-high-speed-interface-devices/]

Problem Statement of a lumped capacitor CDUT

Distributed DUT model

To assess the design solutions, a distributed DUT model, as presented in Figure 3, can be plugged into the CDM tester model, replacing the lumped DUT capacitor

• The maximum voltage difference between Vdut and Vss (Vdd) should not exceed the breakdown voltage of the gates.
• On-die parasitics of Vss and Vdd nets strongly influence the actual voltage waveform at the input gate oxide. In particular, oscillations and spikes in the voltage waveform are sensed by the gate oxide and can lead to damage

Diode capacitance vs. Vpn

TODO 📅

anti-parallel ESD diode

M. Etherton et al., "A new full-chip verification methodology to prevent CDM oxide failures," 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 2015 [https://www.synopsys.com/content/dam/synopsys/implementation&signoff/electrical-layout-verification-documents/cdm-esd-paper.pdf]

PERC

• CD: current density checks

• P2P: point to point resistance checks

• LDL: logic driven layout checks, latch up related

• TOPO: topology, circuit connection and device size checks

database

• CD, P2P, LDL : dfmdb

• TOPO: svdb

Frank Feng. New Approach For Full Chip Electrical Reliability Verification [pdf]

Calibre PERC Catalog Test-Cases & Common Examples Version 2.0

Latchup

Latch-up in CMOS circuits: threat or opportunity (part 1) [https://monthly-pulse.com/2021/01/05/latch-up-in-cmos-circuits-threat-or-opportunity-part-1/]

Latch-up in CMOS circuits: threat or opportunity (part 2) [https://monthly-pulse.com/2021/01/05/latch-up-in-cmos-circuits-threat-or-opportunity-part-2/]

This can happen when a parasitic thyristor, which is essentially a pair of interconnected transistors, is triggered into a latched state, leading to sustained current flow and potential device failure.

Necessary Conditions

Trigger Modes

latchup-prevention technique

Technical Paper Ensuring latch-up guard rings ESDA rules using Calibre PERC [https://resources.sw.siemens.com/en-US/technical-paper-ensuring-latch-up-guard-rings-esda-rules-using-calibre-perc/]

Protect against ESD by ensuring latch-up guard rings [https://semiwiki.com/eda/362551-protect-against-esd-by-ensuring-latch-up-guard-rings/]

Guard Rings

One important technique is the use of guard rings, the heavily doped regions surrounding sensitive components on the IC to divert excess current away from vulnerable areas, thereby reducing the likelihood of latch-up occurrence

These guard rings not only function as barriers against parasitic thyristor (SCR) formation but also serve to isolate different regions of the IC, minimizing unwanted electrical interactions and maintaining pathway integrity

P.E. Allen - 2016. CMOS Analog Circuit Design: Lecture 08 – Latchup and ESD (4/25/16) [https://aicdesign.org/wp-content/uploads/2018/08/lecture08-160425.pdf]

[https://analoghub.ie/category/Layout/article/layoutDependentEffects#Latchup]

Latch-Up triggers:

• Power up
• Overshoot voltages and currents
• Substrate noise
• ESD occurrences

Latch-up key points:

• State of an IC when it is made inoperable by a parasitic shorting of VDD and VSS;
• Triggering of a Low Impedance High Current state between supplies;
• High Current State remains even when trigger signal is removed.

Latch-up prevention:

• Guard rings has a lot of contacts, providing a strong VDD/Ground potential;
• Guard rings add more parallel resistance to the NWELL/Substrate, thereby reducing parasitic resistors;
• NWELL/substrate potentials are held around VDD/Ground, no positive feedback is formed.

Transient-Induced Latchup

OD injector

Diode in ESD Protection

A diode can operate in both forward and reverse modes for ESD protection.

\(R_{ON}\) for a forward-biased diode is lower than that for a reverse-biased diode

One major disadvantage of a forward diode-string for ESD protection is that the leakage current (Ileak) may be enlarged due to the Darlington effect in the diode-string

Silicon Controlled Rectifiers (SCR)

A thyristor (also known as a Silicon Controlled Rectifier or SCR) is a three-terminal semiconductor device used as an electronic switch or rectifier

To turn the thyristor on, a positive voltage pulse is applied to the gate (G) terminal. This voltage pulse needs to be of sufficient magnitude to trigger the device. When the gate is triggered, it allows a small current to flow into the base of the P-N-P transistor within the thyristor structure

[https://ec2-44-207-46-173.compute-1.amazonaws.com/thyristor/]

ESD design window

[https://monthly-pulse.com/2021/06/02/the-esd-design-window-concept/]

[https://www.researching.cn/ArticlePdf/m00098/2020/41/12/122403.pdf]

• Transparency
  • Trigger voltage Vt1
  • Holding/clamping voltage Vh
• Robustness
  • failure current level It2
• Effectiveness
  • maximum voltage of the clamp device: Vmax

You Li. CICC2020: ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies

[https://picture.iczhiku.com/weixin/message1640668908028.html]

ESD工作区称为“设计窗口”

保护设备的触发电压(V t1)定义了它设计为导通的电平; 触发后的保持电压(V Hold)是指应高于施加电压的钳位电平。最后，I t2是指ESD故障电流水平。

如蓝色曲线(1A或1B)所示，NMOS晶体管在触发点V t1处进入双极击穿(npn)，并迅速恢复为称为V Hold的保持电压，并保护高达故障电流I ESD对应于ESD目标水平。(I t2，V t2)是指保护设备可能烧坏的散热点，因此该I t2必须大于I ESD目标电流水平(例如，目标1.5 kV HBM的电流为1 Amp)。如果保护设备的导通电阻(R on)太高，则V t2也可能达到可靠性电压极限。钳位电路必须有效触发，以使其电压累积不超过栅极氧化层击穿电压(BV ox)或晶体管击穿电压。晶体管的V Hold经过设计，使其具有一定的工作电压裕度，如曲线1A所示。相反，在具有V Hold的快速恢复装置小于工作电压(曲线1B)的情况下，存在EOS损坏的风险。

Two-Stage ESD Protection

two-stage primary–secondary ESD protection

a primary ESD protection structure (ESD1), a secondary ESD protection unit (ESD2), and an isolation resistor (\(R\))

The desired specs for ESD2 is low \(V_\text{t1}\) and short \(t_1\), while that for ESD1 include low \(R_{ON}\), low \(V_\text{h}\) and high \(I_\text{t2}\)

• The primary ESD1 structure is typically optimized for high ESD protection level, which however may feature a high ESD \(V_\text{t1}\), not suitable for low-voltage (LV) ICs

• The secondary ESD2 unit serves as a trigger-assisting device that features a lower ESD \(V_\text{t1}\) and fast ESD triggering, which is typically weak in handling large ESD discharge currents

The isolation \(R\) has another role, which is to prevent an ESD pulse from getting into IC core (i.e., stressing the input device) directly, hence avoid possible CMOS gate breakdown

\(R\) involves a design trade-off too: large enough for fast voltage build up, but not too large to avoid adverse impact on signal propagation

The two-stage ESD protection method is re-gaining attention for CDM ESD protection because it can handle large ESD surges without overheating, while preventing CMOS gate breakdown due to the isolation R (i.e., no direct zapping on the input gate)

1. Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors.
2. ESD current through this clamp will build-up voltage across the isolation resistance, while protecting the circuit.
3. The higher voltage at the IN pad will then trigger the primary protection (red current path)

Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors

Extended ESD design window example. The failure voltage of a thin gate oxide in advanced CMOS is about 4V. The primary ESD solution (red IV curve) introduces too much voltage. Thanks to an isolation resistance between primary and secondary local clamp device (green IV curve) additional margin is created.

[https://monthly-pulse.com/2022/03/29/introduction-esd-protection-concepts-for-i-os/]

Okushima, M. and Tsuruta, J., "Secondary ESD clamp circuit for CDM protection of over 6Gbit/s SerDes application in 40nm CMOS", Microelectronics Reliability, vol. 53, no. 2, pp. 215–220, 2013 [https://sci-hub.se/https://doi.org/10.1016/j.microrel.2012.04.010]

Gated diode & STI diode

"gated diode" aka. "poly bound" diode

STI bound diodes typically have lower capacitance

M. Simicic, G. Hellings, S. -H. Chen, N. Horiguchi and D. Linten, "ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology," 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, Germany, 2018

US9653448B2. Electrostatic Discharge (ESD) Diode in FinFET Technology

?? Rotated STI Diode

Loke, Alvin & Yang, (2018). Analog/mixed-signal design challenges in 7-nm CMOS and beyond. 10.1109/CICC.2018.8357060.

Shih-Hung Chen. CICC 2019: Designing Diode Based ESD Protection in Advanced State of the Art Technologies

TLP/vf-TLP

TRANSMISSION LINE PULSE TESTING: THE INDISPENSABLE TOOL FOR ESD CHARACTERIZATION OF DEVICES, CIRCUITS AND SYSTEMS [https://www.esda.org/assets/News/1708-ESD-firstDraft.pdf]

[https://monthly-pulse.com/2021/06/08/transmission-line-pulse-tlp-test-system/]

Jon Barth "TLP and VFTLP Testing of Integrated Circuit ESD Protection" [https://barthelectronics.com/wp-content/uploads/2016/09/TLP-and-VFTLP-Test-of-Integrated-Circuit-ESD-Protection.pdf]

Horst A. Gieser(IZM), "ESD- Testing: HBM to very fast TLP" [https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf]

Vt1: trigger voltage

Vhold: holding voltage

soft failure current: Isoft

hard failure current: It2

TLP vs ESD

• ESD tests simulate real world events (HBM, MM, CDM)
• TLP does not simulate any real-world event
• ESD tests record failure level (Qualification)
• TLP tests record failure level and device behavior (Characterization)

TLP is not a qualification test, but a characterization method, which describes the resistance of a device for a given stimulus, aka. Device Characterization

Unlike ESD waveforms, TLP does not mimic any real world event

TLP and Curve Tracing

• Curve Tracing is DC; TLP is a short pulse
  • Shorter pulse - Reduced duty cycle, less heating, which means higher voltage before failure
  • Controlled Impedance - Allows device behavior to be observed
• Both measure resistance of device with increasing voltage

Device Characterization with TLP

• Turn-on time
• Snapback voltage
• Performance changes with rise time

VF-TLP and CDM differences

Question:

How well will VF-TLP results predict CDM testing performance?

Answer:

VF-TLP can be a guide to CDM failure levels, and provide a lot of understanding of a circuit's operation during CDM stressing, but simple correlations between VF-TLP failure current level and CDM withstand voltage levels are difficult to establish.

I.V and Leakage Evolution Plots

DC leakage current data combined with the I-V data provides electrical indications of where damage begins, and how rapidly it can evolve from soft to hard failures

Henry, Leo & Barth, Jon & Richner, John & Verhaege, Koen. (2000). Transmission Line Pulse Testing of the ESD Protection Structures in ICs - A Failure Analyst's Perspective. 203-213. 10.31399/asm.cp.istfa2000p0203. [https://barthelectronics.com/pdf_files/2000%20ISTFA%20TLP%20Testing%20of%20the%20ESD%20Protection%20Structure.pdf]

Henry, L.G. & Barth, Jon & Verhaege, K. & Richner, J.. (2001). Transmission-line pulse ESD testing of ICs: A new beginning. Compliance Engineering. 18. 46+53. [https://barthelectronics.com/pdf_files/CE%20TLP%20Article%20March-April%202001.pdf]

Snapback devices

Lesson 2 - ESD Clamps [https://aicdesign.org/wp-content/uploads/2021/05/Lesson02_ESD_Clamps210315.pdf]

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis - Device Level [https://www.esdemc.com/public/docs/TechnicalSlides/ESDEMC_TS001.pdf]

BJT

Grounded-gate NMOS (ggNMOS)

[https://monthly-pulse.com/2022/02/02/time-to-say-farewell-to-the-snapback-ggnmos-for-esd-protection/]

[https://monthly-pulse.com/2023/01/26/ggnmos-grounded-gated-nmos/]

snapback ggNMOS for ESD protection

Influence of the pulse rise time on ggNMOS. (left side) A fast ESD pulse can couple the bulk of the NMOS to a higher potential for a short period, reducing the trigger voltage. (right side) A clear Vt1 reduction is visible, while the remaining part of the IV curve remains the same.

[https://picture.iczhiku.com/weixin/message1588643699565.html]

一般都是把Gate/Source/Bulk短接在一起，把Drain结在I/O端承受ESD的浪涌(surge)电压，NMOS称之为GGNMOS (Gate-Grounded NMOS)PMOS称之为GDPMOS (Gate-to-Drain PMOS)。以NMOS为例，原理都是Gate关闭状态，Source/Bulk的PN结本来是短接0偏的，当I/O端有大电压时，则Drain/Bulk PN结雪崩击穿，瞬间bulk有大电流与衬底电阻形成压差导致Bulk/Source的PN正偏，所以这个MOS的寄生横向NPN管进入放大区(发射结正偏,集电结反偏)，所以呈现特性，起到保护作用。PMOS同理推导。

Trigger电压/Hold电压: Trigger电压当然就是之前将的的第一个拐点(Knee-point)，寄生BJT的击穿电压，而且要介于BVCEO与BVCBO之间。而Hold电压就是要维持持续ON，但是又不能进入栅锁(Latch-up)状态，否则就进入二次击穿(热击穿)而损坏了。还有个概念就是二次击穿电流，就是进入Latch-up之后I^2*R热量骤增导致硅融化了，而这个就是要限流，可以通过控制W/L，或者增加一个限流高阻， 最简单最常用的方法是拉大Drain的距离/拉大SAB的距离(ESD rule的普遍做法)。

PN结的击穿分两种，分别是电击穿和热击穿，电击穿指的是雪崩击穿, Avalanche Breakdown (低浓度)和齐纳击穿(高浓度)，而这个电击穿主要是载流子碰撞电离产生新的电子-空穴对(electron-hole)，所以它是可恢复的。但是热击穿是不可恢复的，因为热量聚集导致硅(Si)被熔融烧毁了。所以我们需要控制在导通的瞬间控制电流，一般会在保护二极管再串联一个高电阻，

Gate-coupled NMOS (gcNMOS)

Ming-Dou Ker, Chung-Yu Wu, Tao Cheng and Hun-Hsien Chang, "Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 3, pp. 307-321, Sept. 1996 [https://ir.lib.nycu.edu.tw/bitstream/11536/1053/1/A1996VE01800002.pdf]

Gate-coupled NMOS (gcNMOS) was proposed to effectively reduce the \(V_\text{t1}\)

[https://bbs.eetop.cn/forum.php?mod=redirect&goto=findpost&ptid=353178&pid=7305079]

SCR (thyristor)

Guang Chen, Haigang Feng and A. Wang, "A systematic study of ESD protection structures for RF ICs," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, Philadelphia, PA, USA, 2003 [https://sci-hub.se/10.1109/RFIC.2003.1213959]

[https://www.sharecourse.net/sharecourse/upload/course/180/c574580760de44d2c6fb66d8be4c6d4a.pdf]

Safe operating area (SOA)

power clamp

Thanks to the device scaling the area is actually reasonable. However, the leakage becomes the main bottleneck.

high current diode (HIA)

both diode are reverse-biased in normal operation, the PN Junction capacitance is proportional to forward-bias voltage

HIA_DIO can be used for logic or high speed circuits ESD protection

HIA: high current application purpose (High Amp)

There is no process difference between HIA_DIO and regular diode

• diode is drain/source originated, which is different from MOS (Gate originated)

• The perimeter of diode in DRC is different from that in PERC deck, where PERC excludes the the left and right edge of OD

g after the rule numbers: DFM recommendations and guidelines

^U: the rule is not checked by the DRC

I-V curve

MOS

l in netlist has different definition for MOS and diode.

MOS: length of channel

diode: Gate space

HIA = High Amp

lateral diode: perimeter is key DRC rule for ESD diode

HIA diode process is same with regular junction diode

Dual Stacked Diodes

PS: I/O to GND positively

NS: I/O to GND negatively

PD: I/O to VDD positively

ND: I/O to VDD negatively

Dual diode should be used with power clamp for PS and ND path

PMOS power clamp

EOS

[https://picture.iczhiku.com/weixin/message1640668908028.html]

尽管通常ESD保护的设计并非旨在防止EOS事件，但根据特定的应用和操作，上述器件的ESD保护的IC 设计风格确实可以影响EOS损坏导致的故障率。环境。图2说明了两个不同的骤回设备，其中设备1与设备2的设计相比相对安全。设备2的EOS风险增加是由于V Hold参数低于最大允许VDD。

CMOS集成电路闩锁效应 - 摘录

CMOS闩锁效应的发展

闩锁效应是以体CMOS工艺为基础的集成电路特有的现象，无论是一般的常规体CMOS工艺集成电路，还是从CMOS工艺衍生出来的BiCMO、BCD和HV-CMOS等，都会发生闩锁效应。

• 降低寄生BJT的放大系数
• 降低衬底等效电阻

双极型晶体管

双极型晶体管的四种工作模式下集电结和发射结外加偏置电压

1）正向有源：双极型晶体管的发射结正偏和集电结反偏。工作在正向有源区的双极型晶体管具有电流放大功能，它的放大系数是\(\beta\)，\(\beta\)是集电极电流与基极电流的比，\(\beta\)是一个非常关键的参数，通常双极型晶体管设计和制造工艺参数的变动都是为了获得足够大的\(\beta\)。正向有源是一种常用的工作区

2）饱和：双极型晶体管的发射结和集电结都正偏，它相当于两个并联的二极管。

3）倒置：双极型晶体管发射结反偏和集电结正偏。与正向有源相比，它们的角色倒置了。工作在倒置区的双极型晶体管也具有电流放大功能，不过其放大系数会比正向有源小几倍。实际应用中也很少会把双极型晶体管偏置在倒置区。

4）截止：双极型晶体管的发射结和集电结都反偏，其漏电流非常微弱，就像开路的开关

根据双极型晶体管的电极被输入和输出共用的情况，可以把双极型晶体管分为三种电路连接方式

双极型晶体管的击穿电压

双极型晶体管两个PN结的反向击穿电压有以下三种：

第一种是发射极开路时的BVCBO； 第二种是集电极开路时的BVEBO； 第三种是基极开路时的BVCEO。

这三个击穿电压的关系如下：BVCBO＞BVCEO＞BVEBO

NPN闩锁效应

在CMOS集成电路中，不仅寄生的PNPN结构会发生闩锁效应，单个NMOS自身寄生NPN也会发生闩锁效应

与PNPN类似，从寄生NPN I-V曲线可以看出，有两种方式可以使寄生NPN工作状态进入BC段的闩锁态：

• 第一种是出现瞬态激励电压大于等于Vt1，从而产生雪崩击穿电流，使寄生NPN进入闩锁态，这种方式称为电压触发；
• 第二种是出现瞬态激励电流，该电流大于等于B点对应的电流Ih，使寄生NPN进入闩锁态，这种方式称为电流触发。

Reference

Wang, Albert. Practical ESD Protection Design. John Wiley & Sons, 2021.

温德通. CMOS集成电路闩锁效应. 机械工业出版社, 2020

ANSI/ESDA/JEDEC JS-002-2022: ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) Device Level

ESDA/JEDEC JTR002-01-22: For the User Guide of ANSI/ESDA/JEDEC JS-002 Charged Device Model Testing of Integrated Circuits

JESD22-C101E: Field-Induced Charged-Device Model Test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components

M. Di, H. Wang, F. Zhang, C. Li, Z. Pan and A. Wang, "Does CDM ESD Protection Really Work?," 2019 IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, USA, 2019 [https://sci-hub.se/10.1109/WMED.2019.8714145]

M. Di, C. Li, Z. Pan and A. Wang, "Pad-Based CDM ESD Protection Methods Are Faulty," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 1297-1304, 2020 [pdf]

Introduction to Transmission Line Pulse (TLP), URL: https://tools.thermofisher.com/content/sfs/brochures/TLP%20Presentation%20May%202009.pdf

VF-TLP and CDM differences, URL: https://www.grundtech.com/app-note-vf-tlp-cdm-differences

ESD-Testing: HBM to very fast TLP URL: https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1-6, doi: 10.1109/CICC48029.2020.9075899.

KOEN DECOCK IEEE-SSCSLEUVEN "ON-CHIP ESD PROTECTION: BASIC CONCEPTS AND ADVANCED APPLICATIONS" [https://monthly-pulse.com/wp-content/uploads/2021/11/2021-11-sofics_presentation_ieee_final.pdf]

Yuanzhong Zhou, D. Connerney, R. Carroll and T. Luk, "Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models," Sixth international symposium on quality electronic design (isqed'05), 2005, pp. 476-481, doi: 10.1109/ISQED.2005.81.

Charged Device Model (CDM) Qualification Issues - Expanded [https://www.jedec.org/sites/default/files/IndustryCouncil_CDM_October2021_JEDECversion_September2022_rev1.pdf]

Wang, Albert ZH. On-chip ESD protection for integrated circuits: an IC design perspective. Vol. 663. Springer Science & Business Media, 2002.

Ker, Ming-Dou, and Sheng-Fu Hsu. Transient-induced latchup in CMOS integrated circuits. John Wiley & Sons, 2009. [https://picture.iczhiku.com/resource/eetop/wyiGjQaHOgrYFcxB.pdf]

Milin Zhang, "Low Power Circuit Design Using Advanced CMOS Technology" River Publishers 2018

Barry Fernelius, Evans Analytical Group. Latch-up Testing [https://site.ieee.org/ocs-cpmt/files/2013/06/Latch-up_at_EAG_IEEE_September_2013.pdf]

M. -D. Ker and Z. -H. Jiang, "Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions," in IEEE Journal of the Electron Devices Society, vol. 11, pp. 141-152, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9998049]

Shih-Hung Chen. CICC 2019. ES2-4 "ESD Challenges in Advanced FinFET & GAA Nanowire CMOS technologies"

Y. Li, M. Miao and R. Gauthier, "ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020

藍色天空. 版图Latch up DRC规则解读 [https://www.kaixinspace.com/latch-up-rule/]

—. 一文搞懂闩锁效应（Latch up）[https://www.kaixinspace.com/latch-up/]

Jitter separation lets you learn if the components of jitter are random or deterministic. That is, if they are caused by crosstalk, channel loss, or some other phenomenon. The identification of jitter and noise sources is critical when debugging failure sources in the transmission of high-speed serial signals

• Tail Fit Method
• Spectral method

Jitter Components

dual-Dirac model

Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-scale [https://people.engr.tamu.edu/spalermo/ecen689/jitter_dual_dirac_agilent.pdf]

Spectral method

power spectral density (PSD) represents jitter spectrum and peaks in the spectrum can be interpreted as PJ or DDJ, while the average noise floor is the power of RJ

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S1 = sum(win);
S2 = sum(win.^2);
N = length(win);
spec_nospur2 = (spec_nospur*S1).^2/N/S2;    % To obtain linear spectrum for rj
rj_utj = sqrt(sum(spec_nospur2))*1e12;

spec = 1*ones(length(spec_nospur), 1)*1e-21;
spec(index) = specx(index);
% insert fft nyquist frequency component between positive frequency and
% negative frequency component
% DC;posFreq;nyqFreq;negFreq
spec_ifft = [spec;specnyq;conj(spec(end:-1:2))]';
sfactor = sum(win)/sqrt(2);
spec_ifft = spec_ifft*sfactor;
sig_rec = real(ifft(spec_ifft));
sig_rec = sig_rec(:);
sig_rec_utj = sig_rec./win(1:end);

Tail Fit Method

Tail fitting algorithm based on the Gaussian tail model by using probability distribution of collected jitter value

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bin_sig = bin_sig*1e12;

x = qfuncinv(cdf_sig);

% coef(1)*bin_sig + coef(2) = x
% which x is norm(0, 1)
% bin_sig = (x - coef(2))/coef(1)
% Then bin is norm(-coef(2)/coef(1), 1/coef(1))
coef = polyfit(bin_sig, x, 1);
sigma = 1/coef(1);
mu = -coef(2)*sigma;

fprintf('sigma=%.3fps, mu=%.3fps\n', sigma, mu);

Least Squares (LS) method

It is known that TIE jitter is a linear equation, shown in below formula \[ x[n] = d_n \times \left[ \Delta t_{pj}[n]+\Delta t_{DCD}[n] +\Delta t_{ISI}[n]+\Delta t_{RJ}[n]\right] \] LS can be used to estimate the PJ, DCD, RJ , and ISI parameters \([a,b,J_{DCD},J_0, J_1...J_{(2^k-1)}]\)

Jitter modeling

Periodic Jitter (PJ)

PJ is a repeating jitter \[ \Delta t_{PJ}[n]=A\sin(2\pi f_0\cdot nT_s + \theta)=a \sin(2\pi f_0 \cdot nT_s)+b\cos(2\pi f_0 \cdot nT_s) \] where \(f_0\) represents the fundamental frequency of PJ; \(A\) is the amplitude of PJ; \(T_s\) is the data stream period, and \(\theta\) is the initial phase of PJ

In the spectrum, the frequency of maximum amount of the jitter is PJ frequency \(f_0\).

Duty Cycle Distortion (DCD)

DCD is viewed as a series of adjacent positive and negative impulses \[ \Delta t_{DCD}[n] = J_{DCD}\times (-1)^n = [-J_{DCD},J_{DCD},-J_{DCD},J_{DCD},...] \] Where \(J_{DCD}\) is the DCD amplitude.

Random Jitter (RJ)

RJ is created by unbounded jitter sources, such as Gaussian white noise. The statistical PDF for RJ is enerally treated as a Gaussian distribution \[ f_{RJ}(\Delta t) = \frac{1}{\sqrt{2\pi\sigma}}\exp(-\frac{(\Delta t)^2}{2\sigma^2}) \]

Remarks

Periodic Jitter Generator and Insertion

Analysis and Estimation of Jitter Sub-Components: Classification and Segregation of Jitter Components

DJ/RJ

K. Bidaj, J. -B. Begueret, N. Houdali, J. Deroo and S. Rieubon, "Time-domain PLL modeling and RJ/DJ jitter decomposition," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 2016 [https://sci-hub.se/10.1109/ISCAS.2016.7527201]

Reference

Mike Li. 2007. Jitter, noise, and signal integrity at high-speed (First. ed.). Prentice Hall Press, USA.

余宥浚 Jacky Yu, Keysight Taiwan AEO, Advanced Jitter and Eye-Diagram Analysis

Y. Duan and D. Chen, "Accurate jitter decomposition in high-speed links," 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, pp. 1-6, doi: 10.1109/VTS.2017.7928918.

Y. Duan's phd thesis URL: https://dr.lib.iastate.edu/handle/20.500.12876/30459

Y. Duan and D. Chen, "Fast and Accurate Decomposition of Deterministic Jitter Components in High-Speed Links," in IEEE Transactions on Electromagnetic Compatibility, vol. 61, no. 1, pp. 217-225, Feb. 2019, doi: 10.1109/TEMC.2018.2797122.

"Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-Scale", Whitepaper: Keysight Technologies, U.S.A., Dec. 2017

Sharma, Vijender Kumar and Sujay Deb. "Analysis and Estimation of Jitter Sub-Components." (2014).

Qingqi Dou and J. A. Abraham, "Jitter decomposition in ring oscillators," Asia and South Pacific Conference on Design Automation, 2006

E. Balestrieri, L. De Vito, F. Lamonaca, F. Picariello, S. Rapuano and I. Tudosa, "The jitter measurement ways: The jitter decomposition," in IEEE Instrumentation & Measurement Magazine, vol. 23, no. 7, pp. 3-12, Oct. 2020, doi: 10.1109/MIM.2020.9234759.

McClure, Mark Scott. "Digital jitter measurement and separation." PhD diss., 2005.

Ren, Nan, Zaiming Fu, Shengcu Lei, Hanglin Liu, and Shulin Tian. "Jitter generation model based on timing modulation and cross point calibration for jitter decomposition." Metrology and Measurement Systems 28, no. 1 (2021).

M. P. Li, J. Wilstrup, R. Jessen and D. Petrich, "A new method for jitter decomposition through its distribution tail fitting," International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, pp. 788-794, doi: 10.1109/TEST.1999.805809.

K. Bidaj, J. -B. Begueret and J. Deroo, "RJ/DJ jitter decomposition technique for high speed links," 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) [https://sci-hub.se/10.1109/ICECS.2016.7841269]

divide-by-1.5 circuit

TODO 📅

Phase Interpolator

A phase interpolator (PI) is normally used as a phase shifter (or phase rotator) to generate an output clock whose phase is precisely controlled

TODO 📅

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023. [http://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf]

Deterministic Jitter

j_Djpp can be calculated by PSD,too

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fck = 38.4e6;
Nfft = 15000;
fres = fck/Nfft;
psddBc = -99.3343;
psBc = psddBc + 10*log10(fres);	% psd -> ps; 
phrad2 = 10^(psBc/10);
phrms = sqrt(phrad2);
Jrms = phrms/2/pi*1/fck;
Jpp = 2*sqrt(2)*Jrms;

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Jpp =

   6.4038e-12

For DJ, we usually use peak to peak value

BTW, the psd value at half of fundamental frequency (\(f_s/2\)) is duty cycle distortion due to the NMOS/PMOS imbalance, because of rising only data

Random Jitter

RJ can be accurately and efficiently measured using PSS/Pnoise or HB/HBnoise.

Note that the transient noise can also be used to compute RJ;

However, the computation cost is typically very high, and the accuracy is lesser as compared to PSS/Pnoise and HB/HBnoise.

Since RJ follows a Gaussian distribution, it can be fully characterized using its Root-Mean-Squared value (RMS) or the standard deviation value (\(\sigma\))

The Peak-to-Peak value of RJ (\(\text{RJ}_{\text{p-p}}\)) can be calculated under certain observation conditions \[ \text{RJ}_{\text{p-p}}\equiv K \ast \text{RJ}_{\text{RMS}} \] Here, \(K\) is a constant determined by the BER specification of the system given in the following Table

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K = 14.698;
Ks = K/2;
p = normcdf([-Ks Ks]);
BER = 1 - (p(2)-p(1));

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BER =

   1.9962e-13

Total Jitter

\[ \text{TJ}_{\text{p-p}}\equiv \text{DJ}_{\text{p-p}} + \text{RJ}_{\text{p-p}}(\text{BER}) \]

In the psd of TJ, the spur is DJ and floor is RJ

Phase Noise to Jitter

The phase noise is traditionally defined as the ratio of the power of the signal in 1Hz bandwidth at offset \(f\) from the carrier \(P\), divided by the power of the carrier \[ \ell (f) = \frac {S_v'(f_0+f)}{P} \] where \(S_v'\) is is one-sided voltage PSD and \(f \geqslant 0\)

Under narrow angle assumption \[ S_{\varphi}(f)= \frac {S_v'(f_0+f)}{P} \] where \(\forall f\in \left[-\infty +\infty\right]\)

Using the Wiener-Khinchin theorem, it is possible to easily derive the variance of the absolute jitter(\(J_{ee}\))via integration of the corresponding PSD \[ J_{ee,rms}^2 = \int S_{J_{ee}}(f)df \]

And we know the relationship between absolute jitter and excess phase is \[ J_{ee}=\frac {\varphi}{\omega_0} \] Considering that phase noise is normally symmetrical about the zero frequency, multiplied by two is shown as below \[ J_{ee,rms} = \frac{\sqrt{2\int_{0}^{+\infty}\ell(f)df}}{\omega_0} \] where phase noise is in linear units not in logarithmic ones.

Because the unit of phase noise in Spectre-RF is logarithmic unit (dBc), we have to convert the unit before applying the above equation \[ \ell[linear] = 10^{\frac {\ell [dBc/Hz]}{10}} \] The complete equation using the simulation result of Spectre-RF Pnoise is \[ J_{ee,rms} = \frac{\sqrt{2\int_{0}^{+\infty}10^{\frac {\ell [dBc/Hz]}{10}}df}}{\omega_0} \]

The above equation has been verified for sampled pnoise, i.e. J_ee and Edge Phase Noise.

• For pnoise-sampled(jitter), Direct Plot Form - Function: Jee:Integration Limits can calculate it conveniently
• But for pnoise-timeaveage, you have to use the below equation to get RMS jitter.

One example, integrate to \(\frac{f_{osc}}{2}\) and \(f_{osc} = 16GHz\)

Of course, it apply to conventional pnoise simulation.

On the other hand, output rms voltage noise, \(V_{out,rms}\) divied by slope should be close to \(J_{ee,rms}\) \[ J_{ee,rms} = \frac {V_{out,rms}}{slope} \]

Pulse Width Jitter (PWJ)

TODO 📅

[Spectre Tech Tips: Measuring Noise in Digital Circuits]

Pnoise sampled: Edge Delay mode measures the noise defined by two edges. Both edges are defined by a threshold voltage and rising or falling edges, which measures the noise of the pulse itself and direct plot calculate the variation of the pulse width

Power supply induced jitter (PSIJ)

A sampled pxf analysis can be used to simulate the deterministic jitter of a circuit due to power supply ripple

TODO 📅

DCC & AC-coupled buffer

The amount of correction can be set by intentional injection of an offset current into the summing input node of INV, threshold-adjustable inverter

Note that the change to the threshold is opposite in direction to the change to INV

increasing DC of input signal is equivalent to lower down the threshold of INV

voltage at INV1 will increased by: \[ \frac{\Delta V_{DAC} - \Delta {INV1}}{R_{DAC}} = \frac{\Delta {INV1} +A_0 \Delta {INV1}}{R_{F}} \] therefore \[ \Delta {INV1} = \Delta V_{DAC} \cdot \frac{R_F}{R_F+(A_0+1)R_{DAC}} \approx \Delta V_{DAC} \cdot \frac{R_F}{A_0R_{DAC}} \]

variable \(R_{DAC}\) can be used to tweak tuning resolution & range

If \(R_{DAC} = R_F\) \[ \Delta {INV1}\approx \frac{\Delta V_{DAC}}{A_0} \]

C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS," 2018 IEEE International Solid-State Circuits Conference - (ISSCC) [https://sci-hub.se/https://doi.org/10.1109/ISSCC.2018.8310205],[visual]

M. A. Kossel et al., "8.3 An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021[https://sci-hub.se/10.1109/ISSCC42613.2021.9365784]

C. Menolfi et al., "A 28Gb/s source-series terminated TX in 32nm CMOS SOI," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2012

Bob Lefferts, Navraj Nandra. SNUG Israel 2007 [https://picture.iczhiku.com/resource/eetop/whKYwQorwYoPUVbm.pdf]

Since duty-cycle error is high frequency component, the high-pass filter suppresses the duty-cycle error propagating to the output

• The AC-coupling capacitor blocks the low-frequency component of the input
• The feedback resistor sets common mode voltage to the crossover voltage

Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices, 2020)

Casper B, O'Mahony F. Clocking analysis, implementation and measurement techniques for high-speed data links: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers. 2009;56(1):17-39

reference

Article (20500632) Title: How to simulate Random and Deterministic Jitters URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fiXeEAI

Spectre Tech Tips: Measuring Noise in Digital Circuits - Analog/Custom Design - Cadence Blogs - Cadence Community https://community.cadence.com/cadence_blogs_8/b/cic/posts/s . . .

Cadence RAK: Deterministic Jitter Measurement using SpectreRF

Frank Wiedmann. Using sampled pxf analysis to simulate deterministic jitter [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/51605/using-sampled-pxf-analysis-to-simulate-deterministic-jitter]

supply noise sensitivity: PSS+PAC or PSS+PX [https://designers-guide.org/forum/YaBB.pl?num=1376500816]

J. Kim et al., "A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 29-42, Jan. 2019, doi: 10.1109/JSSC.2018.2874040

— et al., "A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 6-20, Jan. 2022, doi: 10.1109/JSSC.2021.3108969

J. N. Tripathi, V. K. Sharma and H. Shrimali, "A Review on Power Supply Induced Jitter," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 3, pp. 511-524, March 2019 [https://sci-hub.st/10.1109/TCPMT.2018.2872608]

H. Kim, J. Fan and C. Hwang, "Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains," 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Washington, DC, USA, 2017 [https://sci-hub.st/10.1109/ISEMC.2017.8077937]

Yin Sun, Chulsoon Hwang EMC Laboratory. Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model [https://ibis.org/summits/aug20/sun.pdf]

High Speed Communications Part 8 – On Die CMOS Clock Distribution. [https://youtu.be/nx5CiHcwrF0?si=-eSO-LaaaFrVuIA1]

Low-Jitter CMOS Clock Distribution [https://youtu.be/LMT-T41Y64U?si=y8IpWCtU90zpe4Ob]

Mo, Xunjun & Wu, Jiaqi & Wary, Nijwm & Carusone, Tony. (2021). Design Methodologies for Low-Jitter CMOS Clock Distribution. IEEE Open Journal of the Solid-State Circuits Society. 1. 94-103. 10.1109/OJSSCS.2021.3117930. [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9559395]

Mozhgan Mansuri. ISSCC2021 SC3: Clocking, Clock Distribution, and Clock Management in Wireline/Wireless Subsystems [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC3.pdf]

Phillip Restle. ISSCC2021 SC4: Processor Clock Generation, Distribution, and Clock Sensor/Management Loops [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC4.pdf]

Sam Palermo. Spring 2025 ECEN720 : High-Speed Links Circuits and Systems [Lecture 14: Clock Distribution Techniques]