KNOW-HOW

Terminology

The most accurate method to calculate the degradation of transistors is the SPICE-level simulation of the whole netlist with application programming interface (API) and industry-standard stress process models

​ MOSRA: MOSFET reliability analysis Synopsys

​ RelXpert: Cadence

​ TMI: TSMC Model Interface, TSMC

​ OMI: Open Model Interface, Si2 standard,

The Silicon Integration Initiative (Si2) Compact Model Coalition has released the Open Model Interface, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions.OMI allows circuit designers to simulate and analyze such important physical effects as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014.

• TDDB: Time-Dependent Dielectric Breakdown
• HCI: Hot Carrier injection
• BTI: Bias Temperature Instability
  • NBTI: Negative Bias Temperature Instability
  • PBTI: Positive Bias Temperature Instability
• SHE: Self-Heating Effect

Aging & SHE in FinFET

SHE

Self-Heating & EM

Heat Sink (HS)

1. guard ring

   closer OD help reduce dT

2. extended gate

3. source/drain metal stack

BTI

BTI occurs predominantly in PMOS (or p-type or p channel) transistors and causes an increase in the transistor's absolute threshold voltage.

Stress in the case of NBTI means that the PMOS transistor is in inversion; that means that its gate to body potential is substantially below 0 V for analogue circuits or at VGB = −VDD for digital circuits

Higher voltages and higher temperatures both have an exponential impact onto the degradation, induced by NBTI.

NBTI will be accelaerated with thinner gate oxide, at a high temperature and at a high electric field across the oxide region.

During recovery phase where the gate voltage of pMOS is high and stress is removed, the H atoms in the gate oxiede diffuse back to Si-SiO2 interface and the recombination of Si-H bonds reduces the threshold voltage of pMOS.

The net result is an increase in the magnitude of the device threshold voltage |Vt|, and a degradation of the channel carrier mobility.

Caution: The aging model provided by fab may NOT contain recovry effect

HCI

Short-channel MOSFETs may exprience high lateral electric fields if the drain-source voltage is large. while the average velocity of carriers saturate at high fields, the instantaneous velocity and hence the kinetic energy of the carriers continue to increase, especially as they accelerate toward the drain. These are called hot carriers.

In nanometer technologies, hot carrier effects have subsided. This is because the energy required to create an electron-hole pair, \(E_g \simeq 1.12 eV\), is simply not available if the supply voltage is around 1V.

\[ F_E= E \cdot q \]

\[\begin{align} E_k &= F_E \cdot s \\ &= E \cdot q \cdot s \end{align}\]

Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, degrading the current-voltage characteristics of the MOSFET.

The channel hot-electron (CHE) effect is caused by electons flowing in the channel region, from the source to the drain. This effect is more pronounced at large drain-to-source voltage, at which the lateral electric field in the drain end of the channel accelerates the electrons.

Four different hot carrier injectoin mechanisms can be distinguished: - channel hot electron (CHE) injection - drain avalanche hot carrier (DAHC) injection - secondary generated hot electron (SGHE) injection - substrate hot electron (SHE) injection

HCI is more of a drain-localized mechanism, and is primarily a carrier mobility degradation (and a Vt degradation if the device is operated bi-directionally).

For smaller transistor dimensions, CHE dominates the hot carrier degradation effect

The hot-carrier induced damage in nMOS transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both.

The damage caused by hot-carrier injection affects the transistor characteristics by causing a degradation in transconductance, a shift in the threshold voltage, and a general decrease in the drain current capability.

HCI seems to have just a weak temperature dependency. Unlike BTI, it seems to be no or just little recovery. As holes are much "cooler" (i.e. heavier) than electrons, the channel hot carrier effect in nMOS devices is shown to be more significant than in pMOS devices.

Degradation saturation effect

HCI model can reproduce the saturation effect if stress time is long enough

TDDB

TDDB effect is also related to oxide traps. In general, TDDB refers to the loss of isolating properties of a dielectric layer. If this dielectric layer is the gate oxide, TDDB will initially lead to an increase in the gate tunnelling current.

This soft breakdown can already lead to a parametric degradation. After a long accumulation period, TDDB leads to a catastrophic reduction of the channel to gate insulation and thus a functional failure of the transistor.

Scaling drive more concerns in TDDB

waveform-dependent nature

The figure below illustrates the waveform-dependent nature of these mechanisms – as described earlier, BTI and HCI depend upon the region of active device operation. The slew rate of the circuit inputs and output will have a significant impact upon these mechanisms, especially HCI.

• Negative bias temperature instability (NBTI). This is caused by constant electric fields degrading the dielectric, which in turn causes the threshold voltage of the transistor to degrade. That leads to lower switching speeds. This effect depends on the activity level of the circuits, with heavier impact on parts of the design that don’t switch as often, such as gated clocks, control logic, and reset, programming and test circuitry.
• Hot carrier injection (HCI). This is caused by fast-moving electrons inserting themselves into the gate and degrading performance. It primarily occurs on higher-voltage modes and fast switching signals.

• longer channel length help both BTI and HCI
• larger \(V_{ds}\) help BTI, but hurt HCI
• lower temperature help BTI of core device, but hurt that of IO device for 7nm FinFET

MOSRA

MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age analysis

TMI

BTI recovery effect NOT included for N7

Stochastic Nature of Reliability Mechanisms

A fraction of devices will fail

Circuit Simulations

reference

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out - Analog/Custom Design (Analog/Custom design) - Cadence Blogs - Cadence Community https://shar.es/afd31p

S. Liao, C. Huang, and A. C. J. X. T. Guo, "New Generation Reliability Model," Dec 2016. [Online]. Available: http://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf. [Accessed Aug 2018]

Tianlei Guo, Jushan Xie, "A Complete Reliability Solution: Reliability Modeling, Applications, and Integration in Analog Design Environment" [https://mos-ak.org/beijing_2018/presentations/Tianlei_Guo_MOS-AK_Beijing_2018.pdf]

FinFET Reliability Analysis with Device Self-Heating via @DanielNenni https://semiwiki.com/eda/synopsys/5085-finfet-reliability-analysis-with-device-self-heating/

Chris Changze Liu 刘长泽,Hisilicon, Huawei, "Reliability Challenges in Advanced Technology Node" https://www.tek.com.cn/sites/default/files/2018-09/reliability-challenges-in-advanced-technology-node.pdf

Ben Kaczer, imec. FEOL reliability: from essentials to advanced and emerging devices and circuits. 2016 IRPS Tutorial

Ben Kaczer, imec. Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation. 2016 IEDM 2016 [link]

Kang, Sung-Mo Steve, Yusuf Leblebici and Chulwoo Kim. “CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition.” (2014).

Behzad Razavi. "Design of Analog CMOS Integrated Circuits" (2016)

Basel Halak. Ageing of Integrated Circuits : Causes, Effects and Mitigation Techniques. Cham, Switzerland: Springer, 2020. ‌

Elie Maricau, and Georges Gielen. Analog IC Reliability in Nanometer CMOS. Springer Science & Business Media, 2013. ‌

Transistor Aging Intensifies At 10/7nm And Below https://semiengineering.com/transistor-aging-intensifies-10nm/

Modeling Effects of Dynamic BTI Degradation on Analog and Mixed-Signal CMOS Circuits. MOS-AK/GSA Workshop, April 11-12, 2013, Munich https://www.mos-ak.org/munich_2013/presentations/05_Leonhard_Heiss_MOS-AK_Munich_2013.pdf

Challenges and Solutions in Modeling and Simulation of Device Self-heating, Reliability Aging and Statistical Variability Effects https://www.mos-ak.org/beijing_2018/presentations/Dehuang_Wu_MOS-AK_Beijing_2018.pdf

New Generation Reliability Model https://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf

FinFET SPICE Modeling: Synopsys Solutions to Simulation Challenges of Advanced Technology Nodes https://www.mos-ak.org/washington_dc_2015/presentations/T03_Joddy_Wang_MOS-AK_Washington_DC_2015.pdf

A. Zhang et al., "Reliability variability simulation methodology for IC design: An EDA perspective," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2015, pp. 11.5.1-11.5.4, doi: 10.1109/IEDM.2015.7409677.

W. -K. Lee et al., "Unifying self-heating and aging simulations with TMI2," 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan, 2014, pp. 333-336, doi: 10.1109/SISPAD.2014.6931631.

Aging and Self-Heating in FinFETs - Breakfast Bytes - Cadence Blogs - Cadence Community https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/aging-and-self-heating

Article (20482350) Title: Measure the Impact of Aging in Spectre Technology URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESBFUA4

Karimi, Naghmeh, Thorben Moos and Amir Moradi. “Exploring the Effect of Device Aging on Static Power Analysis Attacks.” IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (2019): 233-256.[link]

Self-Heating Issues Spread https://semiengineering.com/self-heating-issues-spread/

Y. Zhao and Y. Qu, "Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 829-836, 2019, doi: 10.1109/JEDS.2019.2911085.

Design Considerations

Modeling Consideration

\[\begin{align} R_{d1} &\propto \frac{1}{N_{fins}} \\ R_{s1} &\propto \frac{1}{N_{fins}} \\ R_{g1} &\propto N_{fins} \\ C_{gd} &\propto N_{fins} \cdot N_{fingers} \cdot N_{multipler} \\ C_{gs} &= Cgd \\ C_{g1d} &\propto N_{fins} \\ C_{g1s} &= C_{g1d} \\ C_{g1d1} &\propto N_{fins} \\ C_{g1s1} &= C_{g1d1} \\ C_{g1d1} &\simeq 2\times C_{g1d} \end{align}\]

Layout Consideration

PODE & CPODE

The PODE devices is extracted as parasitic devices in post-layout netlist

DDB is the PODE (Poly on OD/Diffusion Edge) in TSMC 16FFC process.

SDB is the CPODE (Connected PODE) in TSMC 16FFC process.

PO on OD edge (PODE) is a must and to define GATE that abuts OD vertical edge

CPODE is used to connect two PODE cells together. It will isolate OD to save 1 poly pitch, via STI; Additional mask (12N) is required for manufacture

SAC & SAGC

self-aligned diffusion contacts (SACs)

As shown in Fig. 35 in older planar technology nodes, gate pitch is so relaxed such that S/D contacts and gate contacts can easily be placed next to each other without causing any shorting risk (see Fig. 35(a)).

As the gate pitch scales, there’s no room to put gate contacts next to S/D contacts, and gatecontacts have been pushed away from the active region and are only placed on the STI region.

In addition, at tight gate pitch, even forming S/D contact without shorting to gate metal becomes very challenging.

The idea of self-aligned contacts (SAC) has been introduced to mitigate the issue of S/D contact to gate shorts.

As shown in Fig. 35(b), the gate metal is fully encapsulated by a dielectric spacer and gate cap, which protects the gate from shorting to the S/D contact.

A dielectric cap is added on top of the gate so that if the contact overlaps the gate, no short occurs.

MD layer represent SACs in PDK

self-aligned gate contacts (SAGCs)

Self-aligned gate contacts (SAGCs) have also been implemented and Denser standard cells can be achieved by eliminating the need to land contacts on the gate outside the active area.

SAGCs require the source/drain contacts to be capped with an insulator that is different from both contact and gate cap dielectrics to protect the source/drain contacts against a misaligned gate contact etch.

According to the DRC of T foundary, poly extension > 0 um and space between MP and OD > 0 um., which demonstrate self-aligned gate contact is not introduced.

Contacted-Poly-Pitch (CPP)

Wider Contacted-Poly-Pitch allows wider MD and VD size, which help reduce MEOL IRdrop

Naoto Horiguchi. Entering the Nanosheet Transistor Era [link]

Gate Resistance

non-quasistatic (NQS) effect

reference

Tom Quan, TSMC, Bob Lefferts, Fred Sendig, Synopsys, Custom Design with FinFETs - Best practices designing mixed-signal IP

Jacob, Ajey & Xie, Ruilong & Sung, Min & Liebmann, Lars & Lee, Rinus & Taylor, Bill. (2017). Scaling Challenges for Advanced CMOS Devices. International Journal of High Speed Electronics and Systems. 26. 1740001. 10.1142/S0129156417400018.

Joddy Wang, Synopsys "FinFET SPICE Modeling" Modeling of Systems and Parameter Extraction Working Group 8th International MOS-AK Workshop (co-located with the IEDM Conference and CMC Meeting) Washington DC, December 9 2015

A. L. S. Loke et al., "Analog/mixed-signal design challenges in 7-nm CMOS and beyond," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-8, doi: 10.1109/CICC.2018.8357060.[slides]

Prof. Adam Teman, Advanced Process Technologies, [pdf]

Luke Collins. FinFET variability issues challenge advantages of new process [link]

Loke, Alvin. (2020). FinFET technology considerations for circuit design (invited short course). BCICTS 2020 Monterey, CA

Alvin Leng Sun Loke, TSMC. Device and Physical Design Considerations for Circuits in FinFET Technology", ISSCC 2020

Prof. Adam Teman. Advanced Process Technologies [pdf]

A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

A. L. S. Loke, Migrating Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm. 2016 Symposia on VLSI Technology and Circuits

Lattice Semiconductor, 16FFC Process Technology Introduction December 9th, 2021[pdf]

timing_aocv_derate_mode

1

timing_aocv_derate_mode{aocv_multiplicative | aocv_additive}

Default: aocv_multiplicative

Controls the AOCV derating mode.

When set to aocv_multiplicative, the derating factor will be calculated as AOCV derating * OCV derating, which is set using the set_timing_derate command.

When set to aocv_additive, the derating factor will be calculated as AOCV derating + OCV derating values.

When you use this global variable, the report_timing command shows the total_derate column in the timing report output, which allows you to view and cross-check the calculated total derate factor.

To set this global variable, use the set_global command.

reference

Genus Attribute Reference 22.1

Innovus Text Command Reference 22.10

Article (20416394) Title: Analysis with Advanced On-chip Variation (AOCV) derating in EDI system and ETS URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050NxEAI

1. Common Centroid

   The common centroid technique describes that if there are n blocks which are to be matched then the blocks are arranged symmetrically around the common centre at equal distances from the centre. This technique offers best matching for devices as it helps in avoiding cross-chip gradients

   

2. Inter-digitation

   Interdigitation reduces the device mismatch as it suffers equally from process variations in X dimension. This technique was used to layout current mirrors and resistors in PTAT and BGR circuits. In the Figure-15 below each brown stick represents a PFET of uniform length. This representation is termed as an inter-digitated layout.

   

reference

Mikael Sahrling, Layout Techniques for Integrated Circuit Designers 1st Edition , Artech House 2022

LAYOUT, EE6350 VLSI Design Lab SMART TEMPERATURE SENSOR URL: https://www.ee.columbia.edu/~kinget/EE6350_S16/06_TEMPSENS_Sukanya_Vani/layout.html

temperature coefficient

The parameter that shows the dependence of the reference voltage on temperature variation is called the temperature coefficient and is defined as: \[ TC_F=\frac{1}{V_{\text{REF}}}\left[ \frac{V_{\text{max}}-V_{\text{min}}}{T_{\text{max}}-T_{\text{min}}} \right]\times10^6\;ppm/^oC \]

Choice of n

classic bandgap reference

\[ V_{bg} = \frac{\Delta V_{be}}{R_1} (R_1+R_2) + V_{be2} = \frac{\Delta V_{be}}{R_1} R_2 + V_{be1} \]

\[ V_{bg} = \left(\frac{\Delta V_{be}}{R_1} + \frac{V_{be1}}{R_2}\right)R_3 = \left(\frac{\Delta V_{be}}{R_1} R_2 + V_{be1}\right)\frac{R_3}{R_2} \]

OTA offset effect

\[\begin{align} V_{be1} &= \frac{kT}{q}\ln(\frac{I_{e1}}{I_{ss}}) \\ V_{be2} &= \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \end{align}\]

Here, we assume \(I_e = I_c\)

Hence,

\[\begin{align} \Delta V_{be} &= \frac{kT}{q}\ln(n\frac{I_{e1}}{I_{e2}}) \\ &= \frac{kT}{q}\ln(n) + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \\ &= \Delta V_{be,0} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \end{align}\]

Therefore,

\[\begin{align} V_{bg} &= \frac{\Delta V_{be}+V_{os}}{R_2}(R_1+R_2) + V_{be2} \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}})+\frac{kT}{q}\ln(\frac{I_{e2}}{I_{e2,0}}) \end{align}\]

We omit the last part \[\begin{align} V_{bg} &\approx \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + V_{be2,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \\ &= V_{bg,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \end{align}\]

i.e. the bg variation due to OTA offset \[ \Delta V_{bg} \approx \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \]

• \(V_{os} \gt 0\)

​ \(I_{e1} \gt I_{e2}\): \(\Delta V_{bg} \gt \alpha V_{os}\)

• \(V_{os} \lt 0\)

​ \(I_{e1} \lt I_{e2}\): \(\Delta V_{bg} \lt \alpha V_{os}\)

reference

ECEN 607 (ESS) Bandgap Reference: Basics URL:https://people.engr.tamu.edu/s-sanchez/607%20Lect%204%20Bandgap-2009.pdf

use SpiceIn GUI feature to map MOS parameter correctly in generated schematic

Input

The mos's total width (parameter name "w") value will update during SpiceIn trigger CDF callback automatically

Output

Device Map

User Prop Mapping is significant setup, both xxx.spi and Edit CDF provide the essential information.

The map syntax is spice_para0 cdf_para0 spice_para1 cdf_para01 ... spice_paraN cdf_paraN

reference

Article (20488179) Title: How to use SpiceIn GUI feature to map MOS parameter correctly in generated schematic URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdPWEAY

Article (11724692) Title: SpiceIn maps the netlist parameter to the CDF parameter incorrectly on the generated schematic devices (e.g. w to wf) URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nZ2CEAU

Using Red Hat Enterprise Linux 8, Rocky Linux 8 and the GNOME 3 window manager, the new Virtuoso Schematic/Layout/ADE windows and forms sometimes pop up under or below the Library Manager or on the desktop in the background instead of the foreground and cannot be seen. Sometimes, they are iconized; they do not come on the top in front, though it is the most recent window opened.

solution

Install Focus my window GNOME Shell extension

reference

Article (11612426) Title: New windows and forms appear behind the Library Manager in background or iconized instead of foreground on RHEL and SuSE Linux in GNOME, KDE Desktop, Metacity window manager URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nSXCEA2

MOS capacitances

• oxide capacitance between the gate and the channel \(C_1=WLC_{ox}\)
• depletion capacitance between the channel and the substrate
• junction capacitance between the source/drain areas and the substrate
  • The value of \(C_{SB}\) and \(C_{DB}\) is a function of the source and drain voltages with respect to the substrate

The gate-bulk capacitance is usually neglected in the triode and saturation regions because the inversion layer acts as a "shield" between the gate and the bulk.

Temperature Dependence of Junction Diode CV

where TCJ and TCJSW are positive

https://cmosedu.com/cmos1/BSIM4_manual.pdf

D=S=B varactor

Inversion-mode (I-MOS)

Accumulation-mode (A-MOS)

NMOS in NWELL, aka NMOS in N-Well varactor

Notice: S/D and NWELL are connected togethor in layout

PDK varactor

nmoscap: NMOS in N-Well varactor

• Base Band MOSCAP model (nmoscap) is built without effective series resistance (ESR) and effective series inductance (ESL) calibrations, which is for capacitance simulation only
• LC-Tank MOSCAP model (moscap_rf) is for frequency-dependent Q factor and capacitance simulations

MOS Device as Capacitor

Voltage dependence

• capacitance of MOS gate varies nonmonotonically with \(V_{GS}\)

• "accumulation-mode" varactor varies monotonically with \(V_{GS}\)

Inverter capacitance

reference

R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs," in IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003, doi: 10.1109/JSSC.2003.814416.

T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee and S. S. Wong, "Analysis and optimization of accumulation-mode varactor for RF ICs," 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), 1998, pp. 32-33, doi: 10.1109/VLSIC.1998.687993. URL: http://www-smirc.stanford.edu/papers/VLSI98s-chet.pdf

R. Jacob Baker, 6.1 MOSFET Capacitance Overview/Review, CMOS Circuit Design, Layout, and Simulation, Fourth Edition

B. Razavi, Design of Analog CMOS Integrated Circuits 2nd

none:

​ Does not save any data (currently does save one node chosen at random)

selected:

​ Saves only signals specified with save statements. The default setting.

lvlpub:

Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.

lvl:

​ Saves all signals up to nestlvl deep in the subcircuit hierarchy. This option is relevant for subcircuits.

allpub:

​ Saves only signals that are normally useful.

all:

​ Saves all signals.

Signals that are "normally useful" include the shared node voltages and currents through voltage sources and iprobes, and exclude the internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain, source on a FET, and so on). It also excludes currents through inductors, controlled sources, transmission lines, transformers, etc.

If you use lvl or all instead of lvlpub or allpub, you will also get internal node voltages and currents through other components that happen to compute current.

Thus, using *pub excludes internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain and source on a FET, etc). It also excludes the currents through inductors, controlled sources, transmission lines, transformers, etc.

nestlvl

This variable is used to save groups of signals as results and when signals are saved in subcircuits. The nestlvl parameter also specifies how many levels deep into the subcircuit hierarchy you want to save signals.