KNOW-HOW

Copper Pillar Bump vs Solder bump

Cu-pillar bumping is a next-generation flip chip interconnection between chip & packages, especially for fine pitch applications

• On the wafer end, comparing to solder bump, cu-pillar bump provides the advantage of fine pitch; the die size can be reduced about 5~10%.

• On the package end, the substrate layer can be reduced from 6 layers to 4 layers by fine pitch and bump on trace process and using simplified substrate process.

Why Your Symmetric Layouts Are Showing Mismatches in SPICE Simulations

[https://www.ansys.com/blog/symmetric-layouts-showing-mismatches-spice-simulations]

The root cause of the delay mismatch is related to how parasitic extraction tools distribute coupling capacitances over the nodes of the resistive networks

The most likely reason for such asymmetry is the anisotropy of computational geometry algorithms used by extraction tools.

STRAP

A "strap" refers to a low-impedance connection

NWDMY = NWDMY1, NWDMY2

STRAP = NWSTRAP or PWSTRAP

NWSTRAP = {NP & OD} & {NW not {NW INTERACT NWDMY}}

PWSTRAP = {PP & OD} not NW

Calibre Rule::NOT

Calibre Rule::INTERACT

Antenna Effect

The antenna effect is a common name for the effects of charge accumulation in isolated nodes of an integrated circuit during its processing.

This effect is also sometimes called "Plasma Induced Damage", "Process Induced Damage" (PID) or "charging effect".

antenna ratio

The antenna rule specifies the maximum tolerance for the ratio of a metal line area to the area of connected gates.

metal jumping

Long metal can be taken to higher metal routing layer. This is known as metal jumping.

This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

Diode Insertion

Diode helps dissipate charges accumulated on metal. Diode should be placed as near as possible to the gate of device on low level of metal.

Diode should always be connected in reverse bias, with cathode connected to gate electrode and anode connected to ground potential.

During processing, even if the diodes are reversely biased, because of the elevated wafer temperature (\(200 ^oC\) plus) it will provide a much conductive path

In the reverse bias region, the reverse saturation current of Si and Ge diodes doubles for every \(10 ^oC\) rise in temperature

Tuvia Liran, Antenna effect (PID): Do the design rules really protect us? [link]

Upma Pawan Kumar, Sunandan Chaubey, Antenna Effect in 16nm Technology Node [link]

pulsic.com, Analog layout – Stop the antenna effect from destroying your circuit [link]

BuBuChen, 積體電路的天線效應 (Antenna Effect in IC) [link]

EDN, Antenna violations resolved using new method [link]

edaboard.com, why jump up metal can solve the antenna effect? [link]

siliconvlsi.com, Antenna effect [link]

Prof. Adam Teman, Digital VLSI Design. Lecture-10-The-Manufacturing-Process [pdf]

Zongjian Chen, Processing and Reliability Issues That Impact Design Practice. [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/lect_15_2up.pdf]

Shallow Trench Isolation (STI)

drain and source sharing

Planar process vs. FinFet process

Standard Cell Tapcell

Guard Ring in Custom block

Place well tie and substrate tie where they are needed. Redundant guard ring consume area and increase the routing of critical signal net.

Continuous OD

Performance & Matching

current mirror

split diffusion with dummy transistors

cascode structure

off transistor split diffusion

sharing source & drain

Stacked MOSFETs

Matching

1. Common Centroid

   The common centroid technique describes that if there are n blocks which are to be matched then the blocks are arranged symmetrically around the common centre at equal distances from the centre. This technique offers best matching for devices as it helps in avoiding cross-chip gradients

   

2. Inter-digitation

   Interdigitation reduces the device mismatch as it suffers equally from process variations in X dimension. This technique was used to layout current mirrors and resistors in PTAT and BGR circuits. In the Figure-15 below each brown stick represents a PFET of uniform length. This representation is termed as an inter-digitated layout.

   

Design with FinFETs

Modeling Consideration

\[\begin{align} R_{d1} &\propto \frac{1}{N_{fins}} \\ R_{s1} &\propto \frac{1}{N_{fins}} \\ R_{g1} &\propto N_{fins} \\ C_{gd} &\propto N_{fins} \cdot N_{fingers} \cdot N_{multipler} \\ C_{gs} &= Cgd \\ C_{g1d} &\propto N_{fins} \\ C_{g1s} &= C_{g1d} \\ C_{g1d1} &\propto N_{fins} \\ C_{g1s1} &= C_{g1d1} \\ C_{g1d1} &\simeq 2\times C_{g1d} \end{align}\]

Layout Consideration

PODE & CPODE

The PODE devices is extracted as parasitic devices in post-layout netlist

DDB is the PODE (Poly on OD/Diffusion Edge) in TSMC 16FFC process.

SDB is the CPODE (Connected PODE) in TSMC 16FFC process.

PO on OD edge (PODE) is a must and to define GATE that abuts OD vertical edge

CPODE is used to connect two PODE cells together. It will isolate OD to save 1 poly pitch, via STI; Additional mask (12N) is required for manufacture

SAC & SAGC

self-aligned diffusion contacts (SACs)

As shown in Fig. 35 in older planar technology nodes, gate pitch is so relaxed such that S/D contacts and gate contacts can easily be placed next to each other without causing any shorting risk (see Fig. 35(a)).

As the gate pitch scales, there’s no room to put gate contacts next to S/D contacts, and gatecontacts have been pushed away from the active region and are only placed on the STI region.

In addition, at tight gate pitch, even forming S/D contact without shorting to gate metal becomes very challenging.

The idea of self-aligned contacts (SAC) has been introduced to mitigate the issue of S/D contact to gate shorts.

As shown in Fig. 35(b), the gate metal is fully encapsulated by a dielectric spacer and gate cap, which protects the gate from shorting to the S/D contact.

A dielectric cap is added on top of the gate so that if the contact overlaps the gate, no short occurs.

MD layer represent SACs in PDK

self-aligned gate contacts (SAGCs)

Self-aligned gate contacts (SAGCs) have also been implemented and Denser standard cells can be achieved by eliminating the need to land contacts on the gate outside the active area.

SAGCs require the source/drain contacts to be capped with an insulator that is different from both contact and gate cap dielectrics to protect the source/drain contacts against a misaligned gate contact etch.

According to the DRC of T foundary, poly extension > 0 um and space between MP and OD > 0 um., which demonstrate self-aligned gate contact is not introduced.

Contacted-Poly-Pitch (CPP)

Wider Contacted-Poly-Pitch allows wider MD and VD size, which help reduce MEOL IRdrop

Naoto Horiguchi. Entering the Nanosheet Transistor Era [link]

Gate Resistance

Native NMOS Blocked Implant (NT_N)

Principles of VLSI Design CMOS Processing CMPE 413 [https://redirect.cs.umbc.edu/~cpatel2/links/315/lectures/chap3_lect09_processing2.pdf]

CMOS processing [http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf]

The Fabrication Process of CMOS Transistor [https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/#:~:text=latch%2Dup%20susceptibility.-,N%2D%20well%2F%20P%2D%20well%20Technology,well%20it%20is%20vice%2D%20verse.]

CMOS Processing Technology [link1, link2]

A native layer (NT_N) is usually added under inductors or transformers in the nanoscale CMOS to define the non-doped high-resistance region of substrate, which decreases eddy currents in the substrate thus maintaining high Q of the coils.

For T* PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy currents

OD inside NT_N only can be used for NT_N potential pickup purpose, such as the guarding-ring of MOM and inductor

Derived Geometries

NP: N+ Source/Drain Ion Implantation

PP: P+ Source/Drain Ion Implantation

OD: Gate Oxide and Diffustion

NW: N-WELL

PW: P-WELL

CMOS Processing Technology

Four main CMOS technologies:

• n-well process
• p-well process
• twin-tub process
• silicon on insulator

Triple well, Deep N-Well (optional):

• NWell: NMOS svt, lvt, ulvt ...
• PWell: PMOS svt, lvt, ulvt ...
• DNW: For isolating P-Well from the substrate

The NT_N drawn layer adds no process cost and no extra mask

The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.

The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.

Deep N-well

Chew, K.W., Zhang, J., Shao, K., Loh, W., & Chu, S.F. (2002). Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration. 32nd European Solid-State Device Research Conference, 251-254. URL:[slides, paper]

Mark Waller, Analog layout: Why wells, taps, and guard rings are crucial

KEITH SABINE Using Deep N Wells in Analog Design

Faricelli, J. (2010). Layout-dependent proximity effects in deep nanoscale CMOS. IEEE Custom Integrated Circuits Conference 2010, 1-8.

cmos_processing, URL:http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf

Kuo-Tsai LiPaul ChangAndy Chang, TSMC, US20120053923A1, "Methods of designing integrated circuits and systems thereof"

Substrate noise

A variety of techniques can be used to minimize this noise, for example by keeping analog devices surrounded by guard rings, or using a separate supply for the substrate/well taps.

However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

PMOS are less noisy than NMOS since PMOS has its nwell which isolates the substrate noise, but such is not valid for NMOS .

DNW

The N-channel devices built directly into the P-type substrate are not as effectively isolated as P-channel devices in their N-wells. This is because despite creating a P+ guard ring around the devices, there remains an electrical path below the guard ring for charge to flow.

To overcome this issue, a deep N-well can be used to more effectively isolate these N-channel devices.

pwdnw: PW/DNW diode

dnwpsub: DNW/PSUB diode

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

• the P-well is separated, allowing the voltage to be controlled
• because the circuit within the deep N-well is separated from the p-substrate in this structure, there is the benefit that this circuitry is less susceptible to noise that propagates through the p-substrate.

reference

Mikael Sahrling, Layout Techniques for Integrated Circuit Designers 1st Edition , Artech House 2022

LAYOUT, EE6350 VLSI Design Lab SMART TEMPERATURE SENSOR URL: https://www.ee.columbia.edu/~kinget/EE6350_S16/06_TEMPSENS_Sukanya_Vani/layout.html

Stacked MOSFETs in analog layout https://pulsic.com/stacked-mosfets-in-analog-layout/

JED Hurwitz, ISSCC2011 "T4: Layout: The other half of Nanometer CMOS Analog Design" [slides, transcript]

Tom Quan, TSMC, Bob Lefferts, Fred Sendig, Synopsys, Custom Design with FinFETs - Best practices designing mixed-signal IP

Jacob, Ajey & Xie, Ruilong & Sung, Min & Liebmann, Lars & Lee, Rinus & Taylor, Bill. (2017). Scaling Challenges for Advanced CMOS Devices. International Journal of High Speed Electronics and Systems. 26. 1740001. 10.1142/S0129156417400018.

Joddy Wang, Synopsys "FinFET SPICE Modeling" Modeling of Systems and Parameter Extraction Working Group 8th International MOS-AK Workshop (co-located with the IEDM Conference and CMC Meeting) Washington DC, December 9 2015

A. L. S. Loke et al., "Analog/mixed-signal design challenges in 7-nm CMOS and beyond," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-8, doi: 10.1109/CICC.2018.8357060.[slides]

Prof. Adam Teman, Advanced Process Technologies, [pdf]

Luke Collins. FinFET variability issues challenge advantages of new process [link]

Loke, Alvin. (2020). FinFET technology considerations for circuit design (invited short course). BCICTS 2020 Monterey, CA

Alvin Leng Sun Loke, TSMC. Device and Physical Design Considerations for Circuits in FinFET Technology", ISSCC 2020

A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

A. L. S. Loke, Migrating Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm. 2016 Symposia on VLSI Technology and Circuits

Lattice Semiconductor, 16FFC Process Technology Introduction December 9th, 2021[pdf]

temperature coefficient

The parameter that shows the dependence of the reference voltage on temperature variation is called the temperature coefficient and is defined as: \[ TC_F=\frac{1}{V_{\text{REF}}}\left[ \frac{V_{\text{max}}-V_{\text{min}}}{T_{\text{max}}-T_{\text{min}}} \right]\times10^6\;ppm/^oC \]

Choice of n

classic bandgap reference

\[ V_{bg} = \frac{\Delta V_{be}}{R_1} (R_1+R_2) + V_{be2} = \frac{\Delta V_{be}}{R_1} R_2 + V_{be1} \]

\[ V_{bg} = \left(\frac{\Delta V_{be}}{R_1} + \frac{V_{be1}}{R_2}\right)R_3 = \left(\frac{\Delta V_{be}}{R_1} R_2 + V_{be1}\right)\frac{R_3}{R_2} \]

OTA offset effect

\[\begin{align} V_{be1} &= \frac{kT}{q}\ln(\frac{I_{e1}}{I_{ss}}) \\ V_{be2} &= \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \end{align}\]

Here, we assume \(I_e = I_c\)

Hence,

\[\begin{align} \Delta V_{be} &= \frac{kT}{q}\ln(n\frac{I_{e1}}{I_{e2}}) \\ &= \frac{kT}{q}\ln(n) + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \\ &= \Delta V_{be,0} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \end{align}\]

Therefore,

\[\begin{align} V_{bg} &= \frac{\Delta V_{be}+V_{os}}{R_2}(R_1+R_2) + V_{be2} \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}})+\frac{kT}{q}\ln(\frac{I_{e2}}{I_{e2,0}}) \end{align}\]

We omit the last part \[\begin{align} V_{bg} &\approx \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + V_{be2,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \\ &= V_{bg,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \end{align}\]

i.e. the bg variation due to OTA offset \[ \Delta V_{bg} \approx \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \]

• \(V_{os} \gt 0\)

  ​ \(I_{e1} \gt I_{e2}\): \(\Delta V_{bg} \gt \alpha V_{os}\)

• \(V_{os} \lt 0\)

  ​ \(I_{e1} \lt I_{e2}\): \(\Delta V_{bg} \lt \alpha V_{os}\)

OTA with chopper

\(I_{e1}\), \(I_{e2}\)

\[\begin{align} V_{ip} &= V_{im} + V_{os} \\ \frac{V_{bg}-V_{ip}}{R_2} &= I_{e2} \\ \frac{V_{bg}-V_{im}}{R_2} &= I_{e1} \\ V_{ip} &= I_{e2}R_1 + V_T\frac{I_{e2}}{nI_S} \\ V_{im} &= V_T\frac{I_{e1}}{I_S} \end{align}\] where \(V_T = \frac{kT}{q}\)

we obtain \[ I_{e1} = \frac{V_T\ln n}{R_1} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) - \frac{1}{R_1}\cdot V_T\ln\left(1- \frac{V_{os}}{R_2I_{e1}} \right) \]

we omit the last part \[\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) \\ I_{e2} &= I_{e1} - \frac{V_{os}}{R_2} = I_{e0} + \frac{V_{os}}{R_1} \end{align}\] where \(I_{e0} = \frac{\Delta V_{be}}{R_1}\), \(\Delta V_{be}=V_T\ln n\)

That is, both \(I_{e1}\) and \(I_{e2}\) are proportional to \(V_{os}\)

\(I_{e1}\) and \(I_{e2}\) can be expressed as \[\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) + \frac{V_{os}}{2R_2} \\ I_{e2} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) - \frac{V_{os}}{2R_2} \end{align}\] i.e., \(\Delta I_{e,cm} = V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right)\) and \(\Delta I_{e,dif} =\frac{V_{os}}{2R_2}\)

bandgap output voltage is

\[\begin{align} V_{bg} &= V_T \ln \frac{I_{e1}}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e0}R_2 + V_{os}\frac{R_1+R_2}{R_1} \\ &= I_{e0}R_2 + V_T \ln \frac{I_{e0}}{I_s} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \\ &= V_{bg0} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \end{align}\]

Therefore, the averaged output of bandgap

\[ V_{bg,avg} = V_{bg0} +\frac{1}{2}V_T\ln\left(1-\frac{V_{os}^2\left(\frac{1}{R_1} + \frac{1}{R_2} \right)^2}{I_{e0}^2} \right) \lt V_{bg0} \]

\(V_{bg,avg} \lt V_{bg0}\) due to nonlinearity of BJT

ripple cancellation

phase 0:

\[\begin{align} V_{os}[n] &= V_{os}[n-1] - \frac{\Delta I_1}{g_m} \\ V_{os}[n] &= I_\Delta[n] R_E \\ \beta I_\Delta &= I_1[n] + I_2[n-1] \end{align}\] where \(I_\Delta\) is the variation of \(I_{e1}+I_{e2}\) due to \(V_{os}\) and \(R_E = \frac{R_1R_2}{R_1+2R_2}\)

obtain \[\begin{align} \Delta I_1 &= G\cdot V_{os}[n-1] - K\cdot I_1[n-1] - K\cdot I_2[n-1] \\ I_1[n] &= G\cdot V_{os}[n-1] + (1-K)\cdot I_1[n-1] - K\cdot I_2[n-1] \\ V_{os}[n] &= K\cdot V_{os}[n-1] + R\cdot I_1[n-1] + R\cdot I_2[n-1]\\ \end{align}\]

where \(G=g_m\frac{\beta}{g_m R_E + \beta}\), \(R=R_E\frac{1}{g_m R_E + \beta}\) and \(K=\frac{g_mR_E}{g_m R_E + \beta}\)

and \[ V_{os}[n] = (2K-1)\cdot V_{os}[n-1] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] \]

phase 1:

\[\begin{align} V_{os}[n] &= V_{os}[n-1] - \frac{-\Delta I_2}{g_m} \\ V_{os}[n] &= -I_\Delta[n] R_E \\ \beta I_\Delta &= I_1[n] + I_2[n-1] \end{align}\]

obtain \[\begin{align} \Delta I_2 &= -G\cdot V_{os}[n-1] - K\cdot I_1[n-1] - K\cdot I_2[n-1] \\ I_1[n] &= -G\cdot V_{os}[n-1] -K\cdot I_1[n-1] + (1-K)\cdot I_2[n-1] \\ V_{os}[n] &= K\cdot V_{os}[n-1] - R\cdot I_1[n-1] - R\cdot I_2[n-1]\\ \end{align}\]

similaly \[ V_{os}[n] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] \]

That is, for either phase \[ V_{os}[n] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] \]

reference

ECEN 607 (ESS) Bandgap Reference: Basics URL:https://people.engr.tamu.edu/s-sanchez/607%20Lect%204%20Bandgap-2009.pdf

MOS capacitances

• oxide capacitance (aka gate-channel capacitance) between the gate and the channel \(C_1=WLC_{ox}\)
  • divided between \(C_{GS}\) and \(C_{GD}\)
• depletion capacitance between the channel and the substrate \(C_2\)
• overlap capacitance: direct overlap and fringing field
• junction capacitance between the source/drain areas and the substrate
  • The value of \(C_{SB}\) and \(C_{DB}\) is a function of the source and drain voltages with respect to the substrate

The gate-bulk capacitance is usually neglected in the triode and saturation regions because the inversion layer acts as a "shield" between the gate and the bulk.

classification with Intrinsic and Extrinsic MOS capacitor

[Circuit Insights - 11-CI: Fundamentals 4 Tsinghua Nan Sun]

FinFET Parasitic Fringing Capacitance

Temperature Dependence of Junction Diode CV

where TCJ and TCJSW are positive

https://cmosedu.com/cmos1/BSIM4_manual.pdf

varactor

D=S=B varactor

Inversion-mode (I-MOS)

Accumulation-mode (A-MOS)

NMOS in NWELL, aka NMOS in N-Well varactor

Notice: S/D and NWELL are connected togethor in layout

PDK varactor

nmoscap: NMOS in N-Well varactor

• Base Band MOSCAP model (nmoscap) is built without effective series resistance (ESR) and effective series inductance (ESL) calibrations, which is for capacitance simulation only
• LC-Tank MOSCAP model (moscap_rf) is for frequency-dependent Q factor and capacitance simulations

MOS Device as Capacitor

Voltage dependence

• capacitance of MOS gate varies nonmonotonically with \(V_{GS}\)

• "accumulation-mode" varactor varies monotonically with \(V_{GS}\)

Inverter capacitance

reference

Aditya Varma Muppala. MOS Varactors | Oscillators 15 | MMIC 27 [https://youtu.be/LYCLZPQvIz0?si=yoSBZSD2j_wEx0zZ]

R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs," in IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003, doi: 10.1109/JSSC.2003.814416.

T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee and S. S. Wong, "Analysis and optimization of accumulation-mode varactor for RF ICs," 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), 1998, pp. 32-33, doi: 10.1109/VLSIC.1998.687993. URL: http://www-smirc.stanford.edu/papers/VLSI98s-chet.pdf

R. Jacob Baker, 6.1 MOSFET Capacitance Overview/Review, CMOS Circuit Design, Layout, and Simulation, Fourth Edition

B. Razavi, Design of Analog CMOS Integrated Circuits 2nd

Bing Sheu, TSMC. "Circuit Design using FinFETs" [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T4.pdf]

Due to the fact that long-term drift of temperature sensors and bandgap references caused by package-induced stress is lower with PNP BJTs than with NPN BJTs, PNP BJTs have been used traditionally for temperature sensor design in CMOS

Calibration

TODO 📅

[https://ww1.microchip.com/downloads/en/Appnotes/Atmel-8108-Calibration-of-the-AVRs-Internal-Temperature-Reference_ApplicationNote_AVR122.pdf]

\(V_{BE}\) curvature

curvature results in results in non-linearity

Though it is assumed that \(V_{BE}\) is a linear function of temperature for first oder analysis.

In practice, \(V_{BE}\) is slightly nonlinear, the magnitude of this nonlinearity is referred to as curvature.

curvature depends on the temperature dependency of the saturation current (\(I_s\)), and on that of the collector current (\(I_c\)), it can be written as \[ V_{curv}(T)=\frac{k}{q}(\eta-\delta)(T-T_r-T\cdot \ln(\frac{T}{T_r})) \] where \(\eta\) = a constant depending on the doping level, CMOS substrate pnp transistors have a typically value of \(\eta \cong 4\)

\(\delta\) = order of the temperature dependence of collector current (\(I_c\))

PTAT \(I_c\) help reduce \(V_{curv}(T)\), \(\delta=1\)

Although the temperature dependence of the bias current \(I_b\) doesn’t impact the accuracy of \(V_{BE}\), it does impact the systematic nonlinearity or curvature of \(V_{BE}\), and hence the sensor's systematic error. The curvature in \(V_{BE}\) can be reduced by using a PTAT bias current.

PTAT bias current

\[ I_{bias} = \frac{0.7}{\beta \cdot R^2} \] in which \(\beta=\frac{\mu_{n}\cdot C_{ox}\cdot W}{L}\), where:

\(\mu_n\)=mobility,

\(C_{ox}\) = oxide capacitance density,

\(\frac{W}{L}\) = dimension ratio of unit NMOS used for \(M_1\) and \(M_2\)

\(\mu_n\) is complementary to the absolute temperature and resitor R is implemented using high-R flow in FinFET which has a low temperature dependency, the net temperature dependency of \(I_{bias}\) is proportional to the absolute temperature \[ I_{bias}\propto T \]

Kamath, Umanath Ramachandra. "BJT Based Precision Voltage Reference in FinFET Technology." (2021).

Errors due to V-I Finite Gain

Finite gain introduces errors both in the V-I converters, finite loop gain results in errors in the closed-loop transconductances.

\[\begin{align} (V_{i1} - V_{o1})\cdot A_{OL1} &= V_{o1} \\ V_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}V_{i1} \\ I_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}\frac{1}{R_1}V_{i1} \end{align}\] similarly, \[ I_{o2} = \frac{A_{OL2}}{1+A_{OL2}}\frac{1}{R_2}V_{i2} \]

Then, \(\alpha\) is obtained \[ \alpha = \frac{(1+A_{OL2})A_{OL1}}{A_{OL2}(1+A_{OL1})}\cdot\frac{R_2}{R_1} \] Since the loop gains in the two V-I converters cannot be expected to match, the resulting errors in both converters should be reduced to negligible levels.

First, assume \(A_{OL2}=\infty\) \[\begin{align} \Delta \alpha &= (1-\frac{A_{OL1}}{1+A_{OL1}})\cdot\frac{R_2}{R_1}\\ &=\frac{1}{1+A_{OL1}}\cdot\frac{R_2}{R_1}\\ &\cong \frac{1}{A_{OL1}}\cdot\frac{R_2}{R_1} \end{align}\]

We get \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL1}} \] Follow the same procedure, assume \(A_{OL1}=\infty\) \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL2}} \] The finite gain introduces an error inversely proportional to the loop gain \(A_{OL1}\),\(A_{OL2}\), the resulting errors in both converters should be reduced to negligible levels

Why is it named as "bandgap reference"

Let us write the output voltage as \[ V_{REF} = V_{BE} + V_T\cdot \ln n \] and hence \[ \frac{\partial V_{REF}}{\partial T} = \frac{\partial V_{BE}}{\partial T} + \frac{V_T}{T}\ln n \] Setting this to zero and substituting for \(\frac{\partial V_{BE}}{\partial T}\), we have \[ \frac{V_{BE}-(4+m)V_T-E_g/q}{T}=-\frac{V_T}{T}\ln n \] If \(V_T\ln n\) is found from this equation and inserted in \(V_{REF}\), we obtain \[ V_{REF}=\frac{E_g}{q} + (4+m)V_T \]

The term bandgap is used here because as \(T\to 0\), \(V_{REF} \to E_g/q\)

sinking PTAT-current generator without current mirrors

why without current mirror?

Bakker, Anton. (2000). High-Accuracy CMOS Smart Temperature Sensors. 10.1007/978-1-4757-3190-3. [https://repository.tudelft.nl/record/uuid:fd398056-48dd-4d84-8ae8-27a1b011d2c3]

Readout Circuit

ADC dynamic range

Take \(V_{PTAT}=\alpha \cdot \Delta V_{BE}\) as input and \(V_{REF}\) as reference. The output \(\mu\) of the ADC will then be \[ \mu =\frac{V_{PTAT}}{V_{VREF}}=\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] A final digital output \(D_{out}\) in degrees Celsius can be obtained by linear scaling: \[ D_{out}=A\cdot \mu + B \] where \(A\simeq 600K\) and \(B\simeq -273K\)

While the transfer is simple, it only uses about 30% of the of the ADC (the extremes of the operating range correspond to \(\mu \simeq 1/3\) and \(\mu \simeq 2/3\)). The ratio results in a rather inefficient use of the modulator's dynamic range.

For a first-order \(\Sigma\Delta\) modulator, this means that about 1.5 bits of resolution are lost

A more efficient transfer is \[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] With this more efficient combination, 90% of the dynamic range is used rather than 30%. Thus, the required resolution of the ADC is reduced by a factor of three.

Integrator Output Swing

\[ \mu =\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

\[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

In advanced process, like Finfet 16nm, 7nm, high resistance resistor has +/-15% variation and MOM capacitor has +/-30% variation.

Then, \(R_1\) and \(R_2\) not only determine the \(\alpha\) but also the integrator's output swing, so do \(V_{BE}\) and \(\Delta V_{BE}\), \(C_{int}\).

The integrator's output change per period

example

integrator, comparator offset

integrator offset

comparator offset

integrator design

application in sensor

Offset Errors

The offset of opamp \(A_3\) is much less critical:

1. It affects the integrated currents via the finite output impedances \(R_{out1,2}\) of the V-I converters, and is therefore attenuated by a factor \(R_{out1}/R_1\) when referred back to the input of the sinking V-I converter,

2. or by a factor \(R_{out2}/R_2\) when referred back to the input of the sourcing V-I converter.

Therefore, no special offset cancellation is needed for opamp \(A_3\).

The current change due to offset of \(A_3\): \[\begin{align} \frac{V_{BE,os}}{R_1} &= \frac{V_{ota,os}}{R_{out1}} \\ \frac{\Delta V_{BE,os}}{R_2} &= \frac{V_{ota,os}}{R_{out2}} \end{align}\] Then, the input referenced offset is: \[\begin{align} V_{BE,os} &=\frac{ V_{ota,os}}{R_{out1}/R_1} \\ \Delta V_{BE,os} &= \frac{ V_{ota,os}}{R_{out2}/R_2} \end{align}\]

Errors due to Finite Gain

Finite gain of opamp \(A_3\) results in a non-zero overdrive voltage at its input, which modulates the current Iint due to the finite output impedances of the V-I converters.

Assuming the opamp is implemented as a transconductance amplifier, there are two main causes of this non-zero overdrive voltage

1. The finite transconductance \(g_{m3}\) of the opamp, , which implies that an overdrive voltage is required to provide the feedback current

​ The change in the integrated current

​ \[\begin{align} ​ \Delta I_{int} &= \frac{V_{i,ota}}{R_{out}}\\ ​ &= \frac{I_{int}}{g_{m3}}\cdot \frac{1}{R_{out}} ​ \end{align}\]

2. The finite DC gain \(A_{0,3}\), which implies that an overdrive voltage is required to produce the output voltage \(V_{int}\)

reference

Micheal, A., P., Pertijs., Johan, H., Huijsing., Pertijs., Johan, H., Huijsing. (2006). Precision Temperature Sensors in CMOS Technology.

C. -H. Chang, J. -J. Horng, A. Kundu, C. -C. Chang and Y. -C. Peng, "An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, pp. 165-168, doi: 10.1109/ASSCC.2014.7008886.

EE247 - Analog Digital Interface Integrated Circuits - Fall 2009 Lecture 24- Oversampled ADCs

Hecht, Bruce. (2010). SSCS DL Kofi Makinwa Talks About Smart Sensor Design at SSCS-Boston [People]. Solid-State Circuits Magazine, IEEE. 2. 54 - 56. 10.1109/MSSC.2009.935278.

1
2

@(posedge clk iff(vld));
do_something;

is equivalent to

1
2
3
4
5

forever begin
	@(posedge clk);
    if(vld) break;
end
do_something;

iff is more efficient than if because the expression is recalculated when vld transition rather than clk.

One example, detecting the negative edge of rtr_io.cb.frameo_n[da]

1
2
3

wait(rtr_io.cb.frameo_n[da] !== 0);
@(rtr_io.cb iff(rtr_io.cb.frameo_n[da] === 0 )); 
$display("[DEBUG HGUO] %0t, rtr_io.cb.frameo_n[da] negedge", $realtime);

[DEBUG HGUO] 6887250.0ns, rtr_io.cb.frameo_n[da] negedge

reference

system verilog中的iff, URL: https://www.francisz.cn/2019/07/18/sv-iff/

Linear Time-varying System Theory

We define the ISF of the sampler as the sensitivity of its final output voltage to the impulse arriving at its input at different times, the ISF essentially describes the aperture of the sampler.

An ideal sampler would have the perfect aperture, i.e. sampling the input voltage at exactly one point in time; thus, its ISF would be a Dirac delta function, \(\delta(t-t_s)\) where \(t_s\) is when sampling occurs.

A realistic sampler would rather capture a weighted-average of the input voltage over a certain time window. This weighting function is called the sampling aperture and is equivalent to the ISF

A time-varying impulse response \(h(t, \tau)\) is defined as the circuit response at time \(t\) responding to an impulse arriving at time \(\tau\).

In general, the ISF can be regarded as the time-varying impulse response evaluated at one particular observation time \(t=t_0\).

The system output \(y(t)\) is related to the input \(x(t)\) as: \[ y(t) = \int_{-\infty}^{\infty}h(t, \tau)\cdot x(\tau)d\tau \] Note that in a linear time-invariant (LTI) system, \(h(t,\tau)=h(t-\tau)\) and the above equation reduces to a convolution.

If \(X(j\omega)\) is the Fourier transform of the input signal \(x(t)\), i.e. \[ x(t) = \frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega t}d\omega \] Then \[\begin{align} y(t) &= \int_{-\infty}^{\infty}h(t,\tau)\left[\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega\tau }d\omega \right]\cdot d\tau \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{j\omega\tau}d\tau\right]\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\right]\cdot e^{j\omega t}\cdot d\omega \\ &=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot H(j\omega;t)\cdot e^{j\omega t}\cdot d\omega \end{align}\]

where \(H(j\omega;t)\) is time-varying transfer function, defined as the Fourier transform of the time-varying impulse response. \[ H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \] And it follows that: \[ Y(j\omega)=H(j\omega;t)\cdot X(j\omega) \] And

\[\begin{align} x(\tau) & \overset{FT}{\longrightarrow} X(j\omega) \\ h(t,\tau) & \overset{FT}{\longrightarrow} H(j\omega;t) \end{align}\]

For linear, periodically time-varying (LPTV) systems, \(h(t, \tau) = h(t+T, \tau+T)\) and \(H(j\omega; t) = H(j\omega; t+T)\) where \(T\) is the period of the time-varying dynamics of the system.

We prove \(H(j\omega; t) = H(j\omega; t+T)\):

\[\begin{align} \because H(j\omega;t)&=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ \therefore H(j\omega;t+T) &= \int_{-\infty}^{\infty}h(t+T,\tau)\cdot e^{-j\omega(t+T-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t+T-(\tau+T))}d(\tau+T) \\ &= \int_{-\infty}^{\infty}h(t+T,\tau+T)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= \int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau \\ &= H(j\omega;t) \end{align}\]

PSS + PAC Method

Since \(H(j\omega;t)\) is periodic in \(T\), The time-varying transfer function \(H(j\omega;t)\) can be expressed in a Fourier series: \[ H(j\omega;t)=\sum_{m=-\infty}^{\infty}H_m(j\omega) \cdot e^{jm\omega_c t} \] where \(\omega_c\) is the fundamental frequency of the periodic system. \(H_m(j\omega)\) represent the frequency response of the system at the (m-th) harmonic output sideband to a unit \(j\omega\) sinusoid.

The above equation link time-varying transfer function \(H(j\omega;t)\) with PAC simulation output

The response to a periodic impulse train, that is: \[ x(t)=\sum_{m=-\infty}^{\infty}\delta(t-\tau-nkT) \] The idea is that if the impulse response of the system settles to zero long before the next impulse arrives, then the system response to this impulse train would be approximately equal to the periodic repetition of the true impulse response, i.e.: \[ y(t) \cong \sum_{m=-\infty}^{\infty}h(t;\tau+nkT) \] and \(y(t)\) would be approximately equal to \(h(t;\tau)\) for \(\tau \leq t \le t+kT\)

Without loss of generality and for computation convenience, we set \(k=1\) thereafter.

The Fourier transform \(X(j\omega)\) of the T-periodic impulse train is: \[ X(j\omega)=\omega_c\sum_{n=-\infty}^{\infty}\delta(\omega-n\omega_c)\cdot e^{-j\omega\tau} \] Then the response \(y(t)\) is: \[ y(t)=\frac{1}{T}\sum_{n=-\infty}^{\infty}H(jn\omega_c;t)\cdot e^{jn\omega_c\cdot(t-\tau)} \] The expression for the approximate time-varying impulse response: \[ h(t,\tau) = \left\{ \begin{array}{cl} \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct+jn\omega_c\cdot (t-\tau)} & : \ \tau \leq t \lt \tau+T \\ 0 & : \ \text{elsewhere} \end{array} \right. \] Finally, the ISF \(\Gamma(\tau)\) is equal to \(h(t,\tau)\) when \(t=t_0\) and \(t_0 \gt \tau\) \[ \Gamma(\tau)\cong \frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot e^{jm\omega_ct_0+jn\omega_c\cdot (t_0-\tau)} \] In practice, the summations are carried out over finite ranges of n and m, for example, -50~50.

For each combination of n and m, the PAC analysis needs to be performed to compute \(H_m(jn\omega_c)\), the m-th harmonic response to the excitation at \(n\omega_c\)

The detailed procedure for characterizing the ISF of this sampler is outlined as follows:

• First, apply the proper input voltages that place the sampler in a metastable state and perform the periodic steady-state (PSS) analysis.

• Second, perform the PAC analysis.

• Third, based on the simulated PAC response, pick a time point \(t_0\) at which the ISF is to be computed and derive the ISF

One possible candidate for the ISF measurement point \(t_0\) is the time at which the output voltage is amplified to the largest value. PAC response of the sampler to a small signal DC input, that is, the time-varying transfer function evaluated at \(\omega=0\) \[ H(0;t)=\sum_{m=-\infty}^{\infty}H_m(0) \cdot e^{jm\omega_c t} \]

The total area under the ISF is the sampling gain, which is equal to the time-varying gain measured at \(t_0\) to a small signal DC input (\(\omega=0\))

Because we have \(H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot e^{-j\omega(t-\tau)}d\tau\), i.e. Fourier transform \[ H(0;t)=\int_{-\infty}^{\infty}h(t,\tau)d\tau = \int_{-\infty}^{\infty}\Gamma(\tau)d\tau \]

1
2

time-varying gain at t0 H(0;t0): 19.486305
The total area under the ISF: 19.990230

Align pss_td.pss with ISF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

****************************************************
Periodic Steady-State Analysis `pss': fund = 500 MHz
****************************************************
Trying `homotopy = gmin' for initial conditions.
DC simulation time: CPU = 4.237 ms, elapsed = 4.27389 ms.

===============================
`pss': time = (0 s -> 102.6 ns)
===============================

Opening the PSF file ../psf/pss.tran.pss ...
...
Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 102.6 ns
    period = 2 ns
    maxperiods = 20
    step = 102.6 ps
...

tstab = 102.6 ns can be observed in pss simulation log

1
2
3
4
5

tstab = 102.6e-9;
tshift = mod(tstab, Tc);
tt_shift = tt - tshift;
tt_shift_start_indx = find(tt_shift>=0, 1);
isf_shift = circshift(isf_re, -tt_shift_start_indx);

Align pss_fd.pss with ISF

Since both are frequency originated, time-shift is NOT needed

1
2
3
4
5
6
7
8

function wv = wv_fd(fname,tt)
fd = csvread(fname, 1, 0);
DC = fd(1, 2);
w = 2*pi*fd(2:end, 1);
coef = fd(2:end, 2) + 1i*fd(2:end, 3);
exp_sup = 1i*w.*tt;
wv = sum(real(coef .* exp(exp_sup)), 1) + DC;
end

PSS + PAC Setup

• clock frequency should be low enough to assure system response settle to zero.
• Beat Frequency os PSS should be clock frequency
• For PAC setup,
  • the Sweeptype is absolute
  • Input Frequency Sweep Range(Hz) should be large enough.
  • Sweep Type should be Linear and Step Size should equal PSS Beat Frequency(Hz)
  • SideBands should large enough, like 50 (i.e. 50*2 +1, positive, negative and 0)
  • Specialized Analyses should be None

one example: clock, i.e. beat frequency = 8G PAC: input frequency sweep from -400G to 400G and step is 8G, which is beat frequency, here K=1 Eq.(9) of paper

freqaxis=out: freqaxis of PAC not only affect "Direct Plot"'s output but also simuation data i.e. the phase shift(imaginary part).

matlab matrix nonconjugate transpose:

transpose, .' cf. https://www.mathworks.com/help/matlab/ref/transpose.html

tstab in PSS

Using shooting PSS, the steady waveform starts from tstab+n*tperiod.

• pss_td.pss is one period waveform starting from tstab+n*tperiod
• pss_fd.pss is the complex fourier series coefficient of expanded to left and right pss_td.pss waveform (tstab+n*tperiod : tstab+(n+1)*tperiod)

We have to left-shift mod(tstab, tperiod) pss_fd.pss in order to align it with of pss_tb.pss

simulation log

The below stop = 1.3 ns is actual tstab time, though Stop Time(tstab) field of pss form is filled with 0.3n

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

**************************************************
Periodic Steady-State Analysis `pss': fund = 1 GHz
**************************************************
DC simulation time: CPU = 208 us, elapsed = 211.954 us.

=============================
`pss': time = (0 s -> 1.3 ns)
=============================

Opening the PSF file ../psf/pss.tran.pss ...

Output and IC/nodeset summary:
                 save   1       (current)
                 save   2       (voltage)

Important parameter values in tstab integration:
    start = 0 s
    outputstart = 0 s
    stop = 1.3 ns
    period = 1 ns
    maxperiods = 20
    step = 1.3 ps
    maxstep = 40 ps
    ic = all
    useprevic = no
	...

    pss: time = 64.01 ps    (4.92 %), step = 31.63 ps     (2.43 %)
	...
    pss: time = 1.224 ns    (94.2 %), step = 40 ps        (3.08 %)
    pss: time = 1.3 ns       (100 %), step = 35.99 ps     (2.77 %)
...

PSS simulation result

Align pss_tb and pss_fd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

clear;
clc;

freq = 1e9;
tstab = 1.3e-9;
Tp  = 1e-9;

load('pss_td.matlab')
t = pss_td(:, 1);
ytd = pss_td(:, 2);
plot(t*1e9, ytd, 'k', 'LineWidth',6)
hold on;

% time domian from pss frequency domain information
coff_real = -0.155222;
coff_imag = -0.0247045;
wc = 2*pi*freq;
tfd = (0:1e-11:2e-9);
yfd = coff_real*cos(wc*tfd) - coff_imag*sin(wc*tfd);
plot(tfd*1e9, yfd, 'b')

% actual pss_td.pss one-period waveform
tfd_td = (tstab:1e-11:2e-9);
yfd_td = coff_real*cos(wc*tfd_td) - coff_imag*sin(wc*tfd_td);
plot(tfd_td*1e9, yfd_td, '--b', 'LineWidth', 4)

% align pss_fd with pss_tb by left shift mod(tstab, Tp) pss_fd
tshift = mod(tstab, Tp);
tfd_shift = tfd - tshift;
tfd_shift_start_indx = find(tfd_shift>=0, 1);
tfd_shift = tfd_shift(1, tfd_shift_start_indx:end);
yfd_shift = yfd(1, tfd_shift_start_indx:end);
plot(tfd_shift*1e9, yfd_shift, '-magenta', 'LineWidth', 2)
grid on;

xlabel('t (ps)');
ylabel('V(t)');
legend('Using pss\_td', 'Using pss\_fd', 'pss\_tb one period clip', 'Using pss\_fd with time shift', 'location', 'east');

Transient Method

TODO 📅

reference

J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 386-391, doi: 10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]

M. Jeeradit et al., "Characterizing sampling aperture of clocked comparators," 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2008, pp. 68-69 [https://people.engr.tamu.edu/spalermo/ecen689/sampling_aperature_comparators_vlsi_2008.pdf]

T. Toifl et al., "A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 954-965, April 2006 [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=4d1f0442be77425ed34b9dcfd48fbfff954a707b]

Sam Palermo, ECEN 720 High-Speed Links: Circuits and Systems [Lecture 6: RX Circuits], [Lab4 - Receiver Circuits]

PERC

• CD: current density checks

• P2P: point to point resistance checks

• LDL: logic driven layout checks, latch up related

• TOPO: topology, circuit connection and device size checks

database

• CD, P2P, LDL : dfmdb

• TOPO: svdb

Frank Feng. New Approach For Full Chip Electrical Reliability Verification [pdf]

Calibre PERC Catalog Test-Cases & Common Examples Version 2.0

Latchup

This can happen when a parasitic thyristor, which is essentially a pair of interconnected transistors, is triggered into a latched state, leading to sustained current flow and potential device failure.

latchup-prevention technique

Technical Paper Ensuring latch-up guard rings ESDA rules using Calibre PERC [https://resources.sw.siemens.com/en-US/technical-paper-ensuring-latch-up-guard-rings-esda-rules-using-calibre-perc/]

Guard Rings

One important technique is the use of guard rings, the heavily doped regions surrounding sensitive components on the IC to divert excess current away from vulnerable areas, thereby reducing the likelihood of latch-up occurrence

These guard rings not only function as barriers against parasitic thyristor formation but also serve to isolate different regions of the IC, minimizing unwanted electrical interactions and maintaining pathway integrity

P.E. Allen - 2016. CMOS Analog Circuit Design: Lecture 08 – Latchup and ESD (4/25/16) [https://aicdesign.org/wp-content/uploads/2018/08/lecture08-160425.pdf]

Transient-Induced Latchup

OD injector

Silicon Controlled Rectifiers (SCR)

A thyristor (also known as a Silicon Controlled Rectifier or SCR) is a three-terminal semiconductor device used as an electronic switch or rectifier

To turn the thyristor on, a positive voltage pulse is applied to the gate (G) terminal. This voltage pulse needs to be of sufficient magnitude to trigger the device. When the gate is triggered, it allows a small current to flow into the base of the P-N-P transistor within the thyristor structure

[https://ec2-44-207-46-173.compute-1.amazonaws.com/thyristor/]

ESD design window

[https://monthly-pulse.com/2021/06/02/the-esd-design-window-concept/]

[https://www.researching.cn/ArticlePdf/m00098/2020/41/12/122403.pdf]

• Transparency
  • Trigger voltage Vt1
  • Holding/clamping voltage Vh
• Robustness
  • failure current level It2
• Effectiveness
  • maximum voltage of the clamp device: Vmax

Secondary protection

1. Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors.
2. ESD current through this clamp will build-up voltage across the isolation resistance, while protecting the circuit.
3. The higher voltage at the IN pad will then trigger the primary protection (red current path)

Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors

Extended ESD design window example. The failure voltage of a thin gate oxide in advanced CMOS is about 4V. The primary ESD solution (red IV curve) introduces too much voltage. Thanks to an isolation resistance between primary and secondary local clamp device (green IV curve) additional margin is created.

[https://monthly-pulse.com/2022/03/29/introduction-esd-protection-concepts-for-i-os/]

Gated diode & STI diode

M. Simicic, G. Hellings, S. -H. Chen, N. Horiguchi and D. Linten, "ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology," 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, Germany, 2018

TLP/vf-TLP

TRANSMISSION LINE PULSE TESTING: THE INDISPENSABLE TOOL FOR ESD CHARACTERIZATION OF DEVICES, CIRCUITS AND SYSTEMS [https://www.esda.org/assets/News/1708-ESD-firstDraft.pdf]

[https://monthly-pulse.com/2021/06/08/transmission-line-pulse-tlp-test-system/]

Jon Barth "TLP and VFTLP Testing of Integrated Circuit ESD Protection" [https://barthelectronics.com/wp-content/uploads/2016/09/TLP-and-VFTLP-Test-of-Integrated-Circuit-ESD-Protection.pdf]

Horst A. Gieser(IZM), "ESD- Testing: HBM to very fast TLP" [https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf]

Vt1: trigger voltage

Vhold: holding voltage

soft failure current: Isoft

hard failure current: It2

TLP vs ESD

• ESD tests simulate real world events (HBM, MM, CDM)
• TLP does not simulate any real-world event
• ESD tests record failure level (Qualification)
• TLP tests record failure level and device behavior (Characterization)

TLP is not a qualification test, but a characterization method, which describes the resistance of a device for a given stimulus, aka. Device Characterization

Unlike ESD waveforms, TLP does not mimic any real world event

TLP and Curve Tracing

• Curve Tracing is DC; TLP is a short pulse
  • Shorter pulse - Reduced duty cycle, less heating, which means higher voltage before failure
  • Controlled Impedance - Allows device behavior to be observed
• Both measure resistance of device with increasing voltage

Device Characterization with TLP

• Turn-on time
• Snapback voltage
• Performance changes with rise time

VF-TLP and CDM differences

Question:

How well will VF-TLP results predict CDM testing performance?

Answer:

VF-TLP can be a guide to CDM failure levels, and provide a lot of understanding of a circuit's operation during CDM stressing, but simple correlations between VF-TLP failure current level and CDM withstand voltage levels are difficult to establish.

I.V and Leakage Evolution Plots

DC leakage current data combined with the I-V data provides electrical indications of where damage begins, and how rapidly it can evolve from soft to hard failures

Henry, Leo & Barth, Jon & Richner, John & Verhaege, Koen. (2000). Transmission Line Pulse Testing of the ESD Protection Structures in ICs - A Failure Analyst's Perspective. 203-213. 10.31399/asm.cp.istfa2000p0203. [https://barthelectronics.com/pdf_files/2000%20ISTFA%20TLP%20Testing%20of%20the%20ESD%20Protection%20Structure.pdf]

Henry, L.G. & Barth, Jon & Verhaege, K. & Richner, J.. (2001). Transmission-line pulse ESD testing of ICs: A new beginning. Compliance Engineering. 18. 46+53. [https://barthelectronics.com/pdf_files/CE%20TLP%20Article%20March-April%202001.pdf]

Snapback

Unfortunately, this protection concept is not effective anymore in advanced FinFET technology. Our analysis showed that both core and IO transistors are damaged at the onset of snapback in several FinFET processes.

Lesson 2 - ESD Clamps [https://aicdesign.org/wp-content/uploads/2021/05/Lesson02_ESD_Clamps210315.pdf]

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis - Device Level [https://www.esdemc.com/public/docs/TechnicalSlides/ESDEMC_TS001.pdf]

Safe operating area (SOA)

power clamp

Thanks to the device scaling the area is actually reasonable. However, the leakage becomes the main bottleneck.

high current diode

both diode are reverse-biased in normal operation, the PN Junction capacitance is proportional to forward-bias voltage

HIA_DIO can be used for logic or high speed circuits ESD protection

HIA: high current application purpose (High Amp)

There is no process difference between HIA_DIO and regular diode

• diode is drain/source originated, which is different from MOS (Gate originated)

• The perimeter of diode in DRC is different from that in PERC deck, where PERC excludes the the left and right edge of OD

g after the rule numbers: DFM recommendations and guidelines

^U: the rule is not checked by the DRC

MOS

l in netlist has different definition for MOS and diode.

MOS: length of channel

diode: Gate space

HIA = High Amp

lateral diode: perimeter is key DRC rule for ESD diode

HIA diode process is same with regular junction diode

Dual Stacked Diodes

PS: I/O to GND positively

NS: I/O to GND negatively

PD: I/O to VDD positively

ND: I/O to VDD negatively

Dual diode should be used with power clamp for PS and ND path

PMOS power clamp

Gate grounded N-MOS (ggNMOS)

[https://monthly-pulse.com/2022/02/02/time-to-say-farewell-to-the-snapback-ggnmos-for-esd-protection/]

[https://monthly-pulse.com/2023/01/26/ggnmos-grounded-gated-nmos/]

Influence of the pulse rise time on ggNMOS. (left side) A fast ESD pulse can couple the bulk of the NMOS to a higher potential for a short period, reducing the trigger voltage. (right side) A clear Vt1 reduction is visible, while the remaining part of the IV curve remains the same.

resistance between gate and source that designers typically use to reduce the Vt1 trigger voltage of a ggNMOS ESD protection

The drain (D) is connected to an I/O pad and the gate (G) is grounded.

To ensure “zero” leakage of the ESD protection structure under normal operations.

To to protect gate of core device, tie-high and tie-low shall be used when used as secondary ESD protection.

Positive ESD transient at I/O pad

1. DB junction is reverse-biased all the way to its breakdown.
2. Avalance multiplication takes place and generates electron-hole pairs
3. Hole current flows into the ground via the B-region and build up a potential, VR, across the lateral parasitic resistance R
4. As VR increases, the BS junction turns on, eventually triggers the parasitic lateral NPN transistor Q (DBS)

Negative ESD transient at I/O pad

The forward-biased parasitic diode, BD, will shunt the transient

ggNMOS is commonly used in the GPIO provided by foundry, which alleviate the ESD design burden of customer.

These GPIO is self-protective thanks to the ggNMOS.

Reference

Introduction to Transmission Line Pulse (TLP), URL: https://tools.thermofisher.com/content/sfs/brochures/TLP%20Presentation%20May%202009.pdf

VF-TLP and CDM differences, URL: https://www.grundtech.com/app-note-vf-tlp-cdm-differences

ESD-Testing: HBM to very fast TLP URL: https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1-6, doi: 10.1109/CICC48029.2020.9075899.

KOEN DECOCK IEEE-SSCSLEUVEN "ON-CHIP ESD PROTECTION: BASIC CONCEPTS AND ADVANCED APPLICATIONS" [https://monthly-pulse.com/wp-content/uploads/2021/11/2021-11-sofics_presentation_ieee_final.pdf]

Yuanzhong Zhou, D. Connerney, R. Carroll and T. Luk, "Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models," Sixth international symposium on quality electronic design (isqed'05), 2005, pp. 476-481, doi: 10.1109/ISQED.2005.81.

Charged Device Model (CDM) Qualification Issues - Expanded [https://www.jedec.org/sites/default/files/IndustryCouncil_CDM_October2021_JEDECversion_September2022_rev1.pdf]

Wang, Albert ZH. On-chip ESD protection for integrated circuits: an IC design perspective. Vol. 663. Springer Science & Business Media, 2002.

Wang, Albert. Practical ESD Protection Design. John Wiley & Sons, 2021.

Ker, Ming-Dou, and Sheng-Fu Hsu. Transient-induced latchup in CMOS integrated circuits. John Wiley & Sons, 2009. [https://picture.iczhiku.com/resource/eetop/wyiGjQaHOgrYFcxB.pdf]

Milin Zhang, "Low Power Circuit Design Using Advanced CMOS Technology" River Publishers 2018

Barry Fernelius, Evans Analytical Group. Latch-up Testing [https://site.ieee.org/ocs-cpmt/files/2013/06/Latch-up_at_EAG_IEEE_September_2013.pdf]

M. -D. Ker and Z. -H. Jiang, "Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions," in IEEE Journal of the Electron Devices Society, vol. 11, pp. 141-152, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9998049]

It depends on the simulator:

• QuestaSim, Xcelium: You have to import pkg or `include file in top testbench
• VCS: VCS automatically search testcase in other Compilation Units

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

// test_pkg.sv
package sim_pkg;
	import uvm_pkg::*;
	`include "uvm_macros.svh"

	class my_test extends uvm_test;
		`uvm_component_utils(my_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of my_test", UVM_LOW)
		endtask : run_phase
	endclass : my_test

	class its_test extends uvm_test;
		`uvm_component_utils(its_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of its_test", UVM_LOW)
		endtask : run_phase
	endclass : its_test

endpackage : sim_pkg

1
2
3
4
5
6
7
8
9

// tb_top.sv
module tb_top;
	import uvm_pkg::*;
	//import sim_pkg::*;

	initial begin
		run_test();
	end
endmodule

Xcelium log:

UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. UVM_INFO /home/EDA/Cadence/XCELIUM2109/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 0: reporter [UVM/REPORT/CATCHER]

QuestaSim log:

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) # UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. # UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. # UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]

solution:

uncomment //import sim_pkg::*; in tb_top.sv

FSDB

$fsdbDumpfile

It specifies the FSDB file name created by the Novas object files for FSDB dumping. If it is not specified, then the default FSDB file name is "novas.fsdb".

This command is valid only before executing $fsdbDumpvars and is ignored if specified after $fsdbDumpvars

$fsdbSuppress

The fsdbSuppressutility is used to skip dumping of few instances, scopes, modules and signals. The fsdbSuppressutility is a system task like other fsdb tasks.

For $fsdbSuppress() to be effective, it needs to be specified/called before $fsdbDumpvars

$fsdbAutoSwitchDumpfile

Automatically switch to a new dump file when the working FSDB file reaches the specified size or the specified wall time period.

After the dumping is finished, a virtual FSDB file (*.vf) is automatically created and list all of the generated FSDB files with the correct sequence. Only the virtual FSDB file, rather than all of the FSDB files, needs to be loaded to view the simulation results

When specified in the design to switch based on file size:

1

$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"]);

When specified in the design to switch based on time period

1

$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"], “+by_period”);

“+by_period”

$fsdbDumpvars

This command dumps the change in signal value to the FSDB file.

1

$fsdbDumpvars([ depth, | "level=",depth_var, ],[instance | "instance=",instance_var])

For VCS users, to include memory, MDA, packed array and structure information in the generated FSDB file, the -debug_access option must be included when VCS is invoked to compile the design

• depth

  Specify how many sub-scope levels under the given scope you want to dump.

  • Specify this argument as 1 to dump the signals under the given scope
  • Specify this argument as 0 to dump all signals under the given scope and its descendant scopes.

  0: all signals in all scopes.

  1: all signals in current scope.

  2: all signals in the current scope and all scopes one level below.

  n: all signals in the current scope and all scopes n-1 levels below.

  	tb.clk	tb.u_div2.div2	tb.u_div2.u_div2neg.div2neg
  $fsdbDumpvars(0)	✓	✓	✓
  $fsdbDumpvars(1)	✓	✗	✗
  $fsdbDumpvars(2)	✓	✓	✗
  $fsdbDumpvars(1, tb.u_div2)	✗	✓	✗
  $fsdbDumpvars(0, tb.u_div2)	✗	✓	✓

  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

  module tb; reg clk; divider2 u_div2(clk); initial begin clk = 1'b0; forever #5 clk = ~clk; end initial begin #100; $finish(); end initial begin #10; $fsdbDumpfile("tb.fsdb"); //$fsdbDumpvars(0); // same with $fsdbDumpvars(0, tb) //$fsdbDumpvars(1); // same with $fsdbDumpvars(1, tb) //$fsdbDumpvars(2); // same with $fsdbDumpvars(2, tb) //$fsdbDumpvars(1, tb.u_div2); $fsdbDumpvars(0, tb.u_div2); #80 $finish(); end endmodule module divider2 ( input clk ); reg div2; divider2neg u_div2neg(div2); always@(posedge clk) begin div2 = ~div2; end initial begin div2 = 1'b0; end endmodule module divider2neg ( input clk ); reg div2neg; always@(negedge clk) begin div2neg = ~div2neg; end initial begin div2neg= 1'b0; end endmodule

  compile

  1	vcs -full64 -kdb -debug_access+all tb.v

  simulate

  1

  ./simv

  load fsdb

  1	verdi -ssf tb.fsdb

  

$fsdbDumpon, $fsdbDumpoff

1
2
3

$fsdbDumpon(["+fsdbfile+filename"])

$fsdbDumpoff(["+fsdbfile+filename"])

These FSDB dumping commands turn dumping on and off. fsdbDumpon/fsdbDumpoff has the highest priority and overrides all other FSDB dumping commands.

fsdbDumpon/fsdbDumpoff is not restricted to only fsdbDumpvars. If there is more than one FSDB file open for dumping at one simulation run, fsdbDumpon/fsdbDumpoff may only affect a specific FSDB file by specifying the specific file name.

• +fsdbfile+filename: Specify the FSDB file name. If not specified, the default FSDB file name is "novas.fsdb"

$fsdbDumpFinish

This command closes all FSDB files in the current simulation and stops dumping of signals. Although all FSDB files are closed automatically at the end of simulation, this dumping command can be invoked to explicitly close the FSDB files during the simulation

VCD

$dumpfile

The declaration onf $dumpfile must come before the $dumpvars or any other system tasks that specifies dump.

1

$dumpfile("test.vcd");

argument is necessary, there is no default value

$dumpvars

The $dumpvars is used to specify which variables are to be dumped ( in the file mentioned by $dumpfile). The simplest way to use it is without any argument.

1

$dumpvars(<levels> <, <module_or_variable>>* );

$dumplimit

It is possible that you inadvertantly generate huge file in Gigabytes ( for examples while dumping a Gigahertz clock for one second). To reduce such occurrences, we may use $dumplimit. It usage is

1

$dumplimit(<filesize>);

$dumpoff and $dumpon

During the simulation if you are bothered about about only during a certain interval then you can use $dumpoff and $dumpon. The following example shows its usage. It will dump the changes for first 100 units of time and then between 10200 and 10400 units of time.

1
2
3
4
5
6
7
8
9
10
11
12

initial
    $monitor($time, " reset=%b,clk_out=%b",reset,clk_out);
    initial begin
            $dumpfile("clkdiv2n_tb.vcd");
            $dumpvars(0,clkdiv2n_tb);
            #100;
            $dumpoff;
            #10200;
            $dumpon;
            #10400;
            $dumpoff;
    end

demo

stimulus.v

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

`timescale 1ns / 1ps
module stimulus;
	// Inputs
	reg x;
	reg y;
	// Outputs
	wire z;
	// Instantiate the Unit Under Test (UUT)
	comparator uut (
		.x(x),
		.y(y),
		.z(z)
	);

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0);
		// Initialize Inputs
		x = 0;
		y = 0;

		#20 x = 1;
		#20 y = 1;
		#20 y = 0;
		#20 x = 1;
		#40 ;

	end

	initial begin
		$monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,z, );
	end

endmodule

comparator.v

1
2
3
4
5
6
7
8
9

module comparator(
	input x,
	input y,
	output z
);

	assign z = (~x & ~y) |(x & y);

endmodule

1
2

$ xrun stimulus.v comparator.v -access +rwc
$ simvision test.vcd

reference

$dumpvars and $dumpfile Verilog, http://www.referencedesigner.com/tutorials/verilog/verilog_62.php

plusargs are command-line switches supported by the simulator. As per SystemVerilog LRM arguments beginning with the + character will be available using the $test$plusargs and $value$plusargs PLI APIs.

1
2
3

$test$plusargs (user_string)

$value$plusargs (user_string, variable)

Example

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

// tb.v
module tb;
        int a;
        initial begin
                if($test$plusargs("RUNSIM")) begin
                        $display("There is RUNSIM plusargs");
                end else begin
                        $display("There is NO $test$plusargs");
                end
                if($value$plusargs("SEED=%d",a)) begin
                        $display("SEED=%d",a);
                end else begin
                        $display("There is NO $value$plusargs");
                end
        end
endmodule

• compile

  1 2	$ vlib work $ vlog -sv tb.v

• simulate (QuestaSim)

  • without plusargs

    1	$ vsim work.tb -c -do "run; exit"

    1 2 3 4 5 6 7 8 9

    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is NO $test$plusargs # There is NO $value$plusargs # exit # End time: 13:04:23 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

  • with plusargs

    1	$ vsim work.tb -c -do "run; exit" +SEED=31 +RUNSIM

    +SEED=31 +RUNSIM

    1 2 3 4 5 6 7 8 9

    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is RUNSIM plusargs # SEED= 31 # exit # End time: 13:04:55 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

reference

systemverilog-command-line-input URL: https://www.chipverify.com/systemverilog/systemverilog-command-line-input

PLUSARGS IN SYSTEMVERILOG URL:https://www.theartofverification.com/plusargs-in-systemverilog/