KNOW-HOW

Charged Device Model (CDM)

TODO 📅

Jordan Davis, Samsung Electronics. Full-Chip CDM Analysis: Is Static Simulation Enough? [https://www.synopsys.com/content/dam/synopsys/implementation&signoff/electrical-layout-verification-documents/esd-workshop-2021-pres.pdf]

Diode capacitance vs. Vpn

TODO 📅

PERC

• CD: current density checks

• P2P: point to point resistance checks

• LDL: logic driven layout checks, latch up related

• TOPO: topology, circuit connection and device size checks

database

• CD, P2P, LDL : dfmdb

• TOPO: svdb

Frank Feng. New Approach For Full Chip Electrical Reliability Verification [pdf]

Calibre PERC Catalog Test-Cases & Common Examples Version 2.0

Latchup

Latch-up in CMOS circuits: threat or opportunity (part 1) [https://monthly-pulse.com/2021/01/05/latch-up-in-cmos-circuits-threat-or-opportunity-part-1/]

Latch-up in CMOS circuits: threat or opportunity (part 2) [Latch-up in CMOS circuits: threat or opportunity (part 2)]

This can happen when a parasitic thyristor, which is essentially a pair of interconnected transistors, is triggered into a latched state, leading to sustained current flow and potential device failure.

Necessary Conditions

Trigger Modes

latchup-prevention technique

Technical Paper Ensuring latch-up guard rings ESDA rules using Calibre PERC [https://resources.sw.siemens.com/en-US/technical-paper-ensuring-latch-up-guard-rings-esda-rules-using-calibre-perc/]

Guard Rings

One important technique is the use of guard rings, the heavily doped regions surrounding sensitive components on the IC to divert excess current away from vulnerable areas, thereby reducing the likelihood of latch-up occurrence

These guard rings not only function as barriers against parasitic thyristor (SCR) formation but also serve to isolate different regions of the IC, minimizing unwanted electrical interactions and maintaining pathway integrity

P.E. Allen - 2016. CMOS Analog Circuit Design: Lecture 08 – Latchup and ESD (4/25/16) [https://aicdesign.org/wp-content/uploads/2018/08/lecture08-160425.pdf]

Transient-Induced Latchup

OD injector

Diode in ESD Protection

A diode can operate in both forward and reverse modes for ESD protection.

\(R_{ON}\) for a forward-biased diode is lower than that for a reverse-biased diode

One major disadvantage of a forward diode-string for ESD protection is that the leakage current (Ileak) may be enlarged due to the Darlington effect in the diode-string

Silicon Controlled Rectifiers (SCR)

A thyristor (also known as a Silicon Controlled Rectifier or SCR) is a three-terminal semiconductor device used as an electronic switch or rectifier

To turn the thyristor on, a positive voltage pulse is applied to the gate (G) terminal. This voltage pulse needs to be of sufficient magnitude to trigger the device. When the gate is triggered, it allows a small current to flow into the base of the P-N-P transistor within the thyristor structure

[https://ec2-44-207-46-173.compute-1.amazonaws.com/thyristor/]

ESD design window

[https://monthly-pulse.com/2021/06/02/the-esd-design-window-concept/]

[https://www.researching.cn/ArticlePdf/m00098/2020/41/12/122403.pdf]

• Transparency
  • Trigger voltage Vt1
  • Holding/clamping voltage Vh
• Robustness
  • failure current level It2
• Effectiveness
  • maximum voltage of the clamp device: Vmax

You Li. CICC2020: ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies

[https://picture.iczhiku.com/weixin/message1640668908028.html]

ESD工作区称为“设计窗口”

保护设备的触发电压(V t1)定义了它设计为导通的电平; 触发后的保持电压(V Hold)是指应高于施加电压的钳位电平。最后，I t2是指ESD故障电流水平。

如蓝色曲线(1A或1B)所示，NMOS晶体管在触发点V t1处进入双极击穿(npn)，并迅速恢复为称为V Hold的保持电压，并保护高达故障电流I ESD对应于ESD目标水平。(I t2，V t2)是指保护设备可能烧坏的散热点，因此该I t2必须大于I ESD目标电流水平(例如，目标1.5 kV HBM的电流为1 Amp)。如果保护设备的导通电阻(R on)太高，则V t2也可能达到可靠性电压极限。钳位电路必须有效触发，以使其电压累积不超过栅极氧化层击穿电压(BV ox)或晶体管击穿电压。晶体管的V Hold经过设计，使其具有一定的工作电压裕度，如曲线1A所示。相反，在具有V Hold的快速恢复装置小于工作电压(曲线1B)的情况下，存在EOS损坏的风险。

Two-Stage ESD Protection

two-stage primary–secondary ESD protection

a primary ESD protection structure (ESD1), a secondary ESD protection unit (ESD2), and an isolation resistor (\(R\))

The desired specs for ESD2 is low \(V_\text{t1}\) and short \(t_1\), while that for ESD1 include low \(R_{ON}\), low \(V_\text{h}\) and high \(I_\text{t2}\)

• The primary ESD1 structure is typically optimized for high ESD protection level, which however may feature a high ESD \(V_\text{t1}\), not suitable for low-voltage (LV) ICs

• The secondary ESD2 unit serves as a trigger-assisting device that features a lower ESD \(V_\text{t1}\) and fast ESD triggering, which is typically weak in handling large ESD discharge currents

The isolation \(R\) has another role, which is to prevent an ESD pulse from getting into IC core (i.e., stressing the input device) directly, hence avoid possible CMOS gate breakdown

\(R\) involves a design trade-off too: large enough for fast voltage build up, but not too large to avoid adverse impact on signal propagation

The two-stage ESD protection method is re-gaining attention for CDM ESD protection because it can handle large ESD surges without overheating, while preventing CMOS gate breakdown due to the isolation R (i.e., no direct zapping on the input gate)

1. Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors.
2. ESD current through this clamp will build-up voltage across the isolation resistance, while protecting the circuit.
3. The higher voltage at the IN pad will then trigger the primary protection (red current path)

Adding a (small) clamp behind the isolation resistance can extend the ESD design window, e.g. enabling dual diode protection for thin oxide transistors

Extended ESD design window example. The failure voltage of a thin gate oxide in advanced CMOS is about 4V. The primary ESD solution (red IV curve) introduces too much voltage. Thanks to an isolation resistance between primary and secondary local clamp device (green IV curve) additional margin is created.

[https://monthly-pulse.com/2022/03/29/introduction-esd-protection-concepts-for-i-os/]

Okushima, M. and Tsuruta, J., "Secondary ESD clamp circuit for CDM protection of over 6Gbit/s SerDes application in 40nm CMOS", Microelectronics Reliability, vol. 53, no. 2, pp. 215–220, 2013 [https://sci-hub.se/https://doi.org/10.1016/j.microrel.2012.04.010]

Gated diode & STI diode

"gated diode" aka. "poly bound" diode

STI bound diodes typically have lower capacitance

M. Simicic, G. Hellings, S. -H. Chen, N. Horiguchi and D. Linten, "ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology," 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, Germany, 2018

US9653448B2. Electrostatic Discharge (ESD) Diode in FinFET Technology

?? Rotated STI Diode

Loke, Alvin & Yang, (2018). Analog/mixed-signal design challenges in 7-nm CMOS and beyond. 10.1109/CICC.2018.8357060.

Shih-Hung Chen. CICC 2019: Designing Diode Based ESD Protection in Advanced State of the Art Technologies

TLP/vf-TLP

TRANSMISSION LINE PULSE TESTING: THE INDISPENSABLE TOOL FOR ESD CHARACTERIZATION OF DEVICES, CIRCUITS AND SYSTEMS [https://www.esda.org/assets/News/1708-ESD-firstDraft.pdf]

[https://monthly-pulse.com/2021/06/08/transmission-line-pulse-tlp-test-system/]

Jon Barth "TLP and VFTLP Testing of Integrated Circuit ESD Protection" [https://barthelectronics.com/wp-content/uploads/2016/09/TLP-and-VFTLP-Test-of-Integrated-Circuit-ESD-Protection.pdf]

Horst A. Gieser(IZM), "ESD- Testing: HBM to very fast TLP" [https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf]

Vt1: trigger voltage

Vhold: holding voltage

soft failure current: Isoft

hard failure current: It2

TLP vs ESD

• ESD tests simulate real world events (HBM, MM, CDM)
• TLP does not simulate any real-world event
• ESD tests record failure level (Qualification)
• TLP tests record failure level and device behavior (Characterization)

TLP is not a qualification test, but a characterization method, which describes the resistance of a device for a given stimulus, aka. Device Characterization

Unlike ESD waveforms, TLP does not mimic any real world event

TLP and Curve Tracing

• Curve Tracing is DC; TLP is a short pulse
  • Shorter pulse - Reduced duty cycle, less heating, which means higher voltage before failure
  • Controlled Impedance - Allows device behavior to be observed
• Both measure resistance of device with increasing voltage

Device Characterization with TLP

• Turn-on time
• Snapback voltage
• Performance changes with rise time

VF-TLP and CDM differences

Question:

How well will VF-TLP results predict CDM testing performance?

Answer:

VF-TLP can be a guide to CDM failure levels, and provide a lot of understanding of a circuit's operation during CDM stressing, but simple correlations between VF-TLP failure current level and CDM withstand voltage levels are difficult to establish.

I.V and Leakage Evolution Plots

DC leakage current data combined with the I-V data provides electrical indications of where damage begins, and how rapidly it can evolve from soft to hard failures

Henry, Leo & Barth, Jon & Richner, John & Verhaege, Koen. (2000). Transmission Line Pulse Testing of the ESD Protection Structures in ICs - A Failure Analyst's Perspective. 203-213. 10.31399/asm.cp.istfa2000p0203. [https://barthelectronics.com/pdf_files/2000%20ISTFA%20TLP%20Testing%20of%20the%20ESD%20Protection%20Structure.pdf]

Henry, L.G. & Barth, Jon & Verhaege, K. & Richner, J.. (2001). Transmission-line pulse ESD testing of ICs: A new beginning. Compliance Engineering. 18. 46+53. [https://barthelectronics.com/pdf_files/CE%20TLP%20Article%20March-April%202001.pdf]

Snapback devices

Lesson 2 - ESD Clamps [https://aicdesign.org/wp-content/uploads/2021/05/Lesson02_ESD_Clamps210315.pdf]

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis - Device Level [https://www.esdemc.com/public/docs/TechnicalSlides/ESDEMC_TS001.pdf]

BJT

Grounded-gate NMOS (ggNMOS)

[https://monthly-pulse.com/2022/02/02/time-to-say-farewell-to-the-snapback-ggnmos-for-esd-protection/]

[https://monthly-pulse.com/2023/01/26/ggnmos-grounded-gated-nmos/]

snapback ggNMOS for ESD protection

Influence of the pulse rise time on ggNMOS. (left side) A fast ESD pulse can couple the bulk of the NMOS to a higher potential for a short period, reducing the trigger voltage. (right side) A clear Vt1 reduction is visible, while the remaining part of the IV curve remains the same.

[https://picture.iczhiku.com/weixin/message1588643699565.html]

一般都是把Gate/Source/Bulk短接在一起，把Drain结在I/O端承受ESD的浪涌(surge)电压，NMOS称之为GGNMOS (Gate-Grounded NMOS)PMOS称之为GDPMOS (Gate-to-Drain PMOS)。以NMOS为例，原理都是Gate关闭状态，Source/Bulk的PN结本来是短接0偏的，当I/O端有大电压时，则Drain/Bulk PN结雪崩击穿，瞬间bulk有大电流与衬底电阻形成压差导致Bulk/Source的PN正偏，所以这个MOS的寄生横向NPN管进入放大区(发射结正偏,集电结反偏)，所以呈现特性，起到保护作用。PMOS同理推导。

Trigger电压/Hold电压: Trigger电压当然就是之前将的的第一个拐点(Knee-point)，寄生BJT的击穿电压，而且要介于BVCEO与BVCBO之间。而Hold电压就是要维持持续ON，但是又不能进入栅锁(Latch-up)状态，否则就进入二次击穿(热击穿)而损坏了。还有个概念就是二次击穿电流，就是进入Latch-up之后I^2*R热量骤增导致硅融化了，而这个就是要限流，可以通过控制W/L，或者增加一个限流高阻， 最简单最常用的方法是拉大Drain的距离/拉大SAB的距离(ESD rule的普遍做法)。

PN结的击穿分两种，分别是电击穿和热击穿，电击穿指的是雪崩击穿, Avalanche Breakdown (低浓度)和齐纳击穿(高浓度)，而这个电击穿主要是载流子碰撞电离产生新的电子-空穴对(electron-hole)，所以它是可恢复的。但是热击穿是不可恢复的，因为热量聚集导致硅(Si)被熔融烧毁了。所以我们需要控制在导通的瞬间控制电流，一般会在保护二极管再串联一个高电阻，

Gate-coupled NMOS (gcNMOS)

Ming-Dou Ker, Chung-Yu Wu, Tao Cheng and Hun-Hsien Chang, "Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 3, pp. 307-321, Sept. 1996 [https://ir.lib.nycu.edu.tw/bitstream/11536/1053/1/A1996VE01800002.pdf]

Gate-coupled NMOS (gcNMOS) was proposed to effectively reduce the \(V_\text{t1}\)

[https://bbs.eetop.cn/forum.php?mod=redirect&goto=findpost&ptid=353178&pid=7305079]

SCR (thyristor)

Guang Chen, Haigang Feng and A. Wang, "A systematic study of ESD protection structures for RF ICs," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, Philadelphia, PA, USA, 2003 [https://sci-hub.se/10.1109/RFIC.2003.1213959]

[https://www.sharecourse.net/sharecourse/upload/course/180/c574580760de44d2c6fb66d8be4c6d4a.pdf]

Safe operating area (SOA)

power clamp

Thanks to the device scaling the area is actually reasonable. However, the leakage becomes the main bottleneck.

high current diode (HIA)

both diode are reverse-biased in normal operation, the PN Junction capacitance is proportional to forward-bias voltage

HIA_DIO can be used for logic or high speed circuits ESD protection

HIA: high current application purpose (High Amp)

There is no process difference between HIA_DIO and regular diode

• diode is drain/source originated, which is different from MOS (Gate originated)

• The perimeter of diode in DRC is different from that in PERC deck, where PERC excludes the the left and right edge of OD

g after the rule numbers: DFM recommendations and guidelines

^U: the rule is not checked by the DRC

I-V curve

MOS

l in netlist has different definition for MOS and diode.

MOS: length of channel

diode: Gate space

HIA = High Amp

lateral diode: perimeter is key DRC rule for ESD diode

HIA diode process is same with regular junction diode

Dual Stacked Diodes

PS: I/O to GND positively

NS: I/O to GND negatively

PD: I/O to VDD positively

ND: I/O to VDD negatively

Dual diode should be used with power clamp for PS and ND path

PMOS power clamp

EOS

[https://picture.iczhiku.com/weixin/message1640668908028.html]

尽管通常ESD保护的设计并非旨在防止EOS事件，但根据特定的应用和操作，上述器件的ESD保护的IC 设计风格确实可以影响EOS损坏导致的故障率。环境。图2说明了两个不同的骤回设备，其中设备1与设备2的设计相比相对安全。设备2的EOS风险增加是由于V Hold参数低于最大允许VDD。

CMOS集成电路闩锁效应 - 摘录

CMOS闩锁效应的发展

闩锁效应是以体CMOS工艺为基础的集成电路特有的现象，无论是一般的常规体CMOS工艺集成电路，还是从CMOS工艺衍生出来的BiCMO、BCD和HV-CMOS等，都会发生闩锁效应。

• 降低寄生BJT的放大系数
• 降低衬底等效电阻

双极型晶体管

双极型晶体管的四种工作模式下集电结和发射结外加偏置电压

1）正向有源：双极型晶体管的发射结正偏和集电结反偏。工作在正向有源区的双极型晶体管具有电流放大功能，它的放大系数是\(\beta\)，\(\beta\)是集电极电流与基极电流的比，\(\beta\)是一个非常关键的参数，通常双极型晶体管设计和制造工艺参数的变动都是为了获得足够大的\(\beta\)。正向有源是一种常用的工作区

2）饱和：双极型晶体管的发射结和集电结都正偏，它相当于两个并联的二极管。

3）倒置：双极型晶体管发射结反偏和集电结正偏。与正向有源相比，它们的角色倒置了。工作在倒置区的双极型晶体管也具有电流放大功能，不过其放大系数会比正向有源小几倍。实际应用中也很少会把双极型晶体管偏置在倒置区。

4）截止：双极型晶体管的发射结和集电结都反偏，其漏电流非常微弱，就像开路的开关

根据双极型晶体管的电极被输入和输出共用的情况，可以把双极型晶体管分为三种电路连接方式

双极型晶体管的击穿电压

双极型晶体管两个PN结的反向击穿电压有以下三种：

第一种是发射极开路时的BVCBO； 第二种是集电极开路时的BVEBO； 第三种是基极开路时的BVCEO。

这三个击穿电压的关系如下：BVCBO＞BVCEO＞BVEBO

NPN闩锁效应

在CMOS集成电路中，不仅寄生的PNPN结构会发生闩锁效应，单个NMOS自身寄生NPN也会发生闩锁效应

与PNPN类似，从寄生NPN I-V曲线可以看出，有两种方式可以使寄生NPN工作状态进入BC段的闩锁态：

• 第一种是出现瞬态激励电压大于等于Vt1，从而产生雪崩击穿电流，使寄生NPN进入闩锁态，这种方式称为电压触发；
• 第二种是出现瞬态激励电流，该电流大于等于B点对应的电流Ih，使寄生NPN进入闩锁态，这种方式称为电流触发。

Reference

Wang, Albert. Practical ESD Protection Design. John Wiley & Sons, 2021.

温德通. CMOS集成电路闩锁效应. 机械工业出版社, 2020

Introduction to Transmission Line Pulse (TLP), URL: https://tools.thermofisher.com/content/sfs/brochures/TLP%20Presentation%20May%202009.pdf

VF-TLP and CDM differences, URL: https://www.grundtech.com/app-note-vf-tlp-cdm-differences

ESD-Testing: HBM to very fast TLP URL: https://www.thierry-lequeu.fr/data/ESREF/2004/Tut5.pdf

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1-6, doi: 10.1109/CICC48029.2020.9075899.

KOEN DECOCK IEEE-SSCSLEUVEN "ON-CHIP ESD PROTECTION: BASIC CONCEPTS AND ADVANCED APPLICATIONS" [https://monthly-pulse.com/wp-content/uploads/2021/11/2021-11-sofics_presentation_ieee_final.pdf]

Yuanzhong Zhou, D. Connerney, R. Carroll and T. Luk, "Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models," Sixth international symposium on quality electronic design (isqed'05), 2005, pp. 476-481, doi: 10.1109/ISQED.2005.81.

Charged Device Model (CDM) Qualification Issues - Expanded [https://www.jedec.org/sites/default/files/IndustryCouncil_CDM_October2021_JEDECversion_September2022_rev1.pdf]

Wang, Albert ZH. On-chip ESD protection for integrated circuits: an IC design perspective. Vol. 663. Springer Science & Business Media, 2002.

Ker, Ming-Dou, and Sheng-Fu Hsu. Transient-induced latchup in CMOS integrated circuits. John Wiley & Sons, 2009. [https://picture.iczhiku.com/resource/eetop/wyiGjQaHOgrYFcxB.pdf]

Milin Zhang, "Low Power Circuit Design Using Advanced CMOS Technology" River Publishers 2018

Barry Fernelius, Evans Analytical Group. Latch-up Testing [https://site.ieee.org/ocs-cpmt/files/2013/06/Latch-up_at_EAG_IEEE_September_2013.pdf]

M. -D. Ker and Z. -H. Jiang, "Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions," in IEEE Journal of the Electron Devices Society, vol. 11, pp. 141-152, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9998049]

Shih-Hung Chen. CICC 2019. ES2-4 "ESD Challenges in Advanced FinFET & GAA Nanowire CMOS technologies"

Y. Li, M. Miao and R. Gauthier, "ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020

S. Kim et al., "Technology Scaling of ESD Devices in State of the Art FinFET Technologies," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020

It depends on the simulator:

• QuestaSim, Xcelium: You have to import pkg or `include file in top testbench
• VCS: VCS automatically search testcase in other Compilation Units

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// test_pkg.sv
package sim_pkg;
	import uvm_pkg::*;
	`include "uvm_macros.svh"

	class my_test extends uvm_test;
		`uvm_component_utils(my_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of my_test", UVM_LOW)
		endtask : run_phase
	endclass : my_test

	class its_test extends uvm_test;
		`uvm_component_utils(its_test)
		
		function new(string name, uvm_component parent);
			super.new(name, parent);
		endfunction : new

		task run_phase(uvm_phase phase);
			`uvm_info(get_type_name(), "this is run_phase of its_test", UVM_LOW)
		endtask : run_phase
	endclass : its_test

endpackage : sim_pkg

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// tb_top.sv
module tb_top;
	import uvm_pkg::*;
	//import sim_pkg::*;

	initial begin
		run_test();
	end
endmodule

Xcelium log:

UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. UVM_INFO /home/EDA/Cadence/XCELIUM2109/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 0: reporter [UVM/REPORT/CATCHER]

QuestaSim log:

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) # UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory. # UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=my_test not found. # UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]

solution:

uncomment //import sim_pkg::*; in tb_top.sv

FSDB

$fsdbDumpfile

It specifies the FSDB file name created by the Novas object files for FSDB dumping. If it is not specified, then the default FSDB file name is "novas.fsdb".

This command is valid only before executing $fsdbDumpvars and is ignored if specified after $fsdbDumpvars

$fsdbSuppress

The fsdbSuppressutility is used to skip dumping of few instances, scopes, modules and signals. The fsdbSuppressutility is a system task like other fsdb tasks.

For $fsdbSuppress() to be effective, it needs to be specified/called before $fsdbDumpvars

$fsdbAutoSwitchDumpfile

Automatically switch to a new dump file when the working FSDB file reaches the specified size or the specified wall time period.

After the dumping is finished, a virtual FSDB file (*.vf) is automatically created and list all of the generated FSDB files with the correct sequence. Only the virtual FSDB file, rather than all of the FSDB files, needs to be loaded to view the simulation results

When specified in the design to switch based on file size:

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$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"]);

When specified in the design to switch based on time period

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$fsdbAutoSwitchDumpfile(File_Size | File_Size_var, "FSDB_Name" |FSDB_Name_var, Number_of_Files | Number_of_Files_var[ ,"log_filename" | ,log_filename_var ], ["+no_overwrite"], “+by_period”);

“+by_period”

$fsdbDumpvars

This command dumps the change in signal value to the FSDB file.

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$fsdbDumpvars([ depth, | "level=",depth_var, ],[instance | "instance=",instance_var])

For VCS users, to include memory, MDA, packed array and structure information in the generated FSDB file, the -debug_access option must be included when VCS is invoked to compile the design

• depth

  Specify how many sub-scope levels under the given scope you want to dump.

  • Specify this argument as 1 to dump the signals under the given scope
  • Specify this argument as 0 to dump all signals under the given scope and its descendant scopes.

  0: all signals in all scopes.

  1: all signals in current scope.

  2: all signals in the current scope and all scopes one level below.

  n: all signals in the current scope and all scopes n-1 levels below.

  	tb.clk	tb.u_div2.div2	tb.u_div2.u_div2neg.div2neg
  $fsdbDumpvars(0)	✓	✓	✓
  $fsdbDumpvars(1)	✓	✗	✗
  $fsdbDumpvars(2)	✓	✓	✗
  $fsdbDumpvars(1, tb.u_div2)	✗	✓	✗
  $fsdbDumpvars(0, tb.u_div2)	✗	✓	✓

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  module tb; reg clk; divider2 u_div2(clk); initial begin clk = 1'b0; forever #5 clk = ~clk; end initial begin #100; $finish(); end initial begin #10; $fsdbDumpfile("tb.fsdb"); //$fsdbDumpvars(0); // same with $fsdbDumpvars(0, tb) //$fsdbDumpvars(1); // same with $fsdbDumpvars(1, tb) //$fsdbDumpvars(2); // same with $fsdbDumpvars(2, tb) //$fsdbDumpvars(1, tb.u_div2); $fsdbDumpvars(0, tb.u_div2); #80 $finish(); end endmodule module divider2 ( input clk ); reg div2; divider2neg u_div2neg(div2); always@(posedge clk) begin div2 = ~div2; end initial begin div2 = 1'b0; end endmodule module divider2neg ( input clk ); reg div2neg; always@(negedge clk) begin div2neg = ~div2neg; end initial begin div2neg= 1'b0; end endmodule

  compile

  1	vcs -full64 -kdb -debug_access+all tb.v

  simulate

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  ./simv

  load fsdb

  1	verdi -ssf tb.fsdb

  

$fsdbDumpon, $fsdbDumpoff

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$fsdbDumpon(["+fsdbfile+filename"])

$fsdbDumpoff(["+fsdbfile+filename"])

These FSDB dumping commands turn dumping on and off. fsdbDumpon/fsdbDumpoff has the highest priority and overrides all other FSDB dumping commands.

fsdbDumpon/fsdbDumpoff is not restricted to only fsdbDumpvars. If there is more than one FSDB file open for dumping at one simulation run, fsdbDumpon/fsdbDumpoff may only affect a specific FSDB file by specifying the specific file name.

• +fsdbfile+filename: Specify the FSDB file name. If not specified, the default FSDB file name is "novas.fsdb"

$fsdbDumpFinish

This command closes all FSDB files in the current simulation and stops dumping of signals. Although all FSDB files are closed automatically at the end of simulation, this dumping command can be invoked to explicitly close the FSDB files during the simulation

VCD

$dumpfile

The declaration onf $dumpfile must come before the $dumpvars or any other system tasks that specifies dump.

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$dumpfile("test.vcd");

argument is necessary, there is no default value

$dumpvars

The $dumpvars is used to specify which variables are to be dumped ( in the file mentioned by $dumpfile). The simplest way to use it is without any argument.

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$dumpvars(<levels> <, <module_or_variable>>* );

$dumplimit

It is possible that you inadvertantly generate huge file in Gigabytes ( for examples while dumping a Gigahertz clock for one second). To reduce such occurrences, we may use $dumplimit. It usage is

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$dumplimit(<filesize>);

$dumpoff and $dumpon

During the simulation if you are bothered about about only during a certain interval then you can use $dumpoff and $dumpon. The following example shows its usage. It will dump the changes for first 100 units of time and then between 10200 and 10400 units of time.

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initial
    $monitor($time, " reset=%b,clk_out=%b",reset,clk_out);
    initial begin
            $dumpfile("clkdiv2n_tb.vcd");
            $dumpvars(0,clkdiv2n_tb);
            #100;
            $dumpoff;
            #10200;
            $dumpon;
            #10400;
            $dumpoff;
    end

demo

stimulus.v

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`timescale 1ns / 1ps
module stimulus;
	// Inputs
	reg x;
	reg y;
	// Outputs
	wire z;
	// Instantiate the Unit Under Test (UUT)
	comparator uut (
		.x(x),
		.y(y),
		.z(z)
	);

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0);
		// Initialize Inputs
		x = 0;
		y = 0;

		#20 x = 1;
		#20 y = 1;
		#20 y = 0;
		#20 x = 1;
		#40 ;

	end

	initial begin
		$monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,z, );
	end

endmodule

comparator.v

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module comparator(
	input x,
	input y,
	output z
);

	assign z = (~x & ~y) |(x & y);

endmodule

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$ xrun stimulus.v comparator.v -access +rwc
$ simvision test.vcd

reference

$dumpvars and $dumpfile Verilog, http://www.referencedesigner.com/tutorials/verilog/verilog_62.php

plusargs are command-line switches supported by the simulator. As per SystemVerilog LRM arguments beginning with the + character will be available using the $test$plusargs and $value$plusargs PLI APIs.

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$test$plusargs (user_string)

$value$plusargs (user_string, variable)

Example

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// tb.v
module tb;
        int a;
        initial begin
                if($test$plusargs("RUNSIM")) begin
                        $display("There is RUNSIM plusargs");
                end else begin
                        $display("There is NO $test$plusargs");
                end
                if($value$plusargs("SEED=%d",a)) begin
                        $display("SEED=%d",a);
                end else begin
                        $display("There is NO $value$plusargs");
                end
        end
endmodule

• compile

  1 2	$ vlib work $ vlog -sv tb.v

• simulate (QuestaSim)

  • without plusargs

    1	$ vsim work.tb -c -do "run; exit"

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    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is NO $test$plusargs # There is NO $value$plusargs # exit # End time: 13:04:23 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

  • with plusargs

    1	$ vsim work.tb -c -do "run; exit" +SEED=31 +RUNSIM

    +SEED=31 +RUNSIM

    1 2 3 4 5 6 7 8 9

    # // # Loading sv_std.std # Loading work.tb(fast) # run # There is RUNSIM plusargs # SEED= 31 # exit # End time: 13:04:55 on Jun 04,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0

reference

systemverilog-command-line-input URL: https://www.chipverify.com/systemverilog/systemverilog-command-line-input

PLUSARGS IN SYSTEMVERILOG URL:https://www.theartofverification.com/plusargs-in-systemverilog/

unsigned + unsigned = unsigned

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function [7:0] satadd_uuu8b;   // unsigned + unsigned = unsigned
    input [7:0] a;
    input [7:0] b;

    reg [8:0] t;   // extend 1b
    begin
        t = {1'b0, a} + {1'b0, b};
        satop_uuu16b = t[8] ? {8{1'b1}} : t[7:0];
    end
endfunction

1'b1: overflow

signed + signed = signed

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function [7:0] satadd_sss8b;    // signed + signed = signed
    input signed    [7:0] a;
    input signed    [7:0] b;

    reg signed [8:0] t; // extend 1b
    begin
        t = a + b;  // extend sign bit automatically
        satadd_sss8b =  (t[8:7] == 2'b01) ? {1'b0, 7{1'b1}} : // up sat
                        (t[8:7] == 2'b10) ? {1'b1, 7{1'b0}} : // dn sat
                                            t[7:0];
    end
endfunction

2'b01: overflow

2'b10: underflow

signed + unsigned = unsigned

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function [7:0] satadd_suu8b;    // signed + unsigned = unsigned
    input signed    [7:0] a;
    input           [7:0] b;

    reg signed [8:0] t; // extend 1b
    begin
        t = {a[7], a} + {1'b0, b};
        satadd_ssu8b =  (t[8:7] == 2'b10) ? {8{1'b1}} : // up saturate for unsigned
                        (t[8:7] == 2'b11) ? {8{1'b0}} : // dn saturate for unsigned
                                            t[7:0];
    end
endfunction

signed + unsigned = signed

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function signed [7:0] satop_sus8b;    //signed +/- unsigned = signed
    input signed    [7:0] a;
    input           [7:0] b;
    input plus;

    reg signed [8:0] t;    // extend 1b
    begin
        if(plus) begin
            t = {a[7], a} + {1'b0, b};
            satop_sus8b = (t[8:7]==2'b01) ? {1'b0, {7{1'b1}}}   // up saturate for signed
                                             : t[7:0];
        end else begin
            t = {a[7], a} - {1'b0, b};
            satop_sus8b = (t[8:7]==2'b10) ? {1'b1, {7{1'b0}}}   // dn saturate for signed
                                             : t[7:0];
        end
    end
endfunction

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain (AON).

To prevent corruption of always-on domain, we clamp the nets crossing the power domains to a value depending upon the design.

A simple circuit having a switchable (or gated) power domain

The circuit shown in Figure 1, after isolation cells are inserted

Always-On Buffer

reference

Isolation cells and Level Shifter cells URL: https://vlsitutorials.com/isolation-cells-level-shifter-cells-low-power-vlsi/

Jitter separation lets you learn if the components of jitter are random or deterministic. That is, if they are caused by crosstalk, channel loss, or some other phenomenon. The identification of jitter and noise sources is critical when debugging failure sources in the transmission of high-speed serial signals

• Tail Fit Method
• Spectral method

Jitter Components

dual-Dirac model

Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-scale [https://people.engr.tamu.edu/spalermo/ecen689/jitter_dual_dirac_agilent.pdf]

Spectral method

power spectral density (PSD) represents jitter spectrum and peaks in the spectrum can be interpreted as PJ or DDJ, while the average noise floor is the power of RJ

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S1 = sum(win);
S2 = sum(win.^2);
N = length(win);
spec_nospur2 = (spec_nospur*S1).^2/N/S2;    % To obtain linear spectrum for rj
rj_utj = sqrt(sum(spec_nospur2))*1e12;

spec = 1*ones(length(spec_nospur), 1)*1e-21;
spec(index) = specx(index);
% insert fft nyquist frequency component between positive frequency and
% negative frequency component
% DC;posFreq;nyqFreq;negFreq
spec_ifft = [spec;specnyq;conj(spec(end:-1:2))]';
sfactor = sum(win)/sqrt(2);
spec_ifft = spec_ifft*sfactor;
sig_rec = real(ifft(spec_ifft));
sig_rec = sig_rec(:);
sig_rec_utj = sig_rec./win(1:end);

Tail Fit Method

Tail fitting algorithm based on the Gaussian tail model by using probability distribution of collected jitter value

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bin_sig = bin_sig*1e12;

x = qfuncinv(cdf_sig);

% coef(1)*bin_sig + coef(2) = x
% which x is norm(0, 1)
% bin_sig = (x - coef(2))/coef(1)
% Then bin is norm(-coef(2)/coef(1), 1/coef(1))
coef = polyfit(bin_sig, x, 1);
sigma = 1/coef(1);
mu = -coef(2)*sigma;

fprintf('sigma=%.3fps, mu=%.3fps\n', sigma, mu);

Least Squares (LS) method

It is known that TIE jitter is a linear equation, shown in below formula \[ x[n] = d_n \times \left[ \Delta t_{pj}[n]+\Delta t_{DCD}[n] +\Delta t_{ISI}[n]+\Delta t_{RJ}[n]\right] \] LS can be used to estimate the PJ, DCD, RJ , and ISI parameters \([a,b,J_{DCD},J_0, J_1...J_{(2^k-1)}]\)

Jitter modeling

Periodic Jitter (PJ)

PJ is a repeating jitter \[ \Delta t_{PJ}[n]=A\sin(2\pi f_0\cdot nT_s + \theta)=a \sin(2\pi f_0 \cdot nT_s)+b\cos(2\pi f_0 \cdot nT_s) \] where \(f_0\) represents the fundamental frequency of PJ; \(A\) is the amplitude of PJ; \(T_s\) is the data stream period, and \(\theta\) is the initial phase of PJ

In the spectrum, the frequency of maximum amount of the jitter is PJ frequency \(f_0\).

Duty Cycle Distortion (DCD)

DCD is viewed as a series of adjacent positive and negative impulses \[ \Delta t_{DCD}[n] = J_{DCD}\times (-1)^n = [-J_{DCD},J_{DCD},-J_{DCD},J_{DCD},...] \] Where \(J_{DCD}\) is the DCD amplitude.

Random Jitter (RJ)

RJ is created by unbounded jitter sources, such as Gaussian white noise. The statistical PDF for RJ is enerally treated as a Gaussian distribution \[ f_{RJ}(\Delta t) = \frac{1}{\sqrt{2\pi\sigma}}\exp(-\frac{(\Delta t)^2}{2\sigma^2}) \]

Remarks

Periodic Jitter Generator and Insertion

Analysis and Estimation of Jitter Sub-Components: Classification and Segregation of Jitter Components

Reference

Mike Li. 2007. Jitter, noise, and signal integrity at high-speed (First. ed.). Prentice Hall Press, USA.

余宥浚 Jacky Yu, Keysight Taiwan AEO, Advanced Jitter and Eye-Diagram Analysis

Y. Duan and D. Chen, "Accurate jitter decomposition in high-speed links," 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, pp. 1-6, doi: 10.1109/VTS.2017.7928918.

Y. Duan's phd thesis URL: https://dr.lib.iastate.edu/handle/20.500.12876/30459

Y. Duan and D. Chen, "Fast and Accurate Decomposition of Deterministic Jitter Components in High-Speed Links," in IEEE Transactions on Electromagnetic Compatibility, vol. 61, no. 1, pp. 217-225, Feb. 2019, doi: 10.1109/TEMC.2018.2797122.

"Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-Scale", Whitepaper: Keysight Technologies, U.S.A., Dec. 2017

Sharma, Vijender Kumar and Sujay Deb. "Analysis and Estimation of Jitter Sub-Components." (2014).

Qingqi Dou and J. A. Abraham, "Jitter decomposition in ring oscillators," Asia and South Pacific Conference on Design Automation, 2006

E. Balestrieri, L. De Vito, F. Lamonaca, F. Picariello, S. Rapuano and I. Tudosa, "The jitter measurement ways: The jitter decomposition," in IEEE Instrumentation & Measurement Magazine, vol. 23, no. 7, pp. 3-12, Oct. 2020, doi: 10.1109/MIM.2020.9234759.

McClure, Mark Scott. "Digital jitter measurement and separation." PhD diss., 2005.

Ren, Nan, Zaiming Fu, Shengcu Lei, Hanglin Liu, and Shulin Tian. "Jitter generation model based on timing modulation and cross point calibration for jitter decomposition." Metrology and Measurement Systems 28, no. 1 (2021).

M. P. Li, J. Wilstrup, R. Jessen and D. Petrich, "A new method for jitter decomposition through its distribution tail fitting," International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, pp. 788-794, doi: 10.1109/TEST.1999.805809.

K. Bidaj, J. -B. Begueret and J. Deroo, "RJ/DJ jitter decomposition technique for high speed links," 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) [https://sci-hub.se/10.1109/ICECS.2016.7841269]

divide-by-1.5 circuit

TODO 📅

Phase Interpolator

A phase interpolator (PI) is normally used as a phase shifter (or phase rotator) to generate an output clock whose phase is precisely controlled

TODO 📅

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023. [http://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf]

Deterministic Jitter

j_Djpp can be calculated by PSD,too

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fck = 38.4e6;
Nfft = 15000;
fres = fck/Nfft;
psddBc = -99.3343;
psBc = psddBc + 10*log10(fres);	% psd -> ps; 
phrad2 = 10^(psBc/10);
phrms = sqrt(phrad2);
Jrms = phrms/2/pi*1/fck;
Jpp = 2*sqrt(2)*Jrms;

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Jpp =

   6.4038e-12

For DJ, we usually use peak to peak value

BTW, the psd value at half of fundamental frequency (\(f_s/2\)) is duty cycle distortion due to the NMOS/PMOS imbalance, because of rising only data

Random Jitter

RJ can be accurately and efficiently measured using PSS/Pnoise or HB/HBnoise.

Note that the transient noise can also be used to compute RJ;

However, the computation cost is typically very high, and the accuracy is lesser as compared to PSS/Pnoise and HB/HBnoise.

Since RJ follows a Gaussian distribution, it can be fully characterized using its Root-Mean-Squared value (RMS) or the standard deviation value (\(\sigma\))

The Peak-to-Peak value of RJ (\(\text{RJ}_{\text{p-p}}\)) can be calculated under certain observation conditions \[ \text{RJ}_{\text{p-p}}\equiv K \ast \text{RJ}_{\text{RMS}} \] Here, \(K\) is a constant determined by the BER specification of the system given in the following Table

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K = 14.698;
Ks = K/2;
p = normcdf([-Ks Ks]);
BER = 1 - (p(2)-p(1));

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BER =

   1.9962e-13

Total Jitter

\[ \text{TJ}_{\text{p-p}}\equiv \text{DJ}_{\text{p-p}} + \text{RJ}_{\text{p-p}}(\text{BER}) \]

In the psd of TJ, the spur is DJ and floor is RJ

Phase Noise to Jitter

The phase noise is traditionally defined as the ratio of the power of the signal in 1Hz bandwidth at offset \(f\) from the carrier \(P\), divided by the power of the carrier \[ \ell (f) = \frac {S_v'(f_0+f)}{P} \] where \(S_v'\) is is one-sided voltage PSD and \(f \geqslant 0\)

Under narrow angle assumption \[ S_{\varphi}(f)= \frac {S_v'(f_0+f)}{P} \] where \(\forall f\in \left[-\infty +\infty\right]\)

Using the Wiener-Khinchin theorem, it is possible to easily derive the variance of the absolute jitter(\(J_{ee}\))via integration of the corresponding PSD \[ J_{ee,rms}^2 = \int S_{J_{ee}}(f)df \]

And we know the relationship between absolute jitter and excess phase is \[ J_{ee}=\frac {\varphi}{\omega_0} \] Considering that phase noise is normally symmetrical about the zero frequency, multiplied by two is shown as below \[ J_{ee,rms} = \frac{\sqrt{2\int_{0}^{+\infty}\ell(f)df}}{\omega_0} \] where phase noise is in linear units not in logarithmic ones.

Because the unit of phase noise in Spectre-RF is logarithmic unit (dBc), we have to convert the unit before applying the above equation \[ \ell[linear] = 10^{\frac {\ell [dBc/Hz]}{10}} \] The complete equation using the simulation result of Spectre-RF Pnoise is \[ J_{ee,rms} = \frac{\sqrt{2\int_{0}^{+\infty}10^{\frac {\ell [dBc/Hz]}{10}}df}}{\omega_0} \]

The above equation has been verified for sampled pnoise, i.e. J_ee and Edge Phase Noise.

• For pnoise-sampled(jitter), Direct Plot Form - Function: Jee:Integration Limits can calculate it conveniently
• But for pnoise-timeaveage, you have to use the below equation to get RMS jitter.

One example, integrate to \(\frac{f_{osc}}{2}\) and \(f_{osc} = 16GHz\)

Of course, it apply to conventional pnoise simulation.

On the other hand, output rms voltage noise, \(V_{out,rms}\) divied by slope should be close to \(J_{ee,rms}\) \[ J_{ee,rms} = \frac {V_{out,rms}}{slope} \]

Pulse Width Jitter (PWJ)

TODO 📅

[Spectre Tech Tips: Measuring Noise in Digital Circuits]

Pnoise sampled: Edge Delay mode measures the noise defined by two edges. Both edges are defined by a threshold voltage and rising or falling edges, which measures the noise of the pulse itself and direct plot calculate the variation of the pulse width

Power supply induced jitter (PSIJ)

A sampled pxf analysis can be used to simulate the deterministic jitter of a circuit due to power supply ripple

TODO 📅

DCC & AC-coupled buffer

The amount of correction can be set by intentional injection of an offset current into the summing input node of INV, threshold-adjustable inverter

Note that the change to the threshold is opposite in direction to the change to INV

increasing DC of input signal is equivalent to lower down the threshold of INV

voltage at INV1 will increased by: \[ \frac{\Delta V_{DAC} - \Delta {INV1}}{R_{DAC}} = \frac{\Delta {INV1} +A_0 \Delta {INV1}}{R_{F}} \] therefore \[ \Delta {INV1} = \Delta V_{DAC} \cdot \frac{R_F}{R_F+(A_0+1)R_{DAC}} \approx \Delta V_{DAC} \cdot \frac{R_F}{A_0R_{DAC}} \]

If \(R_{DAC} = R_F\) \[ \Delta {INV1}\approx \frac{\Delta V_{DAC}}{A_0} \]

C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS," 2018 IEEE International Solid-State Circuits Conference - (ISSCC) [https://sci-hub.se/https://doi.org/10.1109/ISSCC.2018.8310205],[visual]

Bob Lefferts, Navraj Nandra. SNUG Israel 2007 [https://picture.iczhiku.com/resource/eetop/whKYwQorwYoPUVbm.pdf]

Since duty-cycle error is high frequency component, the high-pass filter suppresses the duty-cycle error propagating to the output

• The AC-coupling capacitor blocks the low-frequency component of the input
• The feedback resistor sets common mode voltage to the crossover voltage

Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices, 2020)

Casper B, O'Mahony F. Clocking analysis, implementation and measurement techniques for high-speed data links: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers. 2009;56(1):17-39

reference

Article (20500632) Title: How to simulate Random and Deterministic Jitters URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fiXeEAI

Spectre Tech Tips: Measuring Noise in Digital Circuits - Analog/Custom Design - Cadence Blogs - Cadence Community https://community.cadence.com/cadence_blogs_8/b/cic/posts/s . . .

Cadence RAK: Deterministic Jitter Measurement using SpectreRF

Frank Wiedmann. Using sampled pxf analysis to simulate deterministic jitter [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/51605/using-sampled-pxf-analysis-to-simulate-deterministic-jitter]

supply noise sensitivity: PSS+PAC or PSS+PX [https://designers-guide.org/forum/YaBB.pl?num=1376500816]

J. Kim et al., "A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 29-42, Jan. 2019, doi: 10.1109/JSSC.2018.2874040

— et al., "A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 6-20, Jan. 2022, doi: 10.1109/JSSC.2021.3108969

J. N. Tripathi, V. K. Sharma and H. Shrimali, "A Review on Power Supply Induced Jitter," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 3, pp. 511-524, March 2019 [https://sci-hub.st/10.1109/TCPMT.2018.2872608]

H. Kim, J. Fan and C. Hwang, "Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains," 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Washington, DC, USA, 2017 [https://sci-hub.st/10.1109/ISEMC.2017.8077937]

Yin Sun, Chulsoon Hwang EMC Laboratory. Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model [https://ibis.org/summits/aug20/sun.pdf]

High Speed Communications Part 8 – On Die CMOS Clock Distribution. [https://youtu.be/nx5CiHcwrF0?si=-eSO-LaaaFrVuIA1]

Low-Jitter CMOS Clock Distribution [https://youtu.be/LMT-T41Y64U?si=y8IpWCtU90zpe4Ob]

Mo, Xunjun & Wu, Jiaqi & Wary, Nijwm & Carusone, Tony. (2021). Design Methodologies for Low-Jitter CMOS Clock Distribution. IEEE Open Journal of the Solid-State Circuits Society. 1. 94-103. 10.1109/OJSSCS.2021.3117930. [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9559395]

Mozhgan Mansuri. ISSCC2021 SC3: Clocking, Clock Distribution, and Clock Management in Wireline/Wireless Subsystems [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC3.pdf]

Phillip Restle. ISSCC2021 SC4: Processor Clock Generation, Distribution, and Clock Sensor/Management Loops [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/SHORT%20COURSE/ISSCC2021-SC4.pdf]

Sam Palermo. Spring 2025 ECEN720 : High-Speed Links Circuits and Systems [Lecture 14: Clock Distribution Techniques]

DC offset

Performing FFT to a signal with a large DC offset would often result in a big impulse around frequency 0 Hz, thus masking out the signals of interests with relatively small amplitude.

One method to remove DC offset from the original signal before performing FFT

• Subtracting the Mean of Original Signal

You can also not filter the input, but set zero to the zero frequency point for FFT result.

Nyquist component

If we go back to the definition of the DFT \[ X(N/2)=\sum_{n=0}^{N-1}x[n]e^{-j2\pi (N/2)n/2}=\sum_{n=0}^{N-1}x[n]e^{-j\pi n}=\sum_{n=0}^{N-1}x[n](-1)^n \] which is a real number.

The discrete function \[ x[n]=\cos(\pi n) \] is always \((-1)^n\) for integer \(n\)

One general sinusoid at Nyquist and has phase shift \(\theta\), this is \(T=2\) and \(T_s=1\)

\[\begin{align} x[n] &= A \cos(\pi n + \theta) \\ &= A \big( \cos(\pi n) \cos(\theta) - \sin(\pi n) \sin(\theta) \big) \\ &= \big(A\cos(\theta)\big) \cos(\pi n) + \big(-A\sin(\theta)\big) \sin(\pi n) \\ &= \big(A\cos(\theta)\big) (-1)^n + \big(-A\sin(\theta)\big) \cdot 0 \\ &= B \cdot (-1)^n \\ \end{align}\]

Where \(A\cos(\theta)=B\).

Moreover \(B \cdot (-1)^n = B\cdot \cos(\pi n)\), then \[ B\cdot \cos(\pi n) = A \cdot \cos(\pi n + \theta) \] We can NOT distinguish one from another.

In other words, you CAN'T infer the signal from \(X(\frac{N}{2})\) \[\begin{align} X(k)\frac{1}{N}e^{j 2 \pi \frac{nk}{N}}\bigg|_{k=\frac{N}{2}} &= \frac{X\left(\frac{N}{2} \right)}{N}(-1)^n \\ &= \frac{X\left(\frac{N}{2} \right)}{N}\cos(\pi n) \\ &= \frac{X\left(\frac{N}{2} \right)}{N}\left( \cos(\pi n) - \beta \sin(\pi n) \right) \\ &= \frac{X\left(\frac{N}{2} \right)}{N}\sqrt{1+\beta^2}\left(\frac{1}{\sqrt{1+\beta^2}} \cos(\pi n) - \frac{\beta}{\sqrt{1+\beta^2}} \sin(\pi n) \right) \\ &= \frac{X\left(\frac{N}{2} \right)}{N} \frac{1}{\cos(\theta)}\left(\cos(\theta) \cos(\pi n) - \sin(\theta) \sin(\pi n) \right) \\ &= \frac{X\left(\frac{N}{2} \right)}{N} \frac{1}{\cos(\theta)} \cos(\pi n+\theta) \end{align}\]

where \(\beta \in \mathbb{R}\) and you wouldn't know it because \(\sin(\pi n)=0 \quad \forall n \in \mathbb{Z}\)

For example, if \(\theta=0\) \[ X(k)\frac{1}{N}e^{j 2 \pi \frac{nk}{N}}\bigg|_{k=\frac{N}{2}}= \frac{X\left(\frac{N}{2} \right)}{N} \cos(\pi n) \] However, if \(\theta=\frac{\pi}{3}\) \[ X(k)\frac{1}{N}e^{j 2 \pi \frac{nk}{N}}\bigg|_{k=\frac{N}{2}}= \frac{X\left(\frac{N}{2} \right)}{N}\cdot 2 \cos(\pi n+\frac{\pi}{3}) \]

That sort of ambiguity is the reason for the strict inequality of the sampling theorem's condition.

Duty Cycle Distortion

[Prof. Tony Chan Carusone, Low-Jitter CMOS Clock Distribution]

Both edges is used for clock waveform to evaluate the duty cycle distortion,

Assuming TIE is [0 0.2 0 0.2 0 0.2 ...], then subtract DC offset, we get [-0.1 0.1 -0.1 0.1 ...], shown as below

The amplitude is manifested in FFT amplitude spectrum, i.e. Nyquist component, which is 0.1 in follow figure

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N = 32;
n = (1:N);
x = 0.1*(-1).^n;
figure(1)
stem(n-1, x);
X = fft(x)/N;
Xshift = fftshift(X);
fprintf("nyquist component: %.2f\n", Xshift(1));
magXshift = abs(Xshift);
ph = phase(Xshift)/pi*180;
figure(2)
subplot(3, 1, 1)
fx = (-N/2:N/2-1);
stem(fx, magXshift);
xlabel('Freq');
ylabel('|X(k)|');
title('mag of DFT');
grid on;

subplot(3, 1, 2)
stem(fx, ph);
xlabel('Freq');
ylabel('\angle X(k)(^oC)');
title('phase of DFT');
grid on;

%% inverse dft
ninv = (0:32-1);
xinv = Xshift(1)*cos(pi*ninv);
subplot(3, 1, 3);
hold on;
stem(ninv, x, "filled", 'r');
stem(ninv, xinv,'bd-.');
ninfer = (0:0.1:32+1);
xinfer1 = Xshift(1)*cos(pi*ninfer); % theta = 0
xinfer2 = Xshift(1)*2*cos(pi*ninfer+pi/3); % theta = pi/3
plot(ninfer, xinfer1, 'm--');
plot(ninfer, xinfer2, 'c--');
hold off;
legend('original', 'IDFT', '\theta=0', '\theta=\pi/3');
xlabel('time');
ylabel('V');
title('sample points');
grid on;

Single-Sided Amplitude Spectrum

DC and Nyquist frequency of FFT left over

P1(2:end-1) = 2*P1(2:end-1);

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Fs = 1000;            % Sampling frequency
T = 1/Fs;             % Sampling period
L = 1500;             % Length of signal
t = (0:L-1)*T;        % Time vector
S = 0.7*sin(2*pi*50*t) + sin(2*pi*120*t);
X = S + 2*randn(size(t));
figure(1)
plot(1000*t(1:50),X(1:50))
title('Signal Corrupted with Zero-Mean Random Noise')
xlabel('t (milliseconds)')
ylabel('X(t)')

figure(2)
Y = fft(X);
P2 = abs(Y/L);      %!!! two-sided spectrum P2.
P1 = P2(1:L/2+1);   %!!! single-sided spectrum P1
P1(2:end-1) = 2*P1(2:end-1);	% exclude DC and Nyquist freqency
f = Fs*(0:(L/2))/L;
figure(2)
plot(f,P1)
title('Single-Sided Amplitude Spectrum of X(t)')
xlabel('f (Hz)')
ylabel('|P1(f)|')

Alternative View

The direct current (DC) bin (\(k=0\)) and the bin at \(k=N/2\), i.e., the bin that corresponds to the Nyquist frequency are purely real and unique.

sinusoidal waveform with \(10Hz\), amplitude 1 is \(cos(2\pi f_c t)\). The plot is shown as below with sampling frequency is \(20Hz\)

Amplitude and Phase spectrum, sampled with \(f_s=20\) Hz

The FFT magnitude of \(10Hz\) is 1 and its phase is 0 as shown as above, which proves the DFT and IDFT.

Caution: the power of FFT is related to samples (DFT Parseval's theorem), which may not be the power of continuous signal. The average power of samples is ([1 -1 1 -1 -1 1 ...]) is 1, that of corresponding continuous signal is \(\frac{1}{2}\).

Power spectrum derived from FFT provide information of samples, i.e. 1

Moreover, average power of sample [1 -1 1 -1 1 ...] is same with DC [1 1 1 1 ...].

code

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fc = 10;
fs = 2*fc;
fov = 64*fc;

ts = (0:1/fs:26);
tov = (0:1/fov:26);

ys = cos(2*pi*fc*ts);
yov = cos(2*pi*fc*tov);
%% waveform
stem(ts, ys)
hold on;
plot(tov, yov);
legend('sample', 'waveform')
ylim([-1.5 1.5])
grid on;
xlabel('time(s)');
ylabel('mag(V)')

nfft = 256;
X = fftshift(fft(ys, nfft))/nfft;
f = (-nfft/2:nfft/2-1)*fs/nfft;
magX = abs(X);
phsX = atan2(imag(X),real(X));
%% fft spectrum
figure(2)
subplot(2, 1, 1);
stem(f, magX);
xlabel('Frequency(Hz)');
ylabel('mag')
xlim([min(f)-1 max(f)+1])
title('Amplitude spectrum')
subplot(2, 1, 2)
plot(f, phsX);
xlabel('Frequency(Hz)');
ylabel('phase (rad)')
xlim([min(f)-1 max(f)+1])
title('Phase spectrum')

%% power spectrum
yssq_sum_avg = sum(ys(1:nfft).^2)/nfft;
specsq_sum_avg = sum(abs(X).^2);

reference

OriginLab, How to Remove DC Offset before Performing FFT URL: http://blog.originlab.com/how-to-remove-dc-offset-before-performing-fft

How to remove DC component in FFT? URL: https://www.mathworks.com/matlabcentral/answers/712808-how-to-remove-dc-component-in-fft#answer_594373

Analyzing a signal that contains frequency content at Fs/2 doesn't seem to work unless there is a phase shift URL: https://dsp.stackexchange.com/a/59807/59253

Nyquist–Shannon sampling theorem, Critical frequency URL: https://en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theorem#Critical_frequency

Why remove energy at Nyquist before ifft? URL: https://dsp.stackexchange.com/a/22851/59253

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emacs --no-site-file --load path/to/verilog-mode.el --batch filename.v -f verilog-auto-save-compile

CAUTION: filename.v is overwrite by command

verilog-mode.el

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/*AUTOINPUT*/
/*AUTOWIRE*/
/*AUTOINST*/
/*AUTO_TEMPLATE*/

-f verilog-batch-auto

For use with --batch, perform automatic expansions as a stand-alone tool. This sets up the appropriate Verilog mode environment, updates automatics with M-x verilog-auto on all command-line files, and saves the buffers. For proper results, multiple filenames need to be passed on the command line in bottom-up order.

-f verilog-auto-save-compile

Update automatics with M-x verilog-auto, save the buffer, and compile

Emacs

--no-site-file

Another file for site-customization is site-start.el. Emacs loads this before the user's init file (.emacs, .emacs.el or .emacs.d/.emacs.d). You can inhibit the loading of this file with the option --no-site-file

--batch

The command-line option --batch causes Emacs to run noninteractively. The idea is that you specify Lisp programs to run; when they are finished, Emacs should exit.

--load, -l FILE, load Emacs Lisp FILE using the load function;

--funcall, -f FUNC, call Emacs Lisp function FUNC with no arguments

-f FUNC

--funcall, -f FUNC, call Emacs Lisp function FUNC with no arguments

--load, -l FILE

--load, -l FILE, load Emacs Lisp FILE using the load function

Verilog-mode is a standard part of GNU Emacs as of 22.2.

multiple directories

AUTOINST only search in the file's directory default.

You can append below verilog-library-directories for multiple directories search

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// Local Variables:
// verilog-library-directories:("." "subdir" "subdir2")
// End:

reference

Emacs Online Documentation https://doc.endlessparentheses.com/

Emacs verilog-mode 的使用 URL: https://www.wenhui.space/docs/02-emacs/verilog_mode_useguide/