The problem with sine-wave scaling is that the noise power is, on
average, evenly distributed over all FFT bins, whereas the
sine-wave power is concentrated in only a few bins. With
sine-wave scaling, the power of individual sine-wave components can be
read directly from the spectral plot, but in order to determine the
noise power, the powers of all the noise bins must be added
together.
subplot(3,1,1); for N = [162561024] wrect = rectwin(N); Wrect = fftshift(fft(wrect)); Wrect_mag = abs(Wrect)/sum(wrect); nb_rect = sum(Wrect_mag > 0.1); fprintf('Number of nonzero FFT bin(rect window N=%d): %d\n', N, nb_rect); stem(1:N, Wrect_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('rect window')
subplot(3,1,2); for N = [162561024] whann = hann(N); Whann = fftshift(fft(whann)); Whann_mag = abs(Whann)/sum(whann); nb_hann = sum(Whann_mag > 0.1); fprintf('Number of nonzero FFT bin(hann window N=%d): %d\n', N, nb_hann); stem(1:N, Whann_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('Hanning window')
subplot(3,1,3); for N = [162561024] whann2 = (1-cos(2*pi*(0:N-1)/N)).^2/2^2; Whann2 = fftshift(fft(whann2)); Whann2_mag = abs(Whann2)/sum(whann2); nb_hann2 = sum(Whann2_mag > 0.1); fprintf('Number of nonzero FFT bin(hann2 window N=%d): %d\n', N, nb_hann2); stem(1:N, Whann2_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('Hann2 window')
% Number of nonzero FFT bin(rect window N=16): 1 % Number of nonzero FFT bin(rect window N=256): 1 % Number of nonzero FFT bin(rect window N=1024): 1 % Number of nonzero FFT bin(hann window N=16): 3 % Number of nonzero FFT bin(hann window N=256): 3 % Number of nonzero FFT bin(hann window N=1024): 3 % Number of nonzero FFT bin(hann2 window N=16): 5 % Number of nonzero FFT bin(hann2 window N=256): 5 % Number of nonzero FFT bin(hann2 window N=1024): 5
N = 2048; cycles = 67; fs = 1000; fx = fs*cycles/N; LSB = 2/2^10; %generate signal, quantize (mid-tread) and take FFT x = cos(2*pi*fx/fs*[0:N-1]); x = round(x/LSB)*LSB; s = abs(fft(x)); s = s(1:end/2)/N*2; % calculate SNR sigbin = 1 + cycles; noise = [s(1:sigbin-1), s(sigbin+1:end)]; snr = 10*log10( s(sigbin)^2/sum(noise.^2) );
sdb = 20*log10(s);
% How to plot a series of numbers which some of them are inf? % https://www.mathworks.com/matlabcentral/answers/476643-how-to-plot-a-series-of-numbers-which-some-of-them-are-inf plot([0:N/2-1]/N, max(sdb, -120), LineWidth=4) hold on; plot([00.5], [-61.9-61.9], 'r--', LineWidth=2) plot([00.5], [-92-92], 'm--', LineWidth=2) grid on; grid minor; ylim([-1200]); xlim([00.5]); xlabel('Frequency [f/fs]'), ylabel('DFT Magnitude [dBFS]'); title('2048 point FFT, SNR=61.90dB')
Rectangular Window
DFT bin's output noise standard deviation (rms)
value is proportional to \(\sqrt{N}\),
and the DFT's output magnitude for the bin containing the signal
tone is proportional to \(N\)
signal tone power \[
P_{\text{sig}} = 2 \frac{X_{w,sig}^2}{N^2}
\]
noise power \[
P_n = \frac{X_{w,n}^2}{N}
\]
The displayed SNR\[
\mathrm{SNR} = \mathrm{SNR}' - 10\log_{10}(2/N)
\] If we increase a DFT's size from \(N\) to \(2N\), the DFT's output SNR increased by
3dB. So we say that a DFT's processing gain increases
by 3dB whenever \(N\) is doubled.
1 2 3 4 5 6
for N=[2^62^82^102^12] wd = rectwin(N); nbw = enbw(wd)/N; snr_shift = 10*log10(nbw * 2); disp(snr_shift); end
output:
1 2 3 4 5 6 7
-15.0515
-21.0721
-27.0927
-33.1133
How spectrum analyzer work?
We tried to plot a power spectral density together with
something that we want to interpret as a power spectrum
spectrum of a periodic signal
spectral density of a broadband signal such as noise
Sine-wave components are located in individual FFT bins, but
broadband signals like noise have their power spread over all FFT
bins!
The noise floor depends on the length of the
FFT
PS and PSD
The spectral density format is appropriate for random or noise
signals but inappropriate for discrete frequency components because the
latter theoretically have zero bandwidth
Amplitude Correction
A finite-duration window \(w[n]\)
DTFT is \(W[e^{j\omega}]\) and the
maximum magnitude is is at DC frequency, which \(\sum_n w_n\)
Sinusoidal signal \(x[n]\)
DFS is \(X_k\), and DTFT shall be
\(\frac{2\pi}{N}X_k(e^{j\omega})\)
the windowed sequence \(v[n] =
x[n]w[n]\)
with multiplication property, DTFT of \(v[n]\) shall be \(\frac{X_k(e^{j\omega})}{N}\sum_n w_n\)
As we know, DFT of \(v[n]\) is
samples of its DTFT, that is \[
\frac{X_k(e^{j\omega})}{N}\sum_n w_n = X_v[k]
\] Therefore, \[
\frac{X_k(e^{j\omega})}{N} = \frac{X_v[k]}{\sum_n w_n}
\]
Effective Noise BandWidth
(ENBW)
General derivation
The relationship between a power spectrum (\(PS, V^2\)) and a power spectral
density (\(PSD, V^2/Hz\)) is given
by the effective noise bandwidth (ENBW), which
can easily be determined at the time when the DFT is computed.
ENBW should always be recorded when a spectrum or spectral density is
computed, such that the result can be converted to the other form at a
later stage, when the information about the frequency resolution \(f_{res}\) and the window that was used is
normally not easily available any more.
The normalized equivalent noise bandwidth (NENBW) of
the window is given by
\[
\text{NENBW} = \frac{NS_2}{S_1^2}
\] where \(S_1 = \sum
_{k=0}^{N-1}w_k\) and \(S_2 = \sum
_{k=0}^{N-1}w_k^2\)
Equivalent noise bandwidth (ENBW) compares a window to an
ideal, rectangular time-window. It is the bandwidth of the
rectangular window's frequency-domain shape that passes the same
amount of white noise energy as the frequency-domain
shape defined by the other window.
Therefore, the equivalent noise bandwidth \(B_{enbw}\) is given by
Assuming the windowed sequence \(v[n] =
x[n]w[n]\)
\(W[k]\): Fourier Transform of
finite sequence window
\(X_{sig}\): Fourier Transform
of signal
\(X_{n}\): Fourier Transform of
noise
\(X_{v,sig}\): Fourier Transform
of windowed signal
\(X_{v,n}\): Fourier Transform
of windowed noise
From Fig. 6,, we observe that the amplitude of the harmonic estimate
at a given frequency is biased by the accumulated broad-band noise
included in the bandwidth of the window.
In this sense, the window behaves as a filter, gathering
contributions for its estimate over its bandwidth
The Fourier Transform of windowed signal can be expressed as
%Clear variables. clear command window, close all figures: clc; clear all; close all; %%%Setup and define variables f0=10; %frequency of sinusoidal signal (Hz) fs=100; %sampling frequency (Hz) Ts=1/fs; %sampling period (seconds) N0=3000; %number of samples t=[0:Ts:Ts*(N0-1)]; %Sample times noise_PSD=.5; %This is the desired noise power spectral density in W/Hz. variance=noise_PSD*fs;% Variance = sigma^2 sigma=sqrt(variance); noise=transpose(sigma*randn(N0,1));%create sampled white Gaussian noise. xsignal=20*sin(2*pi*f0*t); %create sampled sinusoidal signal x=xsignal+noise; %Add signal to noise figure(1) histogram(noise,30) %plot histogram set(gca,'FontSize',14) %set font size of axis tick labels to 18 xlabel('Noise amplitude','fontsize',14) ylabel('Frequency of occurance','fontsize',14) title('Simulated histogram of white Gaussian noise','fontsize',14) SNR_try1=snr(xsignal,noise); %calculate SNR using built in "snr" function. SNR_try2=10*log10(sum(xsignal.^2)/sum(noise.^2)); %manually calculate SNR. %If everything is correct, the two SNR calculations above should agree. %Plot noise in time-domain figure(2) plot(t,x) set(gca,'FontSize',14) %set font size of axis tick labels to 18 xlabel('Time (s)','fontsize',14) ylabel('Amplitude','fontsize',14) title('Noisey sinusoid','fontsize',14) grid on %Plot power spectral density (PSD) of noise using three different methods: % %Method 1. Calcululate PSD from amplitude spectrum N=2^16; %Number of discrete points in the FFT y=fft(x,N)/fs; %fft of noise z=fftshift(y);%center noise spectrum f_vec=[0:1:N-1]*fs/N-fs/2; %designate sample frequencies amplitude_spectrum=abs(z); %compute two-sided amplitude spectrum ESD1=amplitude_spectrum.^2; %ESD = |F(w)|^2; PSD1=ESD1/((N0-1)*Ts);% PSD=ESD/T where T = total time of sample figure(3) plot(f_vec,10*log10(PSD1)); xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 1','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight %calculate average power using PSD calclated from method 1: Average_power_method_1=sum(PSD1)*fs/N; % Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Method 2 - Calculate PSD from autocorrelation time_lag=((-length(x)+1):1:(length(x)-1))*Ts; auto_cor=xcorr(x,x)/fs; %Use xcorr function to find PSD y=1/fs*fft(auto_cor,N); %fft of auto correlation function PSD2=abs(1/(N0-1)*fftshift(fft(auto_cor,N))); figure(4) plot(f_vec,10*log10(PSD2));%use convolution xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 2','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight %calculate average power using PSD calclated from method 1: Average_power_method_2=sum(PSD2)*fs/N; %Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Method 3 - Calculate PSD using built in pwelch function figure(5) PSD3=periodogram(x,[],N,fs,'centered'); plot(10*log10(PSD3)) xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 3','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight Average_power_method_3=sum(PSD3)*fs/N; %Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Calculate mean and average PSD of noise: PSD_noise=periodogram(noise,[],N,fs,'centered'); Average_noise_PSD=mean(PSD_noise); Mean_noise=mean(noise);
The power spectral density plots for methods 2 and 3 exactly match
that for method 1 (shown above).
A finite-length data record = an infinite record multiplied by a
rectangular window
Windowing is unavoidable
Applying the Hanning window (or any window) to a periodic
signal creates leakage.
leakage:
The component at one frequency leaks into the vicinity of another
compnent owing to the spectral smearing introdued by
window.
Notice side lobes adding out of phase can reduce
the heights of the peaks
Windowed Signal
Short transient signals in the time domain produce high, broadband
frequency content.
To reduce leakage, a mathematical function called a
window is applied to the data. Windows are designed to
reduce the sharp transient in the re-created signal as much as
possible.
Because the sharp transients are reduced and smoothed, the broadband
frequency of the spectral leakage is also reduced.
Periodic versus
Non-Periodic Background
When performing a Fourier Transform on measurement data, a window
affects periodic and non-periodic data differently:
Periodic (No Window needed): A signal captured
in a periodic manner does not require a window, and a resulting Fourier
Transform has no leakage. Applying a window alters the resulting Fourier
transform, and even creates spectral leakage where there would have been
no leakage otherwise.
Non-periodic (Window needed): Windows are used
on signals that are captured in a non-periodic manner to reduce spectral
leakage and get closer to the periodic results. A window can minimize
the leakage present in a non-periodic signal, but cannot eliminate
it.
The signal is repeated and appended mathematically because the
measured data is assumed to be representative of the entire original
signal
Periodic
When a measurement signal is captured in a periodic manner, the
Fourier Transform of the captured signal will have no
leakage in the frequency domain.
A window is not recommended for a periodic signal as it will distort
the signal in an unnecessary manner, and actually creates
spectral leakage.
Maloberti, F. Data Converters. Dordrecht, Netherlands:
Springer, 2007.
Non-periodic
The same sine wave, with a different measurement time, results in a
non-periodic captured signal. Here, when the captured signal is
repeated, the original sine wave signal is not re-created.
In fact, several broadband transient events (circled in red) are
introduced. These transients create a broadband response, or
leakage.
Windows are used to minimize this leakage effect in
the frequency domain.
Hanning
When doing operational noise and vibration measurements, the Hanning
window is commonly used.
Random data has spectral leakage due to the abrupt cutoff at
the beginning and end of the time block. It is
non-periodic.
There is no way to ensure that the captured random
signal is periodic by varying the measurement time.
Hanning windows are often used with random data
because they have moderate impact on the frequency resolution and
amplitude accuracy of the resulting frequency spectrum.
The maximum amplitude error of a Hanning window is
15%
In the cited article, all spectral data had an amplitude
correction factor applied.
while the frequency leakage is typically confined to 1.5
spectral lines to each side of the original sine wave
signal
periodic signal
Applying the Hanning window (or any window) to a periodic signal
creates leakage.
The periodically captured sine wave with the Hanning window
(blue) is wider in frequency than the original signal (red)
In the figure, the sine wave with the Hanning window (blue) is
wider in frequency than the original signal (red).
non-periodic signal
When a Hanning window is applied to a non-periodic signal, the
leakage is greatly reduced and the amplitude is higher.
A non-periodically captured sine wave (magenta) has a
spectral leakage over the entire bandwidth, applying a Hanning window
minimized the leakage (green)
RMS calculation
A RMS calculationsums up the energy within a
frequency range.
both the RMS of the periodic and non-periodic signals with a
Hanning window are equal to the RMS of the leakage-free sine
wave.
Only the RMS of the non-periodic sine wave without a window
applied is not equal to the others
With the leakage spread over a smaller frequency range, doing
analysis calculations like RMS yields more accurate
results.
Flattop
The Flattop window has a better amplitude accuracy in
frequency domain compared to the Hanning window,
The maximum amplitude error of a Flattop window is less than
0.01%. By contrast, the Hanning window maximum amplitude error is
15%.
A Flattop window confines leakage to 3.43 spectral lines
to each side of the original signal.
amplitude errors
These maximum amplitude errors assume that amplitude correction
factors are applied to the frequency spectrums. These amplitude
correction factors compensate for any reduction caused by applying a
window.
leakage
The frequency accuracy of the Flattop window is more coarse compared
to a Hanning window. As a result, the Flattop window is typically
employed on data where frequency peaks are distinct and well separated
from each other.
When the frequency peaks are not guaranteed to be well separated, the
Hanning window is preferred because it is less likely to cause
individual peaks to be lost in the spectrum
Spectrum of two periodically captured tones that are \(4Hz\) apart with a \(1Hz\) frequency resolution. The spectrum
with a Hanning window (green) shows two peaks while the spectrum with a
Flattop window (blue) shows one peak.
Note that at the original frequencies of the tones the amplitude is
correct and equal to one for both windows.
One common application for a flattop window is performing
calibration. For example, a sound pistonphone only produces
one single and distinct frequency during microphone
calibration.
Uniform
A Uniform window has a value of 1.0 across the entire
measurement time. In reality, a Uniform window could be
called no window.
Depending on the data acquisition system used, sometimes the term
Rectangular window is also used.
A Uniform window creates no frequency or amplitude distortion
when the measured signal is periodic.
When a measured signal is not periodic, the amplitude is reduced
by a maximum of 36% and the frequency content is spread over
the entire bandwidth of the measurement.
This is due to sharp transients that are created by
repeating and appending the measured signal.
Whenever a measurement signal is periodic, a Uniform window is
preferred.
Applying a Hanning or Flattop window to a periodic signal will
actually create amplitude and frequency distortion.
Benefit of Reducing Leakage
The benefit is not that the captured signal is
perfectly replicated.
The main benefit is that the leakage is now confined over a
smaller frequency range, instead of affecting the entire
frequency bandwidth of the measurement.
With the leakage spread over a smaller frequency range, doing
analysis calculations like RMS yields more accurate results.
It is impossible to calculate the proper RMS amplitude estimate over
a limited frequency range of the un-windowed sine wave, since
the leakage is over the full frequency range. Therefore the RMS
amplitude is not correct.
Two tones
In the case of two closely spaced sine tones, without a window being
applied, two tones frequencies would leak into each other, which make
determining the true amplitude of individual peaks very difficult.
The window makes it easier to separate and distinguish each tone so a
proper analysis could be performed.
window function in
frequency domain
The transfer function \(a(f)\) of a
window \(w_j, j \in [0, N-1]\)
expresses the response of the window to a sinusoidal signal at an offset
of \(f\) frequency bins, i.e. DFT .
real part:\[
a_r(f)=\sum_{j=0}^{N-1}w_j\cos (2\pi f j/N)
\]
imaginary part:\[
a_i(f)=\sum_{j=0}^{N-1}w_j\sin (2\pi f j/N)
\]
frequency response can be obtained as \[
a(f) = \frac{\sqrt{a_r^2+a_i^2}}{S_1}
\] where \(S_1 = \sum
_{k=0}^{N-1}w_k\)
Rectangular window example
aka. Uniform window, "Rectangular" window, "no window"
Whenever a measurement signal is periodic, a Uniform window is
preferred. Applying a Hanning or Flattop window to a periodic signal
will actually create amplitude and frequency distortion.
When \(f=0\)
\[
a_r(f) + ja_i(f) = \sum_{k=0}^{N-1}w_k = N
\]
When \(f \neq 0\)
\[\begin{align}
a_r(f) + ja_i(f) &= \sum_{k=0}^{N-1} e^{\frac{j2\pi k f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} + e^{\frac{j2\pi (k+N/2)
f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} + e^{j\pi}
e^{\frac{j2\pi k f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} - e^{\frac{j2\pi k
f}{N}} \\
&= 0
\end{align}\]
A Uniform window creates no frequency or amplitude distortion when
the measured signal is periodic.
However, if the signal cannot be guaranteed to be periodic, a Uniform
window should be avoided.
Window Properties
There is no possibility of trade-off between
main-lobe width and sied-lobe amplitude, since the
window length is the only variable parameter.
The rectangular window has the narrowest main lobe for a given
length, i.e. \(\Delta
_{ml}=4\pi/L\)
Other windows include the Bartlett, Hann, and Hamming windows. The
DTFTs of all these windows have main-lobe width \(\Delta _{ml}=8\pi/(L-1)\), which is
approximately twice that of the rectangular window, but they have
significantly smaller side-lobe amplitudes.
figure(1) plot(ff, X, 'r-o', ff, X_rect, 'b-s'); xlabel('Frequency(Hz)'); ylabel('|X|') title('Amplitude spectrum of periodically captured sine wave'); legend('w/ hanning', 'w/ rect'); grid on grid minor % rectangular window provide higher frequency resolution % hanning window induce leakage for the periodically captured sine wave
% fin - 0.5fres fin_lkg0d5 = fin - 0.5*fres; wv_lkg0d5 = cos(2*pi*fin_lkg0d5*tt); power_lkg0d5 = periodogram(wv_lkg0d5, whan, N, fs, 'power'); X_lkg0d5 = (power_lkg0d5).^0.5*2^0.5; psd_lkg0d5 = periodogram(wv_lkg0d5, whan, N, fs, 'psd'); rms_lkg0d5 = sum(psd_lkg0d5*fres)^0.5; fprintf('RMS@-0.5fres & hanning: %.5f\n', rms_lkg0d5);
Pinaki Mazumder; Idongesit E. Ebong, "Lectures on Digital Design
Principles," in Lectures on Digital Design Principles , River
Publishers, 2023
Combinational Logic Minimization using Karnaugh maps
(K-maps)
TODO 📅
IJTAG
While JTAG connects chips externally, IJTAG
extends it inside the chip — linking embedded instruments (MBIST,
sensors, monitors, etc.) through a reconfigurable network.
Pin-Mux Logic Pins are precious in SoC
design!
Pin-Mux Logic lets functional and test signals share the same pins
depending on the mode.
During test mode, JTAG/IJTAG signals are routed internally via
multiplexers — saving pins and silicon area.
Basic idea: use of mean of \(v'(t)\) to approximate
median of \(v'(t)\)
Elmore delay approximates the median of \(h(t)\) by the mean of
\(h(t)\)
Distributed RC-Line
Lumped approximations
\(rc\)-models
If your simulator does not support a distributed \(rc\)-model, or if the computational
complexity of these models slows down your simulation too much, you can
construct a simple yet accurate model yourself by approximating the
distributed \(rc\) by a lumped RC
network with a limited number of elements
The accuracy of the model is determined by the number of stages. For
instance, the error of the \(\Pi -3\)
model is less than 3%, which is generally sufficient.
Why use "\(\Pi\)
Model"
examples
Wire Inductive Effect
RC delay increases quadratically with length
LC delay (speed of light flight time) increases linearly with
length
Inductance will only be important to the delay of low-resistance
signals such as wide clock lines
wave
Signal propagates over the wire as a wave (rather
than diffusing as in RC only models)
Signal propagates by alternately transferring energy from capacitive
to inductive modes
A glitch is an unwanted pulse at the output of a
combinational logic network – a momentary change in an
output that should not have changed
A circuit with the potential for a glitch is said to have a
hazard
In other words a hazard is something intrinsic about a circuit; a
circuit with hazard may or may not have a glitch depending on input
patterns and the electric characteristics of the circuit.
When do circuits have hazards
?
Hazards are potential unwanted transients that occur in the output
when different paths from input to output have different propagation
delays
Isolation cells are additional cells
inserted by the synthesis tools for isolating the buses/wires crossing
from power-gated domain of a circuit to its always-on
domain (AON).
To prevent corruption of always-on domain, we clamp the nets crossing
the power domains to a value depending upon the design.
A simple circuit having a switchable (or gated) power
domain
The circuit shown in Figure 1, after isolation cells are
inserted
Clock Gating is defined as: "Clock gating is a
technique/methodology to turn off the clock to certain parts of the
digital design when not needed".
AND gate-based clock gating
In simplest form a clock gating can be achieved by using an
AND gate as shown in picture below
However, this simplest form of clock gating technique has some
problem of generating glitches in the clock provide to
the FF, which are not desirable.
Glitches in enable/gated clock
Latch based clock gating
These glitches can be removed by introducing a negative edge
triggered FF (assuming downstream FFs are positive edge) or low-level
sensitive latch at the output of the clock enable signal.
This will make sure that any glitch in the clock enable signal will
not be visible to the gated clock output. The Latch output will only be
updated during the negative clock cycle and thus input to AND gate will
be stable high.
Glitch Free Gated Clock
OCV Derating With AOCV
Genus Attribute Reference 22.1
Innovus Text Command Reference 22.10
Article (20416394) Title: Analysis with Advanced On-chip Variation
(AOCV) derating in EDI system and ETS
When set to aocv_multiplicative, the derating factor
will be calculated as AOCV derating * OCV derating, which is set using
the set_timing_derate command.
When set to aocv_additive, the derating factor will be
calculated as AOCV derating + OCV derating values.
When you use this global variable, the report_timing
command shows the total_derate column in the timing report
output, which allows you to view and cross-check the calculated total
derate factor.
To set this global variable, use the set_global
command.
The two-capacitor paradox is a classic puzzle in circuit theory where
energy seems to vanish
If there is any resistance $R $ (always true in reality). $R $
dissipates heat
If the resistance is genuinely zero, Then you can't ignore
inductance — With pure $LC $, the circuit becomes an oscillator
Two capacitors \(C\) in series
around the loop give an effective capacitance \(C_{eq} = C/2\). With inductance \(L\) in the loop, the resonant frequency is
\[
\omega_0 = \frac{1}{\sqrt{LC_{eq}}} = \frac{1}{\sqrt{L(C/2)}} =
\sqrt{\frac{2}{LC}}
\]
\[
v_1(t) = \frac{V_0}{2}\left(1 + \cos\omega_0 t\right), \qquad
v_2(t) = \frac{V_0}{2}\left(1 - \cos\omega_0 t\right)
\] the \(y\)-axis is in units of
\(V_0\), so the curves run between 0
and 1 \[
v_1(t) + v_2(t) = V_0 \quad \text{at all times}
\]
Adam Teman. Digital Integrated Circuits (83-313) Lecture 3: MOSFET
Modeling [pdf]
Zero Temperature Coefficient (ZTC) Bias
Points
M. Coelho et al., "Is There a ZTC Biasing Point in the
Leading-Edge FET Intrinsic Gain gmrDS?," 2025 9th International
Young Engineers Forum on Electrical and Computer Engineering
(YEF-ECE), Caparica / Lisbon, Portugal, 2025
M. Coelho et al., "Analysis of the ZTC Bias Points in the
FinFET Gate Capacitance and Transition Frequency," 2025 37th
International Conference on Microelectronics (ICM), Cairo, Egypt,
2025, pp. 1-6, doi: 10.1109/ICM66518.2025.11322461
there's a specific bias point where the MOSFET transition frequency
(fT) becomes almost temperature‑independent
Gildenblat, G. S. (2010). Compact modeling : principles, techniques
and applications. Springer.
VDS Effect On Channel Noise
\[
\color{red} \overline{i^2_d} \propto V_{DS}
\]
K. Ohmori and S. Amakawa, "Direct White Noise Characterization of
Short-Channel MOSFETs," in IEEE Transactions on Electron
Devices, vol. 68, no. 4, pp. 1478-1482, April 2021 [pdf,
slides]
X. Ding, G. Niu, A. Zhang, W. Cai and K. Imura, "Experimental
Extraction of Thermal Noise γ Factors in a 14-nm RF FinFET technology,"
2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), San Diego, CA, USA, 2021[https://sci-hub.se/10.1109/SiRF51851.2021.9383331]
NF50
TODO 📅
\(\gamma\) vs VDS, VGS
in simulation
N28
fix VDS, sweep VGS
fix VGS, sweep VDS
MOS Flicker Noise
T. Noulis, "CMOS process transient noise simulation analysis and
benchmarking," 2016 26th International Workshop on Power and Timing
Modeling, Optimization and Simulation (PATMOS), Bremen, Germany, 2016
[https://sci-hub.ru/10.1109/PATMOS.2016.7833428]
Above simulation demonstrate that flicker noise is
represented by a drain-source current in BSIM
model, however modeled as a voltage source in series with the gate
is just for calculating convenience
⭐ where \(S_{x_n}^T=\frac{\partial
T}{\partial x_n}\frac{x_n}{T}\) is relative
sensitivity
relative sensitivity connect \(\frac{\mathrm{d}x_n}{x_n}\) with total
relative variation \(\frac{\mathrm{d}T}{T}\)
And \(\mathrm{d}T\) can be expressed
as \[
dT =\sum_{n=1}^N S_{x_n}^T T\cdot \frac{\mathrm{d}x_n}{x_n} =
\sum_{n=1}^N x_n'\cdot \frac{\mathrm{d}x_n}{x_n}
\] ⭐ where \(x_n'= S_{x_n}^T
T\) is the contribution of \(x_n\) in \(T\)
⭐ For parallel or series resistors, it can prove \(\sum_{n=1}^N S_{x_n}^T = 1\) and \(\sum_{n=1}^N x_n'=T\)
Here \(T= R_1 \parallel R_2 =
\frac{R_1R_2}{R_1+R_2}\), and \(T|_{R_1=8000, R_2=2000} = 1600\)
The contribution of \(R_1\) and
\(R_2\) to \(T\)\[\begin{align}
R_1' &= S_{R_1}^T T | _{R_1=8000, R_2=2000} = 320 \\
R_2' &= S_{R_2}^T T | _{R_1=8000, R_2=2000} = 1280
\end{align}\]
If \(V_{DS}\) is slightly
greater than \(V_{GS} - V_{TH}\), then
the inversion layer stops at \(x \leq
L\), and we say the channel is "pinched
off"
Upon passing the pinchoff point, the electrons simply shoot through
the depletion region near the drain junction and arrive at the drain
terminal
\(L^{'}\) is the function of
\(V_{DS}\)
with \(\frac{1}{L^{'}} =
\frac{1}{L-\Delta L}=\frac{L+\Delta L}{L^2-\Delta L^2}\approx
\frac{1}{L}\left(1+\frac{\Delta L}{L}\right)\), we have \[
I_D \approx \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(1+\frac{\Delta
L}{L}\right)(V_{GS}-V_{TH})^2 = \frac{1}{2}\mu_n
C_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2 (1+\lambda V_{DS})
\] assuming \(\frac{\Delta L}{L} =
\lambda V_{DS}\)
\(\lambda\) represents the
relative variation in length for a given increment in \(V_{DS}\). Thus, for longer channels, \(\lambda\) is smaller
In reality, however, \(r_O\) varies
with \(V_{DS}\). As \(V_{DS}\)increases and the
pinch-off point moves toward the source, the rate at which the
depletion region around the source becomes wider decreases,
resulting in a higher incremental output impedance.
In reality, since mismatches are independent statistical
variables
Above shows that the input transistors must be designed for high
gain (\(g_mr_o =
\frac{2}{V_{OV}\lambda}\)), which means they must be designed for
small\(V_{GS}-V_{TH}\).
It is desirable to minimize \(V_{GS}-V_{TH}\) by lowering the tail
current or increasing the transistor widths
M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for
small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17,
no. 1, pp. 31-41, Jan. 2001 [https://kenkundert.com/docs/cd2001-01.pdf]
Then, we get \[
V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m)
\] Due to \(V_o=V_m\) and \(V_o'=V_m'\)\[
V_{os}=(1/A+1)\Delta{V_m}
\] or \[
V_{os}=(1/A+1)\Delta{V_o}
\] if \(A \gg 1\)\[
V_{os}=\Delta{V_o}
\]
we get \[
V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m)
\] or \[
V_{os}=\frac{\Delta V_o}{A}+\beta \Delta V_o
\] if \(A \gg 1\)\[
V_{os}=\beta \Delta V_o
\] or \[
V_{os}=\Delta V_m
\]
Lecture 22 Variability and Mismatch of Dr. Hesham A. Omran's
Analog IC Design
\(C_\text{eq}\) and \(R_\text{eq}\) are obtained \[\begin{align}
C_\text{eq} &= \frac{1+|A|^2-2A_r}{1-A_r}\cdot C_f \\
R_\text{eq} &= \frac{A_i}{1+|A|^2-2A_r}\cdot \frac{1}{\omega C_f}
\end{align}\]
D/S small signal model
The Drain and Source of MOS are determined
in DC operating point, i.e. large signal.
That is, top of \(M_2\) is
drain and bottom is source, \[\begin{align}
R_\text{eq2} &= \frac{r_\text{o2}+R_L}{1+g_\text{m2}r_\text{o2}} \\
& \simeq \frac{1}{g_\text{m2}}
\end{align}\]
PMOS small signal model
polarity
The small-signal models of NMOS and PMOS transistors are
identical
A negative \(\Delta V_\text{GS}\)
leads to a negative \(\Delta I_D\).
Recall that \(I_D\), in the
direction shown here, is negative because the actual current of holes
flows from the source to the drain.
Conversely, a positive \(\Delta
V_\text{GS}\) produces a positive \(\Delta I_D\), as is the case for an NMOS
device.
W. M. Elgharbawy and M. A. Bayoumi, "Leakage sources and possible
solutions in nanometer CMOS technologies," in IEEE Circuits and Systems
Magazine, vol. 5, no. 4, pp. 6-17, Fourth Quarter 2005, doi:
10.1109/MCAS.2005.1550165.
X. Qi et al., "Efficient subthreshold leakage current optimization -
Leakage current optimization and layout migration for 90- and 65- nm
ASIC libraries," in IEEE Circuits and Devices Magazine, vol. 22, no. 5,
pp. 39-47, Sept.-Oct. 2006, doi: 10.1109/MCD.2006.272999.
P. Monsurró, S. Pennisi, G. Scotti and A. Trifiletti, "Exploiting the
Body of MOS Devices for High Performance Analog Design," in IEEE
Circuits and Systems Magazine, vol. 11, no. 4, pp. 8-23, Fourthquarter
2011, doi: 10.1109/MCAS.2011.942751.
Andrea Baschirotto, ISSCC2015 "ADC Design in Scaled Technologies"
As a result of DIBL, threshold voltage is reduced
with shorter channel lengths and, consequently, the subthreshold leakage
current is increased
impact on output impedance
The principal impact of DIBL on circuit design is the degraded output
impedance.
In short-channel devices, as \(V_{DS}\) increases further, drain-induced
barrier lowering becomes significant, reducing the threshold
voltage and increasing the drain current
Impact Ionization and GIDL are different, however both
increase drain current, which flowing from the drain into the
substrate
Gate induced drain leakage
(GIDL)
The large current flows from the drain to bulk and this
drain leakage current is named gate-induced drain leakage
(GIDL) since it is due to a gate-induced high electric
field present in the gate-to-drain overlap region
gate-induced drain leakage (GIDL) increases exponentially due to the
reduced gate oxide thickness
Chauhan, Yogesh Singh, et al. FinFET modeling for IC simulation
and design: using the BSIM-CMG standard. Academic Press, 2015.
\[
\frac{g_m}{I_D} = \frac{2}{V_{GS}-V_{TH}}
\] Decrease of gm/Id results from decrease in VT.
GIDL (Gate induced drain leakage) as at weak
inversion may results in a weak lateral electric field causing leakage
current between drain and bulk, which degrade the efficiency of the
transistor (gm/ID).
In advanced node, gate leakage is also a strong function of
temperature
Power/Ground and I/O Pins
Power / Ground Pin
Information
In both digital and analog I/O, power and ground pins appear at the
sub-circuit definiton, allowing user to use the I/O in voltage islands.
They follow certain naming conventions.
digital I/O sub-circuit
VDD: pre-driver core voltage (supplied by PVDD1CDGM)
VSS: pre-driver ground and also global ground (supplied by
PVDD1CDGM)
VDDPST: I/O post-driver voltage, i.e. 1.8V (supplied by PVDD2CDGM or
PVDD2POCM)
VSSPOST: I/O post-driver ground (supplied by PVDD2CDGM or
PVDD2POCM)
POCCTRL: POCCTRL signal (supplied by PVDD2POCM)
analog I/O placed in a core voltage domain, the convention is
TACVDD: analog core voltage (supplied by PVDD3ACM)
TACVSS: analog core ground (supplied by PVDD3ACM)
VSS: global core ground
analog I/O placed in an I/O voltage domain, the convention is:
TAVDD: analog I/O voltage, i.e. 1.8V (supplied by PVDD3AM)
TAVSS: analog I/O ground (supplied by PVDD3AM)
VSS: global core ground
Power/Ground Combo Cells
power/ground combo pad cell
pins to be connected to bump
to core side pin name
PVDD1CDGM
VDD VSS
VDD VSS
PVDD2CDGM PVDD2POCM
VDDPST VSSPST
N/A
PVDD3AM
TAVDD TAVSS
AVDD AVSS
PVDD3ACM
TACVDD TACVSS
AVDD AVSS
Note for the retention mode
At initial state, IRTE must be 0 when VDD is
off.
IRTE must be kept >= 10us after VDD turns on again (from the
retention mode to the normal operation mode).
IRTE can be switched only when both VDD and VDDPST are on.
When the rention function is needed, IRTE signal must come from an
"always-on" core power domain. If you don't need the rention function,
it is required to tie IRTE to ground. In other words, no matter
the rention feature is needed or not, it is required to have PCBRTE in
each domain.
Note: PCBRTE does not need PAD
connection.
Internal Pins
There are 3 internal global pins, i.e. ESD,
POCCTRL, RTE, in all digital domain
cells.
In real application,
ESD pin is an internal signal and
active in ESD event happening
POCCTRL is an internal signal and active in
Power-on-control event.
However, these special events (i.e. ESD event and Power-on-control
event) are not modeled in NLDM kit (.lib), only normal function is
covered, so ESD and POCCTRL pins are
simply defined as ground in NLDM kit (.lib).
These 3 global pins will be connected automatically after
cell-to-cell abutting in physical layout.
Power-Up sequence in
Digital Domain
Power up the I/O power (VDDPST) first, then the core power (VDD)
PVDDD2POCM cell would generate Power-On-Control signal (POCCTRL) to
have the post-driver NMOS and PMOS off, so that the crowbar current
would not occur in the post-driver fingers when the I/O voltage is on
while the core voltage remains off. As such, I/O cell would be in the
Hi-Z state. when POCCTRL is on, the pll-up/down resistor is disabled and
C is 0.
The POCCTRL signal is transmitted to I/O cells through cell
abutment. There is no need to have routing for POCCTTRL nor
give a control signal to the POCCTRL pin any of I/O cells. Note that the
POCCTRL signal would be cut if inserting a power-cut (PRCUT) cell.
Power-Down sequence in
Digital Domain
It's the reverse of power-up sequence.
Use model in Innovus
1 2 3 4 5 6 7 8 9 10 11 12
set init_gnd_net "vss_core vss DUMMY_ESD DUMMY_POCCTRL"
Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton
Equivalent Circuits, Part 3 IEEE Solid-State Circuits Magazine, Vol. 10,
Issue 4, pp. 7-8, Fall 2018.
—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part
2 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 3, pp. 7-8, Summer
2018.
—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part
1 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 2, pp. 7-8, Spring
2018.
—, Circuit Intuitions: Miller's Approximation IEEE Solid-State
Circuits Magazine, Vol. 7, Issue 4, pp. 7-8, Fall 2015.
The most accurate method to calculate the degradation of transistors
is the SPICE-level simulation of the whole netlist with application
programming interface (API) and industry-standard stress process
models
MOSRA: MOSFET reliability analysis Synopsys
RelXpert: Cadence
TMI: TSMC Model Interface, TSMC
OMI: Open Model Interface, Si2 standard,
The Silicon Integration Initiative (Si2) Compact Model Coalition has
released the Open Model Interface, an Si2 standard, C-language
application programming interface that supports SPICE compact model
extensions.OMI allows circuit designers to simulate and analyze such
important physical effects as self-heating and aging,
and perform extended design optimizations. It is based on TMI2, the TSMC
Model Interface, which was donated to Si2 by TSMC in 2014.
TDDB: Time-Dependent Dielectric Breakdown
HCI: Hot Carrier injection
BTI: Bias Temperature Instability
NBTI: Negative Bias Temperature Instability
PBTI: Positive Bias Temperature Instability
SHE: Self-Heating Effect
Self-Heating Effect (SHE)
Self-heating effect (SHE) is composed of
FEOL self-heat and BEOL
self-heat, both contribute to the \(\Delta T\)
aging w/i SHE
EM w/i SHE
Junjie Chen, Keqing Ouyang ZTE SANECHIPS. Challenges and Solutions of
PI Signoff for Next Generation Large Scale Chips with TSMC 7nm Process
Technology [pdf]
M. Lofrano et al., "Towards accurate temperature prediction
in BEOL for reliability assessment (Invited)," 2023 IEEE
International Reliability Physics Symposium (IRPS), Monterey, CA,
USA, 2023, pp. 1-7, doi: 10.1109/IRPS48203.2023.10117701
Mitigating Self-Heating
A. Loke, "Short Course: Device and Physical Design Considerations for
Circuits in FinFET Technology," 2020 IEEE International Solid-State
Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020 [pdf]
J. E. Proesel, "Short Course: High-Speed and Mixed-Signal Circuit
Design Techniques in FinFET Technology for Wireline and Optical
Interface Applications," 2020 IEEE International Solid-State
Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020
guard ring
closer OD help reduce dT
extended gate
source/drain metal stack
M. Erett et al., "A 0.5–16.3 Gbps Multi-Standard Serial
Transceiver With 219 mW/Channel in 16-nm FinFET," in IEEE Journal of
Solid-State Circuits, vol. 52, no. 7, pp. 1783-1797, July 2017 [https://sci-hub.se/10.1109/JSSC.2017.2702711]
Heat transfer, thermal
resistance
Bias Temperature Instability
(BTI)
BTI occurs predominantly in PMOS (or p-type or p channel)
transistors and causes an increase in the transistor's absolute
threshold voltage.
Stress in the case of NBTI means that the PMOS transistor is
in inversion; that means that its gate to
body potential is substantially below 0 V for analogue circuits
or at VGB = −VDD for digital circuits
Higher voltages and higher temperatures both have
an exponential impact onto the degradation, induced by NBTI.
NBTI will be accelaerated with thinner gate oxide, at a high
temperature and at a high electric field across the oxide region.
During recovery phase where the gate voltage of pMOS is high and
stress is removed, the H atoms in the gate oxiede diffuse back to
Si-SiO2 interface and the recombination of Si-H bonds reduces the
threshold voltage of pMOS.
The net result is an increase in the magnitude of the device
threshold voltage |Vt|, and a degradation of the
channel carrier mobility.
Caution: The aging model provided by fab may
NOT contain recovry effect
Short-channel MOSFETs may exprience high lateral electric
fields if the drain-source voltage is large. while the average
velocity of carriers saturate at high fields, the instantaneous velocity
and hence the kinetic energy of the carriers continue to increase,
especially as they accelerate toward the drain. These are called
hot carriers.
In nanometer technologies, hot carrier effects have
subsided. This is because the energy required to create
an electron-hole pair, \(E_g \simeq 1.12
eV\), is simply not available if the supply voltage is around
1V.
\[
F_E= E \cdot q
\]
\[\begin{align}
E_k &= F_E \cdot s \\
&= E \cdot q \cdot s
\end{align}\]
Electrons and holes gaining high kinetic energies in
the electric field (hot carriers) may be injected into
the gate oxide and cause permanent changes in the
oxide-interface charge distribution, degrading the current-voltage
characteristics of the MOSFET.
The channel hot-electron (CHE) effect is caused by electons flowing
in the channel region, from the source to the drain. This effect is more
pronounced at large drain-to-source voltage, at which the lateral
electric field in the drain end of the channel accelerates the
electrons.
Four different hot carrier injectoin mechanisms can be distinguished:
- channel hot electron (CHE) injection - drain avalanche hot carrier
(DAHC) injection - secondary generated hot electron (SGHE) injection -
substrate hot electron (SHE) injection
HCI is more of a drain-localized mechanism, and is
primarily a carrier mobility degradation (and a Vt
degradation if the device is operated bi-directionally).
For smaller transistor dimensions, CHE dominates the hot
carrier degradation effect
The hot-carrier induced damage in nMOS transistors has been found to
result in either trapping of carriers on defect sites in the oxide or
the creation of interface states at the silicon-oxide interface, or
both.
The damage caused by hot-carrier injection affects the transistor
characteristics by causing a degradation in transconductance, a shift in
the threshold voltage, and a general decrease in the drain current
capability.
HCI seems to have just a weak temperature
dependency
Unlike BTI, it seems to be no or just
little recovery. As holes are much "cooler" (i.e. heavier) than
electrons, the channel hot carrier effect in nMOS devices is shown to be
more significant than in pMOS devices.
Degradation saturation
effect
HCI model can reproduce the saturation effect if stress time is long
enough
K. Yang, R. Zhang, T. Liu, D. -H. Kim and L. Milor, "Optimal
Accelerated Test Regions for Time- Dependent Dielectric Breakdown
Lifetime Parameters Estimation in FinFET Technology," 2018 Conference on
Design of Circuits and Integrated Systems (DCIS), Lyon, France, 2018 [https://par.nsf.gov/servlets/purl/10104486]
Scaling drive more concerns in TDDB
waveform-dependent nature
The figure below illustrates the waveform-dependent nature of these
mechanisms – as described earlier, BTI and HCI depend upon the region of
active device operation. The slew rate of the circuit inputs and output
will have a significant impact upon these mechanisms, especially
HCI.
Negative bias temperature instability (NBTI). This
is caused by constant electric fields degrading the dielectric,
which in turn causes the threshold voltage of the transistor to degrade.
That leads to lower switching speeds. This effect depends on the
activity level of the circuits, with heavier impact on parts of the
design that don’t switch as often, such as gated clocks,
control logic, and reset, programming and test circuitry.
Hot carrier injection (HCI). This is caused by
fast-moving electrons inserting themselves into the gate and
degrading performance. It primarily occurs on higher-voltage modes and
fast switching signals.
longer channel length help both BTI and HCI
larger\(V_{ds}\) help
BTI, but hurt HCI
lower temperature help BTI of core device, but hurt that of
IO device for 7nm FinFET
aging model
MOSRA
MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age
analysis
TMI
BTI recovery effect NOT included for N7
Stochastic Nature
of Reliability Mechanisms
A fraction of devices will fail
Circuit Simulations
Burn-in &
High-temperature operating life (HTOL)
HTOL:
characterization test
characterize the life expectancy
Burn-in:
production test
weed out defective products
HTOL and Burn-in Testing capture the two ends of the reliability
characterization graph known as the "bathtub curve"
Tanya Nigam and Andreas Kerber. Global Foundaries. CICC2014 Session
15 - Challenges for Analog Nanoscale Technologies: Reliability
challenges and modeling of HK MG Technologies
Spectre Tech Tips: Device Aging? Yes, even Silicon wears out -
Analog/Custom Design (Analog/Custom design) - Cadence Blogs - Cadence
Community https://shar.es/afd31p
A. Zhang et al., "Reliability variability simulation methodology for
IC design: An EDA perspective," 2015 IEEE International Electron Devices
Meeting (IEDM), Washington, DC, USA, 2015, pp. 11.5.1-11.5.4, doi:
10.1109/IEDM.2015.7409677.
W. -K. Lee et al., "Unifying self-heating and aging simulations with
TMI2," 2014 International Conference on Simulation of Semiconductor
Processes and Devices (SISPAD), Yokohama, Japan, 2014, pp. 333-336, doi:
10.1109/SISPAD.2014.6931631.
Article (20482350) Title: Measure the Impact of Aging in Spectre
Technology
Karimi, Naghmeh, Thorben Moos and Amir Moradi. “Exploring the Effect
of Device Aging on Static Power Analysis Attacks.” IACR Trans. Cryptogr.
Hardw. Embed. Syst. 2019 (2019): 233-256.[link]
Y. Zhao and Y. Qu, "Impact of Self-Heating Effect on Transistor
Characterization and Reliability Issues in Sub-10 nm Technology Nodes,"
in IEEE Journal of the Electron Devices Society, vol. 7, pp. 829-836,
2019 [https://sci-hub.se/10.1109/JEDS.2019.2911085]
Wafer acceptance testing (WAT) also known as
Process Control Monitoring (PCM)
VT Measurement Methods
A. L. S. Loke, "Constant-Current Threshold Voltage Extraction in
HSPICE for Nanoscake CMOS Analog Design," in Synopsys Users Group
(SNUG) 2010 Conference (San Jose, CA), Mar. 2010. (copyright by AMD) [slides,
paper]
Cu-pillar bumping is a next-generation flip chip interconnection
between chip & packages, especially for fine pitch applications
On the wafer end, comparing to solder bump, cu-pillar bump
provides the advantage of fine pitch; the die size can be reduced about
5~10%.
On the package end, the substrate layer can be reduced from 6
layers to 4 layers by fine pitch and bump on trace process and using
simplified substrate process.
contact to source MD for resistance reduction (to
VDD or VSS)
fully enclosed by M0
electrically insulated from MG
Even VDR is overlap with MG (PO), they are not electrically
connected
MIM capacitor structure
HD MIM: 2-layer MIM between Mtop and
Mtop-1
flexable-high-density MiM capacitor
(FHD-MIM): 2-layer MIM between ALRDL and Mtop
super-high-density MiM capacitor (SHD-MIM)
: 3-layer MIM, between ALRDL and Mtop
SHP-MiM(super-high-performance
metal-insulator-metal): N2 low-resistance redistribution layer
(RDL) and super high-performance metal-insulator-metal (MiM) capacitors
to further boost performance
MIMCAP dummy
add MIMCAP dummy in chip level due to RV
(Mtop to AP) impact
Yaghoobi, Majid & Yavari, Mohammad & Ghafoorifard, Hassan.
(2019). A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in
65-nm CMOS for Phased-Array Receivers. Circuits, Systems, and Signal
Processing. [https://sci-hub.jp/10.1007/s00034-019-01169-z]
five MOM capacitors of interdigitated parallel wires
(IPW), woven, parallel stacked wires
(PSW), multi-layer sandwich (MLS), and
vertical bars (VB)
wo_mx
Monte Carlo model:
\(C_{pa}=C_{pa1}\), \(C_{pb}=C_{pb1}\) for each iteration during
Process Variation
different variation is applied to \(C_{ab}\) and \(C_{a1b1}\) each iteration during
Mismatch Variation, though \(C_{pa}\), \(C_{pb}\), \(C_{pa1}\) and \(C_{pb1}\) remain constant
Symmetric
Layouts Are Showing Mismatches in SPICE Simulations
The root cause of the delay mismatch is related to how parasitic
extraction tools distribute coupling capacitances over the nodes of the
resistive networks
The most likely reason for such asymmetry is the anisotropy of
computational geometry algorithms used by extraction tools.
The antenna effect is a common name for the effects
of charge accumulation in isolated nodes of an
integrated circuit during its processing
This effect is also sometimes called "Plasma Induced
Damage", "Process Induced Damage" (PID) or "charging
effect"
This accumulation of charge is usually, and
misleadingly, called the antenna effect.
antenna ratio
During manufacture, if part of the metal wiring is connected to
the gate, but not a diffusion contact, this
"floating" metal collects charge from the plasma.
Manufacturing rules for the antenna effect are usually expressed as
the ratio of the area of floating metal (i.e. charge
collection area) to the area of the gate.
To prevent the antenna effect from destroying your circuit you need
to reduce the floating metal/gate area ratio or give the charge a safe
way to dissipate to the ground before it can build up and cause
damage
metal jumping (bridging,
metal hopping)
Long metal can be taken to higher metal
routing layer, which is known as metal jumping.
This metal jumping is usually done near the gate,
which will mean that there is a full connection to the diffusion contact
before the area of floating metal becomes too large
The jumper is constructed so that the long track is only connected to
the gate once it has also been connected to a diffusion contact, which
then allows the charge to dissipate through diffusion to the
substrate
Diode Insertion
Diode helps dissipate charges accumulated on metal. Diode should be
placed as near as possible to the gate of device on low level of
metal.
In the reverse bias region, the reverse saturation current of Si and
Ge diodes doubles for every \(10 ^oC\)
rise in temperature
pulsic.com, Analog layout – Stop the antenna effect from destroying
your circuit [link]
Prof. Adam Teman, Digital VLSI Design.
Lecture-10-The-Manufacturing-Process [pdf]
In T* DRC deck, it is based on the voltage recognition CAD layer and
net connection to calculate the voltage difference between two
neighboring nets by the following formula:
\[
\Delta V = \max(V_H(\text{net1})-V_L(\text{net2}),
V_H(\text{net2})-V_L(\text{net1}))
\]
where \[
V_H(\text{netx}) = \max(V(\text{netx}))
\] and \[
V_L(\text{netx}) = \min(V(\text{netx}))
\]
The \(\Delta V\) will be
0 if two nets are connected as same potential
If \(V_L \gt V_H\)on a
net, DRC will report warning on this net
Kanamoto, Toshiki, Yasuhiro Ogasahara, Keiko Natsume, Kenji
Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe and Masanori Hashimoto.
“Impact of well edge proximity effect on timing.” ESSDERC 2007 -
37th European Solid State Device Research Conference (2007)
J. V. Faricelli, "Layout-dependent proximity effects in deep
nanoscale CMOS," IEEE Custom Integrated Circuits Conference
2010, San Jose, CA, USA, 2010 [https://sci-hub.se/10.1109/CICC.2010.5617407]
LOD is the result of the STI formation (Shallow trench
isolation);
STI becomes compressive as the wafer cools down;
The width of STI (active to active spacing) has a strong impact on
determining stress;
LOD improves holes mobility and decreases electron mobility.
Stress has been more effective for PMOS
This has caused beta (N/P) ratio to fall to about unity at
7nm
LOD effect can be prevented by distancing devices away from the WELL
edge (guard ring). This is usually done by placing dummy devices around
the circuit devices, in which case your circuit devices will also
benefit from the equal edge effects (each device will have the same
neighbours).
Well Proximity Effect (WPE)
Since the well implant dopant (acceptor or donor) is the same type as
the channel implant dopant, the additional doping increases
the absolute value of the threshold voltage (VT) of both NMOS and PMOS
devices
A. Rossoni, T. Brozek and Z. M. Kovacs-Vajna, "Impact of the Gate and
Fin Space Variation on Stress Modulation and FinFET Transistor
Performance," in IEEE Transactions on Electron Devices, vol.
73, no. 3, pp. 1120-1128, March 2026, doi: 10.1109/TED.2025.3648978
The overall effect on mobility is dominated by the
longitudinal component, as poly spacing variation
Metal Boundary Effect (MBE)
M. Hamaguchi et al., "New layout dependency in high-k/Metal Gate
MOSFETs," 2011 International Electron Devices Meeting, Washington, DC,
USA, 2011 [https://sci-hub.st/10.1109/IEDM.2011.6131614]
Alvin Loke. 2016 VLSI Circuits Short Courses – 2.2 Migrating
Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm [pdf]
Z. -Y. Li, X. -J. Wang and Y. -L. Jiang, "Metal Boundary Effect
Mitigation by HKMG Thermal Process Optimization in FinFET Integration
Technology," in IEEE Transactions on Electron Devices, vol. 71, no. 4,
pp. 2335-2341, April 2024
The first is that doping the channel reduces mobility and
performance.
Secondly, at very small dimensions there are only a few dopant atoms
in the channels and small changes in the number of dopants referred to
as random dopant fluctuations (RDF) can lead to variations in Vt
Work function
improves mobility in the channel and therefore performance and
avoids RDF
Gate = (ALD MG stack to set \(\Phi_M\))+(metal fill to reduce
RG)
Interdigitation provides good matching
properties against 1D-gradients and is
suitable for the simple circuits
The main concept is that you should create an
imaginary center line and place your devices symmetrically, relative to
this line. The simplest example of that is so called
"ABBA" pattern
Interdigitation reduces the device mismatch as it suffers
equally from process variations in X dimension. This technique
was used to layout current mirrors and resistors in PTAT and BGR
circuits.
Common Centroid
Common Centroid provides better matching
for 2D gradients, which is critical for the
large arrays and advanced (below 28nm) nodes
The main idea behind common centroid is that we make our array
symmetrical of the common centre. In other words, the array should be
symmetrical in both X- and Y- axes
The common centroid technique describes that if there are n
blocks which are to be matched then the blocks are arranged
symmetrically around the common centre at equal distances from the
centre. This technique offers best matching for devices as it helps in
avoiding cross-chip gradients
The PODE devices is extracted as parasitic devices in post-layout
netlist
DDB is the PODE (Poly on
OD/Diffusion Edge) in TSMC 16FFC process.
SDB is the CPODE (Common Poly on
Diffusion Edge) in TSMC 16FFC process.
PO on OD edge (PODE) is a must and to define GATE that abuts OD
vertical edge
CPODE is used to connect two PODE cells together. It will isolate OD
to save 1 poly pitch, via STI; Additional mask (12N) is required for
manufacture
PODE
CPODE
Pro's
simple
density
Con's
density
LDE (LOD/OSE)
edge device
3T PODE(with single side OD): NO ERC 4T M-PODE (with S/D): ERC
(gate tied to power/ground)
won't form device; NO ERC; OD under CPODE is cut
off
A. Rossoni, T. Brozek, S. Saxena, R. Khamankar, L. Colalongo and Z.
M. Kovacs-Vajna, "Stress-Related Local Layout Effects in FinFET
Technology and Device Design Sensitivity," in IEEE Transactions on
Electron Devices, vol. 72, no. 5, pp. 2109-2117, May 2025, doi:
10.1109/TED.2025.3561974
In CNOD, the diffusion is not broken at all. The fabrication process
continues normally, but when standard cells need to be separated, the
gate between them is designated as a dummy gate. This dummy gate is then
connected to a Gate Tie-Down Via to the power rail
This dummy gate tie-down method of CNOD achieves the same horizontal
width savings as SDB, and has the advantage of keeping the
transistor diffusion unbroken and thus can achieve more uniform strain
and performance characteristics
S. Badel et al., "Chip Variability Mitigation through Continuous
Diffusion Enabled by EUV and Self-Aligned Gate Contact," 2018 14th IEEE
International Conference on Solid-State and Integrated Circuit
Technology (ICSICT), Qingdao, China, 2018 [https://sci-hub.st/10.1109/ICSICT.2018.8565694]
4T MPODE (with source/drain) may be formed in
CNOD design layout
potential leakage: channel leakage (S to D);
junction leakage (S/D to bulk)
CNOD (MPODE) is same with primitive
MOS model; PODE is the primitive MOS, just S/D shorted
together
As shown in Fig. 35 in older planar technology nodes, gate pitch is
so relaxed such that S/D contacts and gate contacts can easily be placed
next to each other without causing any shorting risk (see Fig.
35(a)).
As the gate pitch scales, there’s no room to put gate
contacts next to S/D contacts, and gatecontacts have been pushed away
from the active region and are only placed on the STI
region.
In addition, at tight gate pitch, even forming S/D contact
without shorting to gate metal becomes very challenging.
The idea of self-aligned contacts (SAC) has been
introduced to mitigate the issue of S/D contact to gate shorts.
As shown in Fig. 35(b), the gate metal is fully encapsulated by a
dielectric spacer and gate cap, which protects the gate from
shorting to the S/D contact.
A dielectric cap is added on top of the gate so that if the contact
overlaps the gate, no short occurs.
MD layer represent SACs in PDK
self-aligned gate contacts
(SAGCs)
Self-aligned gate contacts (SAGCs) have also been
implemented and Denser standard cells can be achieved by eliminating the
need to land contacts on the gate outside the active area.
SAGCs require the source/drain contacts to be capped with an
insulator that is different from both contact and gate cap dielectrics
to protect the source/drain contacts against a misaligned gate contact
etch.
According to the DRC of T foundary, poly extension > 0 um and
space between MP and OD > 0 um., which demonstrate self-aligned gate
contact is not introduced.
A native layer (NT_N) is usually added under
inductors or transformers in the nanoscale CMOS to define the non-doped
high-resistance region of substrate, which decreases eddy currents in
the substrate thus maintaining high Q of the coils.
For T* PDK offered inductor, a native substrate region is created
under the inductor coil to minimize eddy currents
OD inside NT_N only can be used for NT_N potential pickup purpose,
such as the guarding-ring of MOM and inductor
Derived Geometries
Term
Definition
PW
{NOT NW}
N+OD
{NP AND OD}
P+OD
{PP AND OD}
GATE
{PO AND OD}
TrGATE
{GATE NOT PODE_GATE}
NP: N+ Source/Drain Ion Implantation
PP: P+ Source/Drain Ion Implantation
OD: Gate Oxide and Diffustion
NW: N-WELL
PW: P-WELL
CMOS Processing Technology
Four main CMOS technologies:
n-well process
p-well process
twin-tub process
silicon on insulator
Triple well, Deep N-Well (optional):
NWell: NMOS svt, lvt, ulvt ...
PWell: PMOS svt, lvt, ulvt ...
DNW: For isolating P-Well from the substrate
The NT_N drawn layer adds no process cost and
no extra mask
The N-well / P-well technology, where n-type diffusion is done over a
p-type substrate or p-type diffusion is done over n-type substrate
respectively.
The Twin well technology, where NMOS and
PMOS transistor are developed over the wafer by simultaneous
diffusion over an epitaxial growth base, rather than a substrate.
Deep N-well
Chew, K.W., Zhang, J., Shao, K., Loh, W., & Chu, S.F. (2002).
Impact of Deep N-well Implantation on Substrate Noise Coupling and RF
Transistor Performance for Systems-on-a-Chip Integration. 32nd European
Solid-State Device Research Conference, 251-254. URL:[slides,
paper]
Kuo-Tsai LiPaul ChangAndy Chang, TSMC, US20120053923A1, "Methods of
designing integrated circuits and systems thereof"
Substrate noise
A variety of techniques can be used to minimize this noise, for
example by keeping analog devices surrounded by guard rings, or using a
separate supply for the substrate/well taps.
However guard rings alone cannot prevent noise coupling deep in
the substrate, only surface currents.
PMOS are less noisy than NMOS since PMOS has its nwell which isolates
the substrate noise, but such is not valid for NMOS .
DNW
The N-channel devices built directly into the P-type substrate are
not as effectively isolated as P-channel devices in their N-wells. This
is because despite creating a P+ guard ring around the devices, there
remains an electrical path below the guard ring for charge to flow.
To overcome this issue, a deep N-well can be used to more
effectively isolate these N-channel devices.
the P-well is separated, allowing the voltage to be controlled
because the circuit within the deep N-well is separated from the
p-substrate in this structure, there is the benefit that this circuitry
is less susceptible to noise that propagates through the
p-substrate.
Cheng, Chung-Kuan, Byeonggon Kang, Bill Lin and Yucheng Wang.
“Invited: Scaling Standard Cell Layout Using Track Height Compression
and Design Technology Co-optimization.” Proceedings of the 2025
International Symposium on Physical Design (2025) [https://ispd.cc/ispd2026/slides/2025/protected/2_2_slides.pdf]
JED Hurwitz, ISSCC2011 "T4: Layout: The other half of Nanometer CMOS
Analog Design" [slides,
transcript]
Tom Quan, TSMC, Bob Lefferts, Fred Sendig, Synopsys, Custom Design
with FinFETs - Best practices designing mixed-signal IP
Jacob, Ajey & Xie, Ruilong & Sung, Min & Liebmann, Lars
& Lee, Rinus & Taylor, Bill. (2017). Scaling Challenges for
Advanced CMOS Devices. International Journal of High Speed Electronics
and Systems. 26. 1740001. 10.1142/S0129156417400018.
Joddy Wang, Synopsys "FinFET
SPICE Modeling" Modeling of Systems and Parameter Extraction Working
Group 8th International MOS-AK Workshop (co-located with the IEDM
Conference and CMC Meeting) Washington DC, December 9 2015
A. L. S. Loke et al., "Analog/mixed-signal design challenges in 7-nm
CMOS and beyond," 2018 IEEE Custom Integrated Circuits Conference
(CICC), San Diego, CA, USA, 2018, pp. 1-8, doi:
10.1109/CICC.2018.8357060.[slides]
Prof. Adam Teman, Advanced Process Technologies, [pdf]
Luke Collins. FinFET variability issues challenge advantages of new
process [link]
Loke, Alvin. (2020). FinFET technology considerations for circuit
design (invited short course). BCICTS 2020 Monterey, CA
Alvin Leng Sun Loke, TSMC. Device and Physical Design Considerations
for Circuits in FinFET Technology", ISSCC 2020
A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS
Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated
Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi:
10.1109/CICC.2019.8780267.
A. L. S. Loke, Migrating Analog/Mixed-Signal Designs to FinFET Alvin
Loke / Qualcomm. 2016 Symposia on VLSI Technology and Circuits
Lattice Semiconductor, 16FFC Process Technology Introduction December
9th, 2021[pdf]
Though it is assumed that \(V_{BE}\)
is a linear function of temperature for first oder analysis.
In practice, \(V_{BE}\) is
slightly nonlinear, the magnitude of this nonlinearity is
referred to as curvature.
curvature depends on the temperature dependency of
the saturation current (\(I_s\)), and on that of the collector
current (\(I_c\)), it can be
written as \[
V_{curv}(T)=\frac{k}{q}(\eta-\delta)(T-T_r-T\cdot \ln(\frac{T}{T_r}))
\] where \(\eta\) = a constant
depending on the doping level, CMOS substrate pnp transistors have a
typically value of \(\eta \approx
4\)
\(\delta\) = order of the
temperature dependence of collector current (\(I_c\))
PTAT \(I_c\) help reduce \(V_{curv}(T)\), \(\delta=1\)
Although the temperature dependence of the bias current \(I_b\) doesn’t impact the accuracy of \(V_{BE}\), it does impact the systematic
nonlinearity or curvature of \(V_{BE}\), and hence the sensor's
systematic error. The curvature in \(V_{BE}\) can be reduced by using a PTAT
bias current.
\[
I_{bias} = \frac{0.7}{\beta \cdot R^2}
\] in which \(\beta=\frac{\mu_{n}\cdot
C_{ox}\cdot W}{L}\), where:
\(\mu_n\)=mobility,
\(C_{ox}\) = oxide capacitance
density,
\(\frac{W}{L}\) = dimension ratio of
unit NMOS used for \(M_1\) and \(M_2\)
\(\mu_n\) is complementary
to the absolute temperature and resitor R is implemented using
high-R flow in FinFET which has a low temperature dependency, the net
temperature dependency of \(I_{bias}\)
is proportional to the absolute temperature \[
I_{bias}\propto T
\]
Kamath, Umanath Ramachandra. "BJT Based Precision Voltage Reference
in FinFET Technology." (2021).
Errors due to V-I Finite
Gain
Finite gain introduces errors both in the V-I converters, finite loop
gain results in errors in the closed-loop transconductances.
Then, \(\alpha\) is obtained \[
\alpha =
\frac{(1+A_{OL2})A_{OL1}}{A_{OL2}(1+A_{OL1})}\cdot\frac{R_2}{R_1}
\] Since the loop gains in the two V-I converters cannot be
expected to match, the resulting errors in
both converters should be reduced to negligible
levels.
We get \[
\frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL1}}
\] Follow the same procedure, assume \(A_{OL1}=\infty\)\[
\frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL2}}
\] The finite gain introduces an error inversely proportional to
the loop gain \(A_{OL1}\),\(A_{OL2}\), the resulting errors in both
converters should be reduced to negligible levels
Why named as "bandgap
reference"
Let us write the output voltage as \[
V_{REF} = V_{BE} + V_T\cdot \ln n
\] and hence \[
\frac{\partial V_{REF}}{\partial T} = \frac{\partial V_{BE}}{\partial T}
+ \frac{V_T}{T}\ln n
\] Setting this to zero and substituting for \(\frac{\partial V_{BE}}{\partial T}\), we
have \[
\frac{V_{BE}-(4+m)V_T-E_g/q}{T}=-\frac{V_T}{T}\ln n
\] If \(V_T\ln n\) is found from
this equation and inserted in \(V_{REF}\), we obtain \[
V_{REF}=\frac{E_g}{q} + (4+m)V_T
\]
The term bandgap is used here because as \(T\to 0\), \(V_{REF} \to E_g/q\)
sinking
PTAT-current generator without current mirrors
Take \(V_{PTAT}=\alpha \cdot \Delta
V_{BE}\) as input and \(V_{REF}\) as reference. The output \(\mu\) of the ADC will then be \[
\mu =\frac{V_{PTAT}}{V_{VREF}}=\frac{\alpha \cdot \Delta
V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}}
\] A final digital output \(D_{out}\) in degrees Celsius can
be obtained by linear scaling: \[
D_{out}=A\cdot \mu + B
\] where \(A\approx 600K\) and
\(B\approx -273K\)
While the transfer is simple, it only uses about 30% of the of the
ADC (the extremes of the operating range correspond to \(\mu \approx 1/3\) and \(\mu \approx 2/3\)). The ratio results in a
rather inefficient use of the modulator's dynamic range.
For a first-order \(\Sigma\Delta\)
modulator, this means that about 1.5 bits of resolution
are lost
A more efficient transfer is \[
\mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot
\Delta V_{BE}}
\] With this more efficient combination, 90% of the
dynamic range is used rather than 30%. Thus, the required resolution
of the ADC is reduced by a factor of three.
In advanced process, like Finfet 16nm, 7nm, high resistance resistor
has +/-15% variation and MOM capacitor has
+/-30% variation.
Then, \(R_1\) and \(R_2\) not only determine the \(\alpha\) but also the integrator's output
swing, so do \(V_{BE}\) and \(\Delta V_{BE}\), \(C_{int}\).
The integrator's output change per period
integrator, comparator offset
integrator offset
comparator offset
integrator design
application in sensor
Offset Errors
The offset of opamp \(A_3\) is
much less critical:
It affects the integrated currents via the finite output
impedances \(R_{out1,2}\) of the V-I
converters, and is therefore attenuated by a factor \(R_{out1}/R_1\) when referred back to the
input of the sinking V-I converter,
or by a factor \(R_{out2}/R_2\)
when referred back to the input of the sourcing V-I converter.
Therefore, no special offset cancellation is needed for opamp \(A_3\).
The current change due to offset of \(A_3\): \[\begin{align}
\frac{V_{BE,os}}{R_1} &= \frac{V_{ota,os}}{R_{out1}} \\
\frac{\Delta V_{BE,os}}{R_2} &= \frac{V_{ota,os}}{R_{out2}}
\end{align}\] Then, the input referenced offset is: \[\begin{align}
V_{BE,os} &=\frac{ V_{ota,os}}{R_{out1}/R_1} \\
\Delta V_{BE,os} &= \frac{ V_{ota,os}}{R_{out2}/R_2}
\end{align}\]
Errors due to Finite Gain
Finite gain of opamp \(A_3\) results
in a non-zero overdrive voltage at its input, which modulates the
current Iint due to the finite output impedances of the V-I
converters.
Assuming the opamp is implemented as a transconductance
amplifier, there are two main causes of this non-zero overdrive
voltage
The finite transconductance \(g_{m3}\) of the opamp, , which implies that
an overdrive voltage is required to provide the feedback
current
The finite DC gain \(A_{0,3}\),
which implies that an overdrive voltage is required to produce the
output voltage\(V_{int}\)
reference
Micheal, A., P., Pertijs., Johan, H., Huijsing., Pertijs., Johan, H.,
Huijsing. (2006). Precision Temperature Sensors in CMOS Technology.
C. -H. Chang, J. -J. Horng, A. Kundu, C. -C. Chang and Y. -C. Peng,
"An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy
of +0.64% in 16nm FinFET," 2014 IEEE Asian Solid-State Circuits
Conference (A-SSCC), 2014, pp. 165-168, doi:
10.1109/ASSCC.2014.7008886.
Yan Lu; Chi-Seng Lam, "Selected Topics in Power, RF, and Mixed-Signal
ICs," in Selected Topics in Power, RF, and Mixed-Signal ICs ,
River Publishers, 2017
By square-law, the Eq \(g_m = \sqrt{2\mu
C_{ox}\frac{W}{L}I_D}\), it is possible to obtain a
higer transconductance by increasing \(W\) while maintaining \(I_D\) constant. However, if \(W\) increases while \(I_D\) remains constant, then \(V_{GS} \to V_{TH}\) and device enters the
subthreshold region. \[
I_D = I_0\exp \frac{V_{GS}}{\xi V_T}
\]
where \(I_0\) is proportional to
\(W/L\), \(\xi \gt 1\) is a nonideality factor, and
\(V_T = kT/q\)
As a result, the transconductance in subthreshold region is \[
g_m = \frac{I_D}{\xi V_T}
\]
which is \(g_m \propto I_D\)
PTAT with subthreshold MOS
MOS working in the weak inversion region
("subthreshold conduction") have the similar
characteristics to BJTs and diodes, since the effect of diffusion
current becomes more significant than that of drift current
Hongprasit, Saweth, Worawat Sa-ngiamvibool and Apinan Aurasopon.
"Design of Bandgap Core and Startup Circuits for All CMOS Bandgap
Voltage Reference." Przegląd Elektrotechniczny (2012):
277-280.
Curvature Compensation
VBE
In advanced node, N4P, \(V_{BE}\) is
about -1.45mV/K
The first-order linear temperature
dependence term of \(V_{BE}\) can be
eliminated with IPTAT. \(V_T(\eta - \theta)\ln)T/T_r\) is the
high-order nonlinear temperature-dependent term of \(V_{BE}\), which requires high-order
curvature compensation
G. Zhu, Y. Yang and Q. Zhang, "A 4.6-ppm/°C High-Order Curvature
Compensated Bandgap Reference for BMIC," in IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 66, no. 9, pp.
1492-1496, Sept. 2019 [https://sci-hub.se/10.1109/TCSII.2018.2889808]
X. Fu, D. M. Colombo, Y. Yin and K. El-Sankary, "Low Noise, High
PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap
Reference," in IEEE Access, vol. 10, pp. 110970-110982, 2022
[https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9923910]
The parameter that shows the dependence of the reference voltage on
temperature variation is called the temperature coefficient and is
defined as: \[
TC_F=\frac{1}{V_{\text{REF}}}\left[
\frac{V_{\text{max}}-V_{\text{min}}}{T_{\text{max}}-T_{\text{min}}}
\right]\times10^6\;ppm/^oC
\]
oxide capacitance (aka gate-channel
capacitance) between the gate and the channel\(C_1=WLC_{ox}\)
divided between \(C_{GS}\) and
\(C_{GD}\)
depletion capacitance between the channel
and the substrate\(C_2\)
overlap capacitance: direct overlap and fringing
field
junction capacitance between the
source/drain areas and the substrate
The value of \(C_{SB}\) and \(C_{DB}\) is a function of the source and
drain voltages with respect to the substrate
The gate-bulk capacitance is usually neglected in
the triode and saturation regions because the inversion layer acts as a
"shield" between the gate and the bulk.
classification with Intrinsic and
Extrinsic MOS capacitor
Notice: S/D and NWELL are connected togethor in
layout
I-MOS vs . A-MOS
P. Andreani and S. Mattisson, "On the use of MOS varactors in RF
VCOs," in IEEE Journal of Solid-State Circuits, vol. 35, no. 6,
pp. 905-910, June 2000 [https://sci-hub.se/10.1109/4.845194]
varactor losses
channel resistance & gate resistance
PDK varactor
nmoscap: NMOS in N-Well varactor
Base Band MOSCAP model (nmoscap) is built without effective series
resistance (ESR) and effective series inductance (ESL) calibrations,
which is for capacitance simulation only
LC-Tank MOSCAP model (moscap_rf) is for frequency-dependent Q factor
and capacitance simulations
MOS Device as Capacitor
Voltage dependence
capacitance of MOS gate varies nonmonotonically
with \(V_{GS}\)
"accumulation-mode" varactor varies
monotonically with \(V_{GS}\)
Adam Teman. Practice 7: CMOS Capacitance [note,problem]
R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in
CMOS -G/sub m/ LC VCOs," in IEEE Journal of Solid-State Circuits, vol.
38, no. 8, pp. 1325-1332, Aug. 2003 [https://sci-hub.jp/10.1109/JSSC.2003.814416]
T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee and S. S. Wong,
"Analysis and optimization of accumulation-mode varactor for RF ICs,"
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat.
No.98CH36215), 1998, pp. 32-33, doi: 10.1109/VLSIC.1998.687993. URL: http://www-smirc.stanford.edu/papers/VLSI98s-chet.pdf
R. Jacob Baker, 6.1 MOSFET Capacitance Overview/Review, CMOS Circuit
Design, Layout, and Simulation, Fourth Edition
B. Razavi, Design of Analog CMOS Integrated Circuits 2nd
We define the ISF of the sampler as the sensitivity of its final
output voltage to the impulse arriving at its input at different times,
the ISF essentially describes the aperture of the sampler.
An ideal sampler would have the perfect aperture, i.e. sampling the
input voltage at exactly one point in time; thus, its ISF would be a
Dirac delta function, \(\delta(t-t_s)\)
where \(t_s\) is when sampling
occurs.
A realistic sampler would rather capture a weighted-average of the
input voltage over a certain time window. This weighting function is
called the sampling aperture and is equivalent to the ISF
A time-varying impulse response\(h(t, \tau)\) is defined as the circuit
response at time \(t\) responding to an
impulse arriving at time \(\tau\).
In general, the ISF can be regarded as the time-varying
impulse response evaluated at one particular observation
time\(t=t_0\).
The system output \(y(t)\) is
related to the input \(x(t)\) as: \[
y(t) = \int_{-\infty}^{\infty}h(t, \tau)\cdot x(\tau)d\tau
\] Note that in a linear time-invariant (LTI) system, \(h(t,\tau)=h(t-\tau)\) and the above
equation reduces to a convolution.
If \(X(j\omega)\) is the Fourier
transform of the input signal \(x(t)\),
i.e. \[
x(t) = \frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot e^{j\omega
t}d\omega
\] Then \[\begin{align}
y(t) &=
\int_{-\infty}^{\infty}h(t,\tau)\left[\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot
e^{j\omega\tau }d\omega \right]\cdot d\tau \\
&=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot
e^{j\omega\tau}d\tau\right]\cdot d\omega \\
&=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\left[\int_{-\infty}^{\infty}h(t,\tau)\cdot
e^{-j\omega(t-\tau)}d\tau\right]\cdot e^{j\omega t}\cdot d\omega \\
&=\frac{1}{2\pi}\int_{-\infty}^{\infty}X(j\omega)\cdot
H(j\omega;t)\cdot e^{j\omega t}\cdot d\omega
\end{align}\]
where \(H(j\omega;t)\) is
time-varying transfer function, defined as the Fourier
transform of the time-varying impulse response. \[
H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot
e^{-j\omega(t-\tau)}d\tau
\] And it follows that: \[
Y(j\omega)=H(j\omega;t)\cdot X(j\omega)
\] And
For linear, periodically time-varying (LPTV) systems, \(h(t, \tau) = h(t+T, \tau+T)\) and \(H(j\omega; t) = H(j\omega; t+T)\) where
\(T\) is the period of the time-varying
dynamics of the system.
Since \(H(j\omega;t)\) is periodic
in \(T\), The time-varying transfer
function \(H(j\omega;t)\) can be
expressed in a Fourier series: \[
\color{red}H(j\omega;t)=\sum_{m=-\infty}^{\infty}H_m(j\omega) \cdot
e^{jm\omega_c t}
\] where \(\omega_c\) is the
fundamental frequency of the periodic system. \(H_m(j\omega)\) represent the frequency
response of the system at the \(m\)-th
harmonic output sideband to a unit \(j\omega\) sinusoid.
The above equation link time-varying transfer function \(H(j\omega;t)\) with PAC simulation
output
The response to a periodic impulse train, that is: \[
x(t)=\sum_{n=-\infty}^{\infty}\delta(t-\tau-nkT)
\] The idea is that if the impulse response of the system settles
to zero long before the next impulse arrives, then the system response
to this impulse train would be approximately equal to the periodic
repetition of the true impulse response, i.e. \[
y(t) \cong \sum_{n=-\infty}^{\infty}h(t;\tau+nkT)
\] and \(y(t)\) would be
approximately equal to \(h(t;\tau)\)
for \(\tau \leq t \le \tau+kT\)
Without loss of generality and for computation convenience, we set
\(k=1\) thereafter.
The Fourier transform \(X(j\omega)\)
of the T-periodic impulse train is: \[
X(j\omega)=\omega_c\sum_{n=-\infty}^{\infty}\delta(\omega-n\omega_c)\cdot
e^{-j\omega\tau}
\] Then the response \(y(t)\)
is: \[
y(t)=\frac{1}{T}\sum_{n=-\infty}^{\infty}H(jn\omega_c;t)\cdot
e^{jn\omega_c\cdot(t-\tau)}
\] The expression for the approximate time-varying impulse
response: \[
h(t,\tau) \cong y(t)= \left\{ \begin{array}{cl}
\frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot
e^{jm\omega_ct+jn\omega_c\cdot (t-\tau)} & : \ \tau \leq t \lt
\tau+T \\
0 & : \ \text{elsewhere}
\end{array} \right.
\] Finally, the ISF \(\Gamma(\tau)\) is equal to \(h(t,\tau)\) when \(t=t_0\) if \(t_0
\gt \tau\)\[
\Gamma(\tau)\cong
\frac{1}{T}\sum_{n=-\infty}^{\infty}\sum_{m=-\infty}^{\infty}H_m(jn\omega_c)\cdot
e^{jm\omega_ct_0+jn\omega_c\cdot (t_0-\tau)}
\] In practice, the summations are carried out over finite ranges
of n and m, for example, -50~50
For each combination of n and m,
the PAC analysis needs to be performed to compute \(H_m(jn\omega_c)\) — \(m\)-th harmonic response to the excitation
at \(n\omega_c\)
The detailed procedure for characterizing the ISF of this sampler is
outlined as follows:
First, apply the proper input voltages that place the sampler in
a metastable state and perform PSS
Second, perform PAC
Third, based on the simulated PAC response, pick a time point
\(t_0\) at which the ISF is to be
computed and derive the ISF
One possible candidate for the ISF measurement point \(\color{red}t_0\) is the time at which the
output voltage is amplified to the largest value. Figure 4(a) plots PAC
response of the sampler to a small signal DC
input — the time-varying transfer function evaluated at \(\color{red}\omega=0\)\[
H(0;t)=\sum_{m=-\infty}^{\infty}H_m(0) \cdot e^{jm\omega_c t}
\]
The total area under the ISF is the sampling gain, which is equal to
the time-varying gain measured at \(t_0\) to a small signal DC input (\(\omega=0\))
Because we have \(H(j\omega;t)=\int_{-\infty}^{\infty}h(t,\tau)\cdot
e^{-j\omega(t-\tau)}d\tau\), i.e. Fourier transform \[
H(0;t)=\int_{-\infty}^{\infty}h(t,\tau)d\tau =
\int_{-\infty}^{\infty}\Gamma(\tau)d\tau
\]
1 2
time-varying gain at t0 H(0;t0): 19.486305 The total area under the ISF: 19.990230
clock frequency should be low enough to assure system response
settle to zero.
Beat Frequency os PSS should be clock frequency
For PAC setup,
the Sweeptype is absolute
Input Frequency Sweep Range(Hz) should be large
enough.
Sweep Type should be Linear and
Step Size should equal PSS Beat
Frequency(Hz)
SideBands should large enough, like 50 (i.e. 50*2 +1,
positive, negative and 0)
Specialized Analyses should be None
one example: clock, i.e. beat frequency = 8G PAC: input frequency
sweep from -400G to 400G and step is 8G, which is beat frequency, here
K=1 Eq.(9) of paper
freqaxis=out: freqaxis of PAC not only
affect "Direct Plot"'s output but also simuation data i.e. the phase
shift(imaginary part)
************************************************** Periodic Steady-State Analysis `pss': fund = 1 GHz ************************************************** DC simulation time: CPU = 208 us, elapsed = 211.954 us.
============================= `pss': time = (0 s -> 1.3 ns) =============================
Opening the PSF file ../psf/pss.tran.pss ...
Output and IC/nodeset summary: save 1 (current) save 2 (voltage)
Important parameter values in tstab integration: start = 0 s outputstart = 0 s stop = 1.3 ns period = 1 ns maxperiods = 20 step = 1.3 ps maxstep = 40 ps ic = all useprevic = no ...
xlabel('t (ps)'); ylabel('V(t)'); legend('Using pss\_td', 'Using pss\_fd', 'pss\_tb one period clip', 'Using pss\_fd with time shift', 'location', 'east');
Transient Method
TODO 📅
reference
J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity
function analysis of periodic circuits," 2008 IEEE/ACM International
Conference on Computer-Aided Design, 2008, pp. 386-391, doi:
10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]
.png)
Unlike BTI, it seems to be no or just
little recovery. As holes are much "cooler" (i.e. heavier) than
electrons, the channel hot carrier effect in nMOS devices is shown to be
more significant than in pMOS devices.
