Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022
P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with
>45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and
Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025
ISSCC.2024 7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm
FinFET CMOS
M. S. Jalali, A. Sheikholeslami, M. Kibune and H. Tamura, "A
Reference-Less Single-Loop Half-Rate Binary CDR," in IEEE Journal of
Solid-State Circuits, vol. 50, no. 9, pp. 2037-2047, Sept. 2015 [https://www.eecg.utoronto.ca/~ali/papers/jssc2015-09.pdf]
Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB
IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International
Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]
K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and
J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL
Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE
Workshop on Design and Diagnostics of Electronic Circuits and
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Refclk Clocking
Architectures
PCI Express Base Specification Revision 3.0
Jeff Morriss, Intel Gerry Talbot, AMD. PCI-SIG Devcon 2006. Jitter
Budgeting for Clock Architecture
Common Refclk Rx architectures are characterized by the Tx and Rx
sharing the same Refclk source
Most of the SSC jitter sourced by the Refclk is propagated equally
through Tx and Rx PLLs, and so intrinsically tracks LF
jitter
The amount of jitter appearing at the CDR is then defined by the
difference function between the Tx and Rx PLLs multiplied by the
CDR highpass characteristic
\[
H(s)= H_1(s)e^{-sT} - \left[H_1(s)e^{-sT}(1-H_3(s)) + H_2(s)H_3(s)
\right] = [H_1(s)e^{-sT} -H_2(s)]H_3(s)
\] where \(H_3(s)\) is similar
to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Data Clocked Refclk Rx
Architecture
A data clocked Rx architecture is characterized by requiring the
receiver's CDR to track the entirety of the low frequency jitter,
including SSC
Separate Reference
Clocks with SSC (SRIS)
TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE:
Updated 10 January 2013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev.
3.0 SPONSOR: Intel, HP, AMD
\[\begin{align}
X_{LATCH}(s) &= X_1(s)H_1(s) - \left[X_1(s)H_1(s)(1-H_3(s)) +
X_2(s)H_2(s)H_3(s) \right] \\
& = \left[X_1(s)H_1(s) -X_2(s)H_2(s)\right]H_3(s)
\end{align}\] where \(H_3(s)\)
is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Separate Reference
Clocks with No SSC (SRNS)
reference
Jason Sachs. Linear Feedback Shift Registers for the Uninitiated,
Part XII: Spread-Spectrum Fundamentals [link]
K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and
J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL
Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE
Workshop on Design and Diagnostics of Electronic Circuits and
Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]
accumulating the input for \(N\)
cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input
samples at rate \(1/T\) and delivers
their sum in a single sample at the output. Therefore, the
process comprises a filter (in the accumulation) and a
down-sampler (in the dump)
Moving Average and CIC
Filters
An Intuitive Look at Moving Average and CIC Filters [web,
code]
Let’s focus on decimation: if we decimate by a factor 4, we simply
retain one output sample out of every 4 input samples.
In the example below, the downsampler at the right drops those 3
samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input
rate \(x(n)\):
with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[
Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}}
\]
But if we're going to be throwing away 75% of the calculated values,
can't we just move the downsampler from the end of the pipeline to
somewhere in the middle? Right between the integrator stage and the comb
stage? That answer is yes, but to keep the math working, we
also need to divide the number of delay elements in the comb stage by
the decimation rate:
Cortiula A, Menin D, Bandiziol A, Driussi F, Palestri P. Modeling of
Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4
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G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based
Clock and Data Recovery With Jitter Optimization," in IEEE Open
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Metastability is an undesirable
non-equilibrium electronic state that can persist for a long
period of time
Poisson stochastic process
Synchronizer effect –
latency uncertainty
simulation of DFF
The typical flip-flops comprise master and slave latches and
decoupling inverters.
In metastability, the voltage levels of nodes A and B of the
master latch are roughly midway between logic 1 (VDD) and 0
(GND)
master latch enter metastability
In fact, one popular definition says that if the output of a
flip-flop changes later than the nominal clock-to-Q propagation
delay, then the flip-flop must have been metastable
Noise Seed—Seed for the random number generator (used by
the simulator to vary the noise sources internally). Specifying the
same seed allows you to reproduce a previous
experiment. The default value is 1.
Kinniment, D. J. Synchronization and arbitration in digital systems.
John Wiley & Sons Ltd (2007).
Synchronizers And Data FlipFlops are Different [pdf]
S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The
Devolution of Synchronizers," 2010 IEEE Symposium on Asynchronous
Circuits and Systems, Grenoble, France, 2010 [pdf]
The most significant impairments are considered to be the sensitivity
to sampling phase, and the effect of aliasing out of band signal and
noise into the baseband
D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J.
Savory, "A baud-rate sampled coherent transceiver with digital pulse
shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]
Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end
Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]
Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for
High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]
DC gain is used to compensate the ratio of sampling rate before and
after upsample
Given \[
X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i}
\] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)
Employ definition of DTFT, \(X(e^{j\hat{\omega}})
=\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set
\(\hat{\omega} = 0\)\[
X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n]
\] That is, \(\sum_{n=-\infty}^{+\infty}x[n] =
\sum_{n=-\infty}^{+\infty}x_e[n]\), so \[
\overline{x_e[n]} = \frac{1}{L} \overline{x[n]}
\] It also indicate that dc gain of upsampling is \(1/L\)
a high normal mode
rejection ratio
(NMRR) for input noise at line
frequency
Conversion accuracy is independent of both the capacitance and
the clock frequency, because they affect both the up-slope and the
down-slope by the same ratio
The fixed input signal integration period results in rejection of
noise frequencies on the analog input that have periods that are equal
to or a sub-multiple of the integration time \(T\)
Interference signals with frequencies at integral multiples of the
integration period are, theoretically, completely removed,
since the average value of a sine wave of frequency
(\(1/T\)) averaged
over a period (\(T\)) is
zero
S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan
Carusone, “All-Digital Calibration of Timing Mismatch Error in
Time-Interleaved Analog-to-Digital Converters,” IEEE Transactions on
VLSI Systems, Sept. 2017. [PDF, slides]
similar to increase the resolution of the flash ADC with
more parallel comparators
De-multiplexing Interleaver
it is the front-end samplers that determine
timing/bandwidth mismatch errors
Re-sampling Interleaver
back-end re-sampling occur after the front-end, two \(\frac{KT}{C}\) contribution in total noise
(De-multiplexing Interleaver only one \(\frac{KT}{C}\))
without buffer, charging distribution reduce signal and reduce SNR,
but buffers give excess noise
Interleaver Model
Interleaving Errors
Offset Mismatch Error
Gain Mismatch Error
Timing Mismatch Error
\(\pi/2\)-rad phase: the maximum
error occurs at the zero crossing and not on
the peaks (Gain Mismatch error)
Frequency-dependent: the higher frequency input signal \(f_\text{in}\), the larger error
becomes
Poulton, Ken. ISSCC2009 "Time-Interleaved ADCs, Past and Future" (slides)
—. CICC2010 "GHz ADCs: From Exotic to Mainstream", tutorial session,
(slides)
—. ISSCC2015 "Interleaved ADCs Through the Ages", (slides)
Ewout Martens. ESSCIRC 2019 Tutorials: Advanced Techniques for ADCs
for 5G Massive MIMO [https://youtu.be/7hYichGGU6k]
Athanasios Ramkaj. January 26, 2022, IEEE SSCS Santa Clara Valley
Section Technical Talk: Design Considerations Towards Optimal
High-Resolution Wide-Bandwidth Time-Interleaved ADCs [https://youtu.be/k3jY9NtfYlY?si=K9AdT9QzGxOnI5WG]
Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]
Extensive work on DFEs has produced a multitude of architectures,
which can be broadly categorized as "direct"" or
"unrolled" (speculative) DFEs with
"full-rate" or "half-rate"
clocking
S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for
20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol.
46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]
Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of
Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]
Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity
Technologies to Accelerate AI
H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an
LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET,"
2025 IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2025
Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed
Wireline Interconnects: Design Challenges and Innovations in 224G SerDes
[https://www.youtube.com/live/wHNOlxHFTzY]