KNOW-HOW

Linear distortion includes any amplitude or delay distortion associated with a linear transmission system

Nonlinear distortion includes harmonic distortion, intermodulation distortion (IMD)

CM Noise

Luo, X., Yu, H., Maqbool, K. Q., Huang, Y., Luo, D., & Yue, P. C. (2017). Analysis on EMI Related Common-mode Noise of Serdes Transmitter. Paper presented at DesignCon 2017 [lnk]

—. EMI related common-mode noise analysis in high-speed backplane links. Thesis (Ph.D.)-HKUST 2018 [link]

—. Study on the effects of distortions and common‐mode noise in high‐speed PAM‐4 systems - Luo - 2018 - Electronics Letters - Wiley Online Library [link]

Patrick Yue. MIIT Courses 2024, Shanghai. Advanced Wireline and Optical Communication IC Design [pdf]

Lee, Jri & Chiang, Ping-Chuan & Peng, Pen-Jui & Chen, Li-Yang & Weng, Chih-Chi. (2015). Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies. IEEE Journal of Solid-State Circuits. [pdf]

amplitude distortion

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w0 = 2*pi*1;  % T=1
t = 0:0.01:1.25;

x1 = cos(w0*t);
x2 = -1/3*cos(3*w0*t);
x3 = 1/5*cos(5*w0*t);

subplot(2,1,1)
plot(t, x1, 'm-', LineWidth=1.5); hold on;
plot(t, x2, 'g-', LineWidth=1.5); plot(t, x3, 'b-', LineWidth=1.5);
plot(t, x1+x2+x3, 'r-', LineWidth=3); grid on; xlim([0 1.25])
legend('cos(\omega_0t)', '-1/3cos(3\omega_0t)', '1/5cos(5\omega_0t)', 'cos(\omega_0t)-1/3cos(3\omega_0t)+1/5cos(5\omega_0t)')

subplot(2,1,2)
plot(t, x1+x2+x3, 'r-', LineWidth=2); hold on;
plot(t, x1/2+x2+x3, 'g-', LineWidth=2); 
plot(t, x1+x2+x3/2, 'b-', LineWidth=2); grid on; xlim([0 1.25])
legend('ref', 'Low frequency attenuated', 'high frequency attenuated')

phase delay

Phase delay directly measures the device or system time delay of individual sinusoidal frequency components in the steady-state conditions

group delay

Pupalaikis, Peter. (2006). Group Delay and its Impact on Serial Data Transmission and Testing. [https://cdn.teledynelecroy.com/files/whitepapers/group_delay-designcon2006.pdf]

Phase Delay & Group Delay

W. Bae, B. Nikolić and D. -K. Jeong, "Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3543-3547, Dec. 2017, [https://people.eecs.berkeley.edu/~bora/Journals/2017/TVLSI17.pdf]

Phase Response Compensation

Xiaojun Zhou. Think PAM4 Serdes [https://ibis.org/summits/nov17a/zhou.pdf]

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fs = 1;
f = (0:0.001:1)*fs;
w = f*2*pi;

H_post = 0.65 - 0.35 * exp(-1j*w*1/fs);
mag_post = abs(H_post);
theta_post = unwrap(angle(H_post));
gd_post = - (theta_post(2:end) - theta_post(1:end-1))./(w(2:end) - w(1:end-1));

H_pre = -0.35 +  0.65 * exp(-1j*w*1/fs);
mag_pre = abs(H_pre);
theta_pre = unwrap(angle(H_pre));
gd_pre = - (theta_pre(2:end) - theta_pre(1:end-1))./(w(2:end) - w(1:end-1));

subplot(3,1,1)
plot(f, mag_post, 'r', LineWidth=2); hold on; plot(f, mag_pre, 'b', LineWidth=2);
grid on; legend('Post Tap FFE', 'Pre Tap FFE'); title('FFE Magnitude Response')

subplot(3,1,2)
plot(f, theta_post, 'r', LineWidth=2); hold on; plot(f, theta_pre, 'b', LineWidth=2);
grid on; legend('Post Tap FFE', 'Pre Tap FFE'); title('FFE Phase Response')

subplot(3,1,3)
plot(f(1:end-1), gd_post, 'r', LineWidth=2); hold on; plot(f(1:end-1), gd_pre, 'b', LineWidth=2);
grid on; legend('Post Tap FFE', 'Pre Tap FFE'); title('FFE Group Delay')

Nonlinearity

Even-Order Distortion

Odd-order distortion: symmetry

Even-Order Distortion: non-symmetry (Effect of Mismatch)

[http://cc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter_09_Nonlinearity%20and%20Mismatch.pdf]

Volterra Series

Heng Zhang. ECEN 665 (ESS) : RF Communication Circuits and Systems Volterra Series: Introduction & Application [https://people.engr.tamu.edu/s-sanchez/665_Volterra_2008.pdf]

reference

Hollister, Allen L. Wideband Amplifier Design. Raleigh, NC: SciTech Pub., 2007.

Starič, P. & Margan, E.. (2006). Wideband Amplifiers. 10.1007/978-0-387-28341-8. [pdf]

Haykin, Simon S., and Michael Moher. Communication Systems. 5th ed. John Wiley & Sons, 2009.

—. Digital Communication Systems. 1st edition. Wiley, 2013. [pdf]

Carlson, A. Bruce, and Paul B. Crilly. Communication Systems: An Introduction to Signals and Noise in Electrical Communication. 5th ed. Boston: McGraw-Hill Higher Education, 2010. [pdf]

Pupalaikis, Peter & Yudin, Eric. (2005). Eye Patterns in Scopes. [https://cdn.teledynelecroy.com/files/whitepapers/eye_patterns_in_scopes-designcon_2005.pdf]

Young W. Lim. Group Delay and Phase Delay (1A) [https://upload.wikimedia.org/wikiversity/en/e/e3/Misc.1.A.GroupPhase.20120719.pdf]

Group delay and phase delay example [https://dspillustrations.com/pages/posts/misc/group-delay-and-phase-delay-example.html]

Arkonaire. What is the difference between phase delay and group delay?[https://dsp.stackexchange.com/a/51532/59253]

Andor Bariska. Time Machine, Anyone? [https://www.dsprelated.com/showarticle/54.php]

Julius Orion Smith III. Introduction to Digital Filters: Phase and Group Delay [https://www.dsprelated.com/freebooks/filters/Phase_Group_Delay.html]

Phase delay vs group delay: Common misconceptions. [https://audiosciencereview.com/forum/index.php?threads/phase-delay-vs-group-delay-common-misconceptions.39591/]

Dan Boschen. Why do we care about "Linear Phase Filters"? [link]

CC Chen. Why Group Delay Optimization? [https://youtu.be/Lv7yO_LkKng]

Group and Phase Delay Measurements with Vector Network Analyzer ZVR [https://cdn.rohde-schwarz.com.cn/pws/dl_downloads/dl_application/application_notes/1ez35/1ez35_1e.pdf]

S. Stegemann, W. Mathis. MOS-AK 2012: Interference and Distortion Analysis for Nonlinear Analog Circuits [https://www.mos-ak.org/dresden_2012/publications/T8_Stegemann_MOS-AK_Desden_12.pdf]

Ali Sheikholeslami. A-SSCC 2024 insight: Noise and Distortion, [https://youtu.be/bvsJgHJ19jI]

B. Razavi, "Design considerations for direct-conversion receivers," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 428-435, June 1997 [http://www.seas.ucla.edu/brweb/papers/Journals/RTCAS97.pdf]

Two-Tone Intermodulation [https://www.ittc.ku.edu/~jstiles/622/handouts/Two-Tone%20Intermodulation.pdf]

Intermodulation Distortion [https://www.ittc.ku.edu/~jstiles/622/handouts/Intermodulation%20Distortion.pdf]

A. Sheikholeslami, "“Noise and Distortion, Part II” [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 16, no. 4, pp. 8-11, Fall 2024

A. Sheikholeslami, "Noise and Distortion, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 17, no. 1, pp. 8-11, winter 2025

Ali Sheikholeslami, University of Toronto, A-SSCC 2024 Circuit Insights:FT1 Noise and Distortion [link]

Time domain modeling

While many different analysis methods exist, including frequency and statistical analysis, time domain results remain the final sign-off

serdespy

Richard Barrie. serdespy — A python library for system-level SerDes modelling and simulation [https://github.com/richard259/serdespy]

python 3.10, samplerate

ifft of sampling continuous-time transfer function

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def freq2impulse(H, f):
    #Returns the impulse response, h, and (optionally) the step response,
    #hstep, for a system with complex frequency response stored in the array H
    #and corresponding frequency vector f.  The time array is
    #returned in t.  The frequency array must be linearly spaced.

    Hd = np.concatenate((H,np.conj(np.flip(H[1:H.size-1]))))
    h = np.real(np.fft.ifft(Hd))
    #hstep = sp.convolve(h,np.ones(h.size))
    #hstep = hstep[0:h.size]
    t= np.linspace(0,1/f[1],h.size+1)
    t = t[0:-1]

    return h,t

Maybe, the more straightforward method is sampling impulse response of continuous-time transfer function directly

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import numpy as np
from scipy import signal
import matplotlib.pyplot as plt

fbw = 20e9
wbw = fbw * 2 * np.pi
samples_per_symbol = 64
UI = 1/50e9
Ts = UI/samples_per_symbol
fs = 1/Ts
ws = fs * 2 * np.pi
ttot = 4/fbw # heuristic
N = int(0.5 * fs * ttot)+1
w, H = signal.freqs([1], [1/wbw, 1], np.linspace(0, 0.5*ws, N))

## freq2impulse(H, f), ifft - using sample of continuous-time tranfer function
f = w/(2*np.pi)
Hd = np.concatenate((H,np.conj(np.flip(H[1:H.size-1]))))
hd = np.real(np.fft.ifft(Hd))
t= np.linspace(0,1/f[1],hd.size+1)
t = t[0:-1]

## continuous-time transfer function - impulse
t, hc = signal.impulse(([1], [1/wbw, 1]), T = t)

## hd(kTs) = Ts*hc(kTs)
plt.figure(figsize = (14,10))
plt.plot(t, hc, t, hd/Ts, '--r', linewidth=3)
plt.grid(); plt.legend(['impulse response by continuous-time transfer function','impulse response/Ts by ifft of sampling transfer function'])
plt.ylabel('Mag'); plt.xlabel('time (s)'); plt.show()

JLSD

Kevin Zheng. JLSD — Julia SerDes [https://github.com/kevjzheng/JLSD]

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out = conv(ir, vbits)*tui/osr
lines(tt, out[1:length(vbits)])

Kronecker product to create oversampled waveform

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function gen_wvfm(bits; tui, osr)
	#helper function used to generate oversampled waveform
	
	Vbits = kron(bits, ones(osr)) #Kronecker product to create oversampled waveform
	dt = tui/osr
	tt = 0:dt:(length(Vbits)-1)*dt

	return tt, Vbits
end

normalized to the time step \[ \frac{\alpha}{s+\alpha} \overset{\mathcal{L}^{-1}}{\longrightarrow} \alpha\cdot e^{-\alpha t} \]

The integral of impulse response of low pass RC filter \(\int_{0}^{+\infty} \alpha\cdot e^{-\alpha t}dt = 1\) — sum(ir*dt)

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function gen_ir_rc(dt,bw,t_len)
	#helper function that directly calculates a first order RC response, normalized to the time step
    tt = [0:dt:t_len-dt;]

	#checkout the intuitive symbols!
    ω = (2*π*bw)
    ir = ω*exp.(-tt*ω)
    ir .= ir/sum(ir*dt)

    return ir
end

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using Plots
using LaTeXStrings

tui = 1/10e9;
tlen_ir = 20*tui;


osr_list = [4, 8, 16, 32, 64, 128, 256, 512, 1024];
bw_ir = 8e9;

ω = (2*π*bw_ir);

ir_dt_sum_list = [];

for osr_cur in osr_list
    dt = tui/osr_cur; # Simulation time step
    tt = [0:dt:tlen_ir-dt;]
    ir = ω*exp.(-tt*ω);
    ir_dt_sum = sum(ir*dt);
    push!(ir_dt_sum_list, ir_dt_sum)
end

println(ir_dt_sum_list)
# Any[1.756575097878581, 1.3468434968519964, 1.1652908056870317, 1.0805951388547221, 1.0397838972257087, 1.0197634612560418, 1.0098496044545267, 1.0049167704129547, 1.0024563772359665]

p = plot(osr_list, ir_dt_sum_list, label = "OSR")
gui(p)

Elastic Buffer

the elastic buffer approach would be the most general for modeling say frequency offsets between TX and RX (will be addressed in future development)

generate PAM symbols

here Big Endian

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#generate PAM symbols
   fill!(So, zero(Float64)) #reset So to all 0
   for n = 1:bits_per_sym
       @. So = So + 2^(bits_per_sym-n)*So_bits[n:bits_per_sym:end]
   end

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function int2bits(num, nbit)
    return [Bool((num>>k)%2) for k in nbit-1:-1:0]
end


 Si_bits .= vec(stack(int2bits.(Si, bits_per_sym)))

Detailed Transmitter

DaVE

DaVE — tools regarding on analog modeling, validation, and generation, [https://github.com/StanfordVLSI/DaVE]

Statistical Eye

Sanders, Anthony, Michael Resso and John D'Ambrosia. “Channel Compliance Testing Utilizing Novel Statistical Eye Methodology.” (2004).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

HSPICE® User Guide: Signal Integrity Modeling and Analysis, Version Q-2020.03, March 2020

IA Title: Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]

J. Park and D. Kim, "Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review," in IEEE Access, vol. 12, pp. 22880-22891, 2024 [pdf]

StatOpt

Savo Bajic, ECE1392, Integrated Circuits for Digital Communications: StatOpt in Python [https://savobajic.ca/projects/academic/statopt] [https://www.eecg.utoronto.ca/~ali/statopt/main.html]

Analog Signals Representation

Ben Yochret Sabrine, 2020, "BEHAVIORAL MODELING WITH SYSTEMVERILOG FOR MIXED-SIGNAL VALIDATION" [https://di.uqo.ca/id/eprint/1224/1/Ben-Yochret_Sabrine_2020_memoire.pdf]

PRBS Generator & Checker

PRBS Generator

[https://opencpi.gitlab.io/releases/latest/rst/comp_sdr/components/generator/prbs_generator_b.comp/prbs_generator_b-index.html]

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# Julia

function bist_prbs_gen(;poly, inv, Nsym, seed)
    seq = Vector{Bool}(undef,Nsym)
    for n = 1:Nsym
        seq[n] = inv
        for p in poly
            seq[n] ⊻= seed[p]
        end
        seed .= [seq[n]; seed[1:end-1]]
    end
    return seq, seed
end

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%% Matlab

function [seq, seed] = bist_prbs_gen(poly,inv, Nsym, seed)
    seq = zeros(1,Nsym);
    for n = 1:Nsym
        seq(n) = inv;
        for p = poly
            seq(n) = xor(seq(n), seed(p));
        end
       seed = [seq(n), seed(1:end-1)];
    end
end

[https://github.com/kevjzheng/JLSD/blob/main/Pluto%20Notebooks/pdf/JLSD_pt1_background.pdf]

PRBS Checker

previous bit determine current bit

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function ber_check_prbs(rcvd_bits; poly, inv, seed, lock_status, lock_cnt, lock_threshold, ber_err_cnt, ber_tot_cnt)
	
	nbits_rcvd = lastindex(rcvd_bits)
	
    if lock_status #if prbs already locked, use prbs_gen for reference bits
        ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv,
										Nsym=nbits_rcvd, seed=seed)
        ber_err_cnt += sum(rcvd_bits .⊻ ref_bits)
		ber_tot_cnt += nbits_rcvd

    else # if not locked yet, use received bits as seed
        for n = 1:nbits_rcvd
            brcv = rcvd_bits[n]
            btst = inv
			for p in poly
            	btst ⊻= seed[p]
			end
            seed .= [brcv; seed[1:end-1]]

			#need consecutive non-error for lock. reset when error happens
            lock_cnt = (btst == brcv) ? lock_cnt+1 : 0

            if lock_cnt == lock_threshold
                lock_status = true
                println("prbs locked")
				#run prbs till end
                ref_bits, seed = bist_prbs_gen(poly=poly, inv=inv,
										Nsym=nbits_rcvd-n, seed=seed)
				ber_err_cnt += sum(rcvd_bits[n+1:end] .⊻ ref_bits)
				ber_tot_cnt += nbits_rcvd - n

                break
            end
        end
    end

	return seed, lock_status, lock_cnt, ber_err_cnt, ber_tot_cnt
end

Reference

MATLAB® and Simulink® RF and Mixed Signal [https://www.mathworks.com/help/overview/rf-and-mixed-signal.html]

Lim, Byong Chan, M. Horowitz, "Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1, pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]

—, Ph.D. Dissertation 2012. "Model validation of mixed-signal systems" [https://stacks.stanford.edu/file/druid:xq068rv3398/bclim-thesis-submission-augmented.pdf]

—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, "Digital Analog Design: Enabling Mixed-Signal System Validation," in IEEE Design & Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim, Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]

S. Liao and M. Horowitz, "A Verilog piecewise-linear analog behavior model for mixed-signal validation," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013 [https://sci-hub.se/10.1109/CICC.2013.6658461]

—, M. Horowitz, "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2229-2235, Aug. 2014 [https://sci-hub.se/10.1109/TCSI.2014.2332265]

—,Ph.D. Dissertation 2012. Verilog Piecewise Linear Behavioral Modeling For Mixed-Signal Validation [https://stacks.stanford.edu/file/druid:pb381vh2919/Thesis_submission-augmented.pdf]

Ji-Eun Jang et al. “True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example”. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. 2012 [https://sci-hub.se/10.1109/CICC.2012.6330558]

—, Si-Jung Yang, and Jaeha Kim. “Event-driven simulation of Volterra series models in SystemVerilog”. In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference. 2013 [https://sci-hub.se/10.1109/CICC.2013.6658460]

—, Ph.D. Dissertation 2015. Event-Driven Simulation Methodology for Analog/Mixed-Signal Systems [file:///home/anon/Downloads/000000028723.pdf]

"Creating Analog Behavioral Models VERILOG-AMS ANALOG MODELING" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/CDN_Creating_Analog_Behavioral_Models.pdf]

Rainer Findenig, Infineon Technologies. "Behavioral Modeling for SoC Simulation Bridging Analog and Firmware Demands" [https://www.coseda-tech.com/files/Files/Dokumente/Behavioral_Modeling_for_SoC_Simulation_COSEDA_UGM_2018.pdf]

CC Chen. Why Efficient SPICE Simulation Techniques for BB CDR Verification? [https://youtu.be/Z54MV9nuGUI]

T. Wen and T. Kwasniewski, "Phase Noise Simulation and Modeling of ADPLL by SystemVerilog," 2008 IEEE International Behavioral Modeling and Simulation Workshop, San Jose, CA, USA, 2008 [slides, paper]

Jaeha Kim,Scientific Analog. UCIe PHY Modeling and Simulation with XMODEL [pdf]

S. Katare, "Novel Framework for Modelling High Speed Interface Using Python for Architecture Evaluation," 2020 IEEE REGION 10 CONFERENCE (TENCON), Osaka, Japan, 2020 [https://sci-hub.se/10.1109/TENCON50793.2020.9293846]

Single-Pole LPF Algorithms

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

Jason Sachs, Ten Little Algorithms, Part 2: The Single-Pole Low-Pass Filter [https://www.embeddedrelated.com/showarticle/779.php]

—. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

• Derivatives Approximation (\(H_p(s)=\frac{1}{s\tau +1}\))

  \[\begin{align} H_p(z)&=\frac{\frac{T_s}{T_s+\tau}}{1+(\frac{T_s}{T_s+\tau}-1)z^{-1}}\tag{EQ-0}\\ H_p(z)&=\frac{\frac{T_s}{\tau}}{1+(\frac{T_s}{\tau}-1)z^{-1}}\tag{EQ-1} \end{align}\]

• Matched z-Transform (Root Matching) \[ H_p(z)=\frac{1-e^{-T_s/\tau}}{1-e^{-T_s/\tau}z^{-1}}\tag{EQ-2} \] EQ-2 is connected with EQ-1 by \(1 - e^{-\Delta t/\tau} \approx \frac{\Delta t}{\tau}\)

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import numpy as np
import matplotlib.pyplot as plt
import scipy.signal


dt=0.002; tau=0.05

T=1
t = np.arange(0,T+1e-5,dt)
x = 1-np.abs(4*t-1)
x[4*t>2] = 0.95; x[t>0.75] = 0.02

alpha_derv = dt / (dt + tau)
alpha_derv_approx = dt / tau

yfilt_derv = scipy.signal.lfilter([alpha_derv], [1, alpha_derv - 1], x)
yfilt_derv_approx = scipy.signal.lfilter([alpha_derv_approx], [1, alpha_derv_approx - 1], x)

a1 = -np.exp(-dt/tau)
b0 = [1 + a1]
a = [1, a1]
y_filt_match = scipy.signal.lfilter(b0, a, x)

plt.figure(figsize=(20,10))
plt.plot(t, x, color='k', linewidth=3, label='x')
plt.plot(t, yfilt_derv, color='red', linewidth=3, label=r'$H_p(z)=\frac{\frac{T_s}{T_s+\tau}}{1+(\frac{T_s}{T_s+\tau}-1)z^{-1}}$')
plt.plot(t, yfilt_derv_approx, color='green', marker='D', linestyle='dashed',markersize=4, linewidth=3, label=r'$H_p(z)=\frac{\frac{T_s}{\tau}}{1+(\frac{T_s}{\tau}-1)z^{-1}}$')
plt.plot(t, y_filt_match, color='m', marker='x', linestyle='dashed',markersize=4, linewidth=3, label=r'$H_p(z)=\frac{1-e^{-T_s/\tau}}{1-e^{-T_s/\tau}z^{-1}}$')

plt.legend(loc='upper right', fontsize=20)
plt.grid(which='both');plt.xlabel('Time (s)');plt.show()

Discrete-Time Integrators

Qasim Chaudhari. Discrete-Time Integrators [https://wirelesspi.com/discrete-time-integrators/]

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA?si=_pGb18rhsMUZ-lAf]

Delaying Integrator

Delay-free Integrator

Discrete-Time Differentiator

Qasim Chaudhari. Design of a Discrete-Time Differentiator [https://wirelesspi.com/design-of-a-discrete-time-differentiator/]

TODO 📅

Accumulate-and-dump (AAD) decimator

accumulating the input for \(N\) cycles and then latching the result and resetting the integrator

It adds up \(N\) succeeding input samples at rate \(1/T\) and delivers their sum in a single sample at the output. Therefore, the process comprises a filter (in the accumulation) and a down-sampler (in the dump)

Moving Average and CIC Filters

An Intuitive Look at Moving Average and CIC Filters [web, code]

A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

TODO 📅

Cascaded Integrator-Comb (CIC) filter

Let’s focus on decimation: if we decimate by a factor 4, we simply retain one output sample out of every 4 input samples.

In the example below, the downsampler at the right drops those 3 samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input rate \(x(n)\):

\[\begin{align} Y(z) &= X(z)\frac{1-z^{-4}}{1-z^{-1}} \\ Y^\prime(\xi) &= \frac{1}{4}Y(\xi^{1/4}) = \frac{1}{4}X(\xi^{1/4})\frac{1-\xi^{-1}}{1-\xi^{-1/4}} \end{align}\]

with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[ Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}} \]

But if we're going to be throwing away 75% of the calculated values, can't we just move the downsampler from the end of the pipeline to somewhere in the middle? Right between the integrator stage and the comb stage? That answer is yes, but to keep the math working, we also need to divide the number of delay elements in the comb stage by the decimation rate:

\[\begin{align} A(z) &= X(z)\frac{1}{1-z^{-1}} \\ A^\prime(\xi) &= \frac{1}{4}A(\xi^{1/4}) = \frac{1}{4}X(\xi^{1/4})\frac{1}{1-\xi^{-1/4}} \\ Y^\prime(\xi) &= A^\prime(\xi) (1-\xi^{-1}) = \frac{1}{4}X(\xi^{1/4})\frac{1-\xi^{-1}}{1-\xi^{-1/4}} \end{align}\]

with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[ Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}} \]

And we can do this just the same with cascaded sections (without downsampler or updampler) where integrators and combs have been grouped

• for decimation, the integrators come first and the combs second with the downsampler in between
• For interpolation, the reverse is true
  • the incoming sample rate is fraction of the outgoing sample rate, the combs must come first and the interpolators second

Tom Verbeure. An Intuitive Look at Moving Average and CIC Filters [https://tomverbeure.github.io/2020/09/30/Moving-Average-and-CIC-Filters.html]

—. Half-Band Filters, a Workhorse of Decimation Filters [https://tomverbeure.github.io/2020/12/15/Half-Band-Filters-A-Workhorse-of-Decimation-Filters.html]

—. Design of a Multi-Stage PDM to PCM Decimation Pipeline [https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html]

Arash Loloee, Ph.D. Exploring Decimation Filters [https://www.highfrequencyelectronics.com/Archives/Nov13/1311_HFE_decimationFilters.pdf]

Rick Lyons. A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

reference

Jabbour, Chadi, etc.. "Digitally enhanced mixed signal systems." IEEE International Symposium on Circuits and Systems (ISCAS). 2019.

Sen M. Kuo. Real-Time Digital Signal Processing: Fundamentals, Implementations and Applications, 3rd Edition. John Wiley & Sons 2013

Taylor, Fred. Digital filters: principles and applications with MATLAB. John Wiley & Sons, 2011

Kuo, Sen-Maw. (2013) Real-Time Digital Signal Processing: Implementations and Applications 3rd [pdf]

D. Markovic and R. W. Brodersen, DSP Architecture Design Essentials, Springer, 2012.

Bevan Baas, EEC281 VLSI Digital Signal Processing, [https://www.ece.ucdavis.edu/~bbaas/281/]

Mark Horowitz. EE371: Advanced VLSI Circuit Design Spring 2006-2007 [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/]

謝秉璇. 2019 積體電路設計導論 [link]

Tinoosh Mohsenin. CMPE 691: Digital Signal Processing Hardware Implementation [https://userpages.cs.umbc.edu/tinoosh/cmpe691/]

Keshab K. Parhi [http://www.ece.umn.edu/users/parhi/]

Qasim Chaudhari. FIR vs IIR Filters – A Practical Comparison [https://wirelesspi.com/fir-vs-iir-filters-a-practical-comparison/]

—. Finite Impulse Response (FIR) Filters [https://wirelesspi.com/finite-impulse-response-fir-filters/]

—. Why FIR Filters have Linear Phase [https://wirelesspi.com/why-fir-filters-have-linear-phase/]

—. Moving Average Filter [https://wirelesspi.com/moving-average-filter/]

—. Cascaded Integrator Comb (CIC) Filters – A Staircase of DSP. [https://wirelesspi.com/cascaded-integrator-comb-cic-filters-a-staircase-of-dsp/]

Jason Sachs. Understanding and Preventing Overflow (I Had Too Much to Add Last Night) [https://www.embeddedrelated.com/showarticle/532.php]

—. Round Round Get Around: Why Fixed-Point Right-Shifts Are Just Fine [https://www.embeddedrelated.com/showarticle/1015.php]

—. How to Build a Fixed-Point PI Controller That Just Works: Part I [https://www.embeddedrelated.com/showarticle/121.php]

—. How to Build a Fixed-Point PI Controller That Just Works: Part II [https://www.embeddedrelated.com/showarticle/123.php]

Capacitor Bank

B. Sadhu and R. Harjani, "Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%)," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010 [https://sci-hub.st/10.1109/ISCAS.2010.5537040]

TODO 📅

large value KVCO is not favorable due to noise and possibly spurs at the control voltage

LC Tank

Definitions of Q

Assuming RLC oscillator waveform is \(V_0\sin\omega_0 t\) and \(\omega_0 = \frac{1}{\sqrt{LC}}\) is resonance frequency. suppose the current through \(R\) is cancelled out by additional \(-R\)

Energy stored \[ E_t = \frac{1}{2}LI_0^2 = \frac{1}{2}L(C\omega_0V_0)^2=\frac{1}{2}LC^2\omega_0^2 V_0^2 = \frac{1}{2}CV_0^2 \] Energy Dissipated per Cycle \[ E_d = \frac{V_0^2}{2R}\frac{2\pi}{\omega_0} \] For \(Q_4\) \[ Q_4 = 2\pi\frac{E_s}{E_d} = R\omega_0C = \frac{R}{\omega_0L} \]

For \(Q_3\), suppose RLC tank is driven by \(V_o\cos \omega t\) voltage source, then

Peak Magnetic Energy \[ E_{pL} = \frac{1}{2}LI_0^2 = \frac{1}{2}L\left(\frac{V_0}{L\omega}\right)^2 \] Peak Electric Energy \[ E_{pC} = \frac{1}{2}CV_0^2 \] with Energy Lost per Cycle \(E_d = \frac{V_0^2}{2R}\frac{2\pi}{\omega_0}\), we have \[ Q_3 = \frac{E_{pL} - E_{pC}}{E_d} = \left(\frac{1}{L\omega^2}-C\right)R\omega=\frac{R}{L\omega}\left(1 - \frac{\omega^2}{\omega^2_{SR}}\right) \]

Makarov, Sergey & Ludwig, Reinhold & Bitar, Joyce. (2016). Practical Electrical Engineering. 10.1007/978-3-319-21173-2. [pdf]

TODO 📅

Output Amplitude

Edgar Sanchez-Sinencio. ECEN 665, OSCILLATORS [https://people.engr.tamu.edu/s-sanchez/665%20Oscillators.pdf]

NMOS Realization

common mode current don't contribute to output amplitude

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L0 = 1e-9 * 2;
RL0 = 0.25133 * 2;
C0 = 6.333e-12 / 2;
RC0 = 0.50264 * 2;

w0 = 1/sqrt(L0*C0);   % 12.566 Grad/s

QL = w0*L0/RL0;       % 50
QC = 1/(w0*C0)/RC0;   % 25

RLp0 = QL^2 * RL0;
RCp0 = QC^2 * RC0;
Rp = RLp0 * RCp0 / (RLp0 + RCp0);  % 418.8576 Ohm
Qtot_by_L = Rp/(w0*L0);    % 16.6664
Qtot_by_C = Rp*(w0*C0);    % 16.6664

I0 = 0.5e-3;
vp_p = 2/pi * I0 * Rp/2;     % 66.6633 mV

%%%% compute Qtot from simulation waveform
vp_p2p_sim = 132.8e-3;
Qtot_calc_L0 = vp_p2p_sim*pi/2/I0/(w0*L0);   % 16.6006
Qtot_calc_C0 = vp_p2p_sim*pi/2/I0*(w0*C0);   % 16.6006

CMOS Realization

Owing to switch-off PMOS eliminating common mode current, all \(I_T\) is differentially flowing in the tank.

current limited vs voltage limited

Cross-coupled Differential-pair

?? Triode MOS noise

Common-Mode Effects

P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with >45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025

E. Hegazi, H. Sjoland and A. Abidi, "A filtering technique to lower oscillator phase noise," 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), San Francisco, CA, USA, 2001 [paper, slides]

—, "A filtering technique to lower LC oscillator phase noise," in IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001 [https://people.engr.tamu.edu/spalermo/ecen620/filtering_tech_lc_osc_hegazi_jssc_2001.pdf]

—, "25.3 A VCO with implicit common-mode resonance," 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.st/10.1109/ISSCC.2015.7063116]

Lecture 16: VCO Phase Noise [https://people.engr.tamu.edu/spalermo/ecen620/lecture16_ee620_vco_pn.pdf]

TODO 📅

Tail filter

D. Murphy, H. Darabi and H. Wu, "Implicit Common-Mode Resonance in LC Oscillators," in IEEE Journal of Solid-State Circuits, vol. 52, no. 3, pp. 812-821, March 2017, [https://sci-hub.st/10.1109/JSSC.2016.2642207]

M. Shahmohammadi, M. Babaie and R. B. Staszewski, "A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2610-2624, Nov. 2016 [pdf]

M. Babaie, M. Shahmohammadi, R. B. Staszewski, (2019) "RF CMOS Oscillators for Modern Wireless Applications" River Publishers [https://www.riverpublishers.com/pdf/ebook/RP_E9788793609488.pdf]

TODO 📅

reference

A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC Oscillator," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 45-59, 2025 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10818782]

Pietro Andreani. ISSCC 2011 T1: Integrated LC oscillators [slides,transcript]

—. ISSCC 2017 F2: Integrated Harmonic Oscillators

—. SSCS Distinguished Lecture: RF Harmonic Oscillators Integrated in Silicon Technologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto.pdf]

—. ESSCIRC 2019 Tutorials: RF Harmonic Oscillators Integrated in Silicon Technologies [https://youtu.be/k1I9nP9eEHE]

—. "Harmonic Oscillators in CMOS—A Tutorial Overview," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021 [pdf]

C. Samori, "Tutorial: Understanding Phase Noise in LC VCOs," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016

—, "Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits," in IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 81-91, Fall 2016 [https://sci-hub.se/10.1109/MSSC.2016.2573979]

—, Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-VCO-short.pdf]

Jun Yin. ISSCC 2025 T10: mm-Wave Oscillator Design

Razavi, Behzad. RF Microelectronics. 2nd ed. Prentice Hall, 2012. [pdf]

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007

Manetakis, K. (2023). Topics in LC Oscillators: Principles, phase noise, pulling, inductor design. Springer Nature Switzerland Springer. [eetop link]

spread spectrum clock generation (SSCG) — an advanced clock generation solution for electromagnetic interference (EMI)

SSC modulation profile

[https://www.synopsys.com/blogs/chip-design/understanding-pcie-spread-spectrum-clocking.html]

The most common modulation techniques are down-spread and center-spread:

• Down-spread: Carrier is modulated to lower than nominal frequency by specified percentage, and not higher

• Center-spread: Carrier is modulated both higher and lower than nominal frequency by specified percentage

Steve Glaser, NVidia Corporation. Clocking Mode Terminology-2018-03-01. Workgroup: PCI Express - Protocol

SSCG Architectures

K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]

Due to \(f= K_{vco}V_{ctrl}\), its derivate to \(t\) is \[ \frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt} \]

For chargepump PLL, \(dV_{ctrl} = \frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[ \frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C} \]

Refclk Clocking Architectures

PCI Express Base Specification Revision 3.0

Jeff Morriss, Intel Gerry Talbot, AMD. PCI-SIG Devcon 2006. Jitter Budgeting for Clock Architecture

Verification of SRIS/SRNS Clocking [https://www.esaindia.com/emailer/download/sria-srns-white-paper-final-v3.pdf]

Common Reference Clock (CC)

Common Refclk Rx architectures are characterized by the Tx and Rx sharing the same Refclk source

Most of the SSC jitter sourced by the Refclk is propagated equally through Tx and Rx PLLs, and so intrinsically tracks LF jitter

The amount of jitter appearing at the CDR is then defined by the difference function between the Tx and Rx PLLs multiplied by the CDR highpass characteristic

\[ H(s)= H_1(s)e^{-sT} - \left[H_1(s)e^{-sT}(1-H_3(s)) + H_2(s)H_3(s) \right] = [H_1(s)e^{-sT} -H_2(s)]H_3(s) \] where \(H_3(s)\) is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)

Data Clocked Refclk Rx Architecture

A data clocked Rx architecture is characterized by requiring the receiver's CDR to track the entirety of the low frequency jitter, including SSC

Separate Reference Clocks with SSC (SRIS)

TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE: Updated 10 January 2013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev. 3.0 SPONSOR: Intel, HP, AMD

\[\begin{align} X_{LATCH}(s) &= X_1(s)H_1(s) - \left[X_1(s)H_1(s)(1-H_3(s)) + X_2(s)H_2(s)H_3(s) \right] \\ & = \left[X_1(s)H_1(s) -X_2(s)H_2(s)\right]H_3(s) \end{align}\] where \(H_3(s)\) is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)

Separate Reference Clocks with No SSC (SRNS)

SSC on digital CDR

Gerry Talbot, "Impact of SSC on CDR" , April 12th, 2012, PCI Express EWG

\[\begin{align} f[n] &= \frac{A_1[n]-A_1[n-1]}{T} = \frac{k_1\cdot A_0[n]}{T} \\ \Delta f [n] & = \frac{f[n] -f[n-1]}{T} = \frac{k_0k_1\cdot \Delta}{T^2} \end{align}\]

the polyfit of \(f[n]\) is consistent with \(\Delta f [n]\)

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import matplotlib.pyplot as plt
import numpy as np


f0 = 1
fa = f0/16
fs = 32*f0

Mc = 1000
t = np.arange(0, 1/f0*Mc, 1/fs)
phi_raw = 2*np.pi*f0*t
y = np.sin(phi_raw)

plt.figure(figsize=(24,12))
plt.subplot(3, 1, 1)
plt.plot(t, y); plt.title(r'$\sin(\omega_0 t)$', fontsize='xx-large')

k0 = 0.25
k1 = 0.36

A0 = [0]
A1 = [0]
N = int(Mc*fa/f0)
delta = 0.1
dlsb = delta * 2*np.pi

f_deriv_formula = k0*k1*delta*fa**2
print(f'freq derivation by formula = {f_deriv_formula:.3e}')

for i in range(N):
    A1.append(A1[-1] + k1*A0[-1])
    A0.append(A0[-1] + k0*dlsb)


phi_A1 = np.ones((len(A1), int(fs/fa)))
A1_arr  = np.array(A1).reshape((len(A1), 1))
phi_A1 = phi_A1 * A1_arr
phi_A1 = phi_A1.flatten()

t_phi = np.arange(phi_A1.shape[0])*1/fs

plt.subplot(3, 1, 2)
plt.plot(t_phi, phi_A1); plt.title(r'$\Delta \Phi(t)$', fontsize='xx-large')

Ntot = min(t.shape[0], t_phi.shape[0])
t_tot = t_phi[:Ntot]
phi_tot = phi_raw[:Ntot] + phi_A1[:Ntot]
y_tot = np.sin(phi_tot)

phi_tot_deriv1 = (phi_tot[1:] - phi_tot[:-1])*fs/2/np.pi
phi_tot_deriv2 = (phi_tot_deriv1[1:] - phi_tot_deriv1[:-1])*fs

f_deriv_polyfit, _ = np.polyfit(np.arange(phi_tot_deriv1.shape[0])*1/fs, phi_tot_deriv1, 1) # array([3.51305094e-05, 9.99455375e-01])
print(f'freq derivation by polyfit = {f_deriv_polyfit:.3e}')

plt.subplot(3, 1, 3)
plt.plot(t_tot, y_tot); plt.xlabel(r'$t$', fontsize=24); plt.title(r'$\sin(\omega_0 t+\Delta \Phi(t))$', fontsize='xx-large')
plt.show()

y_raw_export = np.zeros((t.shape[0], 2))
y_raw_export[:,0] = t
y_raw_export[:,1] = y

y_tot_export = np.zeros((t.shape[0], 2))
y_tot_export[:,0] = t_tot
y_tot_export[:,1] = y_tot

np.savetxt('y_raw.csv', y_raw_export, delimiter=',')
np.savetxt('y_tot.csv', y_tot_export, delimiter=',')

# freq derivation by formula = 3.516e-05
# freq derivation by polyfit = 3.513e-05

reference

Jason Sachs. Linear Feedback Shift Registers for the Uninitiated, Part XII: Spread-Spectrum Fundamentals [link]

Jan Meel, Spread Spectrum (SS) — introduction, De Nayer Instituut, Sint-Katelijne-Waver, Belgium, 1999.

Raymond L. Pickholtz, Donald L. Schilling, Laurence B. Milstein, Theory of Spread-Spectrum Communications — A Tutorial, IEEE Transactions on Communications, vol. 30, no. 5, pp. 855-884, May 1982.

Kadeem Samuel. Application Note Clocking for PCIe Applications [https://www.ti.com/lit/an/snaa386/snaa386.pdf?ts=1756864837383]

K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Phase Interpolator (PI)

!!! Clock Edges

And for a phase interpolator, you need those reference clocks to be completely the opposite. Ideally they would be triangular shaped

four input clocks given by the cyan, black, magenta, red

John T. Stonick, ISSCC 2011 tutorial. "DPLL Based Clock and Data Recovery" [https://www.nishanchettri.com/isscc-slides/2011%20ISSCC/TUTORIALS/ISSCC2011Visuals-T5.pdf]

kink problem

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023.(https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf)

Predistortion - sinusoidal

the interpolating inverters near the midscale can be made weaker so as to obtain more uniform phase increments. Alternatively, those at the top and bottom of the array can be made stronger

Single-Quadrant PI

\[ V_o(t) = m \cdot \sin(\omega t + \frac{\pi}{2}) + p\cdot \sin(\omega t) = m\cdot \cos(\omega t) + p\cdot \sin(\omega t) = \sqrt{m^2+p^2} \sin(\omega t + \phi) \]

where \(\tan \phi = \frac{m}{p} = \frac{1-p}{p}\) and \(p = \frac{1}{1+\tan \phi}\)

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phi = (32:-1:0)./32*pi/2;
p_ideal = 1./(1+tan(phi));
delta_p_ideal = abs(p_ideal(1:end-1) - p_ideal(2:end));
phi_ideal = atan((1-p_ideal)./p_ideal);


p_lin = (0:1:32)/32;
phi_lin = atan((1-p_lin)./p_lin);
delta_p_lin = abs(p_lin(1:end-1) - p_lin(2:end));


delta_plr_predist = ones(1,11)*0.035;
delta_pm_predist = ones(1,10) * (1-2*sum(delta_plr_predist))/10;
delta_p_predist = [delta_plr_predist delta_pm_predist delta_plr_predist];
p_predist = [0 cumsum(delta_p_predist)];
phi_predist = atan((1-p_predist)./p_predist);


subplot(2,2,1)
plot(phi/pi*180, p_ideal, 'ro-', LineWidth=3)
hold on
plot(phi_lin/pi*180, p_lin, 'bs-', LineWidth=3)
grid on; legend('ideal', 'linear', fontsize=12)
xlabel('Phase'); ylabel('p')

subplot(2,2,2)
plot(phi(1:end-1)/pi*180, delta_p_ideal, 'ro-', LineWidth=3)
hold on
plot(phi_lin(1:end-1)/pi*180, delta_p_lin, 'bs-', LineWidth=3)
plot(phi_predist(1:end-1)/pi*180, delta_p_predist, 'gd-', LineWidth=3)
grid on; legend('ideal', 'linear', 'predistortion', fontsize=12)
xlabel('Phase'); ylabel('\Delta p')

subplot(2,2, [3,4])

plot(0:1:32, phi/pi*180, 'ro-', LineWidth=3)
hold on
plot(0:1:32, phi_lin/pi*180, 'bs-', LineWidth=3)
plot(0:1:32, phi_predist/pi*180, 'gd-', LineWidth=3)
grid on; legend('ideal', 'linear', 'predistortion', fontsize=12)
xlabel('code p'); ylabel('Phase')

Eight-Quadrant PI

\[\begin{align} V_o(t) &= m \cdot \sin(\omega t + \frac{\pi}{4}) + p\cdot \sin(\omega t) = \frac{\sqrt{2}}{2}m\cdot \cos(\omega t) + \left( \frac{\sqrt{2}}{2}m + p\right)\cdot \sin(\omega t) \\ &= \sqrt{m^2 + p^2 +\sqrt{2}pm}\cdot \sin(\omega t + \phi) \end{align}\]

where \(\tan\phi = \frac{\sqrt{2}m}{\sqrt{2}m+2p} = \frac{\sqrt{2}-\sqrt{2}p}{\sqrt{2}+(2-\sqrt{2})p}\)

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phi = (16:-1:0)./16*pi/4;
p_ideal = 2^0.5*(1-tan(phi))./(2*tan(phi)+2^0.5*(1-tan(phi)));
delta_p_ideal = abs(p_ideal(1:end-1) - p_ideal(2:end));
phi_ideal = atan((2^0.5 - 2^0.5*p_ideal)./(2^0.5 + (2-2^0.5)*p_ideal));


p_lin = (0:1:16)/16;
phi_lin = atan((2^0.5 - 2^0.5*p_lin)./(2^0.5 + (2-2^0.5)*p_lin));
delta_p_lin = abs(p_lin(1:end-1) - p_lin(2:end));


delta_plr_predist = ones(1,4)*0.066;
delta_pm_predist = ones(1,8) * (1-2*sum(delta_plr_predist))/8;
delta_p_predist = [delta_plr_predist delta_pm_predist delta_plr_predist];
p_predist = [0 cumsum(delta_p_predist)];
phi_predist = atan((2^0.5 - 2^0.5*p_predist)./(2^0.5 + (2-2^0.5)*p_predist));


subplot(2,2,1)
plot(phi/pi*180, p_ideal, 'ro-', LineWidth=3)
hold on
plot(phi_lin/pi*180, p_lin, 'bs-', LineWidth=3)
grid on; legend('ideal', 'linear', fontsize=12)
xlabel('Phase'); ylabel('p')

subplot(2,2,2)
plot(phi(1:end-1)/pi*180, delta_p_ideal, 'ro-', LineWidth=3)
hold on
plot(phi_lin(1:end-1)/pi*180, delta_p_lin, 'bs-', LineWidth=3)
plot(phi_predist(1:end-1)/pi*180, delta_p_predist, 'gd-', LineWidth=3)
grid on; legend('ideal', 'linear', 'predistortion', fontsize=12)
xlabel('Phase'); ylabel('\Delta p')

subplot(2,2, [3,4])

plot(0:1:16, phi/pi*180, 'ro-', LineWidth=3)
hold on
plot(0:1:16, phi_lin/pi*180, 'bs-', LineWidth=3)
plot(0:1:16, phi_predist/pi*180, 'gd-', LineWidth=3)
grid on; legend('ideal', 'linear', 'predistortion', fontsize=12)
xlabel('code p'); ylabel('Phase')

Predistortion - square wave

Weinlader, Daniel, Thomas H. Lee and James A. Gasbarro. "Precision CMOS receivers for VLSI testing applications." (2001). [https://www-vlsi.stanford.edu/people/alum/pdf/0111_Weinlader_Precision_CMOS_Receivers_.pdf]

Suppose \(V_i(t) = 1- e^{-\frac{t}{\tau}}\) and \(V_q(t) = 1-e^{-\frac{t-\Delta t}{\tau}}\) with \(t\ge \Delta t\) \[ \frac{1}{2} = (1-\alpha)\cdot V_i(t) + \alpha \cdot V_q(t) \] yield triggering time \[ t = \tau \ln\left[ 1 + \alpha \left(e^{\frac{\Delta t}{\tau}}-1\right)\right] + \tau \ln 2 \] Then \[\begin{align} \frac{\partial t}{\partial \alpha} &= \tau \frac{e^{\frac{\Delta t}{\tau }}-1}{1+\alpha(e^{\frac{\Delta t}{t}}-1)} \gt 0 \\ \frac{\partial^2 t}{\partial \alpha^2} &= -\tau \frac{\left(e^{\frac{\Delta t}{\tau }}-1\right)^2}{\left(1+\alpha(e^{\frac{\Delta t}{t}}-1)\right)^2} \lt 0 \end{align}\]

As a conclusion, heavier weight while \(\alpha\) approaching to 1 in order to improve linearity

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import numpy as np
import matplotlib.pyplot as plt

tau = 15  # ps
t = np.linspace(6, 56, 500001)

vi = 1- np.exp(-t/tau)
vq = 1 - np.exp(-(t-6)/tau)	# \Detla t = 6

td = []
alpha_list = np.linspace(0, 101, 101,  endpoint=False)/100

plt.figure(figsize=(20,8))
plt.subplot(1, 3, 1)
for alpha in alpha_list:
    viq = (1-alpha) * vi + alpha*vq
    differences  = np.abs((viq - 0.5))
    closest_index = np.argmin(differences)
    t_closest = t[closest_index]
    td.append(t_closest)
    plt.plot(t,viq)
plt.plot([0, 60], [0.5,0.5], '--c', linewidth=3); plt.grid()
plt.xlabel('t', fontsize=14); plt.ylabel('Voltage', fontsize=14)

td = np.array(td) - td[0]
d_td = td[1:] - td[:-1]

plt.subplot(1, 3, 2)
plt.plot(alpha_list, td, 'ro-', linewidth=2)
plt.grid(); plt.xlabel(r'$\alpha$', fontsize=14); plt.ylabel(r'$t_d$', fontsize=14)

plt.subplot(1, 3, 3)
plt.plot(alpha_list[:-1], d_td, 'bo-')
plt.grid(); plt.xlabel(r'$\alpha$', fontsize=14); plt.ylabel(r'$\Delta t_d$', fontsize=14)

plt.show()

Input/Output amplitude

A constant Output amplitude is desired because the swing-dependent delay characteristic of the CML-to-CMOS (C2C) circuit results in AM–PM distortion which eventually manifests as phase nonlinearity

Current-Mode Phase Interpolator

Voltage-Mode Phase Interpolator

Integrating-Mode Phase Interpolator

PI vs. PLL based CDR

PCI Express Jitter Modeling Revision 1.0RD July 14, 2004

reference

A. K. Mishra, Y. Li, P. Agarwal and S. Shekhar, "Improving Linearity in CMOS Phase Interpolators," in IEEE Journal of Solid-State Circuits, vol. 58, no. 6, pp. 1623-1635, June 2023 [pdf]

Cortiula A, Menin D, Bandiziol A, Driussi F, Palestri P. Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces. Electronics. 2025; [https://www.mdpi.com/2079-9292/14/10/1979]

G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/document/10184121]

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 4, pp. 6-10, Fall 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf]

Metastability is an undesirable non-equilibrium electronic state that can persist for a long period of time

Poisson stochastic process

Synchronizer effect – latency uncertainty

simulation of DFF

The typical flip-flops comprise master and slave latches and decoupling inverters.

In metastability, the voltage levels of nodes A and B of the master latch are roughly midway between logic 1 (VDD) and 0 (GND)

master latch enter metastability

In fact, one popular definition says that if the output of a flip-flop changes later than the nominal clock-to-Q propagation delay, then the flip-flop must have been metastable

sweep \(\Delta t_{D \to \space \text{CK}}\)

transient noise analysis @ \(\Delta t_{D \to \space \text{CK}} = -3.444525p\)

zoom out

Noise Seed—Seed for the random number generator (used by the simulator to vary the noise sources internally). Specifying the same seed allows you to reproduce a previous experiment. The default value is 1.

reference

Yvain Thonnart, CEA-LIST. ISSCC2021 T8: On-Chip Interconnects: Basic Concepts, Designs and Future Opportunities [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T8.pdf]

R. Ginosar, "Metastability and Synchronizers: A Tutorial," in IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23-35, Sept.-Oct. 2011 [https://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf]

Amr Adel Mohammady. Clock Domain Crossing [linkedin]

Steve Golson. Synchronization and Metastability [https://trilobyte.com/pdf/golson_snug14.pdf]

Kinniment, D. J. Synchronization and arbitration in digital systems. John Wiley & Sons Ltd (2007).

Synchronizers And Data FlipFlops are Different [pdf]

S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The Devolution of Synchronizers," 2010 IEEE Symposium on Asynchronous Circuits and Systems, Grenoble, France, 2010 [pdf]

赵启林 klin, Metastability [https://picture.iczhiku.com/resource/eetop/SHKSFADwZerLPBXN.pdf]

Asad Abidi. ISSCC 2023: Circuit Insights "The CMOS Latch" [https://youtu.be/sVe3VUTNb4Q&t=681]

Matt Venn. Interactive flip flop simulation [https://github.com/mattvenn/flipflop_demo]

Jitter Performance Limitations

Aliasing of baud-rate sampling

The most significant impairments are considered to be the sensitivity to sampling phase, and the effect of aliasing out of band signal and noise into the baseband

Tao Gui (Huawei), etc.. IEEE 802.3dj May Interim meeting San Antonio, Texas May 15, 2013: "Feasibility Study on Baud-Rate Sampling and Equalization (BRSE) for 800G-LR1" [https://www.ieee802.org/3/dj/public/23_05/gui_3dj_01a_2305.pdf]

D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J. Savory, "A baud-rate sampled coherent transceiver with digital pulse shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]

Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]

Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]

reference

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

Jhwan Kim, CICC 2022, ES4-4: Transmitter Design for High-speed Serial Data Communications

Friedel Gerfers, ISSCC2021 T6: Basics of DAC-based Wireline Transmitters [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T6.pdf]

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

Tony Pialis, Alphawave Semi. How DSP is Killing the Analog in SerDes [https://youtu.be/OY2Dn4EDPiA?si=q2Qy_avTIxJjDdOf]

Tony Chan Carusone, Alphawave Semi. High Speed Communications Part 3 – Equalization & MLSD [https://youtu.be/KqwZ23vNqYg?si=pqMFWVVUOrAVhkeU]

—. High Speed Communications Part 9 – Anatomy of a Modern SerDes [https://youtu.be/tlc68UTn6iQ?si=ZkqAy3INlA3Vr8Y7]

—. High Speed Communications Part 10 – 224Gbps Link Impairments [https://youtu.be/m-Msp_2WGAg?si=n5lgrxiz24K7x66a]

—. High Speed Communications Part 11 – SerDes DSP Interactions [https://youtu.be/YIAwLskuVPc?si=1HWB0yA2u2jiixNZ]

ADC ENOB

Dan Boschen, GRCon25: Quantifying Signal Quality: Practical Tools for High-Fidelity Waveform Analysis

[linkedin GRCon25]

decimation filter

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/First_Order_DS_ADC_scan1.pdf]

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/First_Order_DS_ADC_scan2.pdf]

The combination of the the digital post-filter and downsampler is called the decimation filter or decimator

\(\text{sinc}\) filter

Suppose \(T=1\) \[ H_1(e^{j2\pi f}) = \frac{\text{sinc}(Nf)}{\text{sinc}(f)} = \frac{1}{N}\frac{\sin(\pi Nf)}{\sin(\pi f)} \] that is \(\lim_{f\to 0^+}H_1(e^{j2\pi f}) = 1\) and \(H_1 = 0\) when \(f=\frac{n}{N}, n\in \mathbb{Z}\)

A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

\[ |H_1(\omega)|^2 = \left|\frac{1}{N}(1-e^{-j\omega N}) \right| = \frac{2}{N^2}(1-\cos (\omega N)) \] Total noise after \(H_1\) \[ \sigma_{q_1}^2 = 2\int_0^\pi \frac{e^2_{rms}}{2\pi}\cdot |H_1(\omega)|^2d\omega = \frac{2e^2_{rms}}{N^2} \] inband noise before \(H_1\), i.e. ideal LPF with cutoff frequency \(\frac{\pi}{N}\) \[ \sigma_{q_0}^2 = 2\int_0^{\pi/N}\frac{e_{rms}^2}{2\pi}|1-e^{-j\omega}|^2d\omega = \frac{2e_{rms}^2}{\pi}\left(\frac{\pi}{N}-\sin\frac{\pi}{N}\right) \] with Taylor series \(\sin\frac{\pi}{N}\approx \frac{\pi}{N}-\frac{1}{6}\frac{\pi^3}{N^3}\) \[ \sigma_{q_0}^2 \approx \frac{\pi^2}{3N^3}e_{rms}^2 \]

Taylor’s Series of \(\sin x\) [pdf]

[https://analogicus.com/aic2025/2025/02/20/Lecture-6-Oversampling-and-Sigma-Delta-ADCs.html#python-oversample]

\(\text{sinc}^2\) filter

interpolation filter

Notice that the requirements of the first stage are very demanding

replicas suppression

The spectrum of the high resolution digital signal \(u_1\) contains the original baseband portion and its replicas located at integer multiples of \(f_{s1}\), plus a small amount of quantization noise shown as a solid line

Nigel Redmon [https://dsp.stackexchange.com/a/63438/59253]

Inserting zeros changes nothing except what we consider the sample rate

Dan Boschen [https://dsp.stackexchange.com/a/32130/59253]

Bourdopoulos, G. I. (2003). Delta-Sigma modulators : modeling, design and applications. Imperial College Press. [pdf]

DC Gain in Interpolation Filtering

[https://raytroop.github.io/2025/06/21/data-converter-in-action/#dac-zoh]

DC gain is used to compensate the ratio of sampling rate before and after upsample

Given \[ X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i} \] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)

Employ definition of DTFT, \(X(e^{j\hat{\omega}}) =\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set \(\hat{\omega} = 0\) \[ X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n] \] That is, \(\sum_{n=-\infty}^{+\infty}x[n] = \sum_{n=-\infty}^{+\infty}x_e[n]\), so \[ \overline{x_e[n]} = \frac{1}{L} \overline{x[n]} \] It also indicate that dc gain of upsampling is \(1/L\)

ZOH

Zero-Order Hold (ZOH)

dc gain = \(N\)

FOH

First-Order Hold (FOH)

dc gain = \(N\)

reference

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

—, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, Modeling Anti-Alias Filters [https://www.dsprelated.com/showarticle/1418.php]

—, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Arash Loloee, Ph.D. Exploring Decimation Filters [https://www.highfrequencyelectronics.com/Archives/Nov13/1311_HFE_decimationFilters.pdf]

Venkatesh Srinivasan, ISSCC 2019 T5: Noise Shaping in Data Converters

Nan Sun,IEEE CAS 2020: Break the kT/C Noise Limit [https://www.facebook.com/ieeecas/videos/break-the-ktc-noise-limit/322899188976197/]

Yun-Shiang Shu, ISSCC 2022 T3: Noise-Shaping SAR ADCs

Xiyuan Tang, CICC 2025 ES2-1: Noise-Shaping SAR ADCs - From Fundamentals to Recent Advances

Qasim Chaudhari. On Analog-to-Digital Converter (ADC), 6 dB SNR Gain per Bit, Oversampling and Undersampling [https://wirelesspi.com/on-analog-to-digital-converter-adc-6-db-snr-gain-per-bit-oversampling-and-undersampling/]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

Dual Slope ADC

\[ V_{IN} = \frac{V_{REF}}{T}t_\text{x} = \frac{V_{REF}}{2^N}\cdot 2^{N_\text{x}} \]

Normal Mode Rejection

a high normal mode rejection ratio (NMRR) for input noise at line frequency

• Conversion accuracy is independent of both the capacitance and the clock frequency, because they affect both the up-slope and the down-slope by the same ratio

• The fixed input signal integration period results in rejection of noise frequencies on the analog input that have periods that are equal to or a sub-multiple of the integration time \(T\)

  Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (\(1/T\)) averaged over a period (\(T\)) is zero

Linear Circuit Design Handbook, 2008 [https://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter6.pdf]

Precision Analog Front Ends with Dual Slope ADC [https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/21428e.pdf]

Incremental ADC

\[\begin{align} V &= 2^N V_\text{in} - D_\text{out}V_\text{ref} \\ D_\text{out} \frac{V_\text{ref}}{2^N} &= V_\text{in} - \frac{V}{2^N} \end{align}\]

feedforward structure

??? TODO 📅

Temperature Sensor

Calibration

[https://ww1.microchip.com/downloads/en/Appnotes/Atmel-8108-Calibration-of-the-AVRs-Internal-Temperature-Reference_ApplicationNote_AVR122.pdf]

TODO 📅

\(V_{BE}\) curvature

curvature results in results in non-linearity

Though it is assumed that \(V_{BE}\) is a linear function of temperature for first oder analysis.

In practice, \(V_{BE}\) is slightly nonlinear, the magnitude of this nonlinearity is referred to as curvature.

curvature depends on the temperature dependency of the saturation current (\(I_s\)), and on that of the collector current (\(I_c\)), it can be written as \[ V_{curv}(T)=\frac{k}{q}(\eta-\delta)(T-T_r-T\cdot \ln(\frac{T}{T_r})) \] where \(\eta\) = a constant depending on the doping level, CMOS substrate pnp transistors have a typically value of \(\eta \cong 4\)

\(\delta\) = order of the temperature dependence of collector current (\(I_c\))

PTAT \(I_c\) help reduce \(V_{curv}(T)\), \(\delta=1\)

Although the temperature dependence of the bias current \(I_b\) doesn’t impact the accuracy of \(V_{BE}\), it does impact the systematic nonlinearity or curvature of \(V_{BE}\), and hence the sensor's systematic error. The curvature in \(V_{BE}\) can be reduced by using a PTAT bias current.

PTAT bias current

\[ I_{bias} = \frac{0.7}{\beta \cdot R^2} \] in which \(\beta=\frac{\mu_{n}\cdot C_{ox}\cdot W}{L}\), where:

\(\mu_n\)=mobility,

\(C_{ox}\) = oxide capacitance density,

\(\frac{W}{L}\) = dimension ratio of unit NMOS used for \(M_1\) and \(M_2\)

\(\mu_n\) is complementary to the absolute temperature and resitor R is implemented using high-R flow in FinFET which has a low temperature dependency, the net temperature dependency of \(I_{bias}\) is proportional to the absolute temperature \[ I_{bias}\propto T \]

Kamath, Umanath Ramachandra. "BJT Based Precision Voltage Reference in FinFET Technology." (2021).

Errors due to V-I Finite Gain

Finite gain introduces errors both in the V-I converters, finite loop gain results in errors in the closed-loop transconductances.

\[\begin{align} (V_{i1} - V_{o1})\cdot A_{OL1} &= V_{o1} \\ V_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}V_{i1} \\ I_{o1} &= \frac{A_{OL1}}{1+A_{OL1}}\frac{1}{R_1}V_{i1} \end{align}\] similarly, \[ I_{o2} = \frac{A_{OL2}}{1+A_{OL2}}\frac{1}{R_2}V_{i2} \]

Then, \(\alpha\) is obtained \[ \alpha = \frac{(1+A_{OL2})A_{OL1}}{A_{OL2}(1+A_{OL1})}\cdot\frac{R_2}{R_1} \] Since the loop gains in the two V-I converters cannot be expected to match, the resulting errors in both converters should be reduced to negligible levels.

First, assume \(A_{OL2}=\infty\) \[\begin{align} \Delta \alpha &= (1-\frac{A_{OL1}}{1+A_{OL1}})\cdot\frac{R_2}{R_1}\\ &=\frac{1}{1+A_{OL1}}\cdot\frac{R_2}{R_1}\\ &\cong \frac{1}{A_{OL1}}\cdot\frac{R_2}{R_1} \end{align}\]

We get \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL1}} \] Follow the same procedure, assume \(A_{OL1}=\infty\) \[ \frac{\Delta \alpha}{\alpha}=\frac{1}{A_{OL2}} \] The finite gain introduces an error inversely proportional to the loop gain \(A_{OL1}\),\(A_{OL2}\), the resulting errors in both converters should be reduced to negligible levels

Why named as "bandgap reference"

Let us write the output voltage as \[ V_{REF} = V_{BE} + V_T\cdot \ln n \] and hence \[ \frac{\partial V_{REF}}{\partial T} = \frac{\partial V_{BE}}{\partial T} + \frac{V_T}{T}\ln n \] Setting this to zero and substituting for \(\frac{\partial V_{BE}}{\partial T}\), we have \[ \frac{V_{BE}-(4+m)V_T-E_g/q}{T}=-\frac{V_T}{T}\ln n \] If \(V_T\ln n\) is found from this equation and inserted in \(V_{REF}\), we obtain \[ V_{REF}=\frac{E_g}{q} + (4+m)V_T \]

The term bandgap is used here because as \(T\to 0\), \(V_{REF} \to E_g/q\)

sinking PTAT-current generator without current mirrors

why without current mirror?

Bakker, Anton. (2000). High-Accuracy CMOS Smart Temperature Sensors. 10.1007/978-1-4757-3190-3. [https://repository.tudelft.nl/record/uuid:fd398056-48dd-4d84-8ae8-27a1b011d2c3]

Readout Circuit

ADC dynamic range

Take \(V_{PTAT}=\alpha \cdot \Delta V_{BE}\) as input and \(V_{REF}\) as reference. The output \(\mu\) of the ADC will then be \[ \mu =\frac{V_{PTAT}}{V_{VREF}}=\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] A final digital output \(D_{out}\) in degrees Celsius can be obtained by linear scaling: \[ D_{out}=A\cdot \mu + B \] where \(A\simeq 600K\) and \(B\simeq -273K\)

While the transfer is simple, it only uses about 30% of the of the ADC (the extremes of the operating range correspond to \(\mu \simeq 1/3\) and \(\mu \simeq 2/3\)). The ratio results in a rather inefficient use of the modulator's dynamic range.

For a first-order \(\Sigma\Delta\) modulator, this means that about 1.5 bits of resolution are lost

A more efficient transfer is \[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \] With this more efficient combination, 90% of the dynamic range is used rather than 30%. Thus, the required resolution of the ADC is reduced by a factor of three.

Integrator Output Swing

\[ \mu =\frac{\alpha \cdot \Delta V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

\[ \mu '=\frac{2\alpha \cdot \Delta V_{BE}-V_{BE}}{V_{BE}+\alpha \cdot \Delta V_{BE}} \]

In advanced process, like Finfet 16nm, 7nm, high resistance resistor has +/-15% variation and MOM capacitor has +/-30% variation.

Then, \(R_1\) and \(R_2\) not only determine the \(\alpha\) but also the integrator's output swing, so do \(V_{BE}\) and \(\Delta V_{BE}\), \(C_{int}\).

The integrator's output change per period

integrator, comparator offset

integrator offset

comparator offset

integrator design

application in sensor

Offset Errors

The offset of opamp \(A_3\) is much less critical:

1. It affects the integrated currents via the finite output impedances \(R_{out1,2}\) of the V-I converters, and is therefore attenuated by a factor \(R_{out1}/R_1\) when referred back to the input of the sinking V-I converter,

2. or by a factor \(R_{out2}/R_2\) when referred back to the input of the sourcing V-I converter.

Therefore, no special offset cancellation is needed for opamp \(A_3\).

The current change due to offset of \(A_3\): \[\begin{align} \frac{V_{BE,os}}{R_1} &= \frac{V_{ota,os}}{R_{out1}} \\ \frac{\Delta V_{BE,os}}{R_2} &= \frac{V_{ota,os}}{R_{out2}} \end{align}\] Then, the input referenced offset is: \[\begin{align} V_{BE,os} &=\frac{ V_{ota,os}}{R_{out1}/R_1} \\ \Delta V_{BE,os} &= \frac{ V_{ota,os}}{R_{out2}/R_2} \end{align}\]

Errors due to Finite Gain

Finite gain of opamp \(A_3\) results in a non-zero overdrive voltage at its input, which modulates the current Iint due to the finite output impedances of the V-I converters.

Assuming the opamp is implemented as a transconductance amplifier, there are two main causes of this non-zero overdrive voltage

1. The finite transconductance \(g_{m3}\) of the opamp, , which implies that an overdrive voltage is required to provide the feedback current

​ The change in the integrated current

​ \[\begin{align} ​ \Delta I_{int} &= \frac{V_{i,ota}}{R_{out}}\\ ​ &= \frac{I_{int}}{g_{m3}}\cdot \frac{1}{R_{out}} ​ \end{align}\]

2. The finite DC gain \(A_{0,3}\), which implies that an overdrive voltage is required to produce the output voltage \(V_{int}\)

reference

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA]

Maurits Ortmanns , Paul Kaesser , Johannes Wagner (Dec 2025). Incremental Delta-Sigma ADCs Theory, Architectures and Design - Theory, Architectures and Design

temperature sensor

Micheal, A., P., Pertijs., Johan, H., Huijsing., Pertijs., Johan, H., Huijsing. (2006). Precision Temperature Sensors in CMOS Technology.

C. -H. Chang, J. -J. Horng, A. Kundu, C. -C. Chang and Y. -C. Peng, "An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, pp. 165-168, doi: 10.1109/ASSCC.2014.7008886.

EE247 - Analog Digital Interface Integrated Circuits - Fall 2009 Lecture 24- Oversampled ADCs

Hecht, Bruce. (2010). SSCS DL Kofi Makinwa Talks About Smart Sensor Design at SSCS-Boston [People]. Solid-State Circuits Magazine, IEEE. 2. 54 - 56. 10.1109/MSSC.2009.935278.