KNOW-HOW

ISSCC.2024 7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS

[7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS https://www.bilibili.com/video/BV18hYCe7E45/?share_source=copy_web&vd_source=5a095c2d604a5d4392ea78fa2bbc7249]

ISSCC.2018 6.4 A Fully Adaptive 19-to-56Gb/s PAM-4 Wireline Transceiver with a Configurable ADC in 16nm FinFET

[https://sci-hub.st/10.1109/ISSCC.2018.8310207]

M. S. Jalali, A. Sheikholeslami, M. Kibune and H. Tamura, "A Reference-Less Single-Loop Half-Rate Binary CDR," in IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2037-2047, Sept. 2015 [https://www.eecg.utoronto.ca/~ali/papers/jssc2015-09.pdf]

Sigma-Delta DAC

Sigma-delta digital-to-analog converters (SD DAC’s) are often used for discrete-time signals with sample rate much higher than their bandwidth

• Because of the high sample rate relative to signal bandwidth, a very simple DAC reconstruction filter (Analog lowpass filter) suffices, often just a one-pole RC lowpass

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R= 4.7e3;                 % ohms resistor value
C= .01e-6;                % F capacitor value
fs= 1e6;                  % Hz DAC sample rate
% input signal
x= [zeros(1,20) .9*ones(1,200) .1*ones(1,200)];
% find output y of SD DAC and output y_filt of RC filter
[y,y_filt]= sd_dacRC(x,R,C,fs);

t = linspace(0,length(x)-1, length(x))*1/fs*1e3;
subplot(3,1,1)
plot(t, x, '.'); title('x'); grid on
subplot(3,1,2)
plot(t, y, '.'); title('y'); grid on
subplot(3,1,3)
plot(t, y_filt); title('y_{filt}'); xlabel('t(ms)'); grid on

Appendix

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% https://www.dsprelated.com/showarticle/1642.php
% Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter

% function [y,y_filt] = sd_dacRC(x,R,C,fs)  2/5/24 Neil Robertson
% 1-bit sigma-delta DAC with RC filter
% Model does not include a zero-order hold.
%
% x = input signal vector, 0 <= x < 1
% R = series resistor value, Ohms.  Normally R > 1000 for 3.3 V logic.
% C = shunt capacitor value, Farads
% fs = sample frequency, Hz
% y = DAC output signal vector, y(n) = 0 or 1
% y_filt = RC filter output signal vector
%
function [y,y_filt] = sd_dacRC(x,R,C,fs)
N= length(x);
x= fix(x*2^16)/2^16;        % quantize x to 16 bits
%I 1-bit Sigma-delta DAC
s= [x(1) zeros(1,N-1)];
for n= 2:N
    u= x(n) + s(n-1);
    s(n)= mod(u,1);        % sum
    y(n)= fix(u);          % carry
end

%II One-pole RC filter model
% Matched z-Transform https://ocw.mit.edu/courses/2-161-signal-processing-continuous-and-discrete-fall-2008/cc00ac6d468dc9dcf2238fc1d1a194d4_lecture_19.pdf
Ts= 1/fs;
Wc= 1/(R*C);               % rad -3 dB frequency
fc= Wc/(2*pi);             % Hz -3 dB frequency
a1= -exp(-Wc*Ts);
b0= 1 + a1;                % numerator coefficient
a= [1 a1];                 % denominator coeffs
y_filt= filter(b0,a,y);    % filter the DAC's output signal y

reference

Dan Boschen. sigma delta modulator for DAC [https://dsp.stackexchange.com/a/88357/59253]

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

—, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, Modeling Anti-Alias Filters [https://www.dsprelated.com/showarticle/1418.php]

—, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Jason Sachs. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

Woogeun Rhee. ISCAS 2019 Mini Tutorials: Single-Bit Delta-Sigma Modulation Techniques for Robust Wireless Systems [https://youtu.be/OEyTM4-_OyA?si=vllJ5Pe8I3lqb_Vl]

Dual Slope ADC

\[ V_{IN} = \frac{V_{REF}}{T}t_\text{x} = \frac{V_{REF}}{2^N}\cdot 2^{N_\text{x}} \]

Normal Mode Rejection

a high normal mode rejection ratio (NMRR) for input noise at line frequency

• Conversion accuracy is independent of both the capacitance and the clock frequency, because they affect both the up-slope and the down-slope by the same ratio

• The fixed input signal integration period results in rejection of noise frequencies on the analog input that have periods that are equal to or a sub-multiple of the integration time \(T\)

  Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (\(1/T\)) averaged over a period (\(T\)) is zero

Linear Circuit Design Handbook, 2008 [https://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter6.pdf]

Precision Analog Front Ends with Dual Slope ADC [https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/21428e.pdf]

Incremental ADC

\[\begin{align} V &= 2^N V_\text{in} - D_\text{out}V_\text{ref} \\ D_\text{out} \frac{V_\text{ref}}{2^N} &= V_\text{in} - \frac{V}{2^N} \end{align}\]

feedforward structure

??? TODO 📅

Discrete-Time Integrators

Delaying Integrator

Delay-free Integrator

reference

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA?si=_pGb18rhsMUZ-lAf]

Interleaver

Direct Interleaver

similar to increase the resolution of the flash ADC with more parallel comparators

De-multiplexing Interleaver

it is the front-end samplers that determine timing/bandwidth mismatch errors

Re-sampling Interleaver

back-end re-sampling occur after the front-end, two \(\frac{KT}{C}\) contribution in total noise (De-multiplexing Interleaver only one \(\frac{KT}{C}\))

without buffer, charging distribution reduce signal and reduce SNR, but buffers give excess noise

Interleaver Model

Interleaving Errors

Offset Mismatch Error

Gain Mismatch Error

Timing Mismatch Error

\(\pi/2\)-rad phase: the maximum error occurs at the zero crossing and not on the peaks (Gain Mismatch error)

Frequency-dependent: the higher frequency input signal \(f_\text{in}\), the larger error becomes

\(\pi/2\) phase shift \[ e^{j\pi/2} = j \] frequency-dependent \[ V^{'} \propto f \]

In time domain \[ \frac{d\sin(\omega t)}{dt} = \omega \cos(\omega t) \propto \omega \]

Bandwidth Mismatch Errors

Overlapping versus Non-overlapping track time

tracking accuracy stay same, Cin (2Cs) counteract the longer tracking

reference

John P. Keane, ISSCC2020 T5: "Fundamentals of Time-Interleaved ADCs" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T5Visuals.pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

ISSCC2015 F1: High-Speed Interleaved ADCs [https://picture.iczhiku.com/resource/eetop/wykrheUfrWasiMVX.pdf]

Poulton, Ken. ISSCC2015 "Interleaved ADCs Through the Ages", (slides)

Poulton, Ken. CICC2010 "GHz ADCs: From Exotic to Mainstream", tutorial session, (slides)

Poulton, Ken. ISSCC2009 "Time-Interleaved ADCs, Past and Future" (slides)

Athanasios Ramkaj. January 26, 2022, IEEE SSCS Santa Clara Valley Section Technical Talk: Design Considerations Towards Optimal High-Resolution Wide-Bandwidth Time-Interleaved ADCs [https://youtu.be/k3jY9NtfYlY?si=K9AdT9QzGxOnI5WG]

Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]

S. Jang, J. Lee, Y. Choi, D. Kim, and G. Kim, "Recent advances in ultra-high-speed wireline receivers with ADC-DSP-based equalizers," IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), vol. 4, pp. 290-304, Nov. 2024.

Yida Duan. Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters (ADCs) [http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-10.pdf]

Preview Lecture #1 - "Extreme SAR ADCs" Online Course (2024) - Prof. Chi-Hang Chan (U. of Macau) [https://youtu.be/rgMRL4QZ-wA?si=gvJGFrcsrHS8b_mN]

VGA/attenuator: ensure a constant swing at the slicer input regardless of the channel variation

Input network

1 2 3 4 5

>> 10e6/2/pi/400/50 ans = 79.5775

charging parasitic from CTLE + CTLE is signal processing, bypass the capacitor is not feasiable

Inductive Peaking

TODO 📅

series peaking: capacitive splitting - split the load capacitance between the amplifier drain capacitance and the next stage gate capacitance

S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension Techniques for CMOS Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006 [https://people.engr.tamu.edu/spalermo/ecen689_oi/2006_passive_bw_extension_techniques_shekhar_jssc.pdf]

CTLE Linearity

TODO 📅

DFE Error Propagation

TODO 📅

Geoff Zhang. Preliminary Studies on DFE Error Propagation, Precoding, and their Impact on KP4 FEC Performance for PAM4 Signaling Systems [https://www.ieee802.org/3/ck/public/18_09/zhang_3ck_01a_0918.pdf]

CTLE transfer function

Circuit Insights @ ISSCC2025: Circuits for Wireline Communications - Kevin Zheng [https://youtu.be/8NZl81Dj45M?si=J11oGnXnkJYPUi2n&t=1045]

DFE architecture

Extensive work on DFEs has produced a multitude of architectures, which can be broadly categorized as "direct"" or "unrolled" (speculative) DFEs with "full-rate" or "half-rate" clocking

S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for 20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]

S. Ibrahim and B. Razavi, Low-Power DFE Design [https://picture.iczhiku.com/resource/eetop/wykflwIuIQDzYNcB.PDF]

PAM4 DFE

K. -C. Chen, W. W. -T. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 750-762, March 2021 [https://www.mics.caltech.edu/wp-content/uploads/2021/02/JSSC-2020-Xavier-PAM4-Receiver.pdf]

Hongtao Zhang, DesignCon 2016. PAM4 Signaling for 56G Serial Link Applications − A Tutorial [https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

reference

Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg?si=Or-rIUZ-nnygRbQv]

H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025

CML vs. SST based driver

Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

the resistance of MOS is not highly controlled -> \(R_T + Z_N\)

Peak power constraint of TX FIR

Due to circuit limitation, circuit cannot have arbitrarily large voltage on the output, i.e. a limited maximum swing. In order to create the high frequency shape, the best we can do is lower DC gain (low frequency gain < 1)

• FIR is not increasing the amplitude on the edges
• FIR is reducing the inner eye diagram

The maximum swing stays the same, \(\sum_i |c_i|=1\)

Circuit Insights @ ISSCC2025: Circuits for Wireline Communications - Kevin Zheng [https://youtu.be/8NZl81Dj45M?si=2a8FdfGNP6yBgIW8&t=829]

SST Driver

sharing termination in SST transmitter

Sharing termination keep a constant current through leg, which improve TX speed in this way. On the other hand, the sharing termination facilitate drain/source sharing technique in layout.

pull-up and pull-down resistor

Original stacked structure

Pro's:

​ smaller static current when both pull up and pull down path is on

Con's:

​ slowly switching due to parasitic capacitance behind pull-up and pull-down resistor

with single shared linearization resistor

Pro's:

​ The parasitic capacitance behind the resistor still exists but is now always driven high or low actively

Con's:

​ more static current

VM Driver Equalization - differential ended termination

\[ V_o = D_{n+1}C_{-1}+D_nC_0+D_{n-1}C_{+1} \]

where \(D_n \in \{-1, 1\}\)

\[ V_{\text{rx}} = V_{\text{dd}} \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \] With \(R_u=(L+M+N)R_T\)

Normalize above equation, obtain \[ V_{\text{rx,norm}} = \frac{(R_2-R_1)R_T}{R_1R_T+R_2R_T+R_1R_2} \]

Where precursor \(R_L = L\times R_T\), main cursor \(R_M = M\times R_T\) and post cursor \(R_N = N\times R_T\)

Equation-1

\(D_{n-1}D_nD_{n+1}=1,-1,-1\)

\[\begin{align} R_1 &= R_N \\ &= \frac{R_u}{N} \\ R_2 &= R_L\parallel R_M \\ &= \frac{R_u}{L+M} \end{align}\]

We obtain \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \]

Equation-2

\(D_{n-1}D_nD_{n+1}=-1,1,-1\)

with \(R_1=R_T\) and \(R_2=+\infty\), we obtain \[ V_M = \frac{1}{2} \]

Equation-3

\(D_{n-1}D_nD_{n+1}=-1,-1,1\)

\[\begin{align} R_1 &= R_L \\ &= \frac{R_u}{L} \\ R_2 &= R_N\parallel R_M \\ &= \frac{R_u}{N+M} \end{align}\]

We obtain \[ V_N = \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

We define \[\begin{align} l &= \frac{L}{L+M+N} \\ m &= \frac{M}{L+M+N} \\ n &= \frac{N}{L+M+N} \end{align}\]

where \(l+m+n=1\)

Due to Eq1 ~ Eq3 \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = \frac{1}{2}(n-l-m) \\ -C_{-1}+C_0-C_1 & = \frac{1}{2} \\ -C_{-1}-C_0+C_1 & = \frac{1}{2}(l-n-m) \end{array} \right. \] After scaling, we get \[ \left\{ \begin{array}{cl} C_{-1}-C_0-C_1 & = -l-m+n \\ -C_{-1}+C_0-C_1 & = l+m+n \\ -C_{-1}-C_0+C_1 & = l-m-n \end{array} \right. \] Then, the relationship between FIR coefficients and legs is clear, i.e. \[\begin{align} C_{-1} &= -\frac{L}{L+M+N} \\ C_{0} &= \frac{M}{L+M+N} \\ C_{1} &= -\frac{N}{L+M+N} \end{align}\]

For example, \(C_{-1}=-0.1\), \(C_0=0.7\) and \(C_1=-0.2\) \[ H(z) = -0.1+0.7z^{-1}-0.2z^{-2} \]

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w = [-0.1, 0.7, -0.2];
Fs = 32e9;
[mag, w] = freqz(w, 1, [], Fs);
plot(w/1e9, abs(mag));
xlabel('Freq(GHz)');
ylabel('mag');
grid on;

VM Driver Equalization - single ended termination

Equation-1

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \cdot \frac{N}{L+M+N} \\ V_{\text{rxm}} &= \frac{1}{2} \cdot \frac{L+M}{L+M+N} \end{align}\] So \[ V_{L}= \frac{1}{2}\cdot\frac{N-(L+M)}{L+M+N} \] which is same with differential ended termination

Equation-2

\[\begin{align} V_{\text{rxp}} &= \frac{1}{2} \\ V_{\text{rxm}} &= 0 \end{align}\] So \[ V_{M}= \frac{1}{2} \] which is same with differential ended termination

Equation-3

\[ V_{N}= \frac{1}{2}\cdot\frac{L-(N+M)}{L+M+N} \]

Obtain FIR coefficients

Same with differential ended termination driver.

Basic Feed Forward Equalization Theory

Pre-cursor FFE can compensate phase distortion through the channel

Single-ended termination

Differential termination

TX Serializer

mux timing

divider latch timing

Two latches

PAM4 TX

Here, \(d_{\text{LSB}} \in \{-1, 1\}\), \(d_{\text{MSB}} \in \{-2, 2\}\) and \(d' \in \{ -3, -1, 1, 3 \}\)

Implementation-1 could potentially experience performance degradation due to

1. Clock skew, \(\Delta t\), could make the eye misaligned horizontally
2. Gain mismatch, \(\Delta G\), could cause eye nonlinearity
3. Bandwidth mismatch, \(\Delta f_{\text{BW}}\), could make the eye misaligned vertically

Typically, a 3-tap FIR (pre + main + post) TX de-emphasis is used

3-tap FIR results in \(4^3 = 64\) possible distinct signal levels

\[\begin{align} R_U^M \parallel R_D^M &= \frac{3R_T}{2}\\ R_U^L \parallel R_D^L &= 3R_T \end{align}\]

Thevenin Equivalent Circuit is

Which can be simpified as \[\begin{align} V_{\text{rx}} &= \frac{1}{2}(V_p - V_m) \\ &= \frac{1}{2}(\frac{2}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-1) \\ &=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2} \end{align}\]

The above eqations demonstrate that the output \(V_{\text{rx}}\) is the linear sum of MSB and LSB; LSB and MSB have relative weight, i.e. 1 for LSB and 2 for MSB.

Assume pre cusor has \(L\) legs, main cursor \(M\) legs and post cursor \(N\) legs, which is same with the convention in "Voltage-Mode Driver Equalization"

The number of legs connected with supply can expressed as \[ n_{up} = (1-d_{n+1})L + d_{n}M + (1-d_{n-1})N \] Where \(d_n \in \{0, 1\}\), or \[ n_{up} = \frac{1}{2}(-D_{n+1}+1)L + \frac{1}{2}(D_{n}+1)M + \frac{1}{2}(-D_{n-1}+1)N \] Where \(D_n \in \{-1, +1\}\)

Then the number of legs connected with ground is \[ n_{dn}=L+M+N-n_{up} \] where \(n_{up}+n_{dn}=L+M+N\)

Voltage resistor divider \[\begin{align} V_o &= \frac{\frac{R_{U}}{n_{dn}}}{\frac{R_U}{n_{dn}}+\frac{R_U}{n_{up}}} \\ &= \frac{1}{2}- \frac{1}{2}D_{n+1}\frac{L}{L+M+N}+ \frac{1}{2}D_{n}\frac{M}{L+M+N}-\frac{1}{2}D_{n-1}\frac{N}{L+M+N} \\ &= \frac{1}{2}-\frac{1}{2}D_{n+1}\cdot l+ \frac{1}{2}D_{n}\cdot m-\frac{1}{2}D_{n-1}\cdot n \end{align}\]

where \(l+m+n=1\)

\(V_{\text{MSB}}\) and \(V_{\text{LSB}}\) can be obtained

\[\begin{align} V_{\text{MSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot m-\frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \\ V_{\text{LSB}} &= \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot m-\frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n \end{align}\]

Substitute the above equation into \(V_{\text{rx}}\), we obtain the relationship between driver legs and FFE coefficients

\[\begin{align} V_{\text{rx}} &=\frac{1}{3}(2V_{\text{MSB}}+V_{\text{LSB}})-\frac{1}{2} \\ &= \frac{1}{3} \left\{ 2\left( \frac{1}{2}-\frac{1}{2}D^{\text{MSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{MSB}}_{n}\cdot m- \frac{1}{2}D^{\text{MSB}}_{n-1}\cdot n \right) + \left( \frac{1}{2}-\frac{1}{2}D^{\text{LSB}}_{n+1}\cdot l+ \frac{1}{2}D^{\text{LSB}}_{n}\cdot m- \frac{1}{2}D^{\text{LSB}}_{n-1}\cdot n \right) \right\}-\frac{1}{2} \\ &= \left(-\frac{l}{6} \cdot 2 \cdot D^{\text{MSB}}_{n+1}+ \frac{m}{6} \cdot 2 \cdot D^{\text{MSB}}_{n}- \frac{n}{6} \cdot 2 \cdot D^{\text{MSB}}_{n-1}\right) + \left(-\frac{l}{6} \cdot D^{\text{LSB}}_{n+1}+ \frac{m}{6} \cdot D^{\text{LSB}}_{n}- \frac{n}{6} \cdot D^{\text{LSB}}_{n-1}\right) \\ &= -\frac{l}{6}(2 \cdot D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ \frac{m}{6}(2\cdot D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) -\frac{n}{6}(2\cdot D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1}) \end{align}\]

After scaling, we obtain \[ V_{\text{rx}} = -l\cdot(2 \cdot D^{\text{MSB}}_{n+1}+D^{\text{LSB}}_{n+1})+ m\cdot(2\cdot D^{\text{MSB}}_{n}+D^{\text{LSB}}_{n}) - n \cdot(2\cdot D^{\text{MSB}}_{n-1}+D^{\text{LSB}}_{n-1}) \] Where \(C_{-1} = l\), \(C_0 = m\) and \(C_{1}=n\), which is same with that of NRZ

reference

Noman Hai, Synopsys. CICC 2025 Circuit Insights: Basics of Wireline Transmitter Circuits [https://youtu.be/oofViBGlrjM?si=WZnOqtDVG3iDnBHI]

Noman Hai, Synopsys. Design Challenges Of High-Speed Wireline Transmitters [https://semiengineering.com/design-challenges-of-high-speed-wireline-transmitters/]

Jhwan Kim, CICC 2022, ES4-4: Transmitter Design for High-speed Serial Data Communications

Friedel Gerfers, ISSCC2021 T6: Basics of DAC-based Wireline Transmitters [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T6.pdf]

Tod Dickson, IBM. High-Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Interconnects [https://www.youtube.com/watch?v=g1pcZabsRNc&t=13s]

Sam Palermo. High-Performance SERDES Design" Online Course (2025): Current-Mode DAC TX [https://youtu.be/A2VsvCPDWxk?si=14J7JC_bnejAlHGW]

B. Razavi, "Design Techniques for High-Speed Wireline Transmitters," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 53-66, 2021, [https://www.seas.ucla.edu/brweb/papers/Journals/BROJSSCSep21.pdf]

PCIe® 6.0 Specification: The Interconnect for I/O Needs of the Future PCI-SIG® Educational Webinar Series, [https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf]

J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012, doi: 10.1109/JSSC.2012.2216414.

C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 104-106, doi: 10.1109/ISSCC.2018.8310205.

E. Chong et al., "A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 523-526, doi: 10.1109/ESSCIRC53450.2021.9567801.

Wang, Z., Choi, M., Lee, K., Park, K., Liu, Z., Biswas, A., Han, J., Du, S., & Alon, E. (2022). An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE Journal of Solid-State Circuits, 57(1), 21-31. https://doi.org/10.1109/JSSC.2021.3109562

J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 102-104, doi: 10.1109/ISSCC.2018.8310204.

To understand the impact of the clock jitter on the performance of a wireline system, the transfer functions of the PLL in the transmitter side and the CDR loop in the receiver should be taken into consideration

the minimum jitter occurs at the point where the transmit PLL UGB is minimum and the CDR UGB is maximized

• the net rms jitter that impacts the performance of a wireline transceiver is much lower than the rms jitter of the transmit PLL
• the jitter requirements of the transmit PLL on the wireline system is much more relaxed compared to the wireless transceiver

reference

Chembiyan T, A General Theory of Cascaded PLL Design [link]

Nicola Da Dalt, ISSCC 2012 T5: JITTER basic and advanced concepts, statistics and applications [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T5.pdf]

DT & CT Spectral Density

[Sampling of WSS process of Systems, Modulation and Noise]

That is \[ P_{x_s x_s} (f)= \frac{1}{T_s}P_{xx}(f) \] In going from discrete time to continuous time, we must add a scale factor \(1/T\), the sample period

TDC quantization noise

reference

Sam Palermo, ECEN620 2024 Lecture 9: Digital PLLs [https://people.engr.tamu.edu/spalermo/ecen620/lecture09_ee620_digital_PLLs.pdf]

Topics in IC(Wireline Transceiver Design) [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

ISSCC 2008 Tutorial on Digital Phase-Locked Loops Michael H. Perrott [https://www.nishanchettri.com/isscc-slides/2008%20ISSCC/Tutorials/T05_Pres.pdf]

CICC 2009 Tutorial on Digital Phase-Locked Loops Michael H. Perrott [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

Robert Bogdan Staszewski, CICC 2020: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis [link]

Akihide Sai, ISSCC 2023 T5: All-digital PLLs From Fundamental Concepts to Future Trends [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T5.pdf]

Mike Shuo-Wei Chen, CICC 2020 ES2-3: Low-Spur PLL Architectures and Techniques [https://youtu.be/sgPDchYhN-4?si=FAy8N3SuX6vVpYhl]

Saurabh Saxena, IIT Madras. Phase-Locked Loops: Noise Analysis in Digital PLL [https://youtu.be/mddtxcqfiKU?si=yD15KM9WBkT6c68P]

Y. Hu, T. Siriburanon and R. B. Staszewski, "Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 7, pp. 3030-3036, July 2022

L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S. Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021

Neil Robertson. Digital PLL's -- Part 1 [https://www.dsprelated.com/showarticle/967.php]

Neil Robertson. Digital PLL's -- Part 2 [https://www.dsprelated.com/showarticle/973.php]

Neil Robertson. Digital PLL's -- Part 3 [https://www.dsprelated.com/showarticle/1177.php]

TODO 📅

reference

R. S. Ashwin Kumar, Analog circuits for signal processing [https://home.iitk.ac.in/~ashwinrs/2022_EE698W.html]

R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. Wiley-Interscience, 1986 [pdf]

Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]

Boris Murmann. EE315A VLSI Signal Conditioning Circuits

Limit Cycles

Nonlinear Dynamics

[https://adityamuppala.github.io/assets/Notes_YouTube/MMIC_Limit_Cycles.pdf]

ISF assumption

[https://adityamuppala.github.io/assets/Notes_YouTube/Oscillators_ISF_model.pdf]

ISF & \(1/f\)-noise up-conversion

TODO 📅

ISF Simulation

PSS + PXF Method

Yizhe Hu, "A Simulation Technique of Impulse Sensitivity Function (ISF) Based on Periodic Transfer Function (PXF)" [https://bbs.eetop.cn/thread-869343-1-1.html]

TODO 📅

Transient Method

David Dolt. ECEN 620 Network Theory - Broadband Circuit Design: "VCO ISF Simulation" [https://people.engr.tamu.edu/spalermo/ecen620/ISF_SIM.pdf]

To compare the ring oscillator and VCO the total injected charge to both should be the same

Tail filter

TODO 📅

reference

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Matt Charnley. Differential Equations: An Introduction for Engineers [link]

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Strogatz, S.H. (2015). Nonlinear Dynamics and Chaos: With Applications to Physics, Biology, Chemistry, and Engineering (2nd ed.). CRC Press [https://www.biodyn.ro/course/literatura/Nonlinear_Dynamics_and_Chaos_2018_Steven_H._Strogatz.pdf]

Cadence Blog, "Resonant Frequency vs. Natural Frequency in Oscillator Circuits" [link]

Aditya Varma Muppala. Oscillators [https://youtube.com/playlist?list=PL9Trid0A4Da2fOmYTEjhAnUkGPxyiH7H6&si=ILxn8hfkMYjXW5f4]

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Y. Hu, T. Siriburanon and R. B. Staszewski, "Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019 [https://sci-hub.se/10.1109/TCSII.2019.2896483]

S. Levantino, P. Maffezzoni, F. Pepe, A. Bonfanti, C. Samori and A. L. Lacaita, "Efficient Calculation of the Impulse Sensitivity Function in Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 10, pp. 628-632, Oct. 2012 [https://sci-hub.se/10.1109/TCSII.2012.2208679]

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D. Murphy, H. Darabi and H. Wu, "Implicit Common-Mode Resonance in LC Oscillators," in IEEE Journal of Solid-State Circuits, vol. 52, no. 3, pp. 812-821, March 2017, [https://sci-hub.st/10.1109/JSSC.2016.2642207]

D. Murphy, H. Darabi and H. Wu, "25.3 A VCO with implicit common-mode resonance," 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.st/10.1109/ISSCC.2015.7063116]

A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC Oscillator," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 45-59, 2025 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10818782]

Akihide Sai, Toshiba. ISSCC 2023 T5: All-digital PLLs From Fundamental Concepts to Future Trends [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T5.pdf]

Pietro Andreani. ISSCC 2011 T1: Integrated LC oscillators [slides,transcript]

—. ISSCC 2017 F2: Integrated Harmonic Oscillators

—. SSCS Distinguished Lecture: RF Harmonic Oscillators Integrated in Silicon Technologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto.pdf]

—. ESSCIRC 2019 Tutorials: RF Harmonic Oscillators Integrated in Silicon Technologies [https://youtu.be/k1I9nP9eEHE?si=fns9mf3aHjMJobPH]

Jun Yin. ISSCC 2025 T10: mm-Wave Oscillator Design