KNOW-HOW

Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022

[https://sci-hub.st/10.1109/ISSCC42614.2022.9731650]

P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with >45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025

ISSCC.2024 7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS

[7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS https://www.bilibili.com/video/BV18hYCe7E45/?share_source=copy_web&vd_source=5a095c2d604a5d4392ea78fa2bbc7249]

ISSCC.2018 6.4 A Fully Adaptive 19-to-56Gb/s PAM-4 Wireline Transceiver with a Configurable ADC in 16nm FinFET

[https://sci-hub.st/10.1109/ISSCC.2018.8310207]

M. S. Jalali, A. Sheikholeslami, M. Kibune and H. Tamura, "A Reference-Less Single-Loop Half-Rate Binary CDR," in IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2037-2047, Sept. 2015 [https://www.eecg.utoronto.ca/~ali/papers/jssc2015-09.pdf]

Pisati, et.al., "Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC- Based Transceiver in 7nm FinFET," 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019 [https://sci-hub.se/10.1109/ISSCC.2019.8662428]

spread spectrum clock generation (SSCG) — an advanced clock generation solution for electromagnetic interference (EMI)

SSC modulation profile

SSCG Architectures

K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]

Refclk Clocking Architectures

PCI Express Base Specification Revision 3.0

Jeff Morriss, Intel Gerry Talbot, AMD. PCI-SIG Devcon 2006. Jitter Budgeting for Clock Architecture

Verification of SRIS/SRNS Clocking [https://www.esaindia.com/emailer/download/sria-srns-white-paper-final-v3.pdf]

Common Reference Clock (CC)

Common Refclk Rx architectures are characterized by the Tx and Rx sharing the same Refclk source

Most of the SSC jitter sourced by the Refclk is propagated equally through Tx and Rx PLLs, and so intrinsically tracks LF jitter

The amount of jitter appearing at the CDR is then defined by the difference function between the Tx and Rx PLLs multiplied by the CDR highpass characteristic

\[ H(s)= H_1(s)e^{-sT} - \left[H_1(s)e^{-sT}(1-H_3(s)) + H_2(s)H_3(s) \right] = [H_1(s)e^{-sT} -H_2(s)]H_3(s) \] where \(H_3(s)\) is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)

Data Clocked Refclk Rx Architecture

A data clocked Rx architecture is characterized by requiring the receiver's CDR to track the entirety of the low frequency jitter, including SSC

Separate Reference Clocks with SSC (SRIS)

TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE: Updated 10 January 2013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev. 3.0 SPONSOR: Intel, HP, AMD

\[\begin{align} X_{LATCH}(s) &= X_1(s)H_1(s) - \left[X_1(s)H_1(s)(1-H_3(s)) + X_2(s)H_2(s)H_3(s) \right] \\ & = \left[X_1(s)H_1(s) -X_2(s)H_2(s)\right]H_3(s) \end{align}\] where \(H_3(s)\) is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)

Separate Reference Clocks with No SSC (SRNS)

reference

Jason Sachs. Linear Feedback Shift Registers for the Uninitiated, Part XII: Spread-Spectrum Fundamentals [link]

Jan Meel, Spread Spectrum (SS) — introduction, De Nayer Instituut, Sint-Katelijne-Waver, Belgium, 1999.

Raymond L. Pickholtz, Donald L. Schilling, Laurence B. Milstein, Theory of Spread-Spectrum Communications — A Tutorial, IEEE Transactions on Communications, vol. 30, no. 5, pp. 855-884, May 1982.

Kadeem Samuel. Application Note Clocking for PCIe Applications [https://www.ti.com/lit/an/snaa386/snaa386.pdf?ts=1756864837383]

K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Single-Pole LPF Algorithms

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

Jason Sachs, Ten Little Algorithms, Part 2: The Single-Pole Low-Pass Filter [https://www.embeddedrelated.com/showarticle/779.php]

—. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

• Derivatives Approximation (\(H_p(s)=\frac{1}{s\tau +1}\))

  \[\begin{align} H_p(z)&=\frac{\frac{T_s}{T_s+\tau}}{1+(\frac{T_s}{T_s+\tau}-1)z^{-1}}\tag{EQ-0}\\ H_p(z)&=\frac{\frac{T_s}{\tau}}{1+(\frac{T_s}{\tau}-1)z^{-1}}\tag{EQ-1} \end{align}\]

• Matched z-Transform (Root Matching) \[ H_p(z)=\frac{1-e^{-T_s/\tau}}{1-e^{-T_s/\tau}z^{-1}}\tag{EQ-2} \] EQ-2 is connected with EQ-1 by \(1 - e^{-\Delta t/\tau} \approx \frac{\Delta t}{\tau}\)

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import numpy as np
import matplotlib.pyplot as plt
import scipy.signal


dt=0.002; tau=0.05

T=1
t = np.arange(0,T+1e-5,dt)
x = 1-np.abs(4*t-1)
x[4*t>2] = 0.95; x[t>0.75] = 0.02

alpha_derv = dt / (dt + tau)
alpha_derv_approx = dt / tau

yfilt_derv = scipy.signal.lfilter([alpha_derv], [1, alpha_derv - 1], x)
yfilt_derv_approx = scipy.signal.lfilter([alpha_derv_approx], [1, alpha_derv_approx - 1], x)

a1 = -np.exp(-dt/tau)
b0 = [1 + a1]
a = [1, a1]
y_filt_match = scipy.signal.lfilter(b0, a, x)

plt.figure(figsize=(20,10))
plt.plot(t, x, color='k', linewidth=3, label='x')
plt.plot(t, yfilt_derv, color='red', linewidth=3, label=r'$H_p(z)=\frac{\frac{T_s}{T_s+\tau}}{1+(\frac{T_s}{T_s+\tau}-1)z^{-1}}$')
plt.plot(t, yfilt_derv_approx, color='green', marker='D', linestyle='dashed',markersize=4, linewidth=3, label=r'$H_p(z)=\frac{\frac{T_s}{\tau}}{1+(\frac{T_s}{\tau}-1)z^{-1}}$')
plt.plot(t, y_filt_match, color='m', marker='x', linestyle='dashed',markersize=4, linewidth=3, label=r'$H_p(z)=\frac{1-e^{-T_s/\tau}}{1-e^{-T_s/\tau}z^{-1}}$')

plt.legend(loc='upper right', fontsize=20)
plt.grid(which='both');plt.xlabel('Time (s)');plt.show()

Discrete-Time Integrators

Qasim Chaudhari. Discrete-Time Integrators [https://wirelesspi.com/discrete-time-integrators/]

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA?si=_pGb18rhsMUZ-lAf]

Delaying Integrator

Delay-free Integrator

Discrete-Time Differentiator

Qasim Chaudhari. Design of a Discrete-Time Differentiator [https://wirelesspi.com/design-of-a-discrete-time-differentiator/]

TODO 📅

Accumulate-and-dump (AAD) decimator

accumulating the input for \(N\) cycles and then latching the result and resetting the integrator

It adds up \(N\) succeeding input samples at rate \(1/T\) and delivers their sum in a single sample at the output. Therefore, the process comprises a filter (in the accumulation) and a down-sampler (in the dump)

Moving Average and CIC Filters

An Intuitive Look at Moving Average and CIC Filters [web, code]

A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

TODO 📅

Cascaded Integrator-Comb (CIC) filter

Let’s focus on decimation: if we decimate by a factor 4, we simply retain one output sample out of every 4 input samples.

In the example below, the downsampler at the right drops those 3 samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input rate \(x(n)\):

\[\begin{align} Y(z) &= X(z)\frac{1-z^{-4}}{1-z^{-1}} \\ Y^\prime(\xi) &= \frac{1}{4}Y(\xi^{1/4}) = \frac{1}{4}X(\xi^{1/4})\frac{1-\xi^{-1}}{1-\xi^{-1/4}} \end{align}\]

with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[ Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}} \]

But if we're going to be throwing away 75% of the calculated values, can't we just move the downsampler from the end of the pipeline to somewhere in the middle? Right between the integrator stage and the comb stage? That answer is yes, but to keep the math working, we also need to divide the number of delay elements in the comb stage by the decimation rate:

\[\begin{align} A(z) &= X(z)\frac{1}{1-z^{-1}} \\ A^\prime(\xi) &= \frac{1}{4}A(\xi^{1/4}) = \frac{1}{4}X(\xi^{1/4})\frac{1}{1-\xi^{-1/4}} \\ Y^\prime(\xi) &= A^\prime(\xi) (1-\xi^{-1}) = \frac{1}{4}X(\xi^{1/4})\frac{1-\xi^{-1}}{1-\xi^{-1/4}} \end{align}\]

with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[ Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}} \]

And we can do this just the same with cascaded sections (without downsampler or updampler) where integrators and combs have been grouped

• for decimation, the integrators come first and the combs second with the downsampler in between
• For interpolation, the reverse is true
  • the incoming sample rate is fraction of the outgoing sample rate, the combs must come first and the interpolators second

Tom Verbeure. An Intuitive Look at Moving Average and CIC Filters [https://tomverbeure.github.io/2020/09/30/Moving-Average-and-CIC-Filters.html]

—. Half-Band Filters, a Workhorse of Decimation Filters [https://tomverbeure.github.io/2020/12/15/Half-Band-Filters-A-Workhorse-of-Decimation-Filters.html]

—. Design of a Multi-Stage PDM to PCM Decimation Pipeline [https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html]

Arash Loloee, Ph.D. Exploring Decimation Filters [https://www.highfrequencyelectronics.com/Archives/Nov13/1311_HFE_decimationFilters.pdf]

Rick Lyons. A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

reference

Jabbour, Chadi, etc.. "Digitally enhanced mixed signal systems." IEEE International Symposium on Circuits and Systems (ISCAS). 2019.

Sen M. Kuo. Real-Time Digital Signal Processing: Fundamentals, Implementations and Applications, 3rd Edition. John Wiley & Sons 2013

Taylor, Fred. Digital filters: principles and applications with MATLAB. John Wiley & Sons, 2011

Kuo, Sen-Maw. (2013) Real-Time Digital Signal Processing: Implementations and Applications 3rd [pdf]

D. Markovic and R. W. Brodersen, DSP Architecture Design Essentials, Springer, 2012.

Bevan Baas, EEC281 VLSI Digital Signal Processing, [https://www.ece.ucdavis.edu/~bbaas/281/]

Mark Horowitz. EE371: Advanced VLSI Circuit Design Spring 2006-2007 [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/]

謝秉璇. 2019 積體電路設計導論 [link]

Tinoosh Mohsenin. CMPE 691: Digital Signal Processing Hardware Implementation [https://userpages.cs.umbc.edu/tinoosh/cmpe691/]

Keshab K. Parhi [http://www.ece.umn.edu/users/parhi/]

Qasim Chaudhari. FIR vs IIR Filters – A Practical Comparison [https://wirelesspi.com/fir-vs-iir-filters-a-practical-comparison/]

—. Finite Impulse Response (FIR) Filters [https://wirelesspi.com/finite-impulse-response-fir-filters/]

—. Why FIR Filters have Linear Phase [https://wirelesspi.com/why-fir-filters-have-linear-phase/]

—. Moving Average Filter [https://wirelesspi.com/moving-average-filter/]

—. Cascaded Integrator Comb (CIC) Filters – A Staircase of DSP. [https://wirelesspi.com/cascaded-integrator-comb-cic-filters-a-staircase-of-dsp/]

Jason Sachs. Understanding and Preventing Overflow (I Had Too Much to Add Last Night) [https://www.embeddedrelated.com/showarticle/532.php]

—. Round Round Get Around: Why Fixed-Point Right-Shifts Are Just Fine [https://www.embeddedrelated.com/showarticle/1015.php]

—. How to Build a Fixed-Point PI Controller That Just Works: Part I [https://www.embeddedrelated.com/showarticle/121.php]

—. How to Build a Fixed-Point PI Controller That Just Works: Part II [https://www.embeddedrelated.com/showarticle/123.php]

PI vs. PLL based CDR

PCI Express Jitter Modeling Revision 1.0RD July 14, 2004

Phase Interpolator (PI)

!!! Clock Edges

And for a phase interpolator, you need those reference clocks to be completely the opposite. Ideally they would be triangular shaped

four input clocks given by the cyan, black, magenta, red

John T. Stonick, ISSCC 2011 tutorial. "DPLL Based Clock and Data Recovery" [https://www.nishanchettri.com/isscc-slides/2011%20ISSCC/TUTORIALS/ISSCC2011Visuals-T5.pdf]

kink problem

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023.(https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf)

reference

Cortiula A, Menin D, Bandiziol A, Driussi F, Palestri P. Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces. Electronics. 2025; [https://www.mdpi.com/2079-9292/14/10/1979]

G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/document/10184121]

Metastability is an undesirable non-equilibrium electronic state that can persist for a long period of time

Poisson stochastic process

Synchronizer effect – latency uncertainty

simulation of DFF

The typical flip-flops comprise master and slave latches and decoupling inverters.

In metastability, the voltage levels of nodes A and B of the master latch are roughly midway between logic 1 (VDD) and 0 (GND)

master latch enter metastability

In fact, one popular definition says that if the output of a flip-flop changes later than the nominal clock-to-Q propagation delay, then the flip-flop must have been metastable

sweep \(\Delta t_{D \to \space \text{CK}}\)

transient noise analysis @ \(\Delta t_{D \to \space \text{CK}} = -3.444525p\)

zoom out

Noise Seed—Seed for the random number generator (used by the simulator to vary the noise sources internally). Specifying the same seed allows you to reproduce a previous experiment. The default value is 1.

reference

Yvain Thonnart, CEA-LIST. ISSCC2021 T8: On-Chip Interconnects: Basic Concepts, Designs and Future Opportunities [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T8.pdf]

R. Ginosar, "Metastability and Synchronizers: A Tutorial," in IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23-35, Sept.-Oct. 2011 [https://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf]

Amr Adel Mohammady. Clock Domain Crossing [linkedin]

Steve Golson. Synchronization and Metastability [https://trilobyte.com/pdf/golson_snug14.pdf]

Kinniment, D. J. Synchronization and arbitration in digital systems. John Wiley & Sons Ltd (2007).

Synchronizers And Data FlipFlops are Different [pdf]

S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The Devolution of Synchronizers," 2010 IEEE Symposium on Asynchronous Circuits and Systems, Grenoble, France, 2010 [pdf]

赵启林 klin, Metastability [https://picture.iczhiku.com/resource/eetop/SHKSFADwZerLPBXN.pdf]

Asad Abidi. ISSCC 2023: Circuit Insights "The CMOS Latch" [https://youtu.be/sVe3VUTNb4Q&t=681]

Matt Venn. Interactive flip flop simulation [https://github.com/mattvenn/flipflop_demo]

Jitter Performance Limitations

Aliasing of baud-rate sampling

The most significant impairments are considered to be the sensitivity to sampling phase, and the effect of aliasing out of band signal and noise into the baseband

Tao Gui (Huawei), etc.. IEEE 802.3dj May Interim meeting San Antonio, Texas May 15, 2013: "Feasibility Study on Baud-Rate Sampling and Equalization (BRSE) for 800G-LR1" [https://www.ieee802.org/3/dj/public/23_05/gui_3dj_01a_2305.pdf]

D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J. Savory, "A baud-rate sampled coherent transceiver with digital pulse shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]

Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]

Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]

reference

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

Jhwan Kim, CICC 2022, ES4-4: Transmitter Design for High-speed Serial Data Communications

Friedel Gerfers, ISSCC2021 T6: Basics of DAC-based Wireline Transmitters [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T6.pdf]

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

Tony Pialis, Alphawave Semi. How DSP is Killing the Analog in SerDes [https://youtu.be/OY2Dn4EDPiA?si=q2Qy_avTIxJjDdOf]

Tony Chan Carusone, Alphawave Semi. High Speed Communications Part 3 – Equalization & MLSD [https://youtu.be/KqwZ23vNqYg?si=pqMFWVVUOrAVhkeU]

—. High Speed Communications Part 9 – Anatomy of a Modern SerDes [https://youtu.be/tlc68UTn6iQ?si=ZkqAy3INlA3Vr8Y7]

—. High Speed Communications Part 10 – 224Gbps Link Impairments [https://youtu.be/m-Msp_2WGAg?si=n5lgrxiz24K7x66a]

—. High Speed Communications Part 11 – SerDes DSP Interactions [https://youtu.be/YIAwLskuVPc?si=1HWB0yA2u2jiixNZ]

ADC ENOB

Dan Boschen, GRCon25: Quantifying Signal Quality: Practical Tools for High-Fidelity Waveform Analysis

[linkedin GRCon25]

decimation filter

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/First_Order_DS_ADC_scan1.pdf]

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/First_Order_DS_ADC_scan2.pdf]

The combination of the the digital post-filter and downsampler is called the decimation filter or decimator

\(\text{sinc}\) filter

Suppose \(T=1\) \[ H_1(e^{j2\pi f}) = \frac{\text{sinc}(Nf)}{\text{sinc}(f)} = \frac{1}{N}\frac{\sin(\pi Nf)}{\sin(\pi f)} \] that is \(\lim_{f\to 0^+}H_1(e^{j2\pi f}) = 1\) and \(H_1 = 0\) when \(f=\frac{n}{N}, n\in \mathbb{Z}\)

A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]

\[ |H_1(\omega)|^2 = \left|\frac{1}{N}(1-e^{-j\omega N}) \right| = \frac{2}{N^2}(1-\cos (\omega N)) \] Total noise after \(H_1\) \[ \sigma_{q_1}^2 = 2\int_0^\pi \frac{e^2_{rms}}{2\pi}\cdot |H_1(\omega)|^2d\omega = \frac{2e^2_{rms}}{N^2} \] inband noise before \(H_1\), i.e. ideal LPF with cutoff frequency \(\frac{\pi}{N}\) \[ \sigma_{q_0}^2 = 2\int_0^{\pi/N}\frac{e_{rms}^2}{2\pi}|1-e^{-j\omega}|^2d\omega = \frac{2e_{rms}^2}{\pi}\left(\frac{\pi}{N}-\sin\frac{\pi}{N}\right) \] with Taylor series \(\sin\frac{\pi}{N}\approx \frac{\pi}{N}-\frac{1}{6}\frac{\pi^3}{N^3}\) \[ \sigma_{q_0}^2 \approx \frac{\pi^2}{3N^3}e_{rms}^2 \]

Taylor’s Series of sin x [pdf]

[https://analogicus.com/aic2025/2025/02/20/Lecture-6-Oversampling-and-Sigma-Delta-ADCs.html#python-oversample]

\(\text{sinc}^2\) filter

interpolation filter

Notice that the requirements of the first stage are very demanding

DC Gain in Interpolation Filtering

[https://raytroop.github.io/2025/06/21/data-converter-in-action/#dac-zoh]

DC gain is used to compensate the ratio of sampling rate before and after upsample

Given \[ X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i} \] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)

Employ definition of DTFT, \(X(e^{j\hat{\omega}}) =\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set \(\hat{\omega} = 0\) \[ X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n] \] That is, \(\sum_{n=-\infty}^{+\infty}x[n] = \sum_{n=-\infty}^{+\infty}x_e[n]\), so \[ \overline{x_e[n]} = \frac{1}{L} \overline{x[n]} \] It also indicate that dc gain of upsampling is \(1/L\)

ZOH

Zero-Order Hold (ZOH)

dc gain = \(N\)

FOH

First-Order Hold (FOH)

dc gain = \(N\)

reference

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

—, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, Modeling Anti-Alias Filters [https://www.dsprelated.com/showarticle/1418.php]

—, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Arash Loloee, Ph.D. Exploring Decimation Filters [https://www.highfrequencyelectronics.com/Archives/Nov13/1311_HFE_decimationFilters.pdf]

Venkatesh Srinivasan, ISSCC 2019 T5: Noise Shaping in Data Converters

Nan Sun,IEEE CAS 2020: Break the kT/C Noise Limit [https://www.facebook.com/ieeecas/videos/break-the-ktc-noise-limit/322899188976197/]

Yun-Shiang Shu, ISSCC 2022 T3: Noise-Shaping SAR ADCs

Xiyuan Tang, CICC 2025 ES2-1: Noise-Shaping SAR ADCs - From Fundamentals to Recent Advances

Qasim Chaudhari. On Analog-to-Digital Converter (ADC), 6 dB SNR Gain per Bit, Oversampling and Undersampling [https://wirelesspi.com/on-analog-to-digital-converter-adc-6-db-snr-gain-per-bit-oversampling-and-undersampling/]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

Dual Slope ADC

\[ V_{IN} = \frac{V_{REF}}{T}t_\text{x} = \frac{V_{REF}}{2^N}\cdot 2^{N_\text{x}} \]

Normal Mode Rejection

a high normal mode rejection ratio (NMRR) for input noise at line frequency

• Conversion accuracy is independent of both the capacitance and the clock frequency, because they affect both the up-slope and the down-slope by the same ratio

• The fixed input signal integration period results in rejection of noise frequencies on the analog input that have periods that are equal to or a sub-multiple of the integration time \(T\)

  Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (\(1/T\)) averaged over a period (\(T\)) is zero

Linear Circuit Design Handbook, 2008 [https://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter6.pdf]

Precision Analog Front Ends with Dual Slope ADC [https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/21428e.pdf]

Incremental ADC

\[\begin{align} V &= 2^N V_\text{in} - D_\text{out}V_\text{ref} \\ D_\text{out} \frac{V_\text{ref}}{2^N} &= V_\text{in} - \frac{V}{2^N} \end{align}\]

feedforward structure

??? TODO 📅

reference

David Johns (University of Toronto) "Oversampled Data Converters" Course (2019) [https://youtu.be/qIJ2LORYmyA?si=_pGb18rhsMUZ-lAf]

Frequency Domain Model

Skew (Timing Mismatch) Calibration

TODO 📅

M. Gu, Y. Tao, Y. Zhong, L. Jie and N. Sun, "Timing-Skew Calibration Techniques in Time-Interleaved ADCs," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 1-10, 2025 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623]

S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan Carusone, “All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters,” IEEE Transactions on VLSI Systems, Sept. 2017. [PDF, slides]

B. Razavi, "Problem of timing mismatch in interleaved ADCs," Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 2012 [https://www.seas.ucla.edu/brweb/papers/Conferences/BRCICC12.pdf]

resync (alignment)

TODO 📅

Multi-Phase Clock Generation (MPCG)

TODO 📅

Interleaver

Direct Interleaver

similar to increase the resolution of the flash ADC with more parallel comparators

De-multiplexing Interleaver

it is the front-end samplers that determine timing/bandwidth mismatch errors

Re-sampling Interleaver

back-end re-sampling occur after the front-end, two \(\frac{KT}{C}\) contribution in total noise (De-multiplexing Interleaver only one \(\frac{KT}{C}\))

without buffer, charging distribution reduce signal and reduce SNR, but buffers give excess noise

Interleaver Model

Interleaving Errors

Offset Mismatch Error

Gain Mismatch Error

Timing Mismatch Error

\(\pi/2\)-rad phase: the maximum error occurs at the zero crossing and not on the peaks (Gain Mismatch error)

Frequency-dependent: the higher frequency input signal \(f_\text{in}\), the larger error becomes

\(\pi/2\) phase shift \[ e^{j\pi/2} = j \] frequency-dependent \[ V^{'} \propto f \]

In time domain \[ \frac{d\sin(\omega t)}{dt} = \omega \cos(\omega t) \propto \omega \]

Bandwidth Mismatch Errors

Overlapping versus Non-overlapping track time

tracking accuracy stay same, Cin (2Cs) counteract the longer tracking

Summing Interleaved Alias

The sampling function - impulse train is \[ s(t) = \sum_{n=-\infty}^{\infty}\left[ \delta(t-n4T_s) + \delta(t-n4T_s-T_s) + \delta(t-n4T_s-2T_s) + \delta(t-n4T_s-3T_s)\right] \]

Its Fourier transform is \[\begin{align} S(f) &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left[\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot T_s}\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot 2T_s}\delta(f-k\frac{f_s}{4}) + e^{-j2\pi f\cdot 3T_s}\delta(f-k\frac{f_s}{4}) \right] \\ &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left(1+e^{-j2\pi\frac{f}{f_s}} + e^{-j4\pi\frac{f}{f_s}} + e^{-j6\pi\frac{f}{f_s}} \right) \delta(f-k\frac{f_s}{4}) \\ &= \frac{2\pi}{4T}\sum_{k=-\infty}^{\infty}\left(1+e^{-jk\frac{\pi}{2}} + e^{-jk\pi} + e^{-jk\frac{3\pi}{2}} \right) \delta(f-k\frac{f_s}{4}) \end{align}\]

We define \(M[k] = 1+e^{-jk\frac{\pi}{2}} + e^{-jk\pi} + e^{-jk\frac{3\pi}{2}}\), which is periodic, i.e. \(M[k]=M[k+4]\) \[ M[k]=\left\{ \begin{array}{cl} 4 & : \ k = 4m \\ 0 & : \ k=4m+1 \\ 0 & : \ k=4m+2 \\ 0 & : \ k=4m+3 \\ \end{array} \right. \]

That is \[ S(f) = \frac{2\pi}{T}\sum_{k=-\infty}^{\infty} \delta(f-kf_s) \]

Alias has same frequency for each slice but different phase: Alias terms sum to zero if all slices match exactly

Random Chopping in TI-ADC

\[ D_n(kT) = (G_n R(kT) V(kT) + O_n)R(kT)= C_n V(kT) + R(kT)O_n \]

reference

John P. Keane, ISSCC2020 T5: "Fundamentals of Time-Interleaved ADCs" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T5Visuals.pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

ISSCC2015 F1: High-Speed Interleaved ADCs [https://picture.iczhiku.com/resource/eetop/wykrheUfrWasiMVX.pdf]

Poulton, Ken. ISSCC2009 "Time-Interleaved ADCs, Past and Future" (slides)

—. CICC2010 "GHz ADCs: From Exotic to Mainstream", tutorial session, (slides)

—. ISSCC2015 "Interleaved ADCs Through the Ages", (slides)

Ewout Martens. ESSCIRC 2019 Tutorials: Advanced Techniques for ADCs for 5G Massive MIMO [https://youtu.be/7hYichGGU6k]

Athanasios Ramkaj. January 26, 2022, IEEE SSCS Santa Clara Valley Section Technical Talk: Design Considerations Towards Optimal High-Resolution Wide-Bandwidth Time-Interleaved ADCs [https://youtu.be/k3jY9NtfYlY?si=K9AdT9QzGxOnI5WG]

Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]

S. Jang, J. Lee, Y. Choi, D. Kim, and G. Kim, "Recent advances in ultra-high-speed wireline receivers with ADC-DSP-based equalizers," IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), vol. 4, pp. 290-304, Nov. 2024.

Yida Duan. Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters (ADCs) [http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-10.pdf]

Preview Lecture #1 - "Extreme SAR ADCs" Online Course (2024) - Prof. Chi-Hang Chan (U. of Macau) [https://youtu.be/rgMRL4QZ-wA]

speculative DFE is also known as loop unrolled DFE, which solve the critical timing on first tap

VGA/attenuator: ensure a constant swing at the slicer input regardless of the channel variation

Inductive Peaking

TODO 📅

series peaking: capacitive splitting - split the load capacitance between the amplifier drain capacitance and the next stage gate capacitance

S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension Techniques for CMOS Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006 [https://people.engr.tamu.edu/spalermo/ecen689_oi/2006_passive_bw_extension_techniques_shekhar_jssc.pdf]

CTLE Linearity

TODO 📅

Front-End Noise

https://people.engr.tamu.edu/spalermo/ecen689/lecture6_ee720_rx_circuits.pdf

DFE Error Propagation

TODO 📅

Geoff Zhang. Preliminary Studies on DFE Error Propagation, Precoding, and their Impact on KP4 FEC Performance for PAM4 Signaling Systems [https://www.ieee802.org/3/ck/public/18_09/zhang_3ck_01a_0918.pdf]

CTLE transfer function

Circuit Insights @ ISSCC2025: Circuits for Wireline Communications - Kevin Zheng [https://youtu.be/8NZl81Dj45M?si=J11oGnXnkJYPUi2n&t=1045]

DFE architecture

Extensive work on DFEs has produced a multitude of architectures, which can be broadly categorized as "direct"" or "unrolled" (speculative) DFEs with "full-rate" or "half-rate" clocking

S. Ibrahim and B. Razavi, "Low-Power CMOS Equalizer Design for 20-Gb/s Systems," in IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1321-1336, June 2011 [https://sci-hub.se/10.1109/JSSC.2011.2134450]

S. Ibrahim and B. Razavi, Low-Power DFE Design [https://picture.iczhiku.com/resource/eetop/wykflwIuIQDzYNcB.PDF]

PAM4 DFE

K. -C. Chen, W. W. -T. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 750-762, March 2021 [https://www.mics.caltech.edu/wp-content/uploads/2021/02/JSSC-2020-Xavier-PAM4-Receiver.pdf]

Hongtao Zhang, DesignCon 2016. PAM4 Signaling for 56G Serial Link Applications − A Tutorial [https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

reference

Miguel Gandara, MediaTek. CICC 2025 Circuit Insights: Basics of Wireline Receiver Circuits [https://youtu.be/X4JTuh2Gdzg]

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

H. Park et al., "7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025

Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes [https://www.youtube.com/live/wHNOlxHFTzY]