Linear distortion includes any
amplitude or delay distortion associated with a linear
transmission system
Nonlinear distortion includes harmonic
distortion, intermodulation distortion (IMD)
CM Noise
Luo, X., Yu, H., Maqbool, K. Q., Huang, Y., Luo, D., & Yue, P. C.
(2017). Analysis on EMI Related Common-mode Noise of Serdes Transmitter.
Paper presented at DesignCon 2017 [lnk]
—. EMI related common-mode noise analysis in high-speed backplane
links. Thesis (Ph.D.)-HKUST 2018 [link]
—. Study on the effects of distortions and common‐mode noise in
high‐speed PAM‐4 systems - Luo - 2018 - Electronics Letters - Wiley
Online Library [link]
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SciTech Pub., 2007.
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10.1007/978-0-387-28341-8. [pdf]
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ifft of sampling continuous-time transfer
function
1 2 3 4 5 6 7 8 9 10 11 12 13 14
deffreq2impulse(H, f): #Returns the impulse response, h, and (optionally) the step response, #hstep, for a system with complex frequency response stored in the array H #and corresponding frequency vector f. The time array is #returned in t. The frequency array must be linearly spaced.
Hd = np.concatenate((H,np.conj(np.flip(H[1:H.size-1])))) h = np.real(np.fft.ifft(Hd)) #hstep = sp.convolve(h,np.ones(h.size)) #hstep = hstep[0:h.size] t= np.linspace(0,1/f[1],h.size+1) t = t[0:-1]
return h,t
Maybe, the more straightforward method is sampling impulse response
of continuous-time transfer function directly
## freq2impulse(H, f), ifft - using sample of continuous-time tranfer function f = w/(2*np.pi) Hd = np.concatenate((H,np.conj(np.flip(H[1:H.size-1])))) hd = np.real(np.fft.ifft(Hd)) t= np.linspace(0,1/f[1],hd.size+1) t = t[0:-1]
## continuous-time transfer function - impulse t, hc = signal.impulse(([1], [1/wbw, 1]), T = t)
## hd(kTs) = Ts*hc(kTs) plt.figure(figsize = (14,10)) plt.plot(t, hc, t, hd/Ts, '--r', linewidth=3) plt.grid(); plt.legend(['impulse response by continuous-time transfer function','impulse response/Ts by ifft of sampling transfer function']) plt.ylabel('Mag'); plt.xlabel('time (s)'); plt.show()
for osr_cur in osr_list dt = tui/osr_cur; # Simulation time step tt = [0:dt:tlen_ir-dt;] ir = ω*exp.(-tt*ω); ir_dt_sum = sum(ir*dt); push!(ir_dt_sum_list, ir_dt_sum) end
p = plot(osr_list, ir_dt_sum_list, label = "OSR") gui(p)
Elastic Buffer
the elastic buffer approach would be the most general for modeling
say frequency offsets between TX and RX (will be addressed in future
development)
generate PAM symbols
here Big Endian
1 2 3 4 5
#generate PAM symbols fill!(So, zero(Float64)) #reset So to all 0 for n = 1:bits_per_sym @. So = So + 2^(bits_per_sym-n)*So_bits[n:bits_per_sym:end] end
1 2 3 4 5 6
function int2bits(num, nbit) return [Bool((num>>k)%2) for k in nbit-1:-1:0] end
Hm_ds_interp=spline(fds_m,Hm_ds,f_ds_interp); % Interpolate for FFT point number figure(Name='spline function') plot(fds_m, Hm_ds, '-rs', LineWidth=2) hold on plot(f_ds_interp, Hm_ds_interp, '--bo', LineWidth=2) legend('org', 'interpolated'); grid on
impulse response from ifft of interpolated frequency
response
% Generate Random Data nt=1e3; %number of bits m=rand(1,nt+1); %random numbers between 1 and zero, will be quantized later m=-1*sign(m-0.5).^2+sign(m-0.5)+1;
% TX FIR Equalization Taps eq_taps=[1]; m_fir=filter(eq_taps,1,m);
for ( i=55:floor(size(data_channel,2) / bit_period)-500) eye_data(:,j) = 2*data_channel(floor((bit_period*(i-1)))+offset: floor((bit_period*(i+1)))+offset); j=j+1; end
time=0:2*bit_period; plot(time,eye_data);
If your 2D array represents multiple data series (e.g., each
column is a separate line seriessharing the same x-axis
values), the plot() function is the most
straightforward method.
% Take 10 pre-cursor, cursor, and 90 post-cursor samples sample_offset=opt_sample*bit_period; fori=1:101 sample_points(i)=max_data_ch_idx+sample_offset+(i-11)*bit_period; end sample_values=data_channel(sample_points); sample_points=(sample_points-max_data_ch_idx)./bit_period;
% Include DFE Equalization dfe_tap_num=2; dfe_taps(1:dfe_tap_num)=sample_values(12:12+dfe_tap_num-1); % h1, h2...
% Note this isn't a strtict DFE implementation - as I am not making a % decision on the incoming data. Rather, I am just using the known data % that I transmitted, delay matching this with the channel data, and using % it to subtract the ISI after weighting with the tap values. But, I think % it is good enough for these simulations. m_dfe=filter(dfe_taps,1,m); m_dfe_dr=reshape(repmat(m_dfe,bit_period,1),1,bit_period*size(m_dfe,2));
data_channel=data_channel'; dfe_fb_offset=floor(bit_period/2); % Point at which the DFE taps are subtracted - can be anything from 0 to UI-1*time_step data_channel_dfe=data_channel(channel_delay+dfe_fb_offset:channel_delay+dfe_fb_offset+size(m_dfe_dr,2)-1)-m_dfe_dr;
1 2 3 4 5 6 7
plot(m_dr, '--', LineWidth=2); hold on plot(data_channel(channel_delay:end), '--', LineWidth=2) hold on plot(data_channel(channel_delay+dfe_fb_offset:channel_delay+dfe_fb_offset+size(m_dfe_dr,2)-1), '--', LineWidth=2) plot(m_dfe_dr, LineWidth=2); plot(data_channel_dfe, LineWidth=2) xlim([1000, 3000]); ylim([-0.05, 0.3]); xlabel('samples'); grid on legend('lshift channel\_delay', 'lshift channel\_delay + 1/2UI', 'dfe filter', 'after dfe')
X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate
Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 29, no. 7, pp. 1370-1378, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3082208]
HSPICE® User Guide: Signal Integrity Modeling and Analysis, Version
Q-2020.03, March 2020
IA Title: Common Electrical I/O (CEI) - Electrical and Jitter
Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+
bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]
J. Park and D. Kim, "Statistical Eye Diagrams for High-Speed
Interconnects of Packages: A Review," in IEEE Access, vol. 12,
pp. 22880-22891, 2024 [pdf]
function bist_prbs_gen(;poly, inv, Nsym, seed) seq = Vector{Bool}(undef,Nsym) for n = 1:Nsym seq[n] = inv for p in poly seq[n] ⊻= seed[p] end seed .= [seq[n]; seed[1:end-1]] end return seq, seed end
1 2 3 4 5 6 7 8 9 10 11 12
%% Matlab
function[seq, seed] = bist_prbs_gen(poly,inv, Nsym, seed) seq = zeros(1,Nsym); for n = 1:Nsym seq(n) = inv; for p = poly seq(n) = xor(seq(n), seed(p)); end seed = [seq(n), seed(1:end-1)]; end end
Lim, Byong Chan, M. Horowitz, "Error Control and Limit Cycle
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Design: Enabling Mixed-Signal System Validation," in IEEE Design
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— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim,
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Mixed-Signal Validation," in IEEE Transactions on Circuits and
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[https://sci-hub.se/10.1109/TCSI.2014.2332265]
Ji-Eun Jang et al. “True event-driven simulation of
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Foundations Standards, Link Budgets & Models," 2019 IEEE Custom
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[https://picture.iczhiku.com/resource/ieee/SHKhwYfGotkIymBx.pdf]
Mathuranathan Viswanathan. Digital Modulations using Matlab: Build
Simulation Models from Scratch
accumulating the input for \(N\)
cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input
samples at rate \(1/T\) and delivers
their sum in a single sample at the output. Therefore, the
process comprises a filter (in the accumulation) and a
down-sampler (in the dump)
Moving Average and CIC
Filters
An Intuitive Look at Moving Average and CIC Filters [web,
code]
Let’s focus on decimation: if we decimate by a factor 4, we simply
retain one output sample out of every 4 input samples.
In the example below, the downsampler at the right drops those 3
samples out of 4, and the output rate, \(y^\prime(n)\), is one fourth of the input
rate \(x(n)\):
with \(z=e^{j\Omega/f_s}\) and \(\xi =z^4\), we have \[
Y^\prime(z) = \frac{1}{4}X(z)\frac{1-z^{-4}}{1-z^{-1}}
\]
But if we're going to be throwing away 75% of the calculated values,
can't we just move the downsampler from the end of the pipeline to
somewhere in the middle? Right between the integrator stage and the comb
stage? That answer is yes, but to keep the math working, we
also need to divide the number of delay elements in the comb stage by
the decimation rate:
B. Sadhu and R. Harjani, "Capacitor bank design for wide tuning range
LC VCOs: 850MHz-7.1GHz (157%)," Proceedings of 2010 IEEE International
Symposium on Circuits and Systems, Paris, France, 2010 [https://sci-hub.st/10.1109/ISCAS.2010.5537040]
TODO 📅
large value KVCO is not favorable due to noise and possibly spurs at
the control voltage
LC Tank
Definitions of Q
Assuming RLC oscillator waveform is \(V_0\sin\omega_0 t\) and \(\omega_0 = \frac{1}{\sqrt{LC}}\) is
resonance frequency. suppose the current through \(R\) is cancelled out by additional \(-R\)
Energy stored \[
E_t = \frac{1}{2}LI_0^2 =
\frac{1}{2}L(C\omega_0V_0)^2=\frac{1}{2}LC^2\omega_0^2 V_0^2 =
\frac{1}{2}CV_0^2
\] Energy Dissipated per Cycle \[
E_d = \frac{V_0^2}{2R}\frac{2\pi}{\omega_0}
\] For \(Q_4\)\[
Q_4 = 2\pi\frac{E_s}{E_d} = R\omega_0C = \frac{R}{\omega_0L}
\]
For \(Q_3\), suppose RLC tank is
driven by \(V_o\cos \omega t\) voltage
source, then
Peak Magnetic Energy\[
E_{pL} = \frac{1}{2}LI_0^2 =
\frac{1}{2}L\left(\frac{V_0}{L\omega}\right)^2
\]Peak Electric Energy\[
E_{pC} = \frac{1}{2}CV_0^2
\] with Energy Lost per Cycle\(E_d =
\frac{V_0^2}{2R}\frac{2\pi}{\omega_0}\), we have \[
Q_3 = \frac{E_{pL} - E_{pC}}{E_d} =
\left(\frac{1}{L\omega^2}-C\right)R\omega=\frac{R}{L\omega}\left(1 -
\frac{\omega^2}{\omega^2_{SR}}\right)
\]
Owing to switch-off PMOS eliminating common mode current, all \(I_T\) is differentially flowing in the
tank.
current limited vs voltage
limited
Cross-coupled
Differential-pair
?? Triode MOS noise
Common-Mode Effects
P. Liu et al., "A 128Gb/s ADC/DAC Based PAM-4 Transceiver with
>45dB Reach in 3nm FinFET," 2025 Symposium on VLSI Technology and
Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025
E. Hegazi, H. Sjoland and A. Abidi, "A filtering technique to lower
oscillator phase noise," 2001 IEEE International Solid-State
Circuits Conference. Digest of Technical Papers. ISSCC (Cat.
No.01CH37177), San Francisco, CA, USA, 2001 [paper,
slides]
—, "25.3 A VCO with implicit common-mode resonance," 2015 IEEE
International Solid-State Circuits Conference - (ISSCC) Digest of
Technical Papers, San Francisco, CA, USA, 2015 [https://sci-hub.st/10.1109/ISSCC.2015.7063116]
D. Murphy, H. Darabi and H. Wu, "Implicit Common-Mode Resonance in LC
Oscillators," in IEEE Journal of Solid-State Circuits, vol. 52, no. 3,
pp. 812-821, March 2017, [https://sci-hub.st/10.1109/JSSC.2016.2642207]
M. Shahmohammadi, M. Babaie and R. B. Staszewski, "A 1/f Noise
Upconversion Reduction Technique for Voltage-Biased RF CMOS
Oscillators," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11,
pp. 2610-2624, Nov. 2016 [pdf]
—. "Harmonic Oscillators in CMOS—A Tutorial Overview," in IEEE Open
Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021 [pdf]
C. Samori, "Tutorial: Understanding Phase Noise in LC VCOs," 2016
IEEE International Solid-State Circuits Conference (ISSCC), San
Francisco, CA, USA, 2016
—, "Understanding Phase Noise in LC VCOs: A Key Problem in RF
Integrated Circuits," in IEEE Solid-State Circuits Magazine,
vol. 8, no. 4, pp. 81-91, Fall 2016 [https://sci-hub.se/10.1109/MSSC.2016.2573979]
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007
Manetakis, K. (2023). Topics in LC Oscillators: Principles, phase
noise, pulling, inductor design. Springer Nature Switzerland
Springer. [eetop
link]
K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and
J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL
Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE
Workshop on Design and Diagnostics of Electronic Circuits and
Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]
Due to \(f= K_{vco}V_{ctrl}\), its
derivate to \(t\) is \[
\frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt}
\]
For chargepump PLL, \(dV_{ctrl} =
\frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[
\frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C}
\]
Refclk Clocking
Architectures
PCI Express Base Specification Revision 3.0
Jeff Morriss, Intel Gerry Talbot, AMD. PCI-SIG Devcon 2006. Jitter
Budgeting for Clock Architecture
Common Refclk Rx architectures are characterized by the Tx and Rx
sharing the same Refclk source
Most of the SSC jitter sourced by the Refclk is propagated equally
through Tx and Rx PLLs, and so intrinsically tracks LF
jitter
The amount of jitter appearing at the CDR is then defined by the
difference function between the Tx and Rx PLLs multiplied by the
CDR highpass characteristic
\[
H(s)= H_1(s)e^{-sT} - \left[H_1(s)e^{-sT}(1-H_3(s)) + H_2(s)H_3(s)
\right] = [H_1(s)e^{-sT} -H_2(s)]H_3(s)
\] where \(H_3(s)\) is similar
to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Data Clocked Refclk Rx
Architecture
A data clocked Rx architecture is characterized by requiring the
receiver's CDR to track the entirety of the low frequency jitter,
including SSC
Separate Reference
Clocks with SSC (SRIS)
TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE:
Updated 10 January 2013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev.
3.0 SPONSOR: Intel, HP, AMD
\[\begin{align}
X_{LATCH}(s) &= X_1(s)H_1(s) - \left[X_1(s)H_1(s)(1-H_3(s)) +
X_2(s)H_2(s)H_3(s) \right] \\
& = \left[X_1(s)H_1(s) -X_2(s)H_2(s)\right]H_3(s)
\end{align}\] where \(H_3(s)\)
is similar to \(NTF_{VCO}\), \(1-H_3(s)\) is similar to \(NTF_{REF}\)
Separate Reference
Clocks with No SSC (SRNS)
SSC on digital CDR
Gerry Talbot, "Impact of SSC on CDR" , April 12th, 2012, PCI Express
EWG
K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang and
J. -W. Miaw, "A Spread-Spectrum Clock Generator Using Fractional-N PLL
Controlled Delta-Sigma Modulator for Serial-ATA III," 2008 11th IEEE
Workshop on Design and Diagnostics of Electronic Circuits and
Systems, Bratislava, Slovakia, 2008 [https://sci-hub.se/10.1109/DDECS.2008.4538758]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
the interpolating inverters near the midscale can be made weaker so
as to obtain more uniform phase increments. Alternatively, those at the
top and bottom of the array can be made stronger
Single-Quadrant PI
\[
V_o(t) = m \cdot \sin(\omega t + \frac{\pi}{2}) + p\cdot \sin(\omega t)
= m\cdot \cos(\omega t) + p\cdot \sin(\omega t) = \sqrt{m^2+p^2}
\sin(\omega t + \phi)
\]
where \(\tan \phi = \frac{m}{p} =
\frac{1-p}{p}\) and \(p =
\frac{1}{1+\tan \phi}\)
A constant Output amplitude is desired because the
swing-dependent delay characteristic of the CML-to-CMOS (C2C)
circuit results in AM–PM distortion which eventually manifests
as phase nonlinearity
Current-Mode Phase
Interpolator
Voltage-Mode Phase
Interpolator
Integrating-Mode Phase
Interpolator
PI vs. PLL based CDR
PCI Express Jitter Modeling Revision 1.0RD July 14, 2004
reference
A. K. Mishra, Y. Li, P. Agarwal and S. Shekhar, "Improving Linearity
in CMOS Phase Interpolators," in IEEE Journal of Solid-State Circuits,
vol. 58, no. 6, pp. 1623-1635, June 2023 [pdf]
Cortiula A, Menin D, Bandiziol A, Driussi F, Palestri P. Modeling of
Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4
Serial Interfaces. Electronics. 2025; [https://www.mdpi.com/2079-9292/14/10/1979]
G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based
Clock and Data Recovery With Jitter Optimization," in IEEE Open
Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/document/10184121]
Beer, Salomon & Priel, Michael & Dobkin, Rostislav &
Kolodny, Avinoam. (2010). The Devolution of Synchronizers. Proceedings -
International Symposium on Asynchronous Circuits and Systems. [pdf]
\(T_W\), metastability window is
defined differently among published paper
Some PDK provide \(T_0\) and \(\tau\) for the corresponding cascaded flip
flop synchronizer stdcells \[
\text{MTBF} = \frac{1}{T_W\times f_C\times f_D}\space \space
\text{,where}\space\space T_W = T_0 e^{-T_r/\tau}
\] and \(T_r = T_C - T_{DLY} -
T_{SU}\)
Synchronizer
Characterization
I. W. Jones, S. Yang and M. Greenstreet, "Synchronizer Behavior and
Analysis," 2009 15th IEEE Symposium on Asynchronous Circuits and
Systems, Chapel Hill, NC, USA, 2009 [https://sci-hub.ru/10.1109/ASYNC.2009.8]
Xprova. bisect-tau - EDA tool for characterizing the metastability
resolution time constant (Tau) of bistable circuits [https://github.com/xprova/bisect-tau]
For GNU Octave, version 8.4.0, ngspice-42 : Circuit
level simulation program@Ubuntu 24.04.3 LTS x86_64
The typical flip-flops comprise master and slave latches and
decoupling inverters.
In metastability, the voltage levels of nodes A and B of the
master latch are roughly midway between logic 1 (VDD) and 0
(GND)
master latch enter metastability
In fact, one popular definition says that if the output of a
flip-flop changes later than the nominal clock-to-Q propagation
delay, then the flip-flop must have been metastable
Noise Seed—Seed for the random number generator (used by
the simulator to vary the noise sources internally). Specifying the
same seed allows you to reproduce a previous
experiment. The default value is 1.
Kinniment, D. J. Synchronization and arbitration in digital systems.
John Wiley & Sons Ltd (2007).
Synchronizers And Data FlipFlops are Different [pdf]
S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The
Devolution of Synchronizers," 2010 IEEE Symposium on Asynchronous
Circuits and Systems, Grenoble, France, 2010 [pdf]
The most significant impairments are considered to be the sensitivity
to sampling phase, and the effect of aliasing out of band signal and
noise into the baseband
D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J.
Savory, "A baud-rate sampled coherent transceiver with digital pulse
shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]
Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end
Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]
Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for
High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]
Notice that the requirements of the first stage
are very demanding
replicas suppression
The spectrum of the high resolution digital signal \(u_1\) contains the original
baseband portion and its replicas located at integer
multiples of \(f_{s1}\), plus
a small amount of quantization noise shown as
a solid line
DC gain is used to compensate the ratio of sampling rate before and
after upsample
Given \[
X_e = X = \propto \frac{1}{T} = \frac{1}{L\cdot T_i}
\] Then, the lowpass filter (ZOH, FOH .etc) gain shall be \(L\)
Employ definition of DTFT, \(X(e^{j\hat{\omega}})
=\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n}\), and set
\(\hat{\omega} = 0\)\[
X(e^{j0}) = \sum_{n=-\infty}^{+\infty}x[n]
\] That is, \(\sum_{n=-\infty}^{+\infty}x[n] =
\sum_{n=-\infty}^{+\infty}x_e[n]\), so \[
\overline{x_e[n]} = \frac{1}{L} \overline{x[n]}
\] It also indicate that dc gain of upsampling is \(1/L\)
a high normal mode
rejection ratio
(NMRR) for input noise at line
frequency
Conversion accuracy is independent of both the capacitance and
the clock frequency, because they affect both the up-slope and the
down-slope by the same ratio
The fixed input signal integration period results in rejection of
noise frequencies on the analog input that have periods that are equal
to or a sub-multiple of the integration time \(T\)
Interference signals with frequencies at integral multiples of the
integration period are, theoretically, completely removed,
since the average value of a sine wave of frequency
(\(1/T\)) averaged
over a period (\(T\)) is
zero
