扭矩 = 力 x 力臂 (T=FL)
变速箱实现转速和扭矩的转换：低档扭矩大，转速慢； 高档扭矩小，转速慢
发动机小齿轮和变速箱大齿轮啮合处的力相同（力的作用是相互的），但是力臂不同，于是实现了扭矩转换
loop latency is represented as \(e^{-sD}\) in linear model
Sub-Resolution Time Averaging
\(\Delta \Sigma\) modulator effectively dithers the LSB bit between zero and one, such that you can get the effective resolution of a much higher resolution DAC in the number of bits
DLF's input bit-width can be reduced by decimating BBPD's output. Decimation is typically performed by realizing either majority voting (MV) or boxcar filtering.
Note that deserialization is inherent to both MV and boxcar filtering
condition:
Linear model of the CDR is used in a frequency lock condition and is approaching to achieve phase lock
Using this model, the power spectral density (PSD) of jitter in the recovered clock \(S_{out}(f)\) is \[ S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f) \] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they come from independent sources.
\[ H_T(s) = \frac{\varphi_{out}(s)}{\varphi_{in}(s)}|_{\varphi_{vco}=0}=\frac{K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}}{s^2+K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}} \]
Using below notation \[\begin{align} \omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\ \xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2} \end{align}\]
We can rewrite transfer function as follows \[ H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2} \]
The jitter transfer represents a low-pass filter whose magnitude is around 1 (0 dB) for low jitter frequencies and drops at 20 dB/decade for frequencies above \(\omega_n\)
The recovered clock does not suffer from high-frequency jitter even though the input signal may contain high-frequency jitter, which will limit the CDR tolerance to high-frequency jitter.
The peak, slightly larger than 1 (0dB) implies that jitter will be amplified at some frequencies in the CDR, producing a jitter amplitude in the recovered clock, and thus also in the recovered data, that is slightly larger than the jitter amplitude in the input data.
This is certainly undesirable, especially in applications such as repeaters.
If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the recovered clock comes directly from the VCO jitter. The transfer function that relates the VCO jitter to the recovered clock jitter is known as jitter generation. \[ H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi \omega_n s+\omega_n^2} \] Jitter generation is high-pass filter with two zeros, at zero frequency, and two poles identical to those of the jitter transfer function
To quantify jitter tolerance, we often apply a sinusoidal jitter of a fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR's true tolerance to random jitter. Because we are applying "sinusoidal" jitter, which is deterministic signal.
We can deal only with the jitter's amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
\[
JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad
\text{for a fixed BER}
\] Where the subscript \(\text{pp-max}\) indicates the maximum
peak-to-peak amplitude. We can further expand this equation as follows
\[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_{pp-max}
\] 
Relative jitter, \(\varphi_e\) must be less than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude of \(|\varphi_e(f)|\) is 1UI, i.e.,\(|\varphi_e(f)|_{pp-max}=1UI\)
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as \[
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
\] Given the linear CDR model, we can write \[
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
\] Expand \(H_{LF}(f)\) for the
CDR, we can write \[
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
\] 
At frequencies far below and above the natural frequency, the jitter tolerance can be approximated by the following \[ JTOL(f) = \left\{ \begin{array}{cl} \left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\ 1 & : \ f\gg f_n \end{array} \right. \]
Simplified Block Diagram of a Clock-Recovery PLL 
Jitter Transfer Function (JTF)
Observed Jitter Transfer Function
JTF and OJTF for 1st Order PLLs
The observed jitter is a complement to the PLL jitter transfer response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not observed at the output of the CDR as a function of the jitter rate applied to the input.
\[ J_{\text{measured}} = JTF_{\text{DUT}} \cdot OJTF_{\text{instrument}} \]
The combination of the OJTF of a jitter measurement device and the JTF of the clock generator under test gives the measured jitter as a function of frequency.
For example, a clock generator with a type 1, 1st order PLL measured with a jitter measurement device employing a golden PLL is \[ J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2} \]
Accurate measurement of the clock JTF requires that the OJTF cutoff of the jitter measurement be significantly below that of the clock JTF and that the measurement is compensated for the instrument's OJTF.
The overall response is a band pass filter because the clock JTF is low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring the jitter of the reference clock at each jitter rate being tested and comparing the reference jitter with the jitter measured at the output of the DUT.
The lower the cutoff frequency of the jitter measurement device the better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the phase noise of the DUT and measurement time.
How to analyze jitter:
TIE track provides a direct view of how the phase of the clock evolves over time.
histogram provides valuable information about the long term variations in the timing.
FFT allows jitter at specific rates to be measured down to the femto-second range.
Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop bandwidth minimizes the response error
Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and Phase Noise: A Circuits and Systems Perspective.” (2018).
neuhelium, 抖动、眼图和高速数字链路分析基础 URL: http://www.neuhelium.com/ueditor/net/upload/file/20200826/DSOS254A/03.pdf
Keysight JTF & OJTF Concepts, https://rfmw.em.keysight.com/DigitalPhotonics/flexdca/FlexPLL-UG/Content/Topics/Quick-Start/jtf-pll-theory.htm?TocPath=Quick%20Start%7C_____4
Complementary Transmitter and Receiver Jitter Test Methodlogy, URL: https://www.ieee802.org/3/bm/public/mar14/ghiasi_01_0314_optx.pdf
SerDesDesign.com CDR_BangBang_Model URL: https://www.serdesdesign.com/home/web_documents/models/CDR_BangBang_Model.pdf
M. Schnecker, Jitter Transfer Measurement in Clock Circuits, LeCroy Corporation, DesignCon 2009. URL: http://cdn.teledynelecroy.com/files/whitepapers/designcon2009_lecroy_jitter_transfer_measurement_in_clock_circuits.pdf
TODO 📅
respone to vctrl focus on phase
[https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va]
TODO 📅
ENOB - Not sufficient & not accurate enough
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
"total harmonic distortion" (THD) in AFE
Relative to NRZ-based systems, PAM4 transceivers require more stringent circuit linearity, equalizers which can implement multi-level inter-symbol interference (ISI) cancellation, and improved sensitivity
Because if it compresses, it turns out you have to use a much more complicated feedback filter. As long as it behaves linearly, the feedback filter itself can remain a linear FIR
Linearity can actually be a critical constraint in these signal paths, and you really want to stay as linear as you can all the way up until the point where you've canceled all of the ISI
A. Roshan-Zamir, O. Elhadidy, H. -W. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sept. 2017 [https://people.engr.tamu.edu/spalermo/ecen689/2017_reconfigurable_16_32Gbps_NRZ_PAM4_SERDES_roshanzamir_jssc.pdf]
Hongtao Zhang, designcon2016. "PAM4 Signaling for 56G Serial Link Applications − A Tutorial"[https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers"
\[ \text{Var}(X) = E[X^2] - E[X]^2 \]
TX FFE suffers from the peak power constraint, which in effect attenuates the average power of the outgoing signal - the low-frequency signal content has been attenuated down to the high-frequency level
S. Palermo, "CMOS Nanoelectronics Analog and RF VLSI Circuits," Chapter 9: High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems, McGraw-Hill, 2011.
An architecture that evaluates the received signal quality
data slicers, phase slicers, error slicers, scope slicers
Analui, Behnam & Rylyakov, Alexander & Rylov, Sergey & Meghelli, Mounir & Hajimiri, Ali. (2006). A 10-Gb/s two-dimensional eye-opening monitor in 0.13-??m standard CMOS. Solid-State Circuits, IEEE Journal of. 40. 2689 - 2699, [https://chic.caltech.edu/wp-content/uploads/2013/05/B-Analui_JSSC_10-Gbs_05.pdf]
G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link Foundations Standards, Link Budgets & Models," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95 [https://youtu.be/OABG3u2H2J4?si=CxryBSGbxrUpZNBT]
Paul Muller Yusuf Leblebici École Polytechnique Fédérale de Lausanne (EPFL). Pattern generator model for jitter-tolerance simulation; VHDL-AMS models
Savo Bajic, ECE1392, Integrated Circuits for Digital Communications: StatOpt in Python [https://savobajic.ca/projects/academic/statopt]
Anritsu Company, "Measuring Channel Operating Margin," 2016. [https://dl.cdn-anritsu.com/en-us/test-measurement/files/Technical-Notes/White-Paper/11410-00989A.pdf]
JLSD - Julia SerDe [https://github.com/kevjzheng/JLSD]
Kiran Gunnam, Selected Topics in RF, Analog and Mixed Signal Circuits and Systems
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part I: Modeling," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 97-109, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10608184]
H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part II: Optimization and Performance Assessment," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10184121]
hunting jitter is also called as dithering jitter the time error between data clock and input data
- proportional gain
- loop latency
where the proportional gain (\(K_P\)), heavily damped systems means that \(K_P \gg K_I\)
Hanumolu, Pavan Kumar. 2006. Design Techniques for Clocking High Performance Signaling Systems. : Oregon State University. https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]
Hae-Chang Lee, "An Estimation Approach To Clock And Data Recovery" [https://www-vlsi.stanford.edu/people/alum/pdf/0611_HaechangLee_Phase_Estimation.pdf]
R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” in Phase-Locking in High-Performance Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
J. Kim, Design of CMOS Adaptive-Supply Serial Links, Ph.D. Thesis, Stanford University, December 2002. [https://www-vlsi.stanford.edu/people/alum/pdf/0212_Kim_______Design_Of_CMOS_AdaptiveSu.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps Digital Clock and Data Recovery Circuit," IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]
Da Dalt N. A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]
Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phasefrequency detection. IEEE Transactions on Circuits and Systems II: Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]
Denoting the CDR loop latency by \(\Delta T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The resulting right-half-plane zero, \(f_z\) degrades the phase margin and must remain about one decade beyond the BW \[ f_z\simeq \frac{1}{2\pi \Delta T} \]
This assumption is true in practice since the bandwidth of the CDR (few mega Hertz) is much smaller than the data rate (multi giga bits/second).
Fernando , Marvell Italy."Considerations for CDR Bandwidth Proposal" [https://www.ieee802.org/3/bs/public/16_03/debernardinis_3bs_01_0316.pdf]
The closed-loop −3-dB bandwidth is sometimes called the “loop bandwidth”
A rule of thumb often used to ensure slow changes in the loop is to select the loop bandwidth approximately equal to one-tenth of the input frequency.
Gardner, F.M. (1980). Charge-Pump Phase-Lock Loops. IEEE Trans. Commun., 28, 1849-1858.
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
Deog-Kyoon Jeong, Topics in IC Design - 2.1 Introduction to Phase-Locked Loop [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%202%20-%20Charge-Pump%20PLL%2C%20Freuqency%20Synthesizers%2C%20and%20SSCG.pdf]
limit cycles imply self-sustained oscillators due nonlinear nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]
It's ternary, because early, late and no transition
BB Gain is the slope of average BB output \(\mu\), versus phase offset \(\phi\), i.e. \(\frac {\partial \mu}{\partial \phi}\),
BB only produces output for a transition and this de-rates the gain. Transition density = 0.5 for random data
\[ K_{BB} = \frac{1}{2}\frac {\partial \mu}{\partial \phi} \]
where \(\mu = (1)\times \mathrm{P}(\text{late}|\phi) + (-1)\times \mathrm{P}(\text{early}|\phi)\)
Both jitter and amplitude noise distribution are same, just scaled by slope
One price we pay for BB PD versus linear PD is the self-noise term. For small phase errors BB output noise is the full magnitude of the sliced data.
BB-PD don't have any measure as to how early or how late and the way that tell loop is locked, is over a long time average, BB-PD have an equal number of earlies and lates
\[\begin{align} \sigma_{BB} &= [E(X^2) - E(X)^2] \cdot \mathrm{P}(\text{trans}) \\ &= [1 - 0]\cdot 0.5 \\ &= 0.5 \end{align}\]
John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and Data Recovery
Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems. [pdf]
- Clock and Data Recovery for Serial Data Communications, focusing on bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]
The difference equation is \[ \phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi \] z-transform is \[ \frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}} \]
where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)
Here, \(\alpha_T\) is data transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
simple approximation: \[ z = 1 + sT \] bilinear-z transform \[ z =\frac{}{} \]
accumulating the input for \(N\) cycles and then latching the result and resetting the integrator
It adds up \(N\) succeeding input samples at rate \(1/T\) and delivers their sum in a single sample at the output. Therefore, the process comprises a filter (in the accumulation) and a down-sampler (in the dump)
cascade-integrator-comb (CIC) decimator
TODO 📅
An Intuitive Look at Moving Average and CIC Filters [web, code]
A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters [https://www.dsprelated.com/showarticle/1337.php]
TODO 📅
Tristate: \(\alpha=1\)
XOR: \(\alpha=1\)
\(\frac{1}{T}\) in Divider
Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]
\(\frac{1}{T}\) & \(T\) come from CT-DT & DT-CT
H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10630516]
| PLL | CDR |
|---|---|
| Clock edge periodic | Data edge random |
| Phase & Frequency detecting possible | Phase detecting possible , Frequency detecting impossible |
PLL or FD(Frequency Detector) for frequency detecting in CDR
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and Circuits" [slides]
Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery Circuits"
Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems" [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems (lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT OpenCourseWare, [lec21.pdf]
Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental Concepts To Future Trends" [T5.pdf]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
J. Sonntag and J. Stonick, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
Liu, Tao, Tiejun Li, Fangxu Lv, Bin Liang, Xuqiang Zheng, Heming Wang, Miaomiao Wu, Dechao Lu, and Feng Zhao. 2021. "Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits" Electronics 10, no. 16: 1888. https://doi.org/10.3390/electronics10161888
Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1. [https://assets-eu.researchsquare.com/files/rs-1817774/v1_covered.pdf?c=1664188179]
H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10630516]
Marinaci, Stefano. "Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate" [https://cds.cern.ch/record/2870334/files/CERN-THESIS-2023-147.pdf]
P. Palestri et al., "Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]
F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]
Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol. 41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]
M.H. Perrott. CICC 2009 "Tutorial on Digital Phase-Locked Loops" [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]
-, Short Course On Phase-Locked Loops and Their Applications Day 4, PM Lecture "Examples of Leveraging Digital Techniques in PLLs" [https://www.cppsim.com/PLL_Lectures/day4_pm.pdf]
-, Short Course On Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA "Digital Frequency Synthesizers" [https://www.cppsim.com/PLL_Lectures/digital_pll.pdf]
Deog-Kyoon Jeong Topics in IC(Wireline Transceiver Design) - 3.1. Introduction to All Digital PLL [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]
Deog-Kyoon Jeong Topics in IC(Wireline Transceiver Design) - 6.1 Introduction to Clock and Data Recovery [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]
High-speed Serial Interface Lect. 16 – Clock and Data Recovery 3 [http://tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect16_CDR-3.pdf]
TODO 📅
To compare the ring oscillator and VCO the total injected charge to both should be the same
Yizhe Hu, "A Simulation Technique of Impulse Sensitivity Function (ISF) Based on Periodic Transfer Function (PXF)" [https://bbs.eetop.cn/thread-869343-1-1.html]
David Dolt. ECEN 620 Network Theory - Broadband Circuit Design: "VCO ISF Simulation" [https://people.engr.tamu.edu/spalermo/ecen620/ISF_SIM.pdf]
The spectrum of the narrowband FM signal is very similar to that of an amplitude modulation (AM) signal but has the phase reversal for the other sideband component
Assume the modulation frequency of PM and AM are same, \(\omega_m\)
\[\begin{align} x(t) &= (1+A_m\cos{\omega_m t})\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= \cos(\omega_0 t + P_m \sin\omega_m t) + A_m\cos{\omega_m t}\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= X_{pm}(t) + X_{apm}(t) \end{align}\]
\(X_{pm}(t)\), PM only part \[ X_{pm}(t) = \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{P_m}{2}\cos(\omega_0 + \omega_m)t \] \(X_{apm}(t)\), AM & PM part \[\begin{align} X_{apm}(t) &= A_m \cos{\omega_m t} (\cos\omega_0 t-P_m\sin\omega_m t\sin\omega_0 t) \\ &= \frac{A_m}{2}[\cos(\omega_0 + \omega_m)t + \cos(\omega_0 -\omega_m)t] - \frac{A_mP_m}{2}\sin(2\omega_m t)\sin(\omega_0 t) \\ &= \frac{A_m}{2}\cos(\omega_0 + \omega_m)t + \frac{A_m}{2}\cos(\omega_0 -\omega_m)t - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]
That is \[\begin{align} x(t) &= \cos\omega_0 t + \frac{A_m-P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{A_m+P_m}{2}\cos(\omega_0 + \omega_m)t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]
For general case, \(x(t) = (1+A_m\cos{\omega_{am} t})\cos(\omega_0 t + P_m \sin\omega_{pm} t)\), i.e., PM is \(\omega_{pm}\), AM is \(\omega_{am}\)
\[\begin{align} x(t) &= \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_{pm})t + \frac{P_m}{2}\cos(\omega_0 + \omega_{pm})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_m}{2}\cos(\omega_0 - \omega_{am})t + \frac{A_m}{2}\cos(\omega_0 + \omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}-\omega_{am})t + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}+\omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}-\omega_{am})t - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}+\omega_{am})t \end{align}\]
Therefore, sideband is asymmetric if \(\omega_{pm} = \omega_{am}\)
Ken Kundert, Measuring AM, PM & FM Conversion with SpectreRF [https://designers-guide.org/analysis/am-pm-conv.pdf]
Balu Santhanam, Probability Theory & Stochastic Process 2020: Modulation of Random Processes
Hayder Radha, ECE 458 Communications Systems Laboratory Spring 2008: Lecture 7 - EE 179: Introduction to Communications - Winter 2006–2007 Energy and Power Spectral Density and Autocorrelation
Balu Santhanam, Probability Theory & Stochastic Process 2020: Impulse sampling of Random Processes
That is \[ P_{x_s x_s} (f)= \frac{1}{T_s^2}P_{xx}(f) \] where \(x[n]\) is sampled discrete-time sequence, \(x_s(t)\) is sampled impulse train
apply foregoing observation
[https://ece-research.unm.edu/bsanthan/ece541/cyclo.pdf]
Noisy Resistor & Clocked Switch
\[ v_t (t) = v_i(t)\cdot m_t(t) \] where \(v_i(t)\) is input white noise, whose autocorrelation is \(A\delta(\tau)\), and \(m_t(t)\) is periodically operating switch, then autocorrelation of \(v_t(t)\) \[\begin{align} R_t (t_1, t_2) &= E[v_t(t_1)\cdot v_t(t_2)] \\ &= R_i(t_1, t_2)\cdot m_t(t_1)m_t(t_2) \end{align}\]
Then \[\begin{align} R_t(t, t-\tau) &= R_i(\tau)\cdot m_t(t)m_t(t-\tau) \\ & = A\delta(\tau) \cdot m_t(t)m_t(t-\tau) \\ & = A\delta(\tau) \cdot m_t(t) \end{align}\] Because \(m_t(t)=m_t(t+T)\), \(R_t(t, t-\tau)\) is is periodic in the variable \(t\) with period \(T\)
The time-averaged ACF is denoted as \(\tilde{R_t}(\tau)\)
\[ \tilde{R}_{t}(\tau) = m\cdot A\delta(\tau) \] That is, \[ S_t(f) = m\cdot S_{A}(f) \]
\[
\tilde{R_t}(\tau) = R_i(\tau)\cdot m_{tac}(\tau)
\]
where \(m_t(t)m_t(t-\tau)\) averaged on \(t\) is denoted as \(m_{tac}(\tau)\) or \(\overline{m_t(t)m_t(t-\tau)}\)
The DC value of \(m_{tac}(\tau)\) can be calculated as below
for \(m\le 0.5\), the DC value of \(m_{tac}(\tau)\) \[ \frac{m\cdot mT}{T} = m^2 \]
for \(m\gt 0.5\), the DC value of \(m_{tac}(\tau)\) \[ \frac{(m+2m-1)(1-m)T + (2m-1)\{mT -(1-m)T\}}{T} = m^2 \]
Therefore, time-average power spectral density and total power are scaled by \(m^2\) in fundamental frequency sideband
zoom in first harmonic by linear step of pnoise
decreasing the rising/falling time of clock, the harmonics still retain
Much like sinusoidal-steady-state signal analysis, steady-state noise analysis methods assume an input x(t) of infinite duration, which is a Wide-Sense Stationary (WSS) random process
The output \(y(t)\) of a linear time-invariant (LTI) system \(h(t)\) \[\begin{align} R_{yy}(\tau) &= R_{xx}(\tau)*[h(\tau)*h(-\tau)] \\ &= S_{xx}(0)\delta(\tau) * [h(\tau)*h(-\tau)] \\ &= S_{xx}(0)[h(\tau)*h(-\tau)] \\ &= S_{xx}(0) \int_\alpha h(\alpha)h(\alpha-\tau)d\alpha \end{align}\]
with WSS white noise input \(x(t)\), \(R_{xx}(\tau)=S_{xx}(0)\delta(\tau)\), therefore
Assuming the noise applied duration is much less than the time constant, the output voltage does not reach steady-state and WSS noise analysis does not apply
In order to determine the response of an LTI system to a step noise input, the problem is more conveniently solved in the time-domain
input signal: step ramp input
noise current: step
The step noise input \(x(t) =
\nu(t)u(t)\) \[
R_{xx}(t_1,t_2) = E[x(t_1)x(t_2)] = R_{\nu\nu}(t_1,
t_2)u(t_1)u(t_2)=R_{\nu\nu}(t_1, t_2)
\] 
\[ R_{xy}(t_1, t_2) = E[x(t_1)y(t_2)] = E[x(t_1)(x(t_2)*h(t_2))] = E(x(t_1)x(t_2))*h(t_2) = R_{xx}(t_1,t_2)*h(t_2) \]
\[ R_{yy}(t_1,t_2) = E[y(t_1)y(t_2)] = E[(x(t_1)*h(t_1))y(t_2)] = E[x(t_1)y(t_2)]*h(t_1)=R_{xy}(t_1,t_2)*h(t_1) \]
the absolute value of each time index is important for a non-stationary signal, and only the time difference was important for WSS signals
\[\begin{align} R_{yy}(t_1,t_2) &= h(t_1)*R_{\nu\nu}(t_1, t_2)*h(t_2) \\ &= h(t_1)*S_{xx}(0)\delta(t_2-t_1)*h(t_2) \\ &=S_{xx}(0) h(t_1)*(\delta(t_2-t_1)*h(t_2)) \\ &= S_{xx}(0)h(t_1)*h(t_2-t_1) \\ &= S_{xx}(0)\int_\tau h(\tau)h(t_2-t_1+\tau))d\tau \end{align}\]
That is \[ \sigma^2_y (t)= R_{yy}(t_1,t_2)|_{t_1=t_2=t}=S_{xx}(0)\int_{-\infty}^t |h(\tau)|^2d\tau \]
\(t\), the upper limit of integration is just intuitive, which lacks strict derivation
Because stable systems have impulse responses that decay to zero as time goes to infinity, the output noise variance approaches the WSS result as time approaches infinity
Because the definition of the PSD assumes that the variance of the noise process is independent of time, the PSD of a non-stationary process is not very meaningful
Noise Voltage to Timing Jitter Conversion & noise gain
with a step ramp input \(v_X(t) = Mtu(t)\)
The noise gain is \[
|A_N(t_i)| = A_0 (1-e^{t_i/\tau_o})u(t)
\] where \(t_i\) is crossing
time of ideal threshold comparator
\[\begin{align}
\overline{v_n^2} &= \frac{\overline{v_{on}^2}}{|A_N|^2} \\
&=
\frac{G_n}{G_m}\frac{kT}{C}\frac{1}{A_0}\frac{1+e^{-t_i/\tau_o}}{1-e^{-t_i/\tau_o}}
\\
&=4kT\frac{G_n}{G_m^2}\frac{1}{4R_oC} \coth(\frac{t_i}{2\tau_o}) \\
&= 4kTR_n\frac{1}{4\tau_o} \coth(\frac{t_i}{2\tau_o})
\end{align}\]
where \(R_n = \frac{G_n}{G_m^2}\), the equivalent thermal noise resistance
Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]
R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]
John G. Proakis and Masoud Salehi, Fundamentals of communication systems 2nd ed [pdf]
Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons
Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers, oscillators, samplers, and logic: an introduction to cyclostationary noise." Proceedings of the IEEE 2000 Custom Integrated Circuits Conference. [pdf, slides]
Antoni, J., "Cyclostationarity by examples", Mechanical Systems and Signal Processing, vol. 23, no. 4, pp. 987–1036, 2009 [https://docente.unife.it/docenti/dleglc/a-a-2010-2011-dmsm/ciclostazionarieta.pdf]
Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF. URL:https://designers-guide.org/analysis/sc-filters.pdf
STEADY-STATE AND CYCLO-STATIONARY RTS NOISE IN MOSFETS [https://ris.utwente.nl/ws/portalfiles/portal/6038220/thesis-Kolhatkar.pdf]
Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]
T. Sepke, P. Holloway, C. G. Sodini and H. -S. Lee, "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009 [https://dspace.mit.edu/bitstream/handle/1721.1/61660/Speke-2009-Noise%20Analysis%20for%20Comparator-Based%20Circuits.pdf]
Sepke, Todd. "Comparator design and analysis for comparator-based switched-capacitor circuits." (2006). [https://dspace.mit.edu/handle/1721.1/38925]
PID controller makes use of linear extrapolation of the measured output
PI controller does not make use of any prediction of the future state of the system
The prediction by linear extrapolation (D) can generate large undesired control signals because measurement noise is amplified, that's why D is not used widely
Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018. Feedback Control of Dynamic Systems (8th Edition). Pearson.
Åström, K.J. & Murray, Richard. (2021). Feedback Systems: An Introduction for Scientists and Engineers Second Edition [https://www.cds.caltech.edu/~murray/books/AM08/pdf/fbs-public_24Jul2020.pdf]
Yan Lu, ISSCC2021 T10: Fundamentals of Fully Integrated Voltage Regulators [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T10.pdf]
charge pumps are capacitive DC-DC converters. The two most common switched capacitor voltage converters are the voltage inverter and the voltage doubler circuit
To achieve a stable DC output voltage
without load
\[ V_{in} C_p + V_{out,n-1}C_o = (V_{out,n}-V_{in})C_p + V_{out,n}C_o \]
We derive a recursive equation that describes the output voltage \(V_{out,n}\) after the \(n\)th clock cycle \[ V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o} \]
\[\begin{align} (V_t - V_h)(C_p + C_o) &= \frac{I_{load}}{2f_{sw}} \\ (V_h - V_b)C_o &= \frac{I_{load}}{2f_{sw}} \end{align}\]
we obtain \[ V_t - V_b = \frac{I_{load}}{f_{sw}C_o}\left(1 - \frac{C_p}{2(C_p + C_o)}\right) \] That is, peak-to-peak ripple \[ \Delta V_{out,p2p} \approx \frac{I_{load}}{f_{sw}C_o} \space\space\space\space \text{if}\space\space C_o \gg C_p \]
Then, with aforementioned Step-Wise Ramp-Up equation, \(V_t = \frac{2V_{in}C_p + V_bC_o}{C_p + C_o}\) \[\begin{align} V_b &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p}{2C_o}\right) \\ V_t &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 - \frac{C_p}{2(C_p+C_o)}\right) \end{align}\]
Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right) \approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p} \] which results in a simple expression for the output voltage droop
\[ \Delta V_{out} = \frac{I_{load}}{f_{sw}C_p} \]
The charge pump can be modeled as a voltage source with a source resistance \(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage drop across \(R_\text{out}\) due to the load current:
\[
R_{out} = \frac{\Delta V_{out}}{I_{load}} = \frac{1}{f_{sw}C_p}
\] 
increase with switching frequency
slow-switching limit (SSL), fast-switching limit (FSL)
Bernhard Wicht, "Design of Power Management Integrated Circuits". 2024 Wiley-IEEE Press
Breussegem, T. v., & Steyaert, M. (2013). CMOS integrated capacitive DC-DC converters. Springer
Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023).
Anton Bakker, Tim Piessens., ISSCC2014 T9: Charge Pump and Capacitive DC-DC Converter Design
Wicht, B., ISSCC2020 T2: Analog Building Blocks of DC-DC Converters [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T2Visuals.pdf]
Hoi Lee, ISSCC2018 T8: Fundamentals of Switched-Mode Power Converter Design [slides,transcript]
alternative view of sampling, assuming DC value is \(A\)
\(x_c(t)\) and \(x_s(t)\)
\(\overline{x_c} = A\); \(\overline{x_s}=\frac{A}{T}\): therefore \(X_s(j0) = \frac{1}{T}X_c(j0)\)
\(x[n]\) and \(x_d[n]\)
\(\overline{x} = A\); \(\overline{x_d}=\frac{A}{2}\): therefore \(X_d(e^{j0}) = \frac{1}{2}X(e^{j0})\)
expander
\(x[n]\) and \(x_e[n]\)
\(\overline{x} = A\); \(\overline{x_e}=A\): therefore \(X_e(e^{j0}) = X(e^{j0})\)
Fourier transform of the output of the expander is a frequency-scaled version of the Fourier transform of the input
Eqs. (4.72)
the superposition of an infinite set of amplitude-scaled copies of \(X_c(j\Omega)\), frequency scaled through \(\omega = \Omega T_d\) and shifted by integer multiples of \(2\pi\)
Eq. (4.77)
the superposition of \(M\) amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by \(M\) and shifted by integer multiples of \(2\pi\)
downsampled by a factor of \(M = 2\)
downsampling identity
upsampling identity
where \(e_k[n]=h[nM+k]\)
Polyphase Implementation of Decimation Filters & Interpolation Filters
| Decimation system | Interpolation system | |
|---|---|---|
 |
 |
|
 |
 |
|
| sampling identity |  |
 |
TODO 📅
The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a zero-order hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function
Dr. Deepa Kundur, Multirate Digital Signal Processing: Part I [pdf, https://www.comm.utoronto.ca/dkundur/course/discrete-time-systems/]
The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a Zero-Order Hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function
\[
F_1(z) = X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
\]
Split the \(1:LM\) hold process into a \(1 : L\) hold followed by a \(1 : M\) hold \[ Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}} \] then \[\begin{align} F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\ &=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \end{align}\]
That is \(F_1(z)=F_2(z)\), i.e. they are equivalent
Balu Santhanam, Probability Theory & Stochastic Process 2020: Random Signals & Multirate Systems [https://ece-research.unm.edu/bsanthan/ece541/rand.pdf]
The loop gain of a proportional path is unchanged
In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is \[ LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}} \]
In (b), Accumulate-and-dump (AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \] Hence \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot \frac{1}{1-\eta^{-1}} \\ &= \frac{1}{1-\eta^{-1/L}}\cdot \frac{1}{L} \end{align}\]
After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align} \phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &=\frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \end{align}\] That is, \[ LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \]
while bandwidth is less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx 1\), i.e. \(LG_a(z)\approx LG_b(z)\). with
\[ \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx \frac{1}{1-z^{-1}} \]
integral path gain reduced by \(L\)
In (a), \(\phi_o(z)=\frac{1}{(1-z^{-1})^2}\), i.e. \[ LG_a(z) = \frac{1}{(1-z^{-1})^2} \]
In (b), after Accumulate-and-dump (AAD), \(\phi_(\eta)\) is \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \]
After frequency integrator and phase integrator \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \cdot \frac{1}{(1-\eta^{-1})^2} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \cdot \frac{1}{(1-\eta^{-1})^2} \end{align}\] Then \(\phi_f(z)\) is shown as below \[\begin{align} \phi_f(z) &= \phi_o(z^L)\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{(1-z^{-L})^2}\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} \end{align}\]
That is, \[ LG_b(z) = \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} = \frac{1}{L}\cdot LG_a(z) \]
TODO 📅
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]
J. Liang, A. Sheikholeslami, "On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits" [https://tspace.library.utoronto.ca/bitstream/1807/91138/3/Liang_Joshua_201706_PhD_thesis.pdf]
J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]
J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]
M. M. Khanghah, K. D. Sadeghipour, D. Kelly, C. Antony, P. Ossieur and P. D. Townsend, "A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers [https://cora.ucc.ie/bitstreams/7ae5bfaa-8dd9-45a7-8276-99676b7b6078/download]
Alan V Oppenheim, Ronald W. Schafer. 2010. Discrete-Time Signal Processing, 3rd edition
R. E. Crochiere and L. R. Rabiner, "Multirate Digital Signal Processing", Prentice Hall, 1983.
John G. Proakis and Dimitris G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th edition, 2007.
D. Sundararajan. 2024. Digital Signal Processing: An Introduction 2nd Edition
F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]
Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology
Decrease the parasitic R&C
priority: \(R_s \gt R_d\), \(C_s \gt C_d\)
The Cross-Coupled Pair (XCP) can operate as an impedance negator [a.k.a. a negative impedance converter (NIC)]
A common application is to create a negative capacitance that can cancel the positive capacitance seen at a port, thereby improving the speed
\[
I_{NIC} =\frac{V_{im} - V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}} =
\frac{-2V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}}
\] Therefore \[
Z_{NIC} = \frac{V_{ip} - V_{im}}{I_{NIC}}=\frac{2V_{ip}}{I_{NIC}} =-
\frac{2}{g_m}-\frac{1}{sC_c}
\] half-circuit
If \(C_{gd}\) is considered, and apply miller effect. half equivalent circuit is shown as below
B. Razavi, "The Cross-Coupled Pair - Part III [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Issue. 1, pp. 10-13, Winter 2015. [https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine3.pdf]
S. Galal and B. Razavi, "10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18um CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2138-2146, Dec. 2003. [https://www.seas.ucla.edu/brweb/papers/Journals/G&RDec03_2.pdf]
T&H buffer in ADC
Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.
A. Sheikholeslami, "Voltage Follower, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457
Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits (5th. ed.). Wiley Publishing.
\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]
In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end
assume input and reference common voltage are same
Pros of (b)
Cons of (b)
copy aforementioned formula here for convenience \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]
at sample phase \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}= V_\text{cmr}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)
at compare start
\(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{cmr}+\Delta\), \(V_\text{rp}= V_\text{cmr}-\Delta\)
\(I_\text{ip}\lt I_\text{ip0}\), \(I_\text{rp} \gt I_\text{rp0}\)
\(I_\text{im}\gt I_\text{im0}\), \(I_\text{rm} \lt I_\text{rm0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to increase \(V_\text{ip}\) and decrease \(V_\text{im}\).
at the compare finish
\[\begin{align} V_\text{ip}= V_\text{cmi} + \Delta \\ V_\text{im}= V_\text{cmi} - \Delta \end{align}\]
and \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\), \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)
If \(V_\text{cmr} - V_\text{cmi} = \sqrt{2}V_{OV} + \delta\), and \(\delta \gt 0\). one transistor carries the entire tail current
At the end, \(V_\text{im} = V_\text{cmi} - (\Delta - \delta)\), the error is \(\delta\)
In closing, \(V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV}\) for normal work
Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to limited impedance of current source and input pair offset
In the end \[ V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS} \]
Under the condition, every transistor of pairs are on in equilibrium
\[\begin{align} I_{SE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \\ I_{DE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \end{align}\]
The input equivalient offset voltage \[\begin{align} V_{os,SE} &= \frac{I_{SE}}{2g_m} = \frac{\sigma_{vth,0} + \sigma_{vth,1}}{2} \\ V_{os,DE} &= \frac{I_{DE}}{g_m} = \sigma_{vth,0} + \sigma_{vth,1} \end{align}\]
Then \[\begin{align} \sigma_{vos,SE} &= \sqrt{\frac{2\sigma_{vth}^2}{4}} = \frac{\sigma_{vth}}{\sqrt{2}} \\ \sigma_{vos,DE} &= \sqrt{2\sigma_{vth}^2} = \sqrt{2}\sigma_{vth} \end{align}\]
We obtain \[ \sigma_{vos,DE} = 2\sigma_{vos,SE} \]
TODO 📅
How to generate complex poles without inductor? [https://a2d2ic.wordpress.com/2020/02/19/basics-on-active-rc-low-pass-filters/]
Resistive degeneration in differential pairs serves as one major technique for linear amplifier
The linear region for CMOS differential pair would be extended by \(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align} V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\ &= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \end{align}\]
Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf
Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]
Todd Brooks, Broadcom "Input Programmable Gain Amplifier (PGA) Design for ADC Signal Conditioning" [https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/OSU%20Classroom%20Presentaton%20042511.ppt]
Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers" [https://picture.iczhiku.com/resource/eetop/wHKfZPYpAleAKXBV.pdf]
Byungsub Kim, ISSCC 2022, "T11: Basics of Equalization Techniques: Channels, Equalization, and Circuits"
Minsoo Choi et al., "An Approximate Closed-Form Channel Model for Diverse Interconnect Applications," IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct. 2014.
The average output of DSM tracks the input signal
\(\Delta\Sigma\) modulators are nonlinear systems since a quantizer is implemented in the \(\Delta\Sigma\)-loop
TODO 📅
Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.
\[\begin{align} (V_{in} - V_F) &= D_{out} \\ D_{out} &= s V_F \end{align}\]
Therefore \(V_{in} - \frac{D_{out}}{s} = D_{out}\) \[ D_{out} = \frac{s}{s+1} V_{in} \]
attenuates the low-frequency content of the signal, and amplifies high-frequency noise.
\[\begin{align}
v[1] &= u - (0) + e[1] \\
v[2] &= 2u - (v[1]) + e[2] \\
v[3] &= 3u - (v[1]+v[2]) + e[3] \\
v[4] &= 4u - (v[1]+v[2]+v[3]) + e[4]
\end{align}\]
That is \[ v[n] = nu - \sum_{k=1}^{n-1}v[k] + e[n] \] Therefore, we have \(v[n-1] = (n-1)u - \sum_{k=1}^{n-2}v[k] + e[n-1]\), then \[\begin{align} v[n] &= nu - \sum_{k=1}^{n-1}v[k] + e[n] \\ &= u + \left((n-1)u - \sum_{k=1}^{n-2}v[k]\right) - v[n-1] + e[n] \\ &= u + v[n-1] - e[n-1] -v[n-1] + e[n] \\ &= u + e[n] - e[n-1] \end{align}\]
The combination of the the digital post-filter and downsampler is called the decimation filter or decimator
An implementation of a high-resolution integral path using a digital delta-sigma modulator, low-resolution Nyquist DAC, and a lowpass filter
The remaining 11 bits are truncated to 3-levels using a second-order delta-sigma modulator (DSM), thus, obviating the need for a high resolution DAC
Hanumolu, Pavan Kumar. "Design techniques for clocking high performance signaling systems" [https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]
\[\begin{align}
\sum_{i=0}^{n}v[i] + e_\text{DAC}[n] &= y[n] \\
\sum_{i=0}^{n-1}v[i] + e_\text{DAC}[n-1] &= y[n-1]
\end{align}\]
and we have \(w[n] = y[n] - y[n-1]\), then \[ w[n] = v[n] + e_\text{DAC}[n] - e_\text{DAC}[n-1] \] i.e. \[ W = V + (1-z^{-1})e_\text{DAC} \]
Element Rotation:
[http://individual.utoronto.ca/schreier/lectures/12-2.pdf], [http://individual.utoronto.ca/trevorcaldwell/course/Mismatch.pdf]
R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data Converters
Shanthi Pavan, ISSCC2013 T5: Simulation Techniques in Data Converter Design [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T5.pdf]
Bruce A. Wooley , 2012, "The Evolution of Oversampling Analog-to-Digital Converters" [https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf]
B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016. [http://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf]
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
Richard E. Schreier, ECE 1371 Advanced Analog Circuits - 2015 [http://individual.utoronto.ca/schreier/ece1371-2015.html]
Gabor C. Temes. ECE 627-Oversampled Delta-Sigma Data Converters [https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/lecturenotes.html]
TODO 📅
Mueller-Muller type A timing function
Mueller-Muller type B timing function
minimum mean square error (MMSE)
This simplified version of LMS algorithm is identical to the zero-forcing algorithm which minimizes the ISI at data samples
T11: Basics of Equalization Techniques: Channels, Equalization, and Circuits, 2022 IEEE International Solid-State Circuits Conference
V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005, doi: 10.1109/JSSC.2004.842863.
Jinhyung Lee, Design of High-Speed Receiver for Video Interface with Adaptive Equalization; Phd thesis, August 2019. thesis link
Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, 5th edition
E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008
summer output \[ r_k = a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=1}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right) \] error slicer analog output \[ e_k=r_k-\hat{a}_k \hat{h}_0 \] error slicer digital output \[ \hat{e}_k=|e_k| \] It's NOT possible to implement \(e_k\), which need to determine \(\hat{a}_k=|r_k|\) in no time. One method to approach this problem is calculate \(e_k^{a_k=1}=r_k-\hat{a}_k \hat{h}_0\) and \(e_k^{a_k=-1}=r_k+\hat{a}_k \hat{h}_0\), then select the right one based on \(\hat{a}_k\)
The update equation based on Sign-Sign-Least Mean square (SS-LMS) and loss function \(L(\hat{h}_{\text{0~ntap}})=E(e_k^2)\) \[ \hat{h}_n(k+1) = \hat{h}_n(k)+\mu \cdot |e_k|\cdot \hat{a}_{k-n} \] Where \(n \in [0,...,\text{ntap}]\). This way, we can obtain \(\hat{h}_0\), \(\hat{h}_1\), \(\hat{h}_2\), ...
\(\hat{h}_0\) is used in AFE adaptation
We may encounter difficulty if the first tap of DFE is unrolled, its \(e_k\) is modified as follow \[ r_k = a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=2}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right) \] Where there is NO \(\hat{h}_1\)
To find \(\hat{h}_1\), we shall use different pattern for even and odd error slicer
[IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s https://static1.squarespace.com/static/5fb343ad64be791dab79a44f/t/63d807441bcd266de258b975/1675102025481/SLIDES_Track02_IBIS_AMI_Modeling_and_Correlation_Tyshchenko.pdf]
M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A. Sheikholeslami, "Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 97-108, 2022, doi: 10.1109/OJCAS.2022.3173686.
Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link. Undergraduate Research Scholars Program. Available electronically from [https://hdl.handle.net/1969.1/166485]
There are several variants of MLSD (Maximum Likelihood Sequence Detection), including:
[Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches. https://semiengineering.com/evolution-of-equalization-techniques-in-high-speed-serdes-for-extended-reaches/]
MMPD infers the channel response from baud-rate samples of the received data, the adaptation aligns the sampling clock such that pre-cursor is equal to the post-cursor in the pulse response
Faisal A. Musa. "HIGH-SPEED BAUD-RATE CLOCK RECOVERY" [https://www.eecg.utoronto.ca/~tcc/thesis-musa-final.pdf]
Faisal A. Musa."CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS" [https://www.eecg.utoronto.ca/~tcc/faisal_iscas03.pdf]
Eduardo Fuentetaja. "Analysis of the M&M Clock Recovery Algorithm" [https://edfuentetaja.github.io/sdr/m_m_analysis/]
Liu, Tao & Li, Tiejun & Lv, Fangxu & Liang, Bin & Zheng, Xuqiang & Wang, Heming & Wu, Miaomiao & Lu, Dechao & Zhao, Feng. (2021). Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits. Electronics. 10. 1888. 10.3390/electronics10161888.
Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1.
Baud-Rate CDRs [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]
F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010, pp. 366-367, doi: 10.1109/ISSCC.2010.5433823.
K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022
Jaeduk Han, "Design and Automatic Generation of 60Gb/s Wireline Transceivers" [https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.pdf]
\(h_1\) is necessary
without DFE
SS-MMPD locks at the point (\(h_1=h_{-1}\))
With a 1-tap DFE
1-tap adaptive DFE that forces the \(h_1\) to be zero, the SS-MMPD locks wherever the \(h_{-1}\) is zero and drifts eventually.
Consequently, it suffers from a severe multiple-locking problem with an adaptive DFE
Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]
| pattern | main cursor |
|---|---|
| 011 | \(s_{011}=-h_1+h_0+h_{-1}\) |
| 110 | \(s_{110}=h_1+h_0-h_{-1}\) |
| 100 | \(s_{100}=h_1-h_0-h_{-1}\) |
| 001 | \(s_{001}=-h_1-h_0+h_{-1}\) |
During adapting, we make
Then, \(h_{-1}\) and \(h_1\) are same, which is desired
alexander PD or !!PD
The alexander PD locks that edge clock (clkedge) is located at zero crossings of the data. The \(h_{-0.5}\) and \(h_{0.5}\) are equal at the lock point, where the \(h_{-0.5}\) and \(h_{0.5}\) are the cursors located at -0.5 UI and 0.5 UI.
Kwangho Lee, "Design of Receiver with Offset Cancellation of Adaptive Equalizer and Multi-Level Baud-Rate Phase Detector" [https://s-space.snu.ac.kr/bitstream/10371/177584/1/000000167211.pdf]
Shahramian, Shayan, "Adaptive Decision Feedback Equalization With Continuous-time Infinite Impulse Response Filters" [https://tspace.library.utoronto.ca/bitstream/1807/77861/3/Shahramian_Shayan_201606_PhD_thesis.pdf]
MENIN, DAVIDE, "Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization" [https://air.uniud.it/retrieve/e27ce0ca-15f7-055e-e053-6605fe0a7873/Modelling%20and%20Design%20of%20High-Speed%20Wireline%20Transceivers%20with%20Fully-Adaptive%20Equalization.pdf]
Stojanovic, Vladimir & Ho, A. & Garlepp, B. & Chen, Fred & Wei, J. & Alon, Elad & Werner, C. & Zerbe, J. & Horowitz, M.A.. (2004). Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 348 - 351. 10.1109/VLSIC.2004.1346611.
A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design Optimization for Wireline SerDes Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2023.3328807.
