B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and
Applications (2nd ed.). John Wiley & Sons, Inc.
Simon O. Haykin (2014), “Adaptive Filter Theory” Prentice-Hall,
Inc. 5rd edition
Diniz, P. S. R. (2020). Adaptive Filtering: Algorithms and
Practical Implementation (5th ed.). Springer
Jiang X, ed. Digitally-Assisted Analog and Analog-Assisted
Digital IC Design. Cambridge University Press; 2015.
Albert Jerng. ISSCC2012 T7: Digital Calibration for RF
Transceivers [pdf]
Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in
ADCs [pdf]
Salvatore Levantino. ISSCC2024 T5: Calibration Techniques in
PLLs [pdf]
A. Chan Carusone and D. A. Johns, “Analog Filter Adaptation Using a
Dithered Linear Search Algorithm,” IEEE Int. Symp. Circuits and
Syst., May 2002. [PDF], [Slides]
—, J. -E. Jang, J. Mao, J. Kim and M. Horowitz, “Digital Analog
Design: Enabling Mixed-Signal System Validation,” in IEEE Design
& Test, vol. 32, no. 1, pp. 44-52, Feb. 2015 [http://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
— , Mao, James & Horowitz, Mark & Jang, Ji-Eun & Kim,
Jaeha. (2015). Digital Analog Design: Enabling Mixed-Signal System
Validation. Design & Test, IEEE. 32. 44-52. [https://iot.stanford.edu/pubs/lim-mixed-design15.pdf]
—, M. Horowitz, “Error Control and Limit Cycle Elimination in
Event-Driven Piecewise Linear Analog Functional Models,” in IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1,
pp. 23-33, Jan. 2016 [https://sci-hub.se/10.1109/TCSI.2015.2512699]
ΔΣ modulator
effectively dithers the LSB bit
between zero and one, such that you can get the effective
resolution of a much higher resolution DAC in the number of bits
Decimation
how they affect sampling phase
image-20241020140430663
DLF’s input bit-width can be reduced by decimating BBPD’s
output. Decimation is typically performed by realizing either
majority voting (MV) or boxcar
filtering.
Note that deserialization is inherent to both
MV and boxcar filtering
image-20241019225016868
Decimation is commonly employed to alleviate the high-speed
requirement. However, decimation increases loop-latency which causes
excessive dither jitter.
Decimation is basically, widen the data and slowing it down
Decimating by L means
frequency register only added once every L UI, thus integral path
gain reduced by L in
linear model
proportional path gain is unchanged
intg_path_decim.drawio
CDR Linear Model
image-20220504101924272
condition:
Linear model of the CDR is used in a frequency lock
condition and is approaching to achieve phase
lock
Using this model, the power spectral density (PSD) of jitter in the
recovered clock Sout(f)
is Sout(f) = |HT(f)|2Sin(f) + |HG(f)|2SVCO(f)
Here, we assume φin and
φVCO
are uncorrelated as they come from independent sources.
Using below notation $$\begin{align}
\omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\
\xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2}
\end{align}$$
We can rewrite transfer function as follows $$
H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2}
$$
The jitter transfer represents a low-pass filter
whose magnitude is around 1 (0 dB) for low jitter frequencies and drops
at 20 dB/decade for frequencies above ωn
image-20220504104202197
the recovered clock track the low-frequency
jitter of the input data
the recovered clock DONT track the
high-frequency jitter of the input data
The recovered clock does not suffer from high-frequency jitter even
though the input signal may contain high-frequency jitter, which will
limit the CDR tolerance to high-frequency jitter.
Jitter Peaking in
Jitter Transfer Function
The peak, slightly larger than 1 (0dB) implies that jitter will be
amplified at some frequencies in the CDR, producing a
jitter amplitude in the recovered clock, and thus also in the recovered
data, that is slightly larger than the jitter amplitude
in the input data.
This is certainly undesirable, especially in applications such as
repeaters.
image-20220504110722442
Jitter Generation
If the input data to the CDR is clean with no jitter, i.e., φin = 0,
the jitter of the recovered clock comes directly from the VCO jitter.
The transfer function that relates the VCO jitter to the recovered clock
jitter is known as jitter generation. $$
H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi
\omega_n s+\omega_n^2}
$$ Jitter generation is high-pass filter with
two zeros, at zero frequency, and two poles identical to those of the
jitter transfer function
image-20220504110737718
Jitter Tolerance
To quantify jitter tolerance, we often apply a sinusoidal jitter of a
fixed frequency to the CDR input data and observe the BER of the CDR
The jitter tolerance curve DONT capture a CDR’s true
tolerance to random jitter. Because we are applying
“sinusoidal” jitter, which is deterministic signal.
We can deal only with the jitter’s amplitude and frequency instead of
the PSD of the jitter thanks to deterministic sinusoidal jitter signal.
JTOL(f) = |φin(f)|pp-max for
a fixed BER Where the subscript pp-max indicates the maximum peak-to-peak
amplitude. We can further expand this equation as follows $$
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot
|\varphi_e(f)|_{pp-max}
$$
Relative jitter, φe must be less
than 1UIpp for error-free operation
In an ideal CDR, the maximum peak-to-peak amplitude
of |φe(f)|
is 1UI, i.e.,|φe(f)|pp − max = 1UI
Accordingly, jitter tolerance can be expressed in terms of the number
of UIs as $$
JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad
\text{[UI]}
$$ Given the linear CDR model, we can write $$
JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad
\text{[UI]}
$$ Expand HLF(f)
for the CDR, we can write $$
JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) -
\left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]}
$$
At frequencies far below and above the natural frequency, the jitter
tolerance can be approximated by the following $$
JTOL(f) = \left\{ \begin{array}{cl}
\left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\
1 & : \ f\gg f_n
\end{array} \right.
$$
the jitter tolerance at very high jitter frequencies
is limited to 1UIpp
OJTF
Concepts of JTF and OJTF
Simplified Block Diagram of a Clock-Recovery PLL
Jitter Transfer Function (JTF)
Input Signal Versus Recovered Clock
JTF, by jitter frequency, compares how much input signal jitter is
transferred to the output of a clock-recovery’s PLL (recovered
clock)
Input signal jitter that is within the clock recovery PLL’s loop
bandwidth results in jitter that is faithfully transferred (closed-loop
gain) to the clock recovery PLL’s output signal. JTF in this situation
is approximately 1.
Input signal jitter that is outside the clock recovery PLL’s loop
bandwidth results in decreasing jitter (open-loop gain) on the clock
recovery PLL’s output, because the jitter is filtered out and no longer
reaches the PLL’s VCO
Observed Jitter Transfer Function
Input Signal Versus Sampled Signal
OJTF compares how much input signal jitter is transferred to the
output of a receiver’s decision making circuit as
effected by a clock recovery’s PLL. As the recovered clock is the
reference for detecting the input signal
Input signal jitter that is within the clock
recovery PLL’s loop bandwidth results in jitter on the recovered clock
which reduces the amount of jitter that can be detected. The input
signal and clock signal are closer in phase
Input signal jitter that is outside the clock
recovery PLL’s loop bandwidth results in reduced jitter on the
recovered clock which increases the amount of jitter that can
be detected. The input signal and clock signal are more out of phase.
Jitter that is on both the input and clock signals can not detected or
is reduced
JTF and OJTF for 1st Order PLLs
jsa_1st_order_graphneuhelium-jtf-ojtf
The observed jitter is a complement to the PLL jitter transfer
response OJTF=1-JTF (Phase matters!)
OTJF gives the amount of jitter which is tracked and therefore not
observed at the output of the CDR as a function of the jitter rate
applied to the input.
A-jtf-ojtf
Jitter Measurement
Jmeasured = JTFDUT ⋅ OJTFinstrument
The combination of the OJTF of a jitter measurement device and the
JTF of the clock generator under test gives the measured jitter as a
function of frequency.
image-20220716094732273
For example, a clock generator with a type 1, 1st order PLL measured
with a jitter measurement device employing a golden PLL is $$
J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2}
$$
Accurate measurement of the clock JTF requires that the OJTF cutoff
of the jitter measurement be significantly below that of the clock JTF
and that the measurement is compensated for the instrument’s OJTF.
The overall response is a band pass filter because the clock JTF is
low pass and the jitter measurement device OJTF is high pass.
The compensation for the instrument OJTF is performed by measuring
the jitter of the reference clock at each jitter rate being tested and
comparing the reference jitter with the jitter
measured at the output of the DUT.
jtf-ojtf
The lower the cutoff frequency of the jitter measurement device the
better the accuracy of the measurement will be.
The cutoff frequency is limited by several factors including the
phase noise of the DUT and measurement time.
Digital Sampling
Oscilloscope
How to analyze jitter:
TIE (Time Interval Error) track
histogram
FFT
TIE track provides a direct view of how the phase of
the clock evolves over time.
histogram provides valuable information about the
long term variations in the timing.
FFT allows jitter at specific rates to be measured
down to the femto-second range.
Maintaining the record length at a minimum of 1/10 of the inverse of the PLL loop bandwidth
minimizes the response error
reference
Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and
Phase Noise: A Circuits and Systems Perspective.” (2018).
quantization noise is ~ bounded uniform distribution
Using unbounded Gaussian -> pessimistic BER prediction
AFE Nonlinearity
“total harmonic distortion” (THD) in
AFE
Relative to NRZ-based systems, PAM4 transceivers require more
stringent circuit linearity, equalizers which can implement multi-level
inter-symbol interference (ISI) cancellation, and improved
sensitivity
image-20240923204055369
Because if it compresses, it turns out you have to use a much more
complicated feedback filter. As long as it behaves linearly,
the feedback filter itself can remain a linear FIR
image-20240923211841053
Linearity can actually be a critical constraint in these signal
paths, and you really want to stay as linear as you can all the way up
until the point where you’ve canceled all of the ISI
Elad Alon, ISSCC 2014, “T6: Analog Front-End Design for Gb/s Wireline
Receivers”
BER with Quantization Noise
image-20240804110522955
Var(X) = E[X2] − E[X]2
image-20240804110235178
Impulse Response or Pulse
Response
image-20240807221637401
TX FFE
TX FFE suffers from the peak power constraint, which in effect
attenuates the average power of the outgoing signal - the low-frequency
signal content has been attenuated down to the high-frequency level
G. Balamurugan, A. Balankutty and C. -M. Hsu, “56G/112G Link
Foundations Standards, Link Budgets & Models,” 2019 IEEE Custom
Integrated Circuits Conference (CICC), Austin, TX, USA, 2019,
pp. 1-95 [https://youtu.be/OABG3u2H2J4?si=CxryBSGbxrUpZNBT]
H. Shakiba, D. Tonietto and A. Sheikholeslami, “High-Speed Wireline
Links-Part II: Optimization and Performance Assessment,” in IEEE Open
Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024
[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]
R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in
Serial Data Transmission Systems,” in Phase-Locking in High-Performance
Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]
P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, “A 1.6Gbps
Digital Clock and Data Recovery Circuit,” IEEE Custom Integrated
Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]
Da Dalt N. A design-oriented study of the nonlinear dynamics of
digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I:
Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]
Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop
gain tracking all-digital PLL using autocorrelation of bang–bang
phasefrequency detection. IEEE Transactions on Circuits and Systems II:
Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]
ditheringjitter.drawio
image-20240925213924764
CDR Loop Latency
Denoting the CDR loop latency by ΔT , we note that the loop
transmission is multiplied by exp(−sΔT) ≃ 1 − sΔT.The
resulting right-half-plane zero, fz degrades the
phase margin and must remain about one decade beyond the
BW$$
f_z\simeq \frac{1}{2\pi \Delta T}
$$
This assumption is true in practice since the bandwidth of the CDR
(few mega Hertz) is much smaller than the data rate (multi giga
bits/second).
Homayoun, Aliakbar and Behzad Razavi. “On the Stability of
Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and
Systems I: Regular Papers 63 (2016): 741-750.
N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, “Nonlinear
Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In
Ranges,” in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021
limit cycles imply self-sustained oscillators due nonlinear
nature
Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC
LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van
Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design.
Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]
BB PD
It’s ternary, because early, late
and no transition
Linearing BB-PD
BB Gain is the slope of average BB output μ, versus phase offset ϕ, i.e. $\frac {\partial \mu}{\partial \phi}$,
BB only produces output for a transition and this de-rates the gain.
Transition density = 0.5 for random data
Both jitter and amplitude noise distribution are same, just scaled by
slope
Self-Noise Term
One price we pay for BB PD versus
linear PD is the self-noise term.
Forsmall phase errors BB output noise
is the full magnitude of the sliced data
The PD output should be almost 0 for small phase
errors. i.e. ideal PD output noise should be 0
σBB2 = 12 ⋅ P(trans) + 02 ⋅ (1−P(trans)) = 0.5
image-20241127215947017
Input referred jitter from BB PD is
proportional to incoming jitter
image-20241127220933103
John T. Stonick, ISSCC 2011 TUTORIALS T5: DPLL-Based Clock and
Data Recovery
Walker, Richard. (2003). Designing Bang-Bang PLLs for Clock and Data
Recovery in Serial Data Transmission Systems. [pdf]
- Clock and Data Recovery for Serial Data Communications, focusing on
bang-bang CDR design methodology, ISSCC Short Course, February 2002. [slides]
Digital CDR Category
image-20241024221619909
DCO part is analogous so that it cannot be perfectly
modeled
Digital-to-phase converter is well-defined phase output, thus, very
good to model real situation
DCO
image-20241024224500048image-20241024224603927
limit cycle
image-20241026230332655
Z-domain modeling
image-20241027001226490
The difference equation is ϕ[n] = ϕ[n−1] + KDCOVC[n] ⋅ T ⋅ 2π
z-transform is $$
\frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}}
$$
where KDCO
: Δf (Hz/bit)
ΔΣ-dithering in DCO
Quantization noise
image-20241019200102827
Here, αT is data
transition density
BBPD quantization noise
DAC quantization noise
M. -J. Park and J. Kim, “Pseudo-Linear Analysis of Bang-Bang
Controlled Timing Circuits,” in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]
Time to Digital Converter
(TDC)
Digital to Phase Converter
(DPC)
IIR low pass filter
image-20241024232055792
simple approximation: z = 1 + sT
bilinear-z transform $$
z =\frac{}{}
$$
image-20241024232111368
Peak-to-peak jitter in
ADPLL with BBPD
image-20241025001015194
Accumulate-and-dump (AAD)
decimator
accumulating the input for N cycles and then latching the
result and resetting the integrator
image-20241015222205883
It adds up N succeeding
input samples at rate 1/T and
delivers their sum in a single sample at the output. Therefore,
the process comprises a filter (in the accumulation)
and a down-sampler (in the dump)
Moving Average and CIC
Filters
cascade-integrator-comb (CIC) decimator
TODO 📅
An Intuitive Look at Moving Average and CIC Filters [web,
code]
Phase detecting possible , Frequency detecting impossible
PLL or FD(Frequency Detector) for frequency detecting in CDR
reference
J. Stonick. ISSCC 2011 “DPLL-Based Clock and Data Recovery” [slides,transcript]
P. Hanumolu. ISSCC 2015 “Clock and Data Recovery Architectures and
Circuits” [slides]
Amir Amirkhany. ISSCC 2019 “Basics of Clock and Data Recovery
Circuits”
Fulvio Spagna. INTEL, CICC2018, “Clock and Data Recovery Systems” [slides]
M. Perrott. 6.976 High Speed Communication Circuits and Systems
(lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT
OpenCourseWare, [lec21.pdf]
Akihide Sai. ISSCC 2023, T5 “All Digital Plls From Fundamental
Concepts To Future Trends” [T5.pdf]
J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links,” in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
—, “A digital clock and data recovery architecture for
multi-gigabit/s binary links,” Proceedings of the IEEE 2005 Custom
Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
P. Palestri et al., “Analytical Modeling of Jitter in
Bang-Bang CDR Circuits Featuring Phase Interpolation,” in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T.
King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore,
“A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit
Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital
Referenceless Frequency Acquisition,” IEEE J. Solid-State Circuits,
vol. 41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]
—, et al., “Modeling of ADC-Based Serial Link Receivers With
Embedded and Digital Equalization,” in IEEE Transactions on
Components, Packaging and Manufacturing Technology, vol. 9, no. 3,
pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]
K. Zheng, “System-Driven Circuit Design for ADC-Based Wireline Data
Links”, Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]
S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo,
“Statistical modeling of metastability in ADC-based serial I/O
receivers,” 2014 IEEE 23rd Conference on Electrical Performance of
Electronic Packaging and Systems [pdf]
Note that fmin
is related to the observation time. The longer we observe the device
under test, the smaller fmin
must be
image-20250104091109521image-20250104111025626
Lorentzian spectrum
image-20240720134811859
We typically use the two spectra, Sϕn(f)
and Sout(f),
interchangeably, but we must resolve these inconsistencies.
voltage spectrum is called Lorentzian
spectrum
The periodic signal x(t) can be expanded in
Fourier series as:
image-20240720141514040
Assume that the signal is subject to excess phase noise,
which is modeled by adding a time-dependent noise
component α(t). The
noisy signal can be written x(t+α(t)),
the added excess phase $\phi(t)=
\frac{\alpha(t)}{\omega_0}$
image-20250103211650043
The autocorrelation of the noisy signal is by definition:
image-20240720141525576
The autocorrelation averaged over time results in:
image-20240720141659415
By taking the Fourier transform of the autocorrelation, the spectrum
of the signal x(t+α(t))
can be expressed as
image-20240720141813256
It is also interesting to note how the integral in Equation
9.80 around each harmonic is equal to the power of the harmonic
itself |Xn|2
The integral Sx(f)
around harmonic is $$\begin{align}
P_{x,n} &= \int_{f=-\infty}^{\infty}
|X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega
+n\omega_0)^2}df \\
&= |X_n|^2\int_{\Delta
f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f
\\
&= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta
f}{\beta})|_{-\infty}^{\infty} \\
&= |X_n|^2
\end{align}$$
The phase noise does not affect the total power in the
signal, it only affects its distribution
Without phase noise, Sv(f)
is a series of impulse functions at the harmonics of fo.
With phase noise, the impulse functions spread, becoming fatter and
shorter but retaining the same total power
Phase
perturbed by a stationary noise with Gaussian PDF
image-20241227233228376image-20241228022311313
If keep ϕrms
in Rx(τ),
i.e. $$
R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0
\tau)(1+R_\phi(\tau))
$$ The PSD of the signal is $$
S_x(f) = \mathcal{F} \{ R_x(\tau) \} =
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] +
\frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right]
$$ ❗❗above Eq isn’t consistent with stationary
white noise process - the following section
Phase
perturbed by a stationary WHITE noise process
image-20241207091104944
Assuming that the delay line is noiseless
image-20241207100921644image-20241207091457850
Expanding the cosine function we get $$\begin{align}
R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi
f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi
f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\
&+ \frac{A^2}{2}\left\{\cos(4\pi
f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi
f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\}
\end{align}$$
where, both the process ϕ(t) − ϕ(t−τ)
and ϕ(t) + ϕ(t−τ)
are independent of time t,
i.e. E[cos(ϕ(t)+ϕ(t−τ))] = mcos +(τ),
E[cos(ϕ(t)−ϕ(t−τ))] = mcos −(τ),
E[sin(ϕ(t)+ϕ(t−τ))] = msin +(τ)
and E[sin(ϕ(t)−ϕ(t−τ))] = msin −(τ)
The second term in the above expression is periodic in t and to estimate its PSD, we
compute the time-averaged autocorrelation
function$$
R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) -
\sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\}
$$
After nontrivial derivation
image-20241207104018395image-20241227205459845
image-20241207103912086
Phase perturbed by a Weiner
process
image-20241207103414365image-20241207105127885
The phase process ϕ(t) is also gaussian but
with an increasing variance which grows
linearly with timet
The spectrum of y(t) is determined by the
asymptotic behavior of Ry(t,τ)
as t → ∞
❗❗ limt → ∞Ry(t,τ)
rather than time-averaged autocorrelation function of
cyclostationary process, ref. Demir’s paper
We define ζ(t,τ) = ϕ(t) + ϕ(t−τ) = ϕ(t) − ϕ(t−τ) + 2ϕ(t−τ),
the expected value of ζ(t,τ) is 0, the
variance is σζ2 = (kσ)2(τ+4(t−τ)) = (kσ)2(4t−3τ)$$
E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta
= e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)}
$$ i.e., limt → ∞E[cos(ζ(t,τ))] = limt → ∞e−(kσ)2(4t−τ) = 0
For E[sin(ζ(t,τ))],
we have $$
E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi
\sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta
$$ i.e., E[sin(ζ(t,τ))]
is odd function, therefore E[sin(ζ(t,τ))] = 0
To compare the ring oscillator and VCO the total injected
charge to both should be the same
reference
A. Hajimiri and T. H. Lee, “A general theory of phase noise in
electrical oscillators,” in IEEE Journal of Solid-State
Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [paper],
[slides]
—, ISSCC2016, “Understanding Phase Noise in LC VCOs”
A. Demir, A. Mehrotra and J. Roychowdhury, “Phase noise in
oscillators: a unifying theory and numerical methods for
characterization,” in IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674,
May 2000 [https://sci-hub.se/10.1109/81.847872]
Godone, A. & Micalizio, Salvatore & Levi, Filippo. (2008). RF
spectrum of a carrier with a random phase modulation of arbitrary slope.
[https://sci-hub.se/10.1088/0026-1394/45/3/008]
Bae, Woorham; Jeong, Deog-Kyoon: ‘Analysis and Design of CMOS
Clocking Circuits for Low Phase Noise’ (Materials, Circuits and Devices,
2020)
proportional term (P) depends on the present error
integral term (I) depends on past errors
derivative term (D) depends on anticipated future errors
PID controller makes use of linear extrapolation of
the measured output
PI controller does not make use of any prediction of
the future state of the system
The prediction by linear extrapolation (D) can generate large
undesired control signals because measurement noise is amplified, that’s
why D is not used widely
charge pumps are capacitive
DC-DC converters. The two most common switched capacitor
voltage converters are the voltage inverter and the
voltage doubler circuit
We derive a recursive equation that describes the output voltage
Vout, n
after the nth clock cycle
$$
V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o}
$$
Therefore, average output voltage $\overline{V}_{out}$ in steady-state is $$
\overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} -
\frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right)
\approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p}
$$ which results in a simple expression for the output
voltage droop
$$
\Delta V_{out} = \frac{I_{load}}{f_{sw}C_p}
$$
The charge pump can be modeled as a voltage source with a
source resistanceRout. Therefore, ΔVout
can be seen as the voltage drop across Rout due to the load
current:
Polyphase Implementation of Decimation Filters &
Interpolation Filters
Decimation system
Interpolation system
sampling identity
LPTV Implementation
TODO 📅
The interpolation filter following an up-sampler
generally is time varying and cannot be represented by
a simple transfer function. The equivalent filter in a
zero-order hold is an exception, perhaps unique, that
can be represented with a time-invariant transfer function
The interpolation filter following an up-sampler generally is
time varying and cannot be represented by a simple
transfer function. The equivalent filter in a Zero-Order
Hold is an exception, perhaps unique, that can be represented
with a time-invariant transfer function
Split the 1 : LM
hold process into a 1 : L hold
followed by a 1 : M hold $$
Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}}
$$ then $$\begin{align}
F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\
&=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}}
\\
&= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
\end{align}$$
In (a), the loop gain is $\frac{\phi_o(z)}{\phi_e(z)}$, which is $$
LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}}
$$
In (b), Accumulate-and-dump (AAD) is $\frac{1-z^{-L}}{1-z^{-1}}$, then ϕm(η)
can be expressed as $$
\phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}
$$ Hence $$\begin{align}
\phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\
&= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot
\frac{1}{1-\eta^{-1}}
\end{align}$$
After zero-order hold process, we obtain ϕf(z),
which is $$\begin{align}
\phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\
&=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}}
\end{align}$$ i.e., $$
LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1-z^{-L}}{1-z^{-1}}
$$
When bandwidth is much less than sampling rate (data rate), $\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx
1$
J. Stonick. ISSCC 2011 “DPLL-Based Clock and Data Recovery” [slides,transcript]
J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links,” in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
J. Sonntag and J. Stonick, “A digital clock and data recovery
architecture for multi-gigabit/s binary links,” Proceedings of the
IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
Y. Xia et al., “A 10-GHz Low-Power Serial Digital Majority
Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR,”
in IEEE Transactions on Microwave Theory and Techniques,
vol. 68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]
J. Liang, A. Sheikholeslami. ISSCC2017. “A 28Gbps Digital CDR with
Adaptive Loop Gain for Optimum Jitter Tolerance” [slides,paper]
J. Liang, A. Sheikholeslami,, “Loop Gain Adaptation for Optimum
Jitter Tolerance in Digital CDRs,” in IEEE Journal of Solid-State
Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
Z. Guo et al., “A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET,” 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.
A. Sheikholeslami, “Voltage Follower, Part III [Circuit Intuitions],”
in IEEE Solid-State Circuits Magazine, vol. 15, no. 2,
pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457
Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits
(5th. ed.). Wiley Publishing. [pdf]
Double differential Pair
Vip and Vim are input, Vrp and Vrm are reference voltage
$$
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
$$
2diffpair.drawio
In differential comparison mode, the feedback loop ensure Vip = Vrp,
Vim = Vrm
in the end
assume input and reference common voltage are
same
Pros of (b)
larger input range i.e., $\gt \pm
\sqrt{2}V_\text{ov}$ of (a), it works even one
differential is off due to lower voltage
larger gm (smaller
input difference of pair)
Cons of (b)
sensitive to the difference of common voltage between Vip, Vim and Vrp, Vrm
common-mode voltage
difference
doublepair_cm.drawio
copy aforementioned formula here for convenience $$
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
$$
at sample phaseVip = Vim = Vcmi
and Vrp = Vrm = Vcmr
Iip0 = Iim0 = Ii0
Irp0 = Irm0 = Ir0
i.e. $\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} = 0$
at compare start
Vip = Vim = Vcmi
and Vrp = Vcmr + Δ,
Vrp = Vcmr − Δ
Iip < Iip0,
Irp > Irp0
Iim > Iim0,
Irm < Irm0
i.e. $\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} \lt 0$, we need to
increase Vip and
decrease Vim.
Resistive degeneration in differential pairs serves as one
major technique for linear amplifier
image-20240824132739726
The linear region for CMOS differential pair would be extended by
± ISSR/2
as all of ISS/2
flows through R. $$\begin{align}
V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\
&= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2}
\end{align}$$
Byungsub Kim, ISSCC 2022, “T11: Basics of Equalization Techniques:
Channels, Equalization, and Circuits”
Minsoo Choi et al., “An Approximate Closed-Form Channel Model for
Diverse Interconnect Applications,” IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043,
Oct. 2014.
K. Yadav, P. -H. Hsieh and A. Chan Carusone, “Linearity Analysis of
Source-Degenerated Differential Pairs for Wireline Applications,” in
IEEE Open Journal of Circuits and Systems, [link]
$$
X- Y\cdot \beta z^{-1}\cdot \frac{1}{1-z^{-1}} = Y
$$ therefore $$
\frac{Y}{X} = \frac{1-z^{-1}}{1-(1-\beta)z^{-1}}
$$
$$
F_1(z) = X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
$$
$$
I_{NIC} =\frac{V_{im} - V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}} =
\frac{-2V_{ip}}{\frac{2}{g_m}+\frac{1}{sC_c}}
$$ Therefore $$
Z_{NIC} = \frac{V_{ip} - V_{im}}{I_{NIC}}=\frac{2V_{ip}}{I_{NIC}} =-
\frac{2}{g_m}-\frac{1}{sC_c}
$$ half-circuit
