KNOW-HOW

Traditional RC Corners

DPT effect

When using two masks per layer (Double Patterning Technology, DPT) there is an issue of mask alignment where any mis-alignment will cause layer spacing values to change, therefore changing the parasitic coupling capacitance values.

Misalignment scale and direction are not deterministic facts: coupling cap and total cap may be increased or decreased.

Five new corners are added in a DPT flow to account for RC variations accurately:

sapced-dependent side-wall dielectric constant also affect coupling cap

and CC_worst means to increase both K1 and K2

CC_best means to decrease both K1 and K2

• Setup time sign-off would use:

  Cworst_CCworst / RCworst_CCworst

• Hold time sign-off would use:

  Cbest_CCbest / RCbest_CCbest / Cworst_CCworst / RCworst_CCworst

Signoff corner

BEOL Target: typical

The recommended RC corner:

​ cworst_CCworst, cbest_CCbest, rcworst_CCworst, rcbest_CCbest and typical

The others are for pre-color RC calculation purpose

**_T** stands for "Tighten DPT corner"; these are less pessimistic 1.5 sigma corners

Below table is caputre of Aragio's TSMC16: LVDS datasheet

BEOL corner

Spacing variation is implicitly defined by \(\Delta W_m\).

We denote the conductor width and thickness of the layer m by \(W_m\) and \(T_m\), respectively.

Similarly, we denote the thickness of the layer's interlayer dielectric (i.e., the distance between layer m and layer m +1) by \(H_m\)

• C-based means worst and best caps
• RC-based means worst and best R in adjustment with C (RC product)

Based on experience, it was found that C-based extraction provides worst and best case over RC for internal timing paths because Capacitance dominates short wire.

However, for large design, inter-block timing paths were often worst with RC worst parasitic since R dominates for long wires.

signoff corners for setup and hold

reference

Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM https://www.aspdac.com/aspdac2007/pdf/archive/2D-1.pdf

Double Patterning for IC Design, Extraction and Signoff https://semiwiki.com/eda/synopsys/1974-double-patterning-for-ic-design-extraction-and-signoff/

抽刀断水水更流，RC Corner不再愁：STA之RC Corner URL: http://mp.weixin.qq.com/s?__biz=MzUzODczODg2NQ==&mid=2247484115&idx=1&sn=de99f27aadf58ea316c284dad9000b7c&chksm=fad26b0dcda5e21b8c9750f738b55053f695843a66c3c202ff0ba586c738f45aa270254c3722&scene=21#wechat_redirect

一曲新词酒一杯，RC Corner继续飞: STA之RC Corner拾遗 URL:https://mp.weixin.qq.com/s?__biz=MzUzODczODg2NQ==&mid=2247484135&idx=2&sn=bddc632850bd10c32b5688fd7af46218&chksm=fad26b39cda5e22f1c3970f8c8c2e1287c9492c526c4caf02b61f61faffdf829381c392d6ea1&scene=21#wechat_redirect

且将新火试新茶，深究趁年华：STA之RC Corner再论 URL:https://mp.weixin.qq.com/s?__biz=MzUzODczODg2NQ==&mid=2247484144&idx=1&sn=059843381e77cd4008d25166db388d02&chksm=fad26b2ecda5e23816b33b3a949f34d4ca09118bad76f1089dfcb228b7da6491f423a5f4e703&cur_album_id=1326356275000705025&scene=189#wechat_redirect

LDP_IN_800_25V_DN: 1.2GHz LVDS Receiver http://aragiosolutions.com/pdf/rgo_tsmc16_18v25_lvds_product_brief_rev_1a.pdf

Parasitic extraction technologies Advanced node and 3D-IC design https://static.sw.cdn.siemens.com/siemens-disw-assets/public/81845/en-US/Siemens-SW-Parasitic-extraction-technologies-for-advanced-WP-81845-C2.pdf

New Game, New Goal Posts: A Recent History of Timing Closure https://pdfs.semanticscholar.org/9360/5ce48f9bd3b7527ae8979f41a9c7e310efa4.pdf

The Evolution, Pitfalls, and Cargo Cult Engineering of Advanced Digital Timing Sign-off https://www.tauworkshop.com/2021/speaker_slides/christian_l.pdf

T. -B. Chan, S. Dobre and A. B. Kahng, "Improved signoff methodology with tightened BEOL corners," 2014 IEEE 32nd International Conference on Computer Design (ICCD), Seoul, Korea (South), 2014, pp. 311-316, doi: 10.1109/ICCD.2014.6974699.

Chan, T. (2014). Mitigation of Variability and Reliability Margins in IC Implementation /. UC San Diego. ProQuest ID: Chan_ucsd_0033D_14269. Merritt ID: ark:/20775/bb52916761. Retrieved from https://escholarship.org/uc/item/35r1m001

Dr. Adam Temanm, Digital VLSI Design:Lecture 10: Routing https://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-10-Routing.pdf

Article (20487193) Title: Setting Pegasus - LVS to Quantus av_extracted view Flow with TSMC16 packages URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009MprZUAS

Clock Gating is defined as: "Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed".

Clock Gating Overview

AND gate-based clock gating

In simplest form a clock gating can be achieved by using an AND gate as shown in picture below

However, this simplest form of clock gating technique has some problem of generating glitches in the clock provide to the FF, which are not desirable.

Glitches in enable/gated clock

Latch based clock gating

These glitches can be removed by introducing a negative edge triggered FF (assuming downstream FFs are positive edge) or low-level sensitive latch at the output of the clock enable signal.

This will make sure that any glitch in the clock enable signal will not be visible to the gated clock output. The Latch output will only be updated during the negative clock cycle and thus input to AND gate will be stable high.

Glitch Free Gated Clock

reference

The Ultimate Guide to Clock Gating https://anysilicon.com/the-ultimate-guide-to-clock-gating/

dspf extract using starrc

multiple label and rectangle in vssa net

• general dspf

  SHORT_PINS: YES

  

  other pin are short together

• dspf for emir analysis

It seems that dspf_emir don't contain the rectangle pin information.

only label is necessary

shortPins=”yes” is preferred default option for dspf_emir, which has split pins

DSPF Syntax

• ::=*|P ? describes pins in the net. Multiple pin descriptions can be listed in one line.

• ::=( {}?) represents the name of the pin. represents the type of the pin. It can be any of the following: I (Input), O (Output),

  ​ B (Bidirectional), X (don’t care), S (Switch), and J (Jumper). ​ represents the capacitance value associated with the pin. ​ is optional. It represents the location of the pin. Multiple pin locations are allowed

split pins

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*|P (avss_1 O 0 207.7555 59.9170)
*|P (avss_10 O 0 181.1610 151.1130)
*|P (avss_11 O 0 186.6330 151.1130)
*|P (avss_12 O 0 192.1050 151.1130)
*|P (avss_13 O 0 197.5770 151.1130)

reference

Article (20467964) Title: Difference in result on running Spectre APS with EMIR and without EMIR analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000679GRUAY

StarRC User Guide and Command Reference Version O-2018.06, June 2018

To preserve the hand-instantiated cells

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set_dont_touch [get_cells -hierarchical *dont_touch_*]

The instances whose name contain "dont_touch_" shall be preserved during synthesis

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// no performace concerns, rest sync use sync3 is enough

module CN_resetb_sync_cell
(
    input resetb_in,
    input clkdst,
    output resetb_out
);

`ifdef USE_VERILOG
reg [2:0] resetb_dly;
`else
wire [2:0] resetb_dly;
`endif

`ifdef USE_VERILOG
always @(posedge clkdst or negedge resetb_in)
    if (~resetb_in) resetb_dly <= 3'b000;
    else resetb_dly <= {resetb_dly[1:0], 1'b1};
`else
SDFCNQD4 dont_touch_sync_flop0 (
    .SI(1'b0),
    .SE(1'b0),
    .CP(clkdst),
    .CDN(resetb_in),
    .D(1'b1),
    .Q(resetb_dly[0])
);
SDFCNQD4 dont_touch_sync_flop1 (
    .SI(1'b0),
    .SE(1'b0),
    .CP(clkdst),
    .CDN(resetb_in),
    .D(resetb_dly[0]),
    .Q(resetb_dly[1])
);
SDFCNQD4 dont_touch_sync_flop2 (
    .SI(1'b0),
    .SE(1'b0),
    .CP(clkdst),
    .CDN(resetb_in),
    .D(resetb_dly[1]),
    .Q(resetb_dly[2])
);
`endif

assign resetb_out = resetb_dly[2];

endmodule

Create a new file with an extension scs like myDSPF_Files.scs

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* DSPF files to use with Corner Definitions
* This is an example file showing how to define different dspf files for different corners
* using model files for individual components as the
* building blocks.
simulator lang=spectre
library dspf_files_corners

section rctyp_25
dspf_include "DSPF_RC_TYPNOM25.spf"
endsection rctyp_25

section rctyp_125
dspf_include "DSPF_RC_TYP125.spf"
endsection rctyp_125

section rcworst_25
dspf_include "DSPF_RC_WORSE25.spf"
end section rcworst_25

section rcworst_125
dspf_include "DSPF_RC_WORSE125.spf"
end section rcworst_125

endlibrary dspf_files_corners

Add the file created above ‘myDSPF_File.scs’ in ‘Add/Edit Model Files’ of Corners setup form

In order to set up model files automatically in the Model Library Setup form for Spectre or AMS simulator in ADE Explorer or ADE Assembler

Add the following line in your .cdsinit

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envSetVal( "spectre.envOpts" "modelFiles" 'string "<path_to model_file>/myModels.scs")

or

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envSetVal("spectre.envOpts" "modelFiles" 'string "moreModels;ff mymodels;tt")

Generic circuit in textbook

In addition to lowering the required capacitor value, Miller compensation entails a very important property: it moves the output pole away from the origin. This effect is called pole splitting

The 1st stage is replaced with Thevenin equivalent circuit , \(V_i \cong V_i \cdot g_{m1}R_{o1}\)

\[\begin{align} \frac{V_i-V_{o1}}{R_{o1}} &= V_{o1}\cdot sC_{o1}+(V_{o1}-V_o)\cdot sC_c \\ V_{o1} &= \frac{V_i+sR_{o1}C_cV_o}{1+sR_{o1}(C_{o1}+C_c)} \end{align}\] \[ (V_{o1}-V_o)sC_c=g_{m2}V_{o1}+V_o(\frac{1}{R_{o2}+sC_L}) \] substitute \(V_{o1}\), we get

\[\begin{align} \frac{V_o}{V_i} &= \frac{(sC_c-g_{m2})R_{o2}}{s^2R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) \right\} +1} \\ &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)}{s^2R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) \right\} +1} \end{align}\]

left hand plane poles

\[\begin{align} \omega_1 &= \frac{1}{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)} \\ \omega_2 &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \end{align}\]

and RHP (right-hand plane) zero \[ \omega_z=\frac{g_{m2}}{C_c} \]

The circuit with series switch

replace \(sC_L\) with \(1/(R_{sw}+\frac{1}{sC_L})\) \[\begin{align} \frac{V_{o2}}{V_i} &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)(1+sR_{sw}C_L)}{s^3R_{o1}R_{o2}R_{sw}C_{o1}C_cC_L+s^2\left\{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+ \left[ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+0)+R_{o1}(C_{o1}+C_c)\right]R_{sw}C_L \right\}+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) +R_{sw}C_L\right\} +1} \end{align}\] Due to \[ \frac{V_o}{V_{o2}} = \frac{\frac{1}{sC_L}}{R_{sw}+\frac{1}{sC_L}}=\frac{1}{1+sR_{sw}C_L} \] Then \[\begin{align} \frac{V_o}{V_i} &= \frac{V_{o2}}{V_i} \cdot \frac{V_o}{V_{o2}} \\ &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)}{s^3R_{o1}R_{o2}R_{sw}C_{o1}C_cC_L+s^2\left\{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+ \left[ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+0)+R_{o1}(C_{o1}+C_c)\right]R_{sw}C_L \right\}+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) +R_{sw}C_L\right\} +1} \end{align}\]

\(R_{sw}\) and \(R_c\)

\[\begin{align} \frac{V_{o2}}{V_i} &=-g_{m2}R_{o2}\frac{sC_c(R_c-1/g_{m2})+1}{(1+sR_{o1}C_{o1})sR_{o2}C_c+sR_{o1}\cdot g_{m2}R_{o2}C_c+\frac{s(R_{o2}+R_{sw})C_L+1}{sR_{sw}C_L+1}\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \\ &=-g_{m2}R_{o2}\frac{sC_c(R_c-1/g_{m2})+1}{s^2R_{o1}R_{o2}C_{o1}C_c+sR_{o2}C_c+sR_{o1}\cdot g_{m2}R_{o2}C_c+\frac{s(R_{o2}+R_{sw})C_L+1}{sR_{sw}C_L+1}\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \\ &=-g_{m2}R_{o2}\frac{\left[ sC_c(R_c-1/g_{m2})+1 \right](sR_{sw}C_L+1)}{s^2R_{o1}R_{o2}C_{o1}C_c(sR_{sw}C_L+1)+sR_{o2}C_c(sR_{sw}C_L+1)+sR_{o1}\cdot g_{m2}R_{o2}C_c(sR_{sw}C_L+1)+\left[s(R_{o2}+R_{sw})C_L+1\right]\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \end{align}\]

\(s^3\) terms in denominator \[ H_3 = s^3\cdot(R_{o1}R_{o2}R_c+R_{o1}R_{o2}R_{sw} +R_{o1}R_cR_{sw})\cdot C_{o1}C_cC_L \] \(s^2\) terms in denominator \[\begin{align} H_2 &=s^2\cdot(R_{o1}R_{o2}C_{o1}C_c+R_{o1}R_{o2}C_{o1}C_L+R_{o2}R_cC_cC_L+R_{o1}R_{o2}C_cC_L+R_{o1}R_cC_{o1}C_c\\ &+R_{o2}R_{sw}C_cC_L+R_{o1}R_{sw}C_cC_L\cdot g_{m2}R_{o2}+R_{o1}R_{sw}C_{o1}C_L+R_{sw}R_cC_cC_L+R_{o1}R_{sw}C_cC_L) \end{align}\]

\(s^1\) term in denominator \[ H_1=s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_cC_c+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L+R_{sw}C_L) \] \(s^0\) term in denominator \[ H_0=1 \] set \(R_c=0\) and \(R_{sw}=0\), the \(H_*\) reduced to \[\begin{align} H_3 &= 0 \\ H_2 &=s^2R_{o1}R_{o2}(C_{o1}C_c+C_{o1}C_L+C_cC_L) \\ H_1&=s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L) \\ H_0&=1 \end{align}\] That is \[ H=s^2R_{o1}R_{o2}(C_{o1}C_c+C_{o1}C_L+C_cC_L)+s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L)+1 \]

which is same with our previous analysis of Generic circuit in textbook

And we know \[ \frac{V_o}{V_{o2}}=\frac{1}{1+sR_{sw}C_L} \] Finally, we get \(\frac{V_o}{V_i}\) \[\begin{align} \frac{V_o}{V_i} &= \frac{V_{o2}}{V_i} \cdot \frac{V_o}{V_{o2}} \\ &= -g_{m2}R_{o2}\frac{\left[ sC_c(R_c-1/g_{m2})+1 \right](sR_{sw}C_L+1)}{H_3+H_2+H_1+1} \cdot \frac{1}{1+sR_{sw}C_L} \\ &= -g_{m2}R_{o2}\frac{ sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1} \end{align}\]

The loop transfer function is \[ \frac{V_o}{V_i} =-g_{m1}R_{o1}g_{m2}R_{o2}\frac{ sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1} \]

vccs model

simplify the transfer function

omit \(C_{o1}\)

We omit \(C_{o1}\) in frequency range of interest

\[\begin{align} H_3 &= 0 \\ H_2 &=s^2(R_{o2}R_c+R_{o1}R_{o2}+R_{o2}R_{sw}+R_{o1}R_{sw}\cdot g_{m2}R_{o2}+R_{sw}R_c+R_{o1}R_{sw})\cdot C_cC_L \\ H_1 &=s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_cC_c+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L+R_{sw}C_L) \\ H_0 &= 1 \end{align}\]

two poles and 1 zero

more simplification

Then, some terms can be omitted

\[\begin{align} H_2 &=s^2R_{o1}R_{o2}(1+g_{m2}R_{sw})\cdot C_cC_L \\ H_1 &=sR_{o1}\cdot g_{m2}R_{o2}C_c \\ H_0 &= 1 \end{align}\]

The poles can be deduced \[\begin{align} \omega_1 &= \frac{1}{R_{o1}\cdot g_{m2}R_{o2}C_c} \\ \omega_2 &= \frac{1}{1+g_{m2}R_{sw}}\cdot \frac{g_{m2}}{C_L} \\ &= \frac{1}{(gm_2^{-1}+R_{sw})C_L} \end{align}\]

The pole \(\omega_2=\frac{1}{gm_2^{-1}C_L}\) is changed to \(\omega_2=\frac{1}{(gm_2^{-1}+R_{sw})C_L}\)

In order to cancell \(\omega_2\) with \(\omega_z\), \(R_c\) shall be increased

\[ R_{eq}=g_{m2}^{-1}+R_{sw} \]

omit \(C_{o1}\) is same with 2nd system simplification

non-dominant pole in Sansen's book

Following demonstrate how derive \(f_{nd}\) from Razavi's equation. We copy \(\omega_2\) here \[ \omega_2 = \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \] which can be reduced as below

\[\begin{align} \omega_2 &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \\ &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \\ &= \frac{C_c\cdot g_{m2}}{C_cC_{o1}+C_LC_{o1}+C_LC_c} \\ &= \frac{g_{m2}}{C_{o1}+C_L\frac{C_{o1}}{C_c}+C_L} \\ &= \frac{g_{m2}}{C_L\frac{C_{o1}}{C_c}+C_L} \\ &= \frac{g_{m2}}{C_L} \cdot \frac{1}{1+\frac{C_{o1}}{C_c}} \end{align}\]

Exercise of 2-stage opamp

\(R_{o1}\) and \(R_{o2}\) don't affect stability, if \(f_{nd}>3\text{GBW}\)

DC gain: \(g_{m1}g_{m2}R_{o1}R_{o2}\)

dominant pole: \(\omega_d=\frac{1}{R_{o1}\cdot g_{m2}R_{o2}C_c}\)

\(20log_{10}(1.414^2)=6\text{dB}\)

reference

Razavi, Behzad. Design of Analog CMOS Integrated Circuits. India: McGraw-Hill, 2017.

Sansen, Willy M. Analog Design Essentials. Germany: Springer US, 2006.

charge pump

TODO 📅

Charge pumps are capacitive DC-DC converters

The two most common switched capacitor voltage converters are the voltage inverter and the voltage doubler circuit

R-2R & C-2C

TODO 📅

Conceptually, area goes up linearly with number of bit slices

drawback of the R-2R DAC

\(N_b\) bit binary + \(N_t\) bit thermometer DAC

\(N_b\) bit binary can be simplified with Thevenin Equivalent \[ V_B = \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_b-n}} \] with thermometer code

\[\begin{align} V_o &= V_B\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R}+\sum_{n=0}^{2^{N_t}-2}T_n\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R} \\ &= \frac{V_B}{2^{N_t}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \\ &= \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_t+N_b-n}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \end{align}\]

B. Razavi, "The R-2R and C-2C Ladders [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 10-15, Summer 2019 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2019.pdf]

Switched-Capacitor Resistor

\[ R_{eq} = \frac{1}{f_sC} \]

DIBL & GIDL

drain-induced barrier lowering (DIBL)

impact on the threshold voltage

impact on output impedance

In short-channel devices, as \(V_{DS}\) increases further, drain-induced barrier lowering becomes significant, reducing the threshold voltage and increasing the drain current

Gate induced drain leakage (GIDL)

Chauhan, Yogesh Singh, et al. FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press, 2015.

\[ \frac{g_m}{I_D} = \frac{2}{V_{GS}-V_{TH}} \] Decrease of gm/Id results from decrease in VT.

GIDL (Gate induced drain leakage) as at weak inversion may results in a weak lateral electric field causing leakage current between drain and bulk, which degrade the efficiency of the transistor (gm/ID).

[https://www.linkedin.com/posts/master-micro_mastermicro-mastermicro-adt-activity-7214549962833989632-ZoV_?utm_source=share&utm_medium=member_desktop]

Early Voltage indicator

\[ g_m r_o = \frac{g_m}{I_D}I_D \cdot \frac{V_A}{I_D} = \frac{g_m}{I_D} \cdot V_A \]

$g_m r_o $ is the indicator of \(V_A\), if \(\frac{g_m}{I_D}\) is same

Resonator

bandpass filter

Hossein Hashemi, RF Circuits, [https://youtu.be/0f3yZMvD2Jg?si=2c1Q4y6WJq8Jj8oN]

Linearization of resistive degeneration

Resistive degeneration in differential pairs serves as one major technique for linear amplifier

The linear region for CMOS differential pair would be extended by \(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align} V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\ &= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \end{align}\]

Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf

Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]

TIA

\[\begin{align} I_{in} &= \frac{V_i}{R_S} + \frac{V_i - V_o}{R_F} \\ \frac{V_i - V_o}{R_F} &= g_m V_i \end{align}\]

Then

\[\begin{align} V_o &= \frac{I_{in}R_F}{\frac{R_S+R_F}{R_S}\frac{1}{1-g_mR_F}- 1} \\ V_i &= \frac{I_{in}R_F}{\frac{R_F}{R_S}+g_mR_F} \end{align}\] If \(R_S \gg R_F\) \[\begin{align} V_o &= \frac{I_{in}}{g_m}(1-g_mR_F) \\ V_i &= \frac{I_{in}}{g_m} \end{align}\]

Cgd of Common-Source Stage

pay attention to Miller effect of Cgd during layout

Nonlinearity of Differential Circuits

VCO varactor

Two methods: 1. pss + pac; 2. pss+psp

PSS + PAC

pss time domain

using the 0-harmonic

PSS + PSP

using Y11 of psp

results

which are same

Zero in differential pair with active current mirror

Noting the circuit consists of a "slow path" (M1, M3, M4) in parallel with a "fast path" (M2)

• "slow path" \[ H_\text{slow}(s) = \frac{A_0}{(1+s/\omega _{pE})(1+s/\omega _{pO})} \]

• "fast path" \[ H_\text{fast}(s) = \frac{A_0}{1+s/\omega _{pO}} \]

Then \[\begin{align} \frac{V_\text{out}}{V_\text{in}} &= H_\text{slow}(s) + H_\text{fast}(s) \\ &= \frac{A_0}{1+s/\omega _{pO}}\left(\frac{1}{1+s/\omega _{pE}} + 1 \right) \\ &= \frac{A_0(1+s/2\omega _{pE})}{(1+s/\omega _{pO})(1+s/\omega _{pE})} \end{align}\]

That is, the system exhibits a zero at \(2\omega_{pE}\)

signals traveling through two paths within an amplifier may cancel each other at one frequency, creating a zero in the transfer function

\[ \omega_z = \frac{(A_1+A_2)\omega_{p1}\omega_{p2}}{A_1\omega_{p1}+A_2\omega_{p2}} \] noting \(\omega_{p1}\lt \omega_z \lt \omega_{p2}\)

Random offset

The dependence of offset voltage and current mismatches upon the overdrive voltage is similar to our observations for corresponding noise quantities

differential pair

In reality, since mismatches are independent statistical variables

Above shows that the input transistors must be designed for high gain (\(g_mr_o = \frac{2}{V_{OV}\lambda}\)), which means they must be designed for small \(V_{GS}-V_{TH}\).

It is desirable to minimize \(V_{GS}-V_{TH}\) by lowering the tail current or increasing the transistor widths

For \(\frac{\Delta K}{K}\)

\[\begin{align} v_{os} g_m &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} 2K\frac{W}{L}(V_{GS}-V_{TH}) &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} &= \frac{V_{GS}-V_{TH}}{2} \frac{\Delta K}{K} \end{align}\]

The derivation for \(\frac{\Delta W/L}{W/L}\) is same with \(\frac{\Delta K}{K}\)

alternative derivation

\[\begin{align} \Delta V_\beta \cdot g_m &= \frac{\partial I_D}{\partial \beta} \Delta \beta \\ &= I_D \frac{\Delta \beta}{\beta} \end{align}\]

That is \(\Delta V_\beta = \frac{I_D}{g_m}\frac{\Delta \beta}{\beta}\)

\[ \Delta V_R \cdot g_m R = I_D \cdot \Delta R \]

That is \(\Delta V_R = \frac{I_D}{ g_m} \cdot \frac{\Delta R}{R}\)

[https://electronicengineering.phd.upc.edu/en/courses-and-seminars/courses-materials/2008-2009/slides-makinwa-1]

current mirror

To minimize current mismatch, the overdrive voltage must be maximized, a trend opposite to that in differential pair.

This is because as \(V_{GS}-V_{TH}\) increases, threshold mismatch has a lesser effect on the device currents

\(\Delta I_D= g_m \Delta V_{TH} = \frac{2I_D}{V_{OV}}\Delta V_{TH}\)

Effect of Feedback on Noise

Feedback does not improve the noise performance of circuits.

The input-referred noise voltage and current remain the same if the feedback network introduces no noise.

Burn-in & High-temperature operating life (HTOL)

• HTOL:
  • characterization test
  • characterize the life expectancy
• Burn-in:
  • production test
  • weed out defective products

HTOL and Burn-in Testing capture the two ends of the reliability characterization graph known as the "bathtub curve"

[https://arworld.us/the-importance-of-htol-and-burn-in-testing-methods/]

PERC

• CD: current density checks

• P2P: point to point resistance checks

• LDL: logic driven layout checks, latch up related

• TOPO: topology, circuit connection and device size checks

database

• CD, P2P, LDL : dfmdb

• TOPO: svdb

Frank Feng. New Approach For Full Chip Electrical Reliability Verification [pdf]

STRAP

A "strap" refers to a low-impedance connection

NWDMY = NWDMY1, NWDMY2

STRAP = NWSTRAP or PWSTRAP

NWSTRAP = {NP & OD} & {NW not {NW INTERACT NWDMY}}

PWSTRAP = {PP & OD} not NW

Calibre Rule::NOT

Calibre Rule::INTERACT

RC charge and discharge

• charge: \[ V_o(t) = V_{X}(1-e^{-\frac{t}{\tau}}) + V_{o,0}\cdot e^{-\frac{-t}{\tau}} \]

• discharge: \[ V_o(t) = V_{o,0}\cdot e^{-\frac{t}{\tau}} + V_{o,\infty}\cdot(1-e^{-\frac{t}{\tau}}) \]

1. \(e^{-\frac{t}{\tau}}\) item determine the initial state
2. \((1-e^{-\frac{t}{\tau}})\) item determine the final state

AC coupling

\[ \tau = 200 \text{nF} \times (50+50)\text{ohm} = 20 \mu s \]

high level envelope:

switched-capacitor resistor

Switching the capacitor moves a charge proportional to the voltage difference. The resistor achieves the same function only in a continuous manner.

Using a water analogy, we can imagine a couple of scenarios:

1. a steady water flow,
2. or 2) the same water delivered rapidly in buckets. Both create the same flow of water - on average!

Current mirror with source degeneration

Razavi 2nd, problem 14.15

Monitored Analog Critical Parameters

Parameter Definition:

\[\begin{align} I_{\text{D,lin}} &= I_D \mid _{V_G=V_{DD},V_D=0.05V} \\ I_{\text{D,sat}} &= I_D \mid _{V_G=V_D=V_{DD}} \\ V_{\text{t,lin}} &= V_G \mid _{I_D=I_{\text{thx}}\cdot \frac{W}{L}@\{V_D=0.05V\}} \end{align}\]

\(I_{\text{thx}}\) could be different for technologies. (For N16, \(I_{\text{thx}}=10\)nA)

Demystifying stb and pstb in Spectre

All credits to my colleague, Zhang Wenpian.

Spectre's stb analysis

Spectre stb's "loopgain" is negative of "T" in paper^[1] \[ T = \frac{2(AD-BC) - A + D}{2(AD-BC)-A+D-1} \]

AC simulation testbench, shown as below,

1. \(I_{inj}\) = 0, \(V_{inj}\) = 1

   B = if, D = ve

2. \(I_{inj}\) = 1, \(V_{inj}\) = 0

   A = if, C = ve

Spectre's pstb analysis

Spectre pstb is similar to stb, just set pac as 1 instead of ac in current source and voltage source.

This analysis just use harmonic 0 transfer function in pac analysis, which has limitation.

Thevenin and Norton Equivalent Circuits

戴维南定理

等效电阻的计算方法

使用外加电源法时， 全部独立电源需要置零

诺顿定理

Lemma of Razavi

\[ A_V = -G_m R_{out} \]

Design of Analog CMOS Integrated Circuits, Second Edition - Behzad Razavi

Miller's Approximation: right-half-plane zero

A quick inspection of this circuit reveals that a zero lies at a frequency where the current through \(C_{12}\) becomes equal to \(g_2V_1\).

When this occurs, the current through the parallel combination of \(C_2\) and \(R_2\) becomes zero, creating a zero in the transfer function.

In other words, we can write

\[\begin{align} g_2V_1 &= V_1sC_{12} \\ s &= \frac{g_2}{C_{12}} \end{align}\]

Non Overlapping Clock

Single ended Amplifier Offset Voltage

unity gain buffer

\[\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \end{align}\]

Then, we get \[ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) \] Due to \(V_o=V_m\) and \(V_o'=V_m'\) \[ V_{os}=(1/A+1)\Delta{V_m} \] or \[ V_{os}=(1/A+1)\Delta{V_o} \] if \(A \gg 1\) \[ V_{os}=\Delta{V_o} \]

non-inverting amplifier

\[\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \\ V_m &= \beta V_o \\ V_m' &= \beta V_o' \end{align}\]

we get \[ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) \] or \[ V_{os}=\frac{\Delta V_o}{A}+\beta \Delta V_o \] if \(A \gg 1\) \[ V_{os}=\beta \Delta V_o \] or \[ V_{os}=\Delta V_m \]

Lecture 22 Variability and Mismatch of Dr. Hesham A. Omran's Analog IC Design

URL: https://www.master-micro.com/professional-courses/analog-ic-design/course-resources

Gotcha MOS ron

There is discrepancy between model operating point and \(V_{ds}/I_{ds}\)

I believe that the equation \(V_{ds}/I_{ds}\) is more appropriate where mos is used as switch, though \(V_{ds}=0\) is an outlier.

Schmitt Inverter

gm/ID Intuition

small gm/ID for High ro, or high Early voltage \(V_A\)

Transit Frequency \(f_T\)

Defined as the frequency at which the small-signal current gain of a device is unity

MOSFET ZTC Condition Analysis

zero temperature coefficient (ZTC)

MOM cap of wo_mx

Monte Carlo model:

• \(C_{pa}=C_{pa1}\), \(C_{pb}=C_{pb1}\) for each iteration during Process Variation
• different variation is applied to \(C_{ab}\) and \(C_{a1b1}\) each iteration during Mismatch Variation, though \(C_{pa}\), \(C_{pb}\), \(C_{pa1}\) and \(C_{pb1}\) remain constant

Active Inductor

\[\begin{align} A &= \frac{g_mR_L}{1+(g_\text{m\_dio}+ g_\text{ds\_tot})R_L}\cdot \frac{1+R_pC_Ps}{1+\frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}s + \frac{R_LC_LR_PC_P}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}s^2} \\ &= \frac{g_mR_L}{1+(g_\text{m\_dio}+ g_\text{ds\_tot})R_L}\cdot \frac{R_PC_P}{ \frac{R_LC_LR_PC_P}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}}\cdot \frac{1/(R_PC_P)+s}{s^2 + \frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{R_PC_P}s + \frac{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}{R_LC_LR_PC_P}} \\ &= A_0 \cdot A(s) \end{align}\]

That is

\[\begin{align} \omega_z &= \frac{1}{R_PC_P} \tag{1} \\ \omega_n &= \sqrt{\frac{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}{R_LC_LR_PC_P}} = \sqrt{\omega_{p0}\omega_z} \\ \zeta & = \frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{R_PC_P} \frac{1}{2 \omega_n} \end{align}\]

Where \[\begin{align} \omega_{p0} &= \frac{1}{(R_L||\frac{1}{g_\text{m\_dio}}||\frac{1}{g_\text{ds\_tot}})C_L} \tag{2} \end{align}\]

Here, relate \(\omega_{p0}\) and \(\omega_z\) by coefficient \(\alpha\) \[ \omega_{p0} = \alpha \cdot \omega_z \tag{3} \] This way \[ \omega_n= \sqrt{\alpha}\cdot \omega_z \]

\[ \zeta = \frac{1}{2}(K\sqrt{\alpha}+\frac{1+C_P/C_L}{\sqrt{\alpha}}) \tag{4} \] where \[ K = \frac{R_L||\frac{1}{g_\text{m\_dio}}||\frac{1}{g_\text{ds\_tot}}}{R_L||g_\text{ds\_tot}} \]

And \(A(s)\) can be expressed as \[ A(s) = \frac{\frac{s}{\omega_z}+1}{\frac{s^2}{\omega_n^2}+2\frac{\zeta}{\omega_n}s+1} \] It magnitude in dB \[ A_\text{dB} = 10\log\frac{1+(\omega/\omega_z)^2}{1+(\omega/\omega_n)^4+2\omega^2(2\zeta^2-1)/\omega_n^2} \] Substitute \(\omega_n\) with Eq (2), followed is obtained \[ A_\text{dB} = 10\log{\frac{\alpha^2(\omega_z^4 + \omega_z^2\omega^2)}{\alpha^2\omega_z^4+\omega^4+2\alpha\omega_z^2(2\zeta^2-1)\omega^2}} \] peaking frequency \[ \omega_\text{peak} = \omega_z\cdot \sqrt{\sqrt{(\alpha+1)^2 - 4\alpha \zeta^2}-1} \] If \(\zeta=1\) \[\begin{align} \omega_{A_\text{dB = 0dB} }&= \sqrt{1-2/\alpha}\cdot \omega_{p0} \\ \omega_\text{peak} &= \omega_z\sqrt{\alpha-2} \\ A_\text{dB,peak} &= 10\log\frac{\alpha^2}{4(\alpha-1)} \end{align}\]

Miller multiplication of Capacitor

Positive Cap

Negative Cap

gain has limited bandwidth

\(V_o = V_i |A|e^{j\theta}\), and \(A_r = |A|\cos\theta\), \(A_i = |A|\sin\theta\)

Then \(I_i = (V_i - V_o)sC_f= V_i(1-|A|e^{j\theta})sC_f\), impedance is shown as below

\[\begin{align} Z &= \frac{V_i}{I_i} \\ &= \frac{1}{(1-|A|e^{j\theta})j\omega C_f} \\ &= -\frac{j}{\omega C_f\frac{1+|A|^2-2|A|\cos\theta}{1-|A|\cos\theta}} + \frac{|A|\sin\theta}{\omega C_f (1+|A|^2-2|A|\cos\theta)} \\ \end{align}\]

\(C_\text{eq}\) and \(R_\text{eq}\) are obtained \[\begin{align} C_\text{eq} &= \frac{1+|A|^2-2A_r}{1-A_r}\cdot C_f \\ R_\text{eq} &= \frac{A_i}{1+|A|^2-2A_r}\cdot \frac{1}{\omega C_f} \end{align}\]

D/S small signal model

The Drain and Source of MOS are determined in DC operating point, i.e. large signal.

That is, top of \(M_2\) is drain and bottom is source, \[\begin{align} R_\text{eq2} &= \frac{r_\text{o2}+R_L}{1+g_\text{m2}r_\text{o2}} \\ & \simeq \frac{1}{g_\text{m2}} \end{align}\]

PMOS small signal model polarity

The small-signal models of NMOS and PMOS transistors are identical

A negative \(\Delta V_\text{GS}\) leads to a negative \(\Delta I_D\).

Recall that \(I_D\), in the direction shown here, is negative because the actual current of holes flows from the source to the drain.

Conversely, a positive \(\Delta V_\text{GS}\) produces a positive \(\Delta I_D\), as is the case for an NMOS device.

Leakage in MOS

reference

W. M. Elgharbawy and M. A. Bayoumi, "Leakage sources and possible solutions in nanometer CMOS technologies," in IEEE Circuits and Systems Magazine, vol. 5, no. 4, pp. 6-17, Fourth Quarter 2005, doi: 10.1109/MCAS.2005.1550165.

X. Qi et al., "Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries," in IEEE Circuits and Devices Magazine, vol. 22, no. 5, pp. 39-47, Sept.-Oct. 2006, doi: 10.1109/MCD.2006.272999.

P. Monsurró, S. Pennisi, G. Scotti and A. Trifiletti, "Exploiting the Body of MOS Devices for High Performance Analog Design," in IEEE Circuits and Systems Magazine, vol. 11, no. 4, pp. 8-23, Fourthquarter 2011, doi: 10.1109/MCAS.2011.942751.

signal detection circuit

phase I

\[\begin{align} Q_a &= (V_{a0} - 0.5*(V_{ip} + V_{im}))*C + (V_{a0} - V_{th})*C \\ Q_b &= (V_{b0} - 0.5*(V_{ip} + V_{im}))*C + V_{b0}*C \end{align}\]

Phase II

\[\begin{align} Q_a &= (V_{a} - V_{ip})*C + (V_{a} - V_{b})*0.5C \\ Q_b &= (V_{b} - V_{im})*C + (V_{b} - V_{a})*0.5C \end{align}\]

With the law of charge conservation, we get

\[\begin{equation} V_a - V_b = (V_{a0} - V_{b0}) + 0.5*(V_{ip} - V_{im} - V_{th}) \end{equation}\]

REF: D. A. Yokoyama-Martin et al., "A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS," IEEE Custom Integrated Circuits Conference 2006, 2006, pp. 401-404, doi: 10.1109/CICC.2006.320970.

Power/Ground and I/O Pins

Power / Ground Pin Information

In both digital and analog I/O, power and ground pins appear at the sub-circuit definiton, allowing user to use the I/O in voltage islands. They follow certain naming conventions.

1. digital I/O sub-circuit

• VDD: pre-driver core voltage (supplied by PVDD1CDGM)
• VSS: pre-driver ground and also global ground (supplied by PVDD1CDGM)
• VDDPST: I/O post-driver voltage, i.e. 1.8V (supplied by PVDD2CDGM or PVDD2POCM)
• VSSPOST: I/O post-driver ground (supplied by PVDD2CDGM or PVDD2POCM)
• POCCTRL: POCCTRL signal (supplied by PVDD2POCM)

2. analog I/O placed in a core voltage domain, the convention is

• TACVDD: analog core voltage (supplied by PVDD3ACM)
• TACVSS: analog core ground (supplied by PVDD3ACM)
• VSS: global core ground

3. analog I/O placed in an I/O voltage domain, the convention is:

• TAVDD: analog I/O voltage, i.e. 1.8V (supplied by PVDD3AM)
• TAVSS: analog I/O ground (supplied by PVDD3AM)
• VSS: global core ground

Power/Ground Combo Cells

Note for the retention mode

1. At initial state, IRTE must be 0 when VDD is off.
2. IRTE must be kept >= 10us after VDD turns on again (from the retention mode to the normal operation mode).
3. IRTE can be switched only when both VDD and VDDPST are on.

When the rention function is needed, IRTE signal must come from an "always-on" core power domain. If you don't need the rention function, it is required to tie IRTE to ground. In other words, no matter the rention feature is needed or not, it is required to have PCBRTE in each domain.

Note: PCBRTE does not need PAD connection.

Internal Pins

There are 3 internal global pins, i.e. ESD, POCCTRL, RTE, in all digital domain cells.

In real application,

• ESD pin is an internal signal and active in ESD event happening
• POCCTRL is an internal signal and active in Power-on-control event.

However, these special events (i.e. ESD event and Power-on-control event) are not modeled in NLDM kit (.lib), only normal function is covered, so ESD and POCCTRL pins are simply defined as ground in NLDM kit (.lib).

These 3 global pins will be connected automatically after cell-to-cell abutting in physical layout.

Power-Up sequence in Digital Domain

Power up the I/O power (VDDPST) first, then the core power (VDD)

1. PVDDD2POCM cell would generate Power-On-Control signal (POCCTRL) to have the post-driver NMOS and PMOS off, so that the crowbar current would not occur in the post-driver fingers when the I/O voltage is on while the core voltage remains off. As such, I/O cell would be in the Hi-Z state. when POCCTRL is on, the pll-up/down resistor is disabled and C is 0.
2. The POCCTRL signal is transmitted to I/O cells through cell abutment. There is no need to have routing for POCCTTRL nor give a control signal to the POCCTRL pin any of I/O cells. Note that the POCCTRL signal would be cut if inserting a power-cut (PRCUT) cell.

Power-Down sequence in Digital Domain

It's the reverse of power-up sequence.

Use model in Innovus

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set init_gnd_net "vss_core vss DUMMY_ESD DUMMY_POCCTRL"

addInst -moduleBased u_io -ori R270 -physical -status fixed -loc 135 994 -inst u_io/VDDIO_1 -cell PVDD2CDGM_H

addNet u_io_RTE
attachTerm FILLER_6 RTE u_io_RTE
attachTerm VDDIO_1 RTE u_right_RTE
setAttribute -skip_routing true -net u_io_RTE

clearGlobalNets
globalNetConnect DUMMY_POCCTRL -type pgpin -pin POCCTRL -singleInstance u_io/VDDDIO_1 -override
globalNetConnect DUMMY_ESD -type pgpin -pin ESD -singleInstance u_io/VDDDIO_1 -override

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set pins [get_object_name [get_ports *]]
foreach pin $pins {
	set netPtr [dbGetNetByName $pin]
	if { $netPtr == "0x0" } {
		puts "INFO: can't find the port: $pin"
	} else {
		setAttribute -net $pin -skip_routing true
	}
}

foreach net [get_object_name [get_nets -of_objects [get_pins */RTE -hierarchical]]] {
	setAttribute -net $net -skip_routing true
	dbSet [dbGetNetByName $net].dontTouch true
}

Antenna Effect

The antenna effect is a common name for the effects of charge accumulation in isolated nodes of an integrated circuit during its processing.

This effect is also sometimes called "Plasma Induced Damage", "Process Induced Damage" (PID) or "charging effect".

antenna ratio

The antenna rule specifies the maximum tolerance for the ratio of a metal line area to the area of connected gates.

metal jumping

Long metal can be taken to higher metal routing layer. This is known as metal jumping.

This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

Diode Insertion

Diode helps dissipate charges accumulated on metal. Diode should be placed as near as possible to the gate of device on low level of metal.

Diode should always be connected in reverse bias, with cathode connected to gate electrode and anode connected to ground potential.

During processing, even if the diodes are reversely biased, because of the elevated wafer temperature (200 o C plus) it will provide a much conductive path

In the reverse bias region, the reverse saturation current of Si and Ge diodes doubles for every 10° C rise in temperature

Tuvia Liran, Antenna effect (PID): Do the design rules really protect us? [link]

Upma Pawan Kumar, Sunandan Chaubey, Antenna Effect in 16nm Technology Node [link]

pulsic.com, Analog layout – Stop the antenna effect from destroying your circuit [link]

BuBuChen, 積體電路的天線效應 (Antenna Effect in IC) [link]

EDN, Antenna violations resolved using new method [link]

edaboard.com, why jump up metal can solve the antenna effect? [link]

siliconvlsi.com, Antenna effect [link]

Prof. Adam Teman, Digital VLSI Design. Lecture-10-The-Manufacturing-Process [pdf]

Zongjian Chen, Processing and Reliability Issues That Impact Design Practice. [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/lect_15_2up.pdf]

Metastability and Synchronizer

When a flip-flop samples an input that is changing during its aperture, the output Q may momentarily take on a voltage between 0 and VDD that is in the forbidden zone. This is called a metastable state. Eventually, the flip-flop will resolve the output to a stable state of either 0 or 1. However, the resolution time required to reach the stable state is unbounded

Steve Golson. Synchronization and Metastability [https://trilobyte.com/pdf/golson_snug14.pdf]

R. Ginosar, "Metastability and Synchronizers: A Tutorial," in IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23-35, Sept.-Oct. 2011, doi: 10.1109/MDT.2011.113. [https://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf]

Kinniment, D. J. Synchronization and arbitration in digital systems. John Wiley & Sons Ltd (2007).

Slewing

In practice, we choose \(I_P \simeq I_{SS}\)

Avoid zero current in cascodes

• left circuit

  \(I_b \gt I_a\)

• right circuit

  \(I_b \gt 2I_a\)

Step Response of higher order system

Since \(1/sC_1+R_1 \gg R_0\) \[ \frac{V_m}{V_i}(s) \simeq \frac{R_0}{R_0 + 1/sC_0} = \frac{sR_0C_0}{1+sR_0C_0} \] step response of \(V_m\) \[ V_m(t) = e^{-t/R_0C_0} \] where \(\tau = R_0C_0\)

And \(V_o(s)\) can be expressed as \[\begin{align} \frac{V_o}{V_i}(s) & \simeq \frac{sR_0C_0}{1+sR_0C_0} \cdot \frac{sR_1C_1}{1+sR_1C_1} \\ &= \frac{sR_0C_0R_1C_1}{R_0C_0-R_1C_1}\left(\frac{1}{1+sR_1C_1} - \frac{1}{1+sR_0C_0}\right) \end{align}\]

Then step response of \(Vo\) \[\begin{align} Vo(t) &= \frac{R_0C_0R_1C_1}{R_0C_0-R_1C_1} \left(\frac{1}{R_1C_1}e^{-t/R_1C_1} - \frac{1}{R_0C_0}e^{-t/R_0C_0}\right) \\ &= \frac{1}{R_0C_0-R_1C_1}\left(R_0C_0e^{-t/R_1C_1} - R_1C_1e^{-t/R_0C_0}\right) \\ &\simeq = \frac{1}{R_0C_0-R_1C_1}\left(R_0C_0e^{-t/R_1C_1} - R_1C_1\right) \end{align}\]

where \(\tau=R_1C_1\)

Partial-fraction Expansion

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syms C0
syms R0
syms C1
syms R1
syms s

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

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>> partfrac(vm, s)
 
ans =
 
1 - (s*(C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1)
 
>> partfrac(vo, s)
 
ans =
 
1 - (s*(C0*R0 + C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1)

\[\begin{align} V_m(s) &= 1 - \frac{s(C_1R_0+C_1R_1)+1}{C_0C_1R_0R_1s^2+(C_0R_0+C_1R_0+C_1R_1)s+1} \\ V_o(s) &= 1 - \frac{s(C_0R_0+C_1R_0+C_1R_1)+1}{C_0C_1R_0R_1s^2+(C_0R_0+C_1R_0+C_1R_1)s+1} \end{align}\]

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C0 = 200e-9;
R0 = 50;
C1 = 400e-15;
R1 = 200e3;

s = tf("s");

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

vm_exp = 1 - (s*(C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1);
vo_exp = 1 - (s*(C0*R0 + C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1);

figure(1)
subplot(1,2,1)
step(vm, 500e-9, 'k-o');
hold on;
step(vm_exp, 500e-9, 'r-^')
title('vm step response')
grid on;
legend()


subplot(1,2,2)
step(vo, 500e-9, 'k-o');
hold on;
step(vo_exp, 500e-9, 'r-^')
title('vo step response')
grid on;
legend()


% with approximation
figure(2)
vm_exp2 = s*R0*C0/(1+s*R0*C0);
vo_exp2 = s*R0*C0/(1+s*R0*C0) * s*R1*C1/(1+s*R1*C1);

subplot(1,2,1)
step(vm, 500e-9, 'k-o');
hold on;
step(vm_exp2, 500e-9, 'r-^')
title('vm step response')
grid on;
legend()

subplot(1,2,2)
step(vo, 500e-9, 'k-o');
hold on;
step(vo_exp2, 500e-9, 'r-^')
title('vo step response')
grid on;
legend()

spectre simulation vs matlab

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C0 = 200e-9;
R0 = 50;
C1 = 400e-15;
R1 = 200e3;

s = tf("s");

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

step(vm, 500e-9);
hold on;
step(vo, 500e-9);

grid on

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>> vm

vm =
 
          1.024e-44 s^5 + 2.56e-37 s^4 + 1.6e-30 s^3
  -----------------------------------------------------------
  1.024e-44 s^5 + 2.571e-37 s^4 + 1.626e-30 s^3 + 1.6e-25 s^2
 
Continuous-time transfer function.

>> vo

vo =
 
                 8.194e-52 s^6 + 2.048e-44 s^5 + 1.28e-37 s^4
  ---------------------------------------------------------------------------
  8.194e-52 s^6 + 3.081e-44 s^5 + 3.871e-37 s^4 + 1.638e-30 s^3 + 1.6e-25 s^2
 
Continuous-time transfer function.

reference

M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17, no. 1, pp. 31-41, Jan. 2001, doi: 10.1109/101.900125.

Open loop gain analysis and "STB" method [https://www.linkedin.com/pulse/open-loop-gain-analysis-stb-method-jean-francois-debroux]

The Analog Designer's Toolbox (ADT) | Invited Talk by IEEE Santa Clara Valley Section CAS Society, https://youtu.be/FT6kKC5OdE0

ESSCIRC2023 Circuit Insights Ali Sheikholeslami [https://youtu.be/2xFIZM5_FPw?si=XWwSzDgKWZGB0rX1]

Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 3 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 4, pp. 7-8, Fall 2018.

Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 2 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 3, pp. 7-8, Summer 2018.

Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 1 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 2, pp. 7-8, Spring 2018.

Ali Sheikholeslami, Circuit Intuitions: Miller's Approximation IEEE Solid-State Circuits Magazine, Vol. 7, Issue 4, pp. 7-8, Fall 2015.

Ali Sheikholeslami, Circuit Intuitions: Miller's Theorem IEEE Solid-State Circuits Magazine, Vol. 7, Issue 3, pp. 8-10, Summer 2015.

Shanthi Pavan, "Demystifying Linear Time Varying Circuits"

ecircuitcenter. Switched-Capacitor Resistor [http://www.ecircuitcenter.com/Circuits/SWCap/SWCap.htm]

Jørgen Andreas Michaelsen. INF4420 Switched-Capacitor Circuits. [https://www.uio.no/studier/emner/matnat/ifi/INF4420/v13/undervisningsmateriale/inf4420_v13_07_switchedcapacitor_print.pdf]

chembiyan T. OC Lecture 10: A very basic introduction to switched capacitor circuits [https://youtu.be/SaYtemYp4rQ?si=q2qovTKJrLy65pnu

Robert Bogdan Staszewski, Poras T. Balsara. "All‐Digital Frequency Synthesizer in Deep‐Submicron CMOS"

Mayank Parasrampuria, Sandeep Jain, Burn-in 101 [link]

In Guest OS and run

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sudo vmware-toolbox-cmd disk shrink /

https://superuser.com/q/211798

Mismatch between the pole and zero frequencies leads to the “doublet problem”. If the pole and the zero do not exactly coincide, we say that they constitute a doublet

Problem 10.19 in Razavi 2nd book

Suppose the open-loop transfer function of a two-stage op amp is expressed as \[ H_{open}(s)=\frac{A_0(1+\frac{s}{\omega_z})}{\left( 1+ \frac{s}{\omega_{p1}}\right)\left( 1+ \frac{s}{\omega_{p2}}\right)} \] Ideally, \(\omega_z=\omega_2\) and the feedback circuit exhibits a first-order behavior, i.e., its step response contains a single time constant and no overshoot.

Then the transfer function of the amplifier in a unity-gain feedback loop is given by \[\begin{align} H_{closed}(s) &=\frac{A_0\left(1+\frac{s}{\omega_z}\right)}{\frac{s^2}{\omega_{p1}\omega_{p2}}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)s+A_0+1} \\ &=\frac{\frac{A_0}{A_0+1}(1+\frac{s}{\omega_z})}{\frac{s^2}{\omega_{p1}\omega_{p2}(A_0+1)}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)\frac{s}{A_0+1}+1} \end{align}\]

The denominator part of \(H_{closed}(s)\) is \[ D(s) = \frac{s^2}{\omega_{p1}\omega_{p2}}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)s+A_0+1 \]

Assuming two poles (\(\omega_{pA} \ll\omega_{pB}\)) of \(H_{closed}(s)\) are widely spaced, \[\begin{align} D(s) &= \left( 1+ \frac{s}{\omega_{pA}}\right)\left( 1+ \frac{s}{\omega_{pB}}\right)\\ &\cong \frac{s^2}{\omega_{pA}\omega_{pB}}+\frac{s}{\omega_{pA}} + 1 \end{align}\]

Thus, the two poles of the closed-loop transfer function of system are \[\begin{align} \omega_{pA} &= \frac{A_0+1}{\frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}} \\ &= \frac{(A_0+1)\omega_{p1} \omega_{p2}}{\omega_{p1} + \omega_{p2} + \frac{A_0}{\omega_z}\omega_{p1} \omega_{p2}} \\ \omega_{pB} &= \omega_{p1} + \omega_{p2} + \frac{A_0}{\omega_z}\omega_{p1} \omega_{p2} \end{align}\]

Assuming \(\omega_z \simeq \omega_{p2}\) and \(\omega_{p2}\ll (1+A_0)\omega_{p1}\) \[ \omega_{pA} = \omega_{p2} \] and \[ \omega_{pB} = (1+A_0)\omega_{p1} \] The closed-loop transfer function is \[ H_{closed}(s) = \frac{\frac{A_0}{A_0+1}\left(1+\frac{s}{\omega_z}\right)}{\left(1+\frac{s}{(1+A_0)\omega_{p1}}\right)\left( 1+\frac{s}{\omega_{p2}} \right)} \]

The step response of the closed-loop amplifier

Consider the Laplace transform function of step response, \(X(s)=\frac{1}{s}\) \[ Y(s)=\frac{1}{s}\times H_{closed}(s) \] Thus, the small-signal step response of the closed-loop amplifier is \[ y(t)=\frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) \] Since, \(\omega_{p2}\ll (1+A_0)\omega_{p1}\). Therefore, rewrite the \(y(t)\) \[ y(t)\cong \frac{A_0}{A_0+1}\left[1-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) \] The step response contains an exponential term of the form \(\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t}\). This is an important result, indicating that if the zero does not exactly cancel the pole, the step response exhibits an exponential with an amplitude proportional to \(\left(1-\frac{\omega_{p2}}{\omega_z}\right)\), which depends on the mismatch between \(\omega_z\) and \(\omega_{p2}\) and a time constant \(\tau\) of \(\frac{1}{\omega_{p2}}\) or \(\frac{1}{\omega_{z}}\)

perfect pole-zero cancellation

\[\begin{align} y(t) &=\frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) \\ &= \frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}\right]u(t) \end{align}\]

The zero comes from the mirror node

Thanks to unity gain buffer, zero is alleviated for \(C_c\)

reference

Elad Alon, Lecture 10: Settling-Limited Amplifier Design Methodology, EE 240B – Spring 2018, Advanced Analog Integrated Circuits https://inst.eecs.berkeley.edu/~ee240b/sp18/lectures/Lecture10_Settling_Design_2up.pdf

Eric Chang, Prof. Elad Alon EE240B HW3 https://inst.eecs.berkeley.edu/~ee240b/sp18/homeworks/hw3.pdf and https://inst.eecs.berkeley.edu/~ee240b/sp18/homeworks/hw3_soln.pdf

Prof. Tai-Haur Kuo, Analog IC Design ( 類比積體電路設計 ), Operational Amplifiers http://msic.ee.ncku.edu.tw/course/aic/201809/chapter5.pdf

B. Y. T. Kamath, R. G. Meyer and P. R. Gray, "Relationship between frequency response and settling time of operational amplifiers," in IEEE Journal of Solid-State Circuits, vol. 9, no. 6, pp. 347-352, Dec. 1974, doi: 10.1109/JSSC.1974.1050527.

B. Y. T. Kamath, R. G. Meyer and P. R. Gray, "Relationship between frequency response and settling time of operational amplifiers," in IEEE Journal of Solid-State Circuits, vol. 9, no. 6, pp. 347-352, Dec. 1974, doi: 10.1109/JSSC.1974.1050527.

P. R. Gray and R. G. Meyer, "MOS operational amplifier design-a tutorial overview," in IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 969-982, Dec. 1982, doi: 10.1109/JSSC.1982.1051851.

SERGIO FRANCO, Demystifying pole-zero doublets URL:https://www.edn.com/demystifying-pole-zero-doublets/