KNOW-HOW

Generic circuit in textbook

In addition to lowering the required capacitor value, Miller compensation entails a very important property: it moves the output pole away from the origin. This effect is called pole splitting

The 1st stage is replaced with Thevenin equivalent circuit , V_i ≅ V_i ⋅ g_m1R_o1

$$\begin{align} \frac{V_i-V_{o1}}{R_{o1}} &= V_{o1}\cdot sC_{o1}+(V_{o1}-V_o)\cdot sC_c \\ V_{o1} &= \frac{V_i+sR_{o1}C_cV_o}{1+sR_{o1}(C_{o1}+C_c)} \end{align}$$ $$ (V_{o1}-V_o)sC_c=g_{m2}V_{o1}+V_o(\frac{1}{R_{o2}+sC_L}) $$ substitute V_o1, we get

$$\begin{align} \frac{V_o}{V_i} &= \frac{(sC_c-g_{m2})R_{o2}}{s^2R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) \right\} +1} \\ &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)}{s^2R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) \right\} +1} \end{align}$$

left hand plane poles

$$\begin{align} \omega_1 &= \frac{1}{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)} \\ \omega_2 &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \end{align}$$

and RHP (right-hand plane) zero $$ \omega_z=\frac{g_{m2}}{C_c} $$

The circuit with series switch

replace sC_L with $1/(R_{sw}+\frac{1}{sC_L})$ $$\begin{align} \frac{V_{o2}}{V_i} &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)(1+sR_{sw}C_L)}{s^3R_{o1}R_{o2}R_{sw}C_{o1}C_cC_L+s^2\left\{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+ \left[ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+0)+R_{o1}(C_{o1}+C_c)\right]R_{sw}C_L \right\}+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) +R_{sw}C_L\right\} +1} \end{align}$$ Due to $$ \frac{V_o}{V_{o2}} = \frac{\frac{1}{sC_L}}{R_{sw}+\frac{1}{sC_L}}=\frac{1}{1+sR_{sw}C_L} $$ Then $$\begin{align} \frac{V_o}{V_i} &= \frac{V_{o2}}{V_i} \cdot \frac{V_o}{V_{o2}} \\ &= \frac{g_{m2}R_{o2}(s\frac{C_c}{g_{m2}}-1)}{s^3R_{o1}R_{o2}R_{sw}C_{o1}C_cC_L+s^2\left\{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)+ \left[ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+0)+R_{o1}(C_{o1}+C_c)\right]R_{sw}C_L \right\}+s\left\{ R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c) +R_{sw}C_L\right\} +1} \end{align}$$

R_sw and R_c

$$\begin{align} \frac{V_{o2}}{V_i} &=-g_{m2}R_{o2}\frac{sC_c(R_c-1/g_{m2})+1}{(1+sR_{o1}C_{o1})sR_{o2}C_c+sR_{o1}\cdot g_{m2}R_{o2}C_c+\frac{s(R_{o2}+R_{sw})C_L+1}{sR_{sw}C_L+1}\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \\ &=-g_{m2}R_{o2}\frac{sC_c(R_c-1/g_{m2})+1}{s^2R_{o1}R_{o2}C_{o1}C_c+sR_{o2}C_c+sR_{o1}\cdot g_{m2}R_{o2}C_c+\frac{s(R_{o2}+R_{sw})C_L+1}{sR_{sw}C_L+1}\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \\ &=-g_{m2}R_{o2}\frac{\left[ sC_c(R_c-1/g_{m2})+1 \right](sR_{sw}C_L+1)}{s^2R_{o1}R_{o2}C_{o1}C_c(sR_{sw}C_L+1)+sR_{o2}C_c(sR_{sw}C_L+1)+sR_{o1}\cdot g_{m2}R_{o2}C_c(sR_{sw}C_L+1)+\left[s(R_{o2}+R_{sw})C_L+1\right]\left[(1+sR_{o1}C_{o1})(1+sR_cC_c)+sR_{o1}C_c \right]} \end{align}$$

s³ terms in denominator H₃ = s³ ⋅ (R_o1R_o2R_c+R_o1R_o2R_sw+R_o1R_cR_sw) ⋅ C_o1C_cC_L s² terms in denominator $$\begin{align} H_2 &=s^2\cdot(R_{o1}R_{o2}C_{o1}C_c+R_{o1}R_{o2}C_{o1}C_L+R_{o2}R_cC_cC_L+R_{o1}R_{o2}C_cC_L+R_{o1}R_cC_{o1}C_c\\ &+R_{o2}R_{sw}C_cC_L+R_{o1}R_{sw}C_cC_L\cdot g_{m2}R_{o2}+R_{o1}R_{sw}C_{o1}C_L+R_{sw}R_cC_cC_L+R_{o1}R_{sw}C_cC_L) \end{align}$$

s¹ term in denominator H₁ = s(R_o1⋅g_m2R_o2C_c+R_o1C_o1+R_cC_c+R_o1C_c+R_o2C_c+R_o2C_L+R_swC_L) s⁰ term in denominator H₀ = 1 set R_c = 0 and R_sw = 0, the H_* reduced to $$\begin{align} H_3 &= 0 \\ H_2 &=s^2R_{o1}R_{o2}(C_{o1}C_c+C_{o1}C_L+C_cC_L) \\ H_1&=s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_{o1}C_{o1}+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L) \\ H_0&=1 \end{align}$$ That is H = s²R_o1R_o2(C_o1C_c+C_o1C_L+C_cC_L) + s(R_o1⋅g_m2R_o2C_c+R_o1C_o1+R_o1C_c+R_o2C_c+R_o2C_L) + 1

which is same with our previous analysis of Generic circuit in textbook

And we know $$ \frac{V_o}{V_{o2}}=\frac{1}{1+sR_{sw}C_L} $$ Finally, we get $\frac{V_o}{V_i}$ $$\begin{align} \frac{V_o}{V_i} &= \frac{V_{o2}}{V_i} \cdot \frac{V_o}{V_{o2}} \\ &= -g_{m2}R_{o2}\frac{\left[ sC_c(R_c-1/g_{m2})+1 \right](sR_{sw}C_L+1)}{H_3+H_2+H_1+1} \cdot \frac{1}{1+sR_{sw}C_L} \\ &= -g_{m2}R_{o2}\frac{ sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1} \end{align}$$

The loop transfer function is $$ \frac{V_o}{V_i} =-g_{m1}R_{o1}g_{m2}R_{o2}\frac{ sC_c(R_c-1/g_{m2})+1}{H_3+H_2+H_1+1} $$

vccs model

simplify the transfer function

omit C_o1

We omit C_o1 in frequency range of interest

$$\begin{align} H_3 &= 0 \\ H_2 &=s^2(R_{o2}R_c+R_{o1}R_{o2}+R_{o2}R_{sw}+R_{o1}R_{sw}\cdot g_{m2}R_{o2}+R_{sw}R_c+R_{o1}R_{sw})\cdot C_cC_L \\ H_1 &=s(R_{o1}\cdot g_{m2}R_{o2}C_c+R_cC_c+R_{o1}C_c+R_{o2}C_c+R_{o2}C_L+R_{sw}C_L) \\ H_0 &= 1 \end{align}$$

two poles and 1 zero

more simplification

Then, some terms can be omitted

$$\begin{align} H_2 &=s^2R_{o1}R_{o2}(1+g_{m2}R_{sw})\cdot C_cC_L \\ H_1 &=sR_{o1}\cdot g_{m2}R_{o2}C_c \\ H_0 &= 1 \end{align}$$

The poles can be deduced $$\begin{align} \omega_1 &= \frac{1}{R_{o1}\cdot g_{m2}R_{o2}C_c} \\ \omega_2 &= \frac{1}{1+g_{m2}R_{sw}}\cdot \frac{g_{m2}}{C_L} \\ &= \frac{1}{(gm_2^{-1}+R_{sw})C_L} \end{align}$$

The pole $\omega_2=\frac{1}{gm_2^{-1}C_L}$ is changed to $\omega_2=\frac{1}{(gm_2^{-1}+R_{sw})C_L}$

In order to cancell ω₂ with ω_z, R_c shall be increased

R_eq = g_m2⁻¹ + R_sw

omit C_o1 is same with 2nd system simplification

non-dominant pole in Sansen’s book

Following demonstrate how derive f_nd from Razavi’s equation. We copy ω₂ here $$ \omega_2 = \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} $$ which can be reduced as below

$$\begin{align} \omega_2 &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}+R_{o2}(C_c+C_L)+R_{o1}(C_{o1}+C_c)}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \\ &= \frac{R_{o1}C_c\cdot g_{m2}R_{o2}}{R_{o1}R_{o2}(C_cC_{o1}+C_LC_{o1}+C_LC_c)} \\ &= \frac{C_c\cdot g_{m2}}{C_cC_{o1}+C_LC_{o1}+C_LC_c} \\ &= \frac{g_{m2}}{C_{o1}+C_L\frac{C_{o1}}{C_c}+C_L} \\ &= \frac{g_{m2}}{C_L\frac{C_{o1}}{C_c}+C_L} \\ &= \frac{g_{m2}}{C_L} \cdot \frac{1}{1+\frac{C_{o1}}{C_c}} \end{align}$$

Exercise of 2-stage opamp

R_o1 and R_o2 don’t affect stability, if f_nd > 3GBW

DC gain: g_m1g_m2R_o1R_o2

dominant pole: $\omega_d=\frac{1}{R_{o1}\cdot g_{m2}R_{o2}C_c}$

20log₁₀(1.414²) = 6dB

reference

Razavi, Behzad. Design of Analog CMOS Integrated Circuits. India: McGraw-Hill, 2017.

Sansen, Willy M. Analog Design Essentials. Germany: Springer US, 2006.

Gain-boosted cascode

TODO 📅

Zero-Value Time Constant Analysis

TODO 📅

Transmission Gate

Equivalent Resistance is defined by large signal

[https://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/TGlecture.pdf]

Noise and Distortion

TODO 📅

Ali Sheikholeslami, University of Toronto, A-SSCC 2024 Circuit Insights:FT1 Noise and Distortion [link]

Response Speed in Analog Circuits

Hyun-Sik Kim, KAIST, A-SSCC 2024 Circuit Insights: FT3 Accelerating Response Speed in Analog Circuits [link]

Bandwidth limitation

slew rate limitation

Assuming linear response V_o(t) = 1 − e^−ω_Tt

$$ \frac{dV_o}{dt} = \omega_Te^{-\omega_T t} = \frac{g_m}{C_L}e^{-\omega_T t} = \frac{g_m}{I_B}\cdot \frac{I_B}{C_L}\cdot e^{-\omega_T t} \gt \frac{I_B}{C_L} $$

where $\frac{g_m}{I_B} e^{-\omega_T t} \gt 1$ at initial response

Therefore, initial response speed is dominated by SR, rather than G_m (or bandwidth)

Slew Rate vs. Bandwidth

Device Current Components

common gate amplifiers

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_analog-analogdesign-rfdesign-activity-7126946716938878976-GeW6?utm_source=share&utm_medium=member_desktop]

Shot Noise

Any dc current flowing through a diode generates the so-called “shot noise” due to the random nature of the hole and electron transitions across the pn junction

Shot noise is not relevant in CMOS devices since it is only present in bipolar transistors and junction diodes

Level Shifter

TIA

$$\begin{align} I_{in} &= \frac{V_i}{R_S} + \frac{V_i - V_o}{R_F} \\ \frac{V_i - V_o}{R_F} &= g_m V_i \end{align}$$

Then

$$\begin{align} V_o &= \frac{I_{in}R_F}{\frac{R_S+R_F}{R_S}\frac{1}{1-g_mR_F}- 1} \\ V_i &= \frac{I_{in}R_F}{\frac{R_F}{R_S}+g_mR_F} \end{align}$$ If R_S ≫ R_F $$\begin{align} V_o &= \frac{I_{in}}{g_m}(1-g_mR_F) \\ V_i &= \frac{I_{in}}{g_m} \end{align}$$

linearity

TIA stage allows for improved gain with better linearity, as mostly signal current passes through R_F TODO 📅 ??? Quantitative analysis

Switched-Capacitor Resistor

$$ R_{eq} = \frac{1}{f_sC} $$

Channel-Length Modulation & Pinched off

• $\lambda \propto \frac{1}{L_g}$
• $\lambda \propto \frac{1}{V_{DS}}$

• If V_DS is slightly greater than V_GS − V_TH, then the inversion layer stops at x ≤ L, and we say the channel is “pinched off”
• Upon passing the pinchoff point, the electrons simply shoot through the depletion region near the drain junction and arrive at the drain terminal

L^′ is the function of V_DS

with $\frac{1}{L^{'}} = \frac{1}{L-\Delta L}=\frac{L+\Delta L}{L^2-\Delta L^2}\approx \frac{1}{L}\left(1+\frac{\Delta L}{L}\right)$, we have $$ I_D \approx \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(1+\frac{\Delta L}{L}\right)(V_{GS}-V_{TH})^2 = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2 (1+\lambda V_{DS}) $$ assuming $\frac{\Delta L}{L} = \lambda V_{DS}$

λ represents the relative variation in length for a given increment in V_DS. Thus, for longer channels, λ is smaller

In reality, however, r_O varies with V_DS. As V_DS increases and the pinch-off point moves toward the source, the rate at which the depletion region around the source becomes wider decreases, resulting in a higher incremental output impedance.

Early Voltage indicator

$$ g_m r_o = \frac{g_m}{I_D}I_D \cdot \frac{V_A}{I_D} = \frac{g_m}{I_D} \cdot V_A $$

$g_m r_o $ is the indicator of V_A, if $\frac{g_m}{I_D}$ is same

Resonator

bandpass filter

Hossein Hashemi, RF Circuits, [https://youtu.be/0f3yZMvD2Jg?si=2c1Q4y6WJq8Jj8oN]

Cgd of Common-Source Stage

Miller effect of Cgd during layout

Nonlinearity of Differential Circuits

$$ \cos^3\omega t = \frac{3\cos \omega t + \cos(3\omega t)}{4} $$

Zero in differential pair with active current mirror

Noting the circuit consists of a “slow path” (M1, M3, M4) in parallel with a “fast path” (M2)

• “slow path” $$ H_\text{slow}(s) = \frac{A_0}{(1+s/\omega _{pE})(1+s/\omega _{pO})} $$

• “fast path” $$ H_\text{fast}(s) = \frac{A_0}{1+s/\omega _{pO}} $$

Then $$\begin{align} \frac{V_\text{out}}{V_\text{in}} &= H_\text{slow}(s) + H_\text{fast}(s) \\ &= \frac{A_0}{1+s/\omega _{pO}}\left(\frac{1}{1+s/\omega _{pE}} + 1 \right) \\ &= \frac{A_0(1+s/2\omega _{pE})}{(1+s/\omega _{pO})(1+s/\omega _{pE})} \end{align}$$

That is, the system exhibits a zero at 2ω_pE

signals traveling through two paths within an amplifier may cancel each other at one frequency, creating a zero in the transfer function

$$ \omega_z = \frac{(A_1+A_2)\omega_{p1}\omega_{p2}}{A_1\omega_{p1}+A_2\omega_{p2}} $$ noting ω_p1 < ω_z < ω_p2

“Zero” by Inspection

a method to predict the existence of “zero” by inspection, based on the concept of “Analog Phase Interpolation”

TODO 📅

Debashis Dhar, How to Recognize “Zero” by Inspection (Utilizing Analog Phase Interpolation) [https://www.linkedin.com/posts/debashis-dhar-12487024_how-to-recognize-zero-by-inspection-activity-7163364364329160704-9qOq?utm_source=share&utm_medium=member_desktop]

Random offset

The dependence of offset voltage and current mismatches upon the overdrive voltage is similar to our observations for corresponding noise quantities

differential pair

In reality, since mismatches are independent statistical variables

Above shows that the input transistors must be designed for high gain ($g_mr_o = \frac{2}{V_{OV}\lambda}$), which means they must be designed for small V_GS − V_TH.

It is desirable to minimize V_GS − V_TH by lowering the tail current or increasing the transistor widths

For $\frac{\Delta K}{K}$

$$\begin{align} v_{os} g_m &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} 2K\frac{W}{L}(V_{GS}-V_{TH}) &= \Delta K \frac{W}{L}(V_{GS}-V_{TH})^2 \\ v_{os} &= \frac{V_{GS}-V_{TH}}{2} \frac{\Delta K}{K} \end{align}$$

The derivation for $\frac{\Delta W/L}{W/L}$ is same with $\frac{\Delta K}{K}$

alternative derivation

$$\begin{align} \Delta V_\beta \cdot g_m &= \frac{\partial I_D}{\partial \beta} \Delta \beta \\ &= I_D \frac{\Delta \beta}{\beta} \end{align}$$

That is $\Delta V_\beta = \frac{I_D}{g_m}\frac{\Delta \beta}{\beta}$

ΔV_R ⋅ g_mR = I_D ⋅ ΔR

That is $\Delta V_R = \frac{I_D}{ g_m} \cdot \frac{\Delta R}{R}$

[https://electronicengineering.phd.upc.edu/en/courses-and-seminars/courses-materials/2008-2009/slides-makinwa-1]

current mirror

To minimize current mismatch, the overdrive voltage must be maximized, a trend opposite to that in differential pair.

This is because as V_GS − V_TH increases, threshold mismatch has a lesser effect on the device currents

$\Delta I_D= g_m \Delta V_{TH} = \frac{2I_D}{V_{OV}}\Delta V_{TH}$

Effect of Feedback on Noise

Feedback does not improve the noise performance of circuits.

The input-referred noise voltage and current remain the same if the feedback network introduces no noise.

Burn-in & High-temperature operating life (HTOL)

• HTOL:
  • characterization test
  • characterize the life expectancy
• Burn-in:
  • production test
  • weed out defective products

HTOL and Burn-in Testing capture the two ends of the reliability characterization graph known as the “bathtub curve”

[https://arworld.us/the-importance-of-htol-and-burn-in-testing-methods/]

RC charge & discharge

• charge: $$ V_o(t) = V_{X}(1-e^{-\frac{t}{\tau}}) + V_{o,0}\cdot e^{-\frac{-t}{\tau}} $$

• discharge: $$ V_o(t) = V_{o,0}\cdot e^{-\frac{t}{\tau}} + V_{o,\infty}\cdot(1-e^{-\frac{t}{\tau}}) $$

1. $e^{-\frac{t}{\tau}}$ item determine the initial state
2. $(1-e^{-\frac{t}{\tau}})$ item determine the final state

AC coupling

$V_m=\frac{1}{4},\space \frac{3}{4}$ and its common voltage $\frac{1}{2}$

$V_o=-\frac{1}{4},\space \frac{1}{4}$ and its common voltage 0

τ = 200nF × (50+50)ohm = 20μs

high level envelope:

Current mirror with source degeneration

Razavi 2nd, problem 14.15

Monitored Analog Critical Parameters

Parameter Definition:

$$\begin{align} I_{\text{D,lin}} &= I_D \mid _{V_G=V_{DD},V_D=0.05V} \\ I_{\text{D,sat}} &= I_D \mid _{V_G=V_D=V_{DD}} \\ V_{\text{t,lin}} &= V_G \mid _{I_D=I_{\text{thx}}\cdot \frac{W}{L}@\{V_D=0.05V\}} \end{align}$$

I_thx could be different for technologies. (For N16, I_thx = 10nA)

Constant Current Threshold Voltage

gm-Maximum Method

[Inspect 4. Extracting Standard Parameters]

STB and PSTB in Spectre/RF

All credits to my colleague, Zhang Wenpian. > F. Wiedmann, “Loop gain simulation,” Online:[https://sites.google.com/site/frankwiedmann/loopgain]

STB analysis

Spectre stb’s “loopgain” is negative of “T” in paper^[1] $$ T = \frac{2(AD-BC) - A + D}{2(AD-BC)-A+D-1} $$

AC simulation testbench, shown as below,

1. I_inj = 0, V_inj = 1

   B = if, D = ve

2. I_inj = 1, V_inj = 0

   A = if, C = ve

PSTB analysis

Spectre pstb is similar to stb, just set pac as 1 instead of ac in current source and voltage source.

This analysis just use harmonic 0 transfer function in pac analysis, which has limitation.

Thevenin and Norton Equivalent Circuits

戴维南定理

等效电阻的计算方法

使用外加电源法时， 全部独立电源需要置零

诺顿定理

Lemma of Razavi

A_V =  − G_mR_out

Design of Analog CMOS Integrated Circuits, Second Edition - Behzad Razavi

Miller’s Approximation: right-half-plane zero

A quick inspection of this circuit reveals that a zero lies at a frequency where the current through C₁₂ becomes equal to g₂V₁.

When this occurs, the current through the parallel combination of C₂ and R₂ becomes zero, creating a zero in the transfer function.

In other words, we can write

$$\begin{align} g_2V_1 &= V_1sC_{12} \\ s &= \frac{g_2}{C_{12}} \end{align}$$

Nonoverlapping clock

Classical

DWC

C2PHIa is important to ensure nonoverlapping and DelayA2B is due to level shifter

Single ended Amplifier Offset Voltage

unity gain buffer

$$\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \end{align}$$

Then, we get $$ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) $$ Due to V_o = V_m and V_o′ = V_m′ V_os = (1/A+1)ΔV_m or V_os = (1/A+1)ΔV_o if A ≫ 1 V_os = ΔV_o

non-inverting amplifier

$$\begin{align} V_o &= V_{o,dc}+A(V_p-V_m) \\ V_o' &= V_{o,dc}+A(V_p+V_{os}-V_m') \\ V_m &= \beta V_o \\ V_m' &= \beta V_o' \end{align}$$

we get $$ V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m) $$ or $$ V_{os}=\frac{\Delta V_o}{A}+\beta \Delta V_o $$ if A ≫ 1 V_os = βΔV_o or V_os = ΔV_m

Lecture 22 Variability and Mismatch of Dr. Hesham A. Omran’s Analog IC Design

URL: https://www.master-micro.com/professional-courses/analog-ic-design/course-resources

Gotcha MOS ron

There is discrepancy between model operating point and V_ds/I_ds

I believe that the equation V_ds/I_ds is more appropriate where mos is used as switch, though V_ds = 0 is an outlier.

Schmitt Inverter

gm/ID Intuition

small gm/ID for High ro, or high Early voltage V_A

Transit Frequency f_T

Defined as the frequency at which the small-signal current gain of a device is unity

MOSFET ZTC Condition Analysis

zero temperature coefficient (ZTC)

MOM cap of wo_mx

Monte Carlo model:

• C_pa = C_pa1, C_pb = C_pb1 for each iteration during Process Variation
• different variation is applied to C_ab and C_a1b1 each iteration during Mismatch Variation, though C_pa, C_pb, C_pa1 and C_pb1 remain constant

Active Inductor

$$\begin{align} A &= \frac{g_mR_L}{1+(g_\text{m\_dio}+ g_\text{ds\_tot})R_L}\cdot \frac{1+R_pC_Ps}{1+\frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}s + \frac{R_LC_LR_PC_P}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}s^2} \\ &= \frac{g_mR_L}{1+(g_\text{m\_dio}+ g_\text{ds\_tot})R_L}\cdot \frac{R_PC_P}{ \frac{R_LC_LR_PC_P}{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}}\cdot \frac{1/(R_PC_P)+s}{s^2 + \frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{R_PC_P}s + \frac{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}{R_LC_LR_PC_P}} \\ &= A_0 \cdot A(s) \end{align}$$

That is

$$\begin{align} \omega_z &= \frac{1}{R_PC_P} \tag{1} \\ \omega_n &= \sqrt{\frac{1+(g_\text{m\_dio}+g_\text{ds\_tot})R_L}{R_LC_LR_PC_P}} = \sqrt{\omega_{p0}\omega_z} \\ \zeta & = \frac{(1+g_\text{ds\_tot}R_L)R_PC_P+C_PR_L+R_LC_L}{R_PC_P} \frac{1}{2 \omega_n} \end{align}$$

Where $$\begin{align} \omega_{p0} &= \frac{1}{(R_L||\frac{1}{g_\text{m\_dio}}||\frac{1}{g_\text{ds\_tot}})C_L} \tag{2} \end{align}$$

Here, relate ω_p0 and ω_z by coefficient α ω_p0 = α ⋅ ω_z This way $$ \omega_n= \sqrt{\alpha}\cdot \omega_z $$

$$ \zeta = \frac{1}{2}(K\sqrt{\alpha}+\frac{1+C_P/C_L}{\sqrt{\alpha}}) \tag{4} $$ where $$ K = \frac{R_L||\frac{1}{g_\text{m\_dio}}||\frac{1}{g_\text{ds\_tot}}}{R_L||g_\text{ds\_tot}} $$

And A(s) can be expressed as $$ A(s) = \frac{\frac{s}{\omega_z}+1}{\frac{s^2}{\omega_n^2}+2\frac{\zeta}{\omega_n}s+1} $$ It magnitude in dB $$ A_\text{dB} = 10\log\frac{1+(\omega/\omega_z)^2}{1+(\omega/\omega_n)^4+2\omega^2(2\zeta^2-1)/\omega_n^2} $$ Substitute ω_n with Eq (2), followed is obtained $$ A_\text{dB} = 10\log{\frac{\alpha^2(\omega_z^4 + \omega_z^2\omega^2)}{\alpha^2\omega_z^4+\omega^4+2\alpha\omega_z^2(2\zeta^2-1)\omega^2}} $$ peaking frequency $$ \omega_\text{peak} = \omega_z\cdot \sqrt{\sqrt{(\alpha+1)^2 - 4\alpha \zeta^2}-1} $$ If ζ = 1 $$\begin{align} \omega_{A_\text{dB = 0dB} }&= \sqrt{1-2/\alpha}\cdot \omega_{p0} \\ \omega_\text{peak} &= \omega_z\sqrt{\alpha-2} \\ A_\text{dB,peak} &= 10\log\frac{\alpha^2}{4(\alpha-1)} \end{align}$$

Miller multiplication of Capacitor

Positive Cap

Negative Cap

gain has limited bandwidth

V_o = V_i|A|e^jθ, and A_r = |A|cos θ, A_i = |A|sin θ

Then I_i = (V_i−V_o)sC_f = V_i(1−|A|e^jθ)sC_f, impedance is shown as below

$$\begin{align} Z &= \frac{V_i}{I_i} \\ &= \frac{1}{(1-|A|e^{j\theta})j\omega C_f} \\ &= -\frac{j}{\omega C_f\frac{1+|A|^2-2|A|\cos\theta}{1-|A|\cos\theta}} + \frac{|A|\sin\theta}{\omega C_f (1+|A|^2-2|A|\cos\theta)} \\ \end{align}$$

C_eq and R_eq are obtained $$\begin{align} C_\text{eq} &= \frac{1+|A|^2-2A_r}{1-A_r}\cdot C_f \\ R_\text{eq} &= \frac{A_i}{1+|A|^2-2A_r}\cdot \frac{1}{\omega C_f} \end{align}$$

D/S small signal model

The Drain and Source of MOS are determined in DC operating point, i.e. large signal.

That is, top of M₂ is drain and bottom is source, $$\begin{align} R_\text{eq2} &= \frac{r_\text{o2}+R_L}{1+g_\text{m2}r_\text{o2}} \\ & \simeq \frac{1}{g_\text{m2}} \end{align}$$

PMOS small signal model polarity

The small-signal models of NMOS and PMOS transistors are identical

A negative ΔV_GS leads to a negative ΔI_D.

Recall that I_D, in the direction shown here, is negative because the actual current of holes flows from the source to the drain.

Conversely, a positive ΔV_GS produces a positive ΔI_D, as is the case for an NMOS device.

Leakage in MOS

• Subthreshold leakage
  • Drain-Induced Barrier Lowering (DIBL)
• Reverse-bias Source/Drain junction leakages
• Gate leakage
• two other leakage mechanisms
  • Gate Induced Drain Leakage (GIDL)
  • Punchthrough

W. M. Elgharbawy and M. A. Bayoumi, “Leakage sources and possible solutions in nanometer CMOS technologies,” in IEEE Circuits and Systems Magazine, vol. 5, no. 4, pp. 6-17, Fourth Quarter 2005, doi: 10.1109/MCAS.2005.1550165.

X. Qi et al., “Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries,” in IEEE Circuits and Devices Magazine, vol. 22, no. 5, pp. 39-47, Sept.-Oct. 2006, doi: 10.1109/MCD.2006.272999.

P. Monsurró, S. Pennisi, G. Scotti and A. Trifiletti, “Exploiting the Body of MOS Devices for High Performance Analog Design,” in IEEE Circuits and Systems Magazine, vol. 11, no. 4, pp. 8-23, Fourthquarter 2011, doi: 10.1109/MCAS.2011.942751.

Andrea Baschirotto, ISSCC2015 “ADC Design in Scaled Technologies”

Joachim Assenmacher Infineon Technologies, “BSIM4 Modeling and Parameter Extraction” [https://ewh.ieee.org/r5/denver/sscs/References/2003_03_Assenmacher.pdf]

Stefan Rusu, Intel ISSCC 2008 Tutorial: “Leakage Reduction Techniques” [https://www.nishanchettri.com/isscc-slides/2008%20ISSCC/Tutorials/T06_Pres.pdf]

Drain-Induced Barrier Lowering (DIBL)

As a result of DIBL, threshold voltage is reduced with shorter channel lengths and, consequently, the subthreshold leakage current is increased

impact on output impedance

The principal impact of DIBL on circuit design is the degraded output impedance.

In short-channel devices, as V_DS increases further, drain-induced barrier lowering becomes significant, reducing the threshold voltage and increasing the drain current

Impact Ionization and GIDL are different, however both increase drain current, which flowing from the drain into the substrate

Gate induced drain leakage (GIDL)

The large current flows from the drain to bulk and this drain leakage current is named gate-induced drain leakage (GIDL) since it is due to a gate-induced high electric field present in the gate-to-drain overlap region

gate-induced drain leakage (GIDL) increases exponentially due to the reduced gate oxide thickness

Chauhan, Yogesh Singh, et al. FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press, 2015.

$$ \frac{g_m}{I_D} = \frac{2}{V_{GS}-V_{TH}} $$ Decrease of gm/Id results from decrease in VT.

GIDL (Gate induced drain leakage) as at weak inversion may results in a weak lateral electric field causing leakage current between drain and bulk, which degrade the efficiency of the transistor (gm/ID).

[https://www.linkedin.com/posts/master-micro_mastermicro-mastermicro-adt-activity-7214549962833989632-ZoV_?utm_source=share&utm_medium=member_desktop]

Voltage Dependence

Temperature Dependence

In advanced node, gate leakage is also a strong function of temperature

signal detection circuit

phase I

$$\begin{align} Q_a &= (V_{a0} - 0.5*(V_{ip} + V_{im}))*C + (V_{a0} - V_{th})*C \\ Q_b &= (V_{b0} - 0.5*(V_{ip} + V_{im}))*C + V_{b0}*C \end{align}$$

Phase II

$$\begin{align} Q_a &= (V_{a} - V_{ip})*C + (V_{a} - V_{b})*0.5C \\ Q_b &= (V_{b} - V_{im})*C + (V_{b} - V_{a})*0.5C \end{align}$$

With the law of charge conservation, we get

V_a − V_b = (V_a0−V_b0) + 0.5 * (V_ip−V_im−V_th)

REF: D. A. Yokoyama-Martin et al., “A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS,” IEEE Custom Integrated Circuits Conference 2006, 2006, pp. 401-404, doi: 10.1109/CICC.2006.320970.

Power/Ground and I/O Pins

Power / Ground Pin Information

In both digital and analog I/O, power and ground pins appear at the sub-circuit definiton, allowing user to use the I/O in voltage islands. They follow certain naming conventions.

1. digital I/O sub-circuit

• VDD: pre-driver core voltage (supplied by PVDD1CDGM)
• VSS: pre-driver ground and also global ground (supplied by PVDD1CDGM)
• VDDPST: I/O post-driver voltage, i.e. 1.8V (supplied by PVDD2CDGM or PVDD2POCM)
• VSSPOST: I/O post-driver ground (supplied by PVDD2CDGM or PVDD2POCM)
• POCCTRL: POCCTRL signal (supplied by PVDD2POCM)

2. analog I/O placed in a core voltage domain, the convention is

• TACVDD: analog core voltage (supplied by PVDD3ACM)
• TACVSS: analog core ground (supplied by PVDD3ACM)
• VSS: global core ground

3. analog I/O placed in an I/O voltage domain, the convention is:

• TAVDD: analog I/O voltage, i.e. 1.8V (supplied by PVDD3AM)
• TAVSS: analog I/O ground (supplied by PVDD3AM)
• VSS: global core ground

Power/Ground Combo Cells

Note for the retention mode

1. At initial state, IRTE must be 0 when VDD is off.
2. IRTE must be kept >= 10us after VDD turns on again (from the retention mode to the normal operation mode).
3. IRTE can be switched only when both VDD and VDDPST are on.

When the rention function is needed, IRTE signal must come from an “always-on” core power domain. If you don’t need the rention function, it is required to tie IRTE to ground. In other words, no matter the rention feature is needed or not, it is required to have PCBRTE in each domain.

Note: PCBRTE does not need PAD connection.

Internal Pins

There are 3 internal global pins, i.e. ESD, POCCTRL, RTE, in all digital domain cells.

In real application,

• ESD pin is an internal signal and active in ESD event happening
• POCCTRL is an internal signal and active in Power-on-control event.

However, these special events (i.e. ESD event and Power-on-control event) are not modeled in NLDM kit (.lib), only normal function is covered, so ESD and POCCTRL pins are simply defined as ground in NLDM kit (.lib).

These 3 global pins will be connected automatically after cell-to-cell abutting in physical layout.

Power-Up sequence in Digital Domain

Power up the I/O power (VDDPST) first, then the core power (VDD)

1. PVDDD2POCM cell would generate Power-On-Control signal (POCCTRL) to have the post-driver NMOS and PMOS off, so that the crowbar current would not occur in the post-driver fingers when the I/O voltage is on while the core voltage remains off. As such, I/O cell would be in the Hi-Z state. when POCCTRL is on, the pll-up/down resistor is disabled and C is 0.
2. The POCCTRL signal is transmitted to I/O cells through cell abutment. There is no need to have routing for POCCTTRL nor give a control signal to the POCCTRL pin any of I/O cells. Note that the POCCTRL signal would be cut if inserting a power-cut (PRCUT) cell.

Power-Down sequence in Digital Domain

It’s the reverse of power-up sequence.

Use model in Innovus

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set init_gnd_net "vss_core vss DUMMY_ESD DUMMY_POCCTRL"

addInst -moduleBased u_io -ori R270 -physical -status fixed -loc 135 994 -inst u_io/VDDIO_1 -cell PVDD2CDGM_H

addNet u_io_RTE
attachTerm FILLER_6 RTE u_io_RTE
attachTerm VDDIO_1 RTE u_right_RTE
setAttribute -skip_routing true -net u_io_RTE

clearGlobalNets
globalNetConnect DUMMY_POCCTRL -type pgpin -pin POCCTRL -singleInstance u_io/VDDDIO_1 -override
globalNetConnect DUMMY_ESD -type pgpin -pin ESD -singleInstance u_io/VDDDIO_1 -override

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set pins [get_object_name [get_ports *]]
foreach pin $pins {
	set netPtr [dbGetNetByName $pin]
	if { $netPtr == "0x0" } {
		puts "INFO: can't find the port: $pin"
	} else {
		setAttribute -net $pin -skip_routing true
	}
}

foreach net [get_object_name [get_nets -of_objects [get_pins */RTE -hierarchical]]] {
	setAttribute -net $net -skip_routing true
	dbSet [dbGetNetByName $net].dontTouch true
}

Metastability & Synchronizer

Clock Domain Crossing (CDC)

When a flip-flop samples an input that is changing during its aperture, the output Q may momentarily take on a voltage between 0 and VDD that is in the forbidden zone. This is called a metastable state. Eventually, the flip-flop will resolve the output to a stable state of either 0 or 1. However, the resolution time required to reach the stable state is unbounded

Mean Time Between Failure (MTBF)

TODO 📅

Steve Golson. Synchronization and Metastability [https://trilobyte.com/pdf/golson_snug14.pdf]

R. Ginosar, “Metastability and Synchronizers: A Tutorial,” in IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23-35, Sept.-Oct. 2011, doi: 10.1109/MDT.2011.113. [https://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf]

Kinniment, D. J. Synchronization and arbitration in digital systems. John Wiley & Sons Ltd (2007).

Amr Adel Mohammady, Clock Domain Crossing. [https://media.licdn.com/dms/document/media/D4E1FAQFGmDwVxj-A3Q/feedshare-document-pdf-analyzed/0/1727431256521?e=1728518400&v=beta&t=aY8BaqSPrHuQCesh_1hEPs-wYHQAF9XMI4eRfMij7zI]

Slewing of Folded-Cascode Op Amps

In practice, we choose I_P ≃ I_SS

Avoid zero current in cascodes

• left circuit

  I_b > I_a

• right circuit

  I_b > 2I_a

reference

M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, “Striving for small-signal stability,” in IEEE Circuits and Devices Magazine, vol. 17, no. 1, pp. 31-41, Jan. 2001, doi: 10.1109/101.900125.

Open loop gain analysis and “STB” method [https://www.linkedin.com/pulse/open-loop-gain-analysis-stb-method-jean-francois-debroux]

The Analog Designer’s Toolbox (ADT) | Invited Talk by IEEE Santa Clara Valley Section CAS Society, https://youtu.be/FT6kKC5OdE0

ESSCIRC2023 Circuit Insights Ali Sheikholeslami [https://youtu.be/2xFIZM5_FPw?si=XWwSzDgKWZGB0rX1]

Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 3 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 4, pp. 7-8, Fall 2018.

—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 2 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 3, pp. 7-8, Summer 2018.

—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part 1 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 2, pp. 7-8, Spring 2018.

—, Circuit Intuitions: Miller’s Approximation IEEE Solid-State Circuits Magazine, Vol. 7, Issue 4, pp. 7-8, Fall 2015.

—, Circuit Intuitions: Miller’s Theorem IEEE Solid-State Circuits Magazine, Vol. 7, Issue 3, pp. 8-10, Summer 2015.

Shanthi Pavan, “Demystifying Linear Time Varying Circuits”

ecircuitcenter. Switched-Capacitor Resistor [http://www.ecircuitcenter.com/Circuits/SWCap/SWCap.htm]

Jørgen Andreas Michaelsen. INF4420 Switched-Capacitor Circuits. [https://www.uio.no/studier/emner/matnat/ifi/INF4420/v13/undervisningsmateriale/inf4420_v13_07_switchedcapacitor_print.pdf]

chembiyan T. OC Lecture 10: A very basic introduction to switched capacitor circuits [https://youtu.be/SaYtemYp4rQ?si=q2qovTKJrLy65pnu

Robert Bogdan Staszewski, Poras T. Balsara. “All‐Digital Frequency Synthesizer in Deep‐Submicron CMOS”

Mayank Parasrampuria, Sandeep Jain, Burn-in 101 [link]

In Guest OS and run

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sudo vmware-toolbox-cmd disk shrink /

https://superuser.com/q/211798

Mismatch between the pole and zero frequencies leads to the “doublet problem”. If the pole and the zero do not exactly coincide, we say that they constitute a doublet

Problem 10.19 in Razavi 2nd book

Suppose the open-loop transfer function of a two-stage op amp is expressed as $$ H_{open}(s)=\frac{A_0(1+\frac{s}{\omega_z})}{\left( 1+ \frac{s}{\omega_{p1}}\right)\left( 1+ \frac{s}{\omega_{p2}}\right)} $$ Ideally, ω_z = ω₂ and the feedback circuit exhibits a first-order behavior, i.e., its step response contains a single time constant and no overshoot.

Then the transfer function of the amplifier in a unity-gain feedback loop is given by $$\begin{align} H_{closed}(s) &=\frac{A_0\left(1+\frac{s}{\omega_z}\right)}{\frac{s^2}{\omega_{p1}\omega_{p2}}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)s+A_0+1} \\ &=\frac{\frac{A_0}{A_0+1}(1+\frac{s}{\omega_z})}{\frac{s^2}{\omega_{p1}\omega_{p2}(A_0+1)}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)\frac{s}{A_0+1}+1} \end{align}$$

The denominator part of H_closed(s) is $$ D(s) = \frac{s^2}{\omega_{p1}\omega_{p2}}+\left( \frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}\right)s+A_0+1 $$

Assuming two poles (ω_pA ≪ ω_pB) of H_closed(s) are widely spaced, $$\begin{align} D(s) &= \left( 1+ \frac{s}{\omega_{pA}}\right)\left( 1+ \frac{s}{\omega_{pB}}\right)\\ &\cong \frac{s^2}{\omega_{pA}\omega_{pB}}+\frac{s}{\omega_{pA}} + 1 \end{align}$$

Thus, the two poles of the closed-loop transfer function of system are $$\begin{align} \omega_{pA} &= \frac{A_0+1}{\frac{1}{\omega_{p1}} + \frac{1}{\omega_{p2}}+\frac{A_0}{\omega_{z}}} \\ &= \frac{(A_0+1)\omega_{p1} \omega_{p2}}{\omega_{p1} + \omega_{p2} + \frac{A_0}{\omega_z}\omega_{p1} \omega_{p2}} \\ \omega_{pB} &= \omega_{p1} + \omega_{p2} + \frac{A_0}{\omega_z}\omega_{p1} \omega_{p2} \end{align}$$

Assuming ω_z ≃ ω_p2 and ω_p2 ≪ (1+A₀)ω_p1 ω_pA = ω_p2 and ω_pB = (1+A₀)ω_p1 The closed-loop transfer function is $$ H_{closed}(s) = \frac{\frac{A_0}{A_0+1}\left(1+\frac{s}{\omega_z}\right)}{\left(1+\frac{s}{(1+A_0)\omega_{p1}}\right)\left( 1+\frac{s}{\omega_{p2}} \right)} $$

The step response of the closed-loop amplifier

Consider the Laplace transform function of step response, $X(s)=\frac{1}{s}$ $$ Y(s)=\frac{1}{s}\times H_{closed}(s) $$ Thus, the small-signal step response of the closed-loop amplifier is $$ y(t)=\frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) $$ Since, ω_p2 ≪ (1+A₀)ω_p1. Therefore, rewrite the y(t) $$ y(t)\cong \frac{A_0}{A_0+1}\left[1-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) $$ The step response contains an exponential term of the form $\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t}$. This is an important result, indicating that if the zero does not exactly cancel the pole, the step response exhibits an exponential with an amplitude proportional to $\left(1-\frac{\omega_{p2}}{\omega_z}\right)$, which depends on the mismatch between ω_z and ω_p2 and a time constant τ of $\frac{1}{\omega_{p2}}$ or $\frac{1}{\omega_{z}}$

perfect pole-zero cancellation

$$\begin{align} y(t) &=\frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}-\left(1-\frac{\omega_{p2}}{\omega_z}\right)e^{-\omega_{p2}t} \right]u(t) \\ &= \frac{A_0}{A_0+1}\left[1-e^{-(A_0+1)\omega_{p1}t}\right]u(t) \end{align}$$

The zero comes from the mirror node

Thanks to unity gain buffer, zero is alleviated for C_c

reference

Elad Alon, Lecture 10: Settling-Limited Amplifier Design Methodology, EE 240B – Spring 2018, Advanced Analog Integrated Circuits https://inst.eecs.berkeley.edu/~ee240b/sp18/lectures/Lecture10_Settling_Design_2up.pdf

Eric Chang, Prof. Elad Alon EE240B HW3 https://inst.eecs.berkeley.edu/~ee240b/sp18/homeworks/hw3.pdf and https://inst.eecs.berkeley.edu/~ee240b/sp18/homeworks/hw3_soln.pdf

Prof. Tai-Haur Kuo, Analog IC Design ( 類比積體電路設計 ), Operational Amplifiers http://msic.ee.ncku.edu.tw/course/aic/201809/chapter5.pdf

SERGIO FRANCO, Demystifying pole-zero doublets URL:https://www.edn.com/demystifying-pole-zero-doublets/

B. Y. T. Kamath, R. G. Meyer and P. R. Gray, “Relationship between frequency response and settling time of operational amplifiers,” in IEEE Journal of Solid-State Circuits, vol. 9, no. 6, pp. 347-352, Dec. 1974, [https://sci-hub.se/10.1109/JSSC.1974.1050527]

P. R. Gray and R. G. Meyer, “MOS operational amplifier design-a tutorial overview,” in IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 969-982, Dec. 1982, [https://sci-hub.se/10.1109/JSSC.1982.1051851]

—. 2024. Analysis and Design of Analog Integrated Circuits, 6th Edition. Wiley Publishing

Terminology

The most accurate method to calculate the degradation of transistors is the SPICE-level simulation of the whole netlist with application programming interface (API) and industry-standard stress process models

​ MOSRA: MOSFET reliability analysis Synopsys

​ RelXpert: Cadence

​ TMI: TSMC Model Interface, TSMC

​ OMI: Open Model Interface, Si2 standard,

The Silicon Integration Initiative (Si2) Compact Model Coalition has released the Open Model Interface, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions.OMI allows circuit designers to simulate and analyze such important physical effects as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014.

• TDDB: Time-Dependent Dielectric Breakdown
• HCI: Hot Carrier injection
• BTI: Bias Temperature Instability
  • NBTI: Negative Bias Temperature Instability
  • PBTI: Positive Bias Temperature Instability
• SHE: Self-Heating Effect

Aging & SHE in FinFET

SHE

Self-Heating & EM

Heat Sink (HS)

1. guard ring

   closer OD help reduce dT

2. extended gate

3. source/drain metal stack

Bias Temperature Instability (BTI)

BTI occurs predominantly in PMOS (or p-type or p channel) transistors and causes an increase in the transistor’s absolute threshold voltage.

Stress in the case of NBTI means that the PMOS transistor is in inversion; that means that its gate to body potential is substantially below 0 V for analogue circuits or at VGB = −VDD for digital circuits

Higher voltages and higher temperatures both have an exponential impact onto the degradation, induced by NBTI.

NBTI will be accelaerated with thinner gate oxide, at a high temperature and at a high electric field across the oxide region.

During recovery phase where the gate voltage of pMOS is high and stress is removed, the H atoms in the gate oxiede diffuse back to Si-SiO2 interface and the recombination of Si-H bonds reduces the threshold voltage of pMOS.

The net result is an increase in the magnitude of the device threshold voltage |Vt|, and a degradation of the channel carrier mobility.

Caution: The aging model provided by fab may NOT contain recovry effect

HCI

Short-channel MOSFETs may exprience high lateral electric fields if the drain-source voltage is large. while the average velocity of carriers saturate at high fields, the instantaneous velocity and hence the kinetic energy of the carriers continue to increase, especially as they accelerate toward the drain. These are called hot carriers.

In nanometer technologies, hot carrier effects have subsided. This is because the energy required to create an electron-hole pair, E_g ≃ 1.12eV, is simply not available if the supply voltage is around 1V.

F_E = E ⋅ q

$$\begin{align} E_k &= F_E \cdot s \\ &= E \cdot q \cdot s \end{align}$$

Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, degrading the current-voltage characteristics of the MOSFET.

The channel hot-electron (CHE) effect is caused by electons flowing in the channel region, from the source to the drain. This effect is more pronounced at large drain-to-source voltage, at which the lateral electric field in the drain end of the channel accelerates the electrons.

Four different hot carrier injectoin mechanisms can be distinguished: - channel hot electron (CHE) injection - drain avalanche hot carrier (DAHC) injection - secondary generated hot electron (SGHE) injection - substrate hot electron (SHE) injection

HCI is more of a drain-localized mechanism, and is primarily a carrier mobility degradation (and a Vt degradation if the device is operated bi-directionally).

For smaller transistor dimensions, CHE dominates the hot carrier degradation effect

The hot-carrier induced damage in nMOS transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both.

The damage caused by hot-carrier injection affects the transistor characteristics by causing a degradation in transconductance, a shift in the threshold voltage, and a general decrease in the drain current capability.

HCI seems to have just a weak temperature dependency. Unlike BTI, it seems to be no or just little recovery. As holes are much “cooler” (i.e. heavier) than electrons, the channel hot carrier effect in nMOS devices is shown to be more significant than in pMOS devices.

Degradation saturation effect

HCI model can reproduce the saturation effect if stress time is long enough

TDDB

TDDB effect is also related to oxide traps. In general, TDDB refers to the loss of isolating properties of a dielectric layer. If this dielectric layer is the gate oxide, TDDB will initially lead to an increase in the gate tunnelling current.

This soft breakdown can already lead to a parametric degradation. After a long accumulation period, TDDB leads to a catastrophic reduction of the channel to gate insulation and thus a functional failure of the transistor.

Scaling drive more concerns in TDDB

waveform-dependent nature

The figure below illustrates the waveform-dependent nature of these mechanisms – as described earlier, BTI and HCI depend upon the region of active device operation. The slew rate of the circuit inputs and output will have a significant impact upon these mechanisms, especially HCI.

• Negative bias temperature instability (NBTI). This is caused by constant electric fields degrading the dielectric, which in turn causes the threshold voltage of the transistor to degrade. That leads to lower switching speeds. This effect depends on the activity level of the circuits, with heavier impact on parts of the design that don’t switch as often, such as gated clocks, control logic, and reset, programming and test circuitry.
• Hot carrier injection (HCI). This is caused by fast-moving electrons inserting themselves into the gate and degrading performance. It primarily occurs on higher-voltage modes and fast switching signals.

• longer channel length help both BTI and HCI
• larger V_ds help BTI, but hurt HCI
• lower temperature help BTI of core device, but hurt that of IO device for 7nm FinFET

MOSRA

MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age analysis

TMI

BTI recovery effect NOT included for N7

Stochastic Nature of Reliability Mechanisms

A fraction of devices will fail

Circuit Simulations

Heat transfer, thermal resistance

reference

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out - Analog/Custom Design (Analog/Custom design) - Cadence Blogs - Cadence Community https://shar.es/afd31p

S. Liao, C. Huang, and A. C. J. X. T. Guo, “New Generation Reliability Model,” Dec 2016. [Online]. Available: http://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf. [Accessed Aug 2018]

Tianlei Guo, Jushan Xie, “A Complete Reliability Solution: Reliability Modeling, Applications, and Integration in Analog Design Environment” [https://mos-ak.org/beijing_2018/presentations/Tianlei_Guo_MOS-AK_Beijing_2018.pdf]

FinFET Reliability Analysis with Device Self-Heating via @DanielNenni https://semiwiki.com/eda/synopsys/5085-finfet-reliability-analysis-with-device-self-heating/

Chris Changze Liu 刘长泽,Hisilicon, Huawei, “Reliability Challenges in Advanced Technology Node” https://www.tek.com.cn/sites/default/files/2018-09/reliability-challenges-in-advanced-technology-node.pdf

Ben Kaczer, imec. FEOL reliability: from essentials to advanced and emerging devices and circuits. 2016 IRPS Tutorial

Ben Kaczer, imec. Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation. 2016 IEDM 2016 [link]

Kang, Sung-Mo Steve, Yusuf Leblebici and Chulwoo Kim. “CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition.” (2014).

Behzad Razavi. “Design of Analog CMOS Integrated Circuits” (2016)

Basel Halak. Ageing of Integrated Circuits : Causes, Effects and Mitigation Techniques. Cham, Switzerland: Springer, 2020. ‌

Elie Maricau, and Georges Gielen. Analog IC Reliability in Nanometer CMOS. Springer Science & Business Media, 2013. ‌

Transistor Aging Intensifies At 10/7nm And Below https://semiengineering.com/transistor-aging-intensifies-10nm/

Modeling Effects of Dynamic BTI Degradation on Analog and Mixed-Signal CMOS Circuits. MOS-AK/GSA Workshop, April 11-12, 2013, Munich https://www.mos-ak.org/munich_2013/presentations/05_Leonhard_Heiss_MOS-AK_Munich_2013.pdf

Challenges and Solutions in Modeling and Simulation of Device Self-heating, Reliability Aging and Statistical Variability Effects https://www.mos-ak.org/beijing_2018/presentations/Dehuang_Wu_MOS-AK_Beijing_2018.pdf

New Generation Reliability Model https://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf

FinFET SPICE Modeling: Synopsys Solutions to Simulation Challenges of Advanced Technology Nodes https://www.mos-ak.org/washington_dc_2015/presentations/T03_Joddy_Wang_MOS-AK_Washington_DC_2015.pdf

A. Zhang et al., “Reliability variability simulation methodology for IC design: An EDA perspective,” 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2015, pp. 11.5.1-11.5.4, doi: 10.1109/IEDM.2015.7409677.

W. -K. Lee et al., “Unifying self-heating and aging simulations with TMI2,” 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan, 2014, pp. 333-336, doi: 10.1109/SISPAD.2014.6931631.

Aging and Self-Heating in FinFETs - Breakfast Bytes - Cadence Blogs - Cadence Community https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/aging-and-self-heating

Article (20482350) Title: Measure the Impact of Aging in Spectre Technology URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESBFUA4

Karimi, Naghmeh, Thorben Moos and Amir Moradi. “Exploring the Effect of Device Aging on Static Power Analysis Attacks.” IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (2019): 233-256.[link]

Self-Heating Issues Spread https://semiengineering.com/self-heating-issues-spread/

Y. Zhao and Y. Qu, “Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes,” in IEEE Journal of the Electron Devices Society, vol. 7, pp. 829-836, 2019, doi: 10.1109/JEDS.2019.2911085.

timing_aocv_derate_mode

1

timing_aocv_derate_mode{aocv_multiplicative | aocv_additive}

Default: aocv_multiplicative

Controls the AOCV derating mode.

When set to aocv_multiplicative, the derating factor will be calculated as AOCV derating * OCV derating, which is set using the set_timing_derate command.

When set to aocv_additive, the derating factor will be calculated as AOCV derating + OCV derating values.

When you use this global variable, the report_timing command shows the total_derate column in the timing report output, which allows you to view and cross-check the calculated total derate factor.

To set this global variable, use the set_global command.

reference

Genus Attribute Reference 22.1

Innovus Text Command Reference 22.10

Article (20416394) Title: Analysis with Advanced On-chip Variation (AOCV) derating in EDI system and ETS URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050NxEAI

Why Your Symmetric Layouts Are Showing Mismatches in SPICE Simulations

[https://www.ansys.com/blog/symmetric-layouts-showing-mismatches-spice-simulations]

The root cause of the delay mismatch is related to how parasitic extraction tools distribute coupling capacitances over the nodes of the resistive networks

The most likely reason for such asymmetry is the anisotropy of computational geometry algorithms used by extraction tools.

PERC

• CD: current density checks

• P2P: point to point resistance checks

• LDL: logic driven layout checks, latch up related

• TOPO: topology, circuit connection and device size checks

database

• CD, P2P, LDL : dfmdb

• TOPO: svdb

Frank Feng. New Approach For Full Chip Electrical Reliability Verification [pdf]

STRAP

A “strap” refers to a low-impedance connection

NWDMY = NWDMY1, NWDMY2

STRAP = NWSTRAP or PWSTRAP

NWSTRAP = {NP & OD} & {NW not {NW INTERACT NWDMY}}

PWSTRAP = {PP & OD} not NW

Calibre Rule::NOT

Calibre Rule::INTERACT

Antenna Effect

The antenna effect is a common name for the effects of charge accumulation in isolated nodes of an integrated circuit during its processing.

This effect is also sometimes called “Plasma Induced Damage”, “Process Induced Damage” (PID) or “charging effect”.

antenna ratio

The antenna rule specifies the maximum tolerance for the ratio of a metal line area to the area of connected gates.

metal jumping

Long metal can be taken to higher metal routing layer. This is known as metal jumping.

This metal jumping will break the long interconnect and hence the charge collected on the long interconnect will not discharge through gate oxide because the higher metal layer is not yet fabricated.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

Diode Insertion

Diode helps dissipate charges accumulated on metal. Diode should be placed as near as possible to the gate of device on low level of metal.

Diode should always be connected in reverse bias, with cathode connected to gate electrode and anode connected to ground potential.

During processing, even if the diodes are reversely biased, because of the elevated wafer temperature (200^oC plus) it will provide a much conductive path

In the reverse bias region, the reverse saturation current of Si and Ge diodes doubles for every 10^oC rise in temperature

Tuvia Liran, Antenna effect (PID): Do the design rules really protect us? [link]

Upma Pawan Kumar, Sunandan Chaubey, Antenna Effect in 16nm Technology Node [link]

pulsic.com, Analog layout – Stop the antenna effect from destroying your circuit [link]

BuBuChen, 積體電路的天線效應 (Antenna Effect in IC) [link]

EDN, Antenna violations resolved using new method [link]

edaboard.com, why jump up metal can solve the antenna effect? [link]

siliconvlsi.com, Antenna effect [link]

Prof. Adam Teman, Digital VLSI Design. Lecture-10-The-Manufacturing-Process [pdf]

Zongjian Chen, Processing and Reliability Issues That Impact Design Practice. [https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/lect_15_2up.pdf]

Shallow Trench Isolation (STI)

drain and source sharing

Planar process vs. FinFet process

Standard Cell Tapcell

Guard Ring in Custom block

Place well tie and substrate tie where they are needed. Redundant guard ring consume area and increase the routing of critical signal net.

Continuous OD

Performance & Matching

current mirror

split diffusion with dummy transistors

cascode structure

off transistor split diffusion

sharing source & drain

Stacked MOSFETs

Matching

1. Common Centroid

   The common centroid technique describes that if there are n blocks which are to be matched then the blocks are arranged symmetrically around the common centre at equal distances from the centre. This technique offers best matching for devices as it helps in avoiding cross-chip gradients

   

2. Inter-digitation

   Interdigitation reduces the device mismatch as it suffers equally from process variations in X dimension. This technique was used to layout current mirrors and resistors in PTAT and BGR circuits. In the Figure-15 below each brown stick represents a PFET of uniform length. This representation is termed as an inter-digitated layout.

   

Design with FinFETs

Modeling Consideration

$$\begin{align} R_{d1} &\propto \frac{1}{N_{fins}} \\ R_{s1} &\propto \frac{1}{N_{fins}} \\ R_{g1} &\propto N_{fins} \\ C_{gd} &\propto N_{fins} \cdot N_{fingers} \cdot N_{multipler} \\ C_{gs} &= Cgd \\ C_{g1d} &\propto N_{fins} \\ C_{g1s} &= C_{g1d} \\ C_{g1d1} &\propto N_{fins} \\ C_{g1s1} &= C_{g1d1} \\ C_{g1d1} &\simeq 2\times C_{g1d} \end{align}$$

Layout Consideration

PODE & CPODE

The PODE devices is extracted as parasitic devices in post-layout netlist

DDB is the PODE (Poly on OD/Diffusion Edge) in TSMC 16FFC process.

SDB is the CPODE (Connected PODE) in TSMC 16FFC process.

PO on OD edge (PODE) is a must and to define GATE that abuts OD vertical edge

CPODE is used to connect two PODE cells together. It will isolate OD to save 1 poly pitch, via STI; Additional mask (12N) is required for manufacture

SAC & SAGC

self-aligned diffusion contacts (SACs)

As shown in Fig. 35 in older planar technology nodes, gate pitch is so relaxed such that S/D contacts and gate contacts can easily be placed next to each other without causing any shorting risk (see Fig. 35(a)).

As the gate pitch scales, there’s no room to put gate contacts next to S/D contacts, and gatecontacts have been pushed away from the active region and are only placed on the STI region.

In addition, at tight gate pitch, even forming S/D contact without shorting to gate metal becomes very challenging.

The idea of self-aligned contacts (SAC) has been introduced to mitigate the issue of S/D contact to gate shorts.

As shown in Fig. 35(b), the gate metal is fully encapsulated by a dielectric spacer and gate cap, which protects the gate from shorting to the S/D contact.

A dielectric cap is added on top of the gate so that if the contact overlaps the gate, no short occurs.

MD layer represent SACs in PDK

self-aligned gate contacts (SAGCs)

Self-aligned gate contacts (SAGCs) have also been implemented and Denser standard cells can be achieved by eliminating the need to land contacts on the gate outside the active area.

SAGCs require the source/drain contacts to be capped with an insulator that is different from both contact and gate cap dielectrics to protect the source/drain contacts against a misaligned gate contact etch.

According to the DRC of T foundary, poly extension > 0 um and space between MP and OD > 0 um., which demonstrate self-aligned gate contact is not introduced.

Contacted-Poly-Pitch (CPP)

Wider Contacted-Poly-Pitch allows wider MD and VD size, which help reduce MEOL IRdrop

Naoto Horiguchi. Entering the Nanosheet Transistor Era [link]

Gate Resistance

Native NMOS Blocked Implant (NT_N)

Principles of VLSI Design CMOS Processing CMPE 413 [https://redirect.cs.umbc.edu/~cpatel2/links/315/lectures/chap3_lect09_processing2.pdf]

CMOS processing [http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf]

The Fabrication Process of CMOS Transistor [https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/#:~:text=latch%2Dup%20susceptibility.-,N%2D%20well%2F%20P%2D%20well%20Technology,well%20it%20is%20vice%2D%20verse.]

CMOS Processing Technology [link1, link2]

A native layer (NT_N) is usually added under inductors or transformers in the nanoscale CMOS to define the non-doped high-resistance region of substrate, which decreases eddy currents in the substrate thus maintaining high Q of the coils.

For T* PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy currents

OD inside NT_N only can be used for NT_N potential pickup purpose, such as the guarding-ring of MOM and inductor

Derived Geometries

NP: N+ Source/Drain Ion Implantation

PP: P+ Source/Drain Ion Implantation

OD: Gate Oxide and Diffustion

NW: N-WELL

PW: P-WELL

CMOS Processing Technology

Four main CMOS technologies:

• n-well process
• p-well process
• twin-tub process
• silicon on insulator

Triple well, Deep N-Well (optional):

• NWell: NMOS svt, lvt, ulvt …
• PWell: PMOS svt, lvt, ulvt …
• DNW: For isolating P-Well from the substrate

The NT_N drawn layer adds no process cost and no extra mask

The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.

The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.

Deep N-well

Chew, K.W., Zhang, J., Shao, K., Loh, W., & Chu, S.F. (2002). Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration. 32nd European Solid-State Device Research Conference, 251-254. URL:[slides, paper]

Mark Waller, Analog layout: Why wells, taps, and guard rings are crucial

KEITH SABINE Using Deep N Wells in Analog Design

Faricelli, J. (2010). Layout-dependent proximity effects in deep nanoscale CMOS. IEEE Custom Integrated Circuits Conference 2010, 1-8.

cmos_processing, URL:http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf

Kuo-Tsai LiPaul ChangAndy Chang, TSMC, US20120053923A1, “Methods of designing integrated circuits and systems thereof”

Substrate noise

A variety of techniques can be used to minimize this noise, for example by keeping analog devices surrounded by guard rings, or using a separate supply for the substrate/well taps.

However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

PMOS are less noisy than NMOS since PMOS has its nwell which isolates the substrate noise, but such is not valid for NMOS .

DNW

The N-channel devices built directly into the P-type substrate are not as effectively isolated as P-channel devices in their N-wells. This is because despite creating a P+ guard ring around the devices, there remains an electrical path below the guard ring for charge to flow.

To overcome this issue, a deep N-well can be used to more effectively isolate these N-channel devices.

pwdnw: PW/DNW diode

dnwpsub: DNW/PSUB diode

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

• the P-well is separated, allowing the voltage to be controlled
• because the circuit within the deep N-well is separated from the p-substrate in this structure, there is the benefit that this circuitry is less susceptible to noise that propagates through the p-substrate.

reference

Mikael Sahrling, Layout Techniques for Integrated Circuit Designers 1st Edition , Artech House 2022

LAYOUT, EE6350 VLSI Design Lab SMART TEMPERATURE SENSOR URL: https://www.ee.columbia.edu/~kinget/EE6350_S16/06_TEMPSENS_Sukanya_Vani/layout.html

Stacked MOSFETs in analog layout https://pulsic.com/stacked-mosfets-in-analog-layout/

JED Hurwitz, ISSCC2011 “T4: Layout: The other half of Nanometer CMOS Analog Design” [slides, transcript]

Tom Quan, TSMC, Bob Lefferts, Fred Sendig, Synopsys, Custom Design with FinFETs - Best practices designing mixed-signal IP

Jacob, Ajey & Xie, Ruilong & Sung, Min & Liebmann, Lars & Lee, Rinus & Taylor, Bill. (2017). Scaling Challenges for Advanced CMOS Devices. International Journal of High Speed Electronics and Systems. 26. 1740001. 10.1142/S0129156417400018.

Joddy Wang, Synopsys “FinFET SPICE Modeling” Modeling of Systems and Parameter Extraction Working Group 8th International MOS-AK Workshop (co-located with the IEDM Conference and CMC Meeting) Washington DC, December 9 2015

A. L. S. Loke et al., “Analog/mixed-signal design challenges in 7-nm CMOS and beyond,” 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-8, doi: 10.1109/CICC.2018.8357060.[slides]

Prof. Adam Teman, Advanced Process Technologies, [pdf]

Luke Collins. FinFET variability issues challenge advantages of new process [link]

Loke, Alvin. (2020). FinFET technology considerations for circuit design (invited short course). BCICTS 2020 Monterey, CA

Alvin Leng Sun Loke, TSMC. Device and Physical Design Considerations for Circuits in FinFET Technology”, ISSCC 2020

A. L. S. Loke, C. K. Lee and B. M. Leary, “Nanoscale CMOS Implications on Analog/Mixed-Signal Design,” 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi: 10.1109/CICC.2019.8780267.

A. L. S. Loke, Migrating Analog/Mixed-Signal Designs to FinFET Alvin Loke / Qualcomm. 2016 Symposia on VLSI Technology and Circuits

Lattice Semiconductor, 16FFC Process Technology Introduction December 9th, 2021[pdf]

temperature coefficient

The parameter that shows the dependence of the reference voltage on temperature variation is called the temperature coefficient and is defined as: $$ TC_F=\frac{1}{V_{\text{REF}}}\left[ \frac{V_{\text{max}}-V_{\text{min}}}{T_{\text{max}}-T_{\text{min}}} \right]\times10^6\;ppm/^oC $$

Choice of n

classic bandgap reference

$$ V_{bg} = \frac{\Delta V_{be}}{R_1} (R_1+R_2) + V_{be2} = \frac{\Delta V_{be}}{R_1} R_2 + V_{be1} $$

$$ V_{bg} = \left(\frac{\Delta V_{be}}{R_1} + \frac{V_{be1}}{R_2}\right)R_3 = \left(\frac{\Delta V_{be}}{R_1} R_2 + V_{be1}\right)\frac{R_3}{R_2} $$

OTA offset effect

$$\begin{align} V_{be1} &= \frac{kT}{q}\ln(\frac{I_{e1}}{I_{ss}}) \\ V_{be2} &= \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \end{align}$$

Here, we assume I_e = I_c

Hence,

$$\begin{align} \Delta V_{be} &= \frac{kT}{q}\ln(n\frac{I_{e1}}{I_{e2}}) \\ &= \frac{kT}{q}\ln(n) + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \\ &= \Delta V_{be,0} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) \end{align}$$

Therefore,

$$\begin{align} V_{bg} &= \frac{\Delta V_{be}+V_{os}}{R_2}(R_1+R_2) + V_{be2} \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}})+\frac{kT}{q}\ln(\frac{I_{e2}}{I_{e2,0}}) \end{align}$$

We omit the last part $$\begin{align} V_{bg} &\approx \alpha \Delta V_{be,0} + \alpha \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}}) + \alpha V_{os} + \frac{kT}{q}\ln(\frac{I_{e2,0}}{nI_{ss}}) \\ &= \alpha \Delta V_{be,0} + V_{be2,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \\ &= V_{bg,0} + \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) \end{align}$$

i.e. the bg variation due to OTA offset $$ \Delta V_{bg} \approx \alpha \left(V_{os} + \frac{kT}{q}\ln(\frac{I_{e1}}{I_{e2}})\right) $$

• V_os > 0

  ​ I_e1 > I_e2: ΔV_bg > αV_os

• V_os < 0

  ​ I_e1 < I_e2: ΔV_bg < αV_os

OTA with chopper

I_e1, I_e2

$$\begin{align} V_{ip} &= V_{im} + V_{os} \\ \frac{V_{bg}-V_{ip}}{R_2} &= I_{e2} \\ \frac{V_{bg}-V_{im}}{R_2} &= I_{e1} \\ V_{ip} &= I_{e2}R_1 + V_T\frac{I_{e2}}{nI_S} \\ V_{im} &= V_T\frac{I_{e1}}{I_S} \end{align}$$ where $V_T = \frac{kT}{q}$

we obtain $$ I_{e1} = \frac{V_T\ln n}{R_1} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) - \frac{1}{R_1}\cdot V_T\ln\left(1- \frac{V_{os}}{R_2I_{e1}} \right) $$

we omit the last part $$\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right) \\ I_{e2} &= I_{e1} - \frac{V_{os}}{R_2} = I_{e0} + \frac{V_{os}}{R_1} \end{align}$$ where $I_{e0} = \frac{\Delta V_{be}}{R_1}$, ΔV_be = V_Tln n

That is, both I_e1 and I_e2 are proportional to V_os

I_e1 and I_e2 can be expressed as $$\begin{align} I_{e1} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) + \frac{V_{os}}{2R_2} \\ I_{e2} &= I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right) - \frac{V_{os}}{2R_2} \end{align}$$ i.e., $\Delta I_{e,cm} = V_{os}\left(\frac{1}{R_1} + \frac{1}{2R_2} \right)$ and $\Delta I_{e,dif} =\frac{V_{os}}{2R_2}$

bandgap output voltage is

$$\begin{align} V_{bg} &= V_T \ln \frac{I_{e1}}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e1}R_2 \\ &= V_T \ln \frac{I_{e0} + V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_s} + I_{e0}R_2 + V_{os}\frac{R_1+R_2}{R_1} \\ &= I_{e0}R_2 + V_T \ln \frac{I_{e0}}{I_s} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \\ &= V_{bg0} + V_T\ln\left(1+\frac{V_{os}\left(\frac{1}{R_1} + \frac{1}{R_2} \right)}{I_{e0}} \right) + V_{os}\frac{R_1+R_2}{R_1} \end{align}$$

Therefore, the averaged output of bandgap

$$ V_{bg,avg} = V_{bg0} +\frac{1}{2}V_T\ln\left(1-\frac{V_{os}^2\left(\frac{1}{R_1} + \frac{1}{R_2} \right)^2}{I_{e0}^2} \right) \lt V_{bg0} $$

V_bg, avg < V_bg0 due to nonlinearity of BJT

ripple cancellation

phase 0:

$$\begin{align} V_{os}[n] &= V_{os}[n-1] - \frac{\Delta I_1}{g_m} \\ V_{os}[n] &= I_\Delta[n] R_E \\ \beta I_\Delta &= I_1[n] + I_2[n-1] \end{align}$$ where I_Δ is the variation of I_e1 + I_e2 due to V_os and $R_E = \frac{R_1R_2}{R_1+2R_2}$

obtain $$\begin{align} \Delta I_1 &= G\cdot V_{os}[n-1] - K\cdot I_1[n-1] - K\cdot I_2[n-1] \\ I_1[n] &= G\cdot V_{os}[n-1] + (1-K)\cdot I_1[n-1] - K\cdot I_2[n-1] \\ V_{os}[n] &= K\cdot V_{os}[n-1] + R\cdot I_1[n-1] + R\cdot I_2[n-1]\\ \end{align}$$

where $G=g_m\frac{\beta}{g_m R_E + \beta}$, $R=R_E\frac{1}{g_m R_E + \beta}$ and $K=\frac{g_mR_E}{g_m R_E + \beta}$

and $$ V_{os}[n] = (2K-1)\cdot V_{os}[n-1] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] $$

phase 1:

$$\begin{align} V_{os}[n] &= V_{os}[n-1] - \frac{-\Delta I_2}{g_m} \\ V_{os}[n] &= -I_\Delta[n] R_E \\ \beta I_\Delta &= I_1[n] + I_2[n-1] \end{align}$$

obtain $$\begin{align} \Delta I_2 &= -G\cdot V_{os}[n-1] - K\cdot I_1[n-1] - K\cdot I_2[n-1] \\ I_1[n] &= -G\cdot V_{os}[n-1] -K\cdot I_1[n-1] + (1-K)\cdot I_2[n-1] \\ V_{os}[n] &= K\cdot V_{os}[n-1] - R\cdot I_1[n-1] - R\cdot I_2[n-1]\\ \end{align}$$

similaly $$ V_{os}[n] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] $$

That is, for either phase $$ V_{os}[n] = (1-\frac{2\beta}{g_mR_E+\beta})\cdot V_{os}[n-1] $$

reference

ECEN 607 (ESS) Bandgap Reference: Basics URL:https://people.engr.tamu.edu/s-sanchez/607%20Lect%204%20Bandgap-2009.pdf

Using Red Hat Enterprise Linux 8, Rocky Linux 8 and the GNOME 3 window manager, the new Virtuoso Schematic/Layout/ADE windows and forms sometimes pop up under or below the Library Manager or on the desktop in the background instead of the foreground and cannot be seen. Sometimes, they are iconized; they do not come on the top in front, though it is the most recent window opened.

solution

Install Focus my window GNOME Shell extension

reference

Article (11612426) Title: New windows and forms appear behind the Library Manager in background or iconized instead of foreground on RHEL and SuSE Linux in GNOME, KDE Desktop, Metacity window manager URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nSXCEA2

MOS capacitances

• oxide capacitance (aka gate-channel capacitance) between the gate and the channel C₁ = WLC_ox
  • divided between C_GS and C_GD
• depletion capacitance between the channel and the substrate C₂
• overlap capacitance: direct overlap and fringing field
• junction capacitance between the source/drain areas and the substrate
  • The value of C_SB and C_DB is a function of the source and drain voltages with respect to the substrate

The gate-bulk capacitance is usually neglected in the triode and saturation regions because the inversion layer acts as a “shield” between the gate and the bulk.

classification with Intrinsic and Extrinsic MOS capacitor

[Circuit Insights - 11-CI: Fundamentals 4 Tsinghua Nan Sun]

FinFET Parasitic Fringing Capacitance

Temperature Dependence of Junction Diode CV

where TCJ and TCJSW are positive

https://cmosedu.com/cmos1/BSIM4_manual.pdf

D=S=B varactor

Inversion-mode (I-MOS)

Accumulation-mode (A-MOS)

NMOS in NWELL, aka NMOS in N-Well varactor

Notice: S/D and NWELL are connected togethor in layout

PDK varactor

nmoscap: NMOS in N-Well varactor

• Base Band MOSCAP model (nmoscap) is built without effective series resistance (ESR) and effective series inductance (ESL) calibrations, which is for capacitance simulation only
• LC-Tank MOSCAP model (moscap_rf) is for frequency-dependent Q factor and capacitance simulations

MOS Device as Capacitor

Voltage dependence

• capacitance of MOS gate varies nonmonotonically with V_GS

• “accumulation-mode” varactor varies monotonically with V_GS

Inverter capacitance

reference

R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003, doi: 10.1109/JSSC.2003.814416.

T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee and S. S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), 1998, pp. 32-33, doi: 10.1109/VLSIC.1998.687993. URL: http://www-smirc.stanford.edu/papers/VLSI98s-chet.pdf

R. Jacob Baker, 6.1 MOSFET Capacitance Overview/Review, CMOS Circuit Design, Layout, and Simulation, Fourth Edition

B. Razavi, Design of Analog CMOS Integrated Circuits 2nd

Bing Sheu, TSMC. “Circuit Design using FinFETs” [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T4.pdf]