A. Deutsch et al., "When are transmission-line effects
important for on-chip interconnections?," in IEEE Transactions on
Microwave Theory and Techniques, vol. 45, no. 10, pp. 1836-1846,
Oct. 1997
Pupalaikis, P. (2020). S-Parameters for Signal Integrity.
Cambridge: Cambridge University Press. doi:10.1017/9781108784863
Coelho, C. P., Phillips, J. R., & Silveira, L. M. (n.d.). Robust
rational function approximation algorithm for model generation.
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).
doi:10.1109/dac.1999.781313
Three fast time-domain system simulation techniques:
single-bit response method
double-edge response method
multiple-edge response method
Single-Bit Response (SBR)
Method
Overlapping portions of a pulse response from neighboring bits are
referred to as intersymbol interference (ISI). A received waveform is
formed by superimposing, in time, the pulse responses of each
bit in the sequence, as illustrated in Figure 9, assuming
symmetric positive and negative pulses are
transmitted for 1s and 0s
To avoid spurious glitches between consecutive ones, rising and
falling edge responses shall be symmetric. This is the
limitation of SBR method.
Let \(p(t)\) be the SBR of the
channel, \(t_s\) be the data sampling
phase, \(T\) be the bit time, \(N_c\) is the number of UI in stored pulse
response and \(b_m\) be the \(m\)th transmitted symbol. The voltage seen
by the receiver's data sampler at the \(m\)th data sample is determined by \[
y_m = \sum_{k=m-N_c+1}^{m}b_kp(t_s+(m-k)T)
\] where \(b_k \in [0, 1]\) and
\(p(t) \ge 0\)
We always prepend \(Nc-1\) 0s in
random bit stream for consistency.
For computation convenient, the pulse need to be positive. For
differential signal and amplitude \(V_{peak}\), the peak to peak is \(-V_{peak}\) to \(+V_{peak}\). After pulse added by \(V_{peak}\), peak to peak is \(0\) to \(+2V_{peak}\).
yy_sum = zeros(OSR*Ns, Ns); for idxBit = 1:Ns bs_split = zeros(1, Ns+Nc-1); bs_split(idxBit) = bs(idxBit); yy = zeros(OSR, Ns); for ii = Nc:Nc+Ns-1 bb = bs_split(ii:-1:ii-Nc+1); yy(:,ii-Nc+1) = sum(bb.*yrps, 2); end yy_cont2 = reshape(yy, [], 1); h = plot(yy_cont2); h.Annotation.LegendInformation.IconDisplayStyle = 'off'; yy_sum(:, idxBit) = yy_cont2; end yy_sum = sum(yy_sum, 2); % merge plot(yy_sum, 'k--'); plot(yy_cont, 'm-.'); grid on; legend('sum', 'syn'); title('merge all single bit'); ylabel('mag'); xlabel('Time (\times Ts)');
The pulse response contain rising and falling edge. The 1 bit
first rise from -1 to 1, then fall to -1; The 0
bit just do nothing for synthesized waveform with the help of
falling edge of 1 bit.
To handle the more general cases, with asymmetric rising and
falling edges, the system response can be constructed in terms
of edge transitions instead of bit responses.
The DER method decomposes the input data pattern, in terms of
rising and falling edge transitions. The system
response can be calculated by superimposing the shifted versions of
the rising and falling edge responses : \[
y_m = \sum_{k=m-N_c+1}^{m}(b_k-b_{k-1})s_k(t_s+(m-k)T) + y_{int}
\] where
\(r(t)\) and \(f(t)\) are the rising and falling edge
responses,respectively. \(V_{high}\)
and \(V_{low}\) are the steady state DC
levels, in response to a constant stream of ones and zeros,
respectively. \(y_{int}\) is the
initial DC state (either \(V_{high}\)
or \(V_{low}\) ).
We always prepend \(Nc\) 0s in
random bit stream for consistency.
figure(2) hold on; for idx = idxPreRspStart+1-Nc:idxCurData+32-Nc ys = yy(:, idx); tt = ((idx-1)*OSR+1:idx*OSR); h = plot(tt(:), ys(:), 'LineWidth',3); h.Annotation.LegendInformation.IconDisplayStyle = 'off'; end plot(yy_cont, 'm--', 'LineWidth',1); hold off; legend('syn') ylabel('mag'); xlabel('Time (\times Ts)'); title('synthesize with step response'); grid on;
Reference
T. C. Carusone, "Introduction to Digital I/O: Constraining I/O Power
Consumption in High-Performance Systems," in IEEE Solid-State
Circuits Magazine, vol. 7, no. 4, pp. 14-22, Fall 2015
Oh, Kyung Suk Dan, and Xing Chao Chuck Yuan. High-Speed Signaling:
Jitter Modeling, Analysis, and Budgeting. Prentice Hall, 2011.
Ren, Jihong and Kyung Suk Oh. “Multiple Edge Responses for Fast and
Accurate System Simulations.” IEEE Transactions on Advanced
Packaging 31 (2008): 741-748.
Shi, Rui. “Off-chip wire distribution and signal analysis.”
(2008).
X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate
Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 29, no. 7, pp. 1370-1378, July 2021, doi:
10.1109/TVLSI.2021.3082208.
L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S.
Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of
Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]
Even-odd Jitter (EOJ)
Jitter measurement
Description
F/2
F/2 is the peak-to-peak amplitude of the
periodic jitter occurring at 1/2 of the data rate.
Even-odd jitter, also known as F/2
jitter, arises from a clock signal's duty cycle not being
perfectly 50%
Even-odd jitter has been referred to as
duty cycle distortion by other Physical Layer
specifications for operation over electrical backplane or twinaxial
copper cable assemblies
There are two primary causes of DCD jitter which are usually
generated within a transmitter
If the data input to a transmitter is theoretically perfect, but if
the transmitter sampling threshold is offset
from its ideal level, then the output of transmitter will have duty
cycle distortion as a function of the slew rate of the data
signal
Another cause of duty cycle distortion can be a
mismatch/asymmetry in rising and falling edge
speeds
Unfortunately, other sources such as ISI almost always exist making
it sometimes difficult to isolate the DCD component. One technique to
test for DCD is to stimulate your system/components with a
repeating 1-0-1-0… data pattern. This
technique will eliminate inter-symbol interference (ISI) jitter and make
viewing the DCD within the spectrum display much easier
Why clock pattern? That's because all symbols experience
same inter-symbol interference, which are
canceled out
If the PDF of one jitter source changes when the PDF of another
source is changed, then those two sources are
dependent or
correlated
Inter-Symbol Interference
(ISI)
The primary cause of Data Dependent Jitter
Jitter measurements can be classified into three categories:
cycle-to-cycle jitter, period jitter, and
long-term jitter
Jitter is a key performance parameter. Need to know what matters in
each case:
PJ for digital timing
LTJ for data converters and serial data
Phase noise for communications (not all bandwidths
matter)
The above Cycle-Cycle Jitter equation is wrong,
\(\tau_1\) and \(\tau_2\) are not independent
Short Term Jitter
Period jitter, Jper is the short term
variation in clock period compared to the average (mean) clock
period.
Cycle-to-Cycle, Jcc is the time difference
of two adjacent clock periods
Long Term Jitter (LTJ)
measuring LTJ
Jitter Calculation Examples
Jcc vs Jper
Estimating the RMS cycle-to-cycle jitter if all you have available is
the RMS period jitter.
Cycle-to-cycle jitter - The short-term
variation in clock period between adjacent clock cycles. This
jitter measure, abbreviated here as \(J_{CC}\), may be specified as either an RMS
or peak-to-peak quantity.
Period jitter - The short-term variation
in clock period over all measured clock cycles, compared to the
average clock period. This jitter measure, abbreviated here as \(J_{PER}\), may be specified as either an
RMS or peak-to-peak quantity.
Let the variable below represent the variance of a single edge's
timing jitter, i.e. the difference in time of a jittery edge versus an
ideal edge, \(\sigma^2_j\)
If each edge's jitter is independent then the variance of
the period jitter can be written as \[\begin{align}
\sigma^2_\text{jper} &= (\sigma_\text{j(n+1)}-\sigma_\text{j(n)})^2
\\
&=
\sigma_\text{j(n+1)}^2-2\sigma_\text{j(n+1)}\sigma_\text{j(n)})+\sigma_\text{j(n)})^2\\
&= \sigma_\text{j(n+1)}^2+\sigma_\text{j(n)})^2 \\
&=2\sigma^2_j
\end{align}\]
In every cycle-to-cycle measurement we use one
"interior" clock edge twice and therefore we
must account for this
The ratio of the variances is therefore \[
\frac{\sigma^2_\text{jcc}}{\sigma^2_\text{jper}} =
\frac{6\sigma_\text{j}^2} {2\sigma_\text{j}^2}=3
\] Then \[
\sigma_\text{jcc} = \sqrt{3}\sigma_\text{per}
\]
N. Da Dalt, "Tutorial: Jitter: Basic and Advanced Concepts,
Statistics, and Applications," 2012 IEEE International Solid-State
Circuits Conference, San Francisco, CA, USA, 2012 [slides,
transcript
]
Current return paths are frequency dependent \(Z = R +j\omega L\)
Low frequency
\(R\) dominates - current use as
many returns as possible to have parallel resistances
High frequency
\(j\omega L\) dominates - current
use the closest possible return path to form the smallest
possible loop inductance
Very high frequency
The current would be confined to the nearest possible
return only at ultra-high frequencies (skin effect)
skin effect & Dielectric
loss
EMX simulation
setup:
frequency sweep:
Cadence October 2020, Analysis of a Figure-Eight Inductor with
EMX RAK
proximity effect & skin
effect
Skin effect concentrates current near the
surface of a single conductor, while
proximity effect concentrates current in specific
regions of multiple conductors due to their
interaction
Skin effect is caused by the conductor's
own magnetic field, while proximity effect is
caused by the magnetic field of a nearby
conductor
proximity effect is a redistribution of
electric current occurring in nearby parallel
electrical conductors carrying alternating current
(AC), caused by magnetic effects (eddy
currents)
skin effect is the tendency of
AC current flow near the surface (or "skin")
of a conductor, rather than throughout its cross-section, due to the
magnetic field generated by the current
itself
Cause of skin effect
A main current \(I\) flowing through
a conductor induces a magnetic field \(H\). If the current increases, as in this
figure, the resulting increase in \(H\)
induces separate, circulating eddy currents\(I_W\) which partially cancel the
current flow in the center and reinforce it near the skin
Eddy current
By Lenz's
law, an eddy current creates a magnetic field that
opposes the change in the magnetic field that
created it, and thus eddy currents react back
on the source of the magnetic field
Electromagnetic coupling
Electric field coupling (also called
capacitive coupling) occurs when energy is coupled from
one circuit to another through an electric field
Magnetic field coupling (also called
inductive coupling) occurs when energy is coupled from
one circuit to another through a magnetic field
For instance
magnetic coupling between multiple inductors
capacitive coupling between multiple transmission lines
ISSCC2002. Special Topic Evening Discussion Sessions SE1: Inductance:
Implications and Solutions for High-Speed Digital Circuits [vSE1_Blaauw],
[vSE1_Gauthier],
[vSE1_Morton,
[vSE1_Restle]]
Y. Massoud and Y. Ismail, "Gasping the impact of on-chip inductance,"
in IEEE Circuits and Devices Magazine, vol. 17, no. 4, pp. 14-21, July
2001 [https://sci-hub.se/10.1109/101.950046]
Raymond Y. Chen, Raymond Y. Chen. Fundamentals of S Fundamentals of
S-Parameter Parameter Modeling for Power Distribution Modeling for Power
Distribution System (PDS) and SSO Analysis System (PDS) and SSO Analysis
[https://ibis.org/summits/jun05/chen.pdf]
similarly finger 1 \[
\overline{i_{tot,1}^2} =
g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2}
\] Assuming uncorrelated \[
\overline{i_{tot}^2} = \sum_{N=0}^1\overline{i_{tot,N}^2}
=g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2\cdot 2} \cdot 2 =
g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{2^2}
\] Generally \[
\overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2}
\] where the gate is decomposed into \(N\) parallel fingers
two-side poly contact
We fracture Gate poly at the center point, then we obtain 2
segments, both have same \(\frac{g_m}{2}\) and \(R_G/2\).
The derivation procedure is same with folding structure, i.e. plug
\(N=2\) into \(\overline{i_{tot}^2} =
g_m^2\left(4kT\frac{R_G}{3}\right)\frac{1}{N^2}\)
That is \[
\overline{i_{tot}^2} = g_m^2\left(4kT\frac{R_G}{12}\right)
\] The input referred noise of gate resistance \[
\overline{V_{nRG}^2} = 4kT\frac{R_G}{12}
\]
Gate
resistance handling by parasitic extraction tools
They fracture the poly line at the intersection with the active
(diffusion) layer, breaking it into "gate poly"(poly over
active) and "field poly" (poly outside
active)
gploy, fpoly
Gate poly is also fractured at the center point. Gate instance pin of
the MOSFET (SPICE model) is connected to the center point of the gate
poly. Gate poly is described by two parasitic resistors,
connecting the fracture points.
MOSFET extrinsic parasitic capacitance between gate poly and source /
drain diffusion and contacts is calculated by parasitic extraction
tools, and assigned to the nodes of the resistive networks.
Different extraction tools do this differently - some tools connect
these parasitic capacitances to the center point of the gate poly, while
some other tools connect them to the end points of the gate poly
resistors.
\(\Delta\)
gate model
This distributed network has a different AC and transient response
than a simple lumped one-R and one-C circuit.
It was shown [B. Razavi] that such RC network behaves approximately
the same as a network with one R and one C element, where C is the
total capacitance, and R=1/3 * W/L rsh for single-side
connected poly, and R=1/12 W/L * rsh for double-sided connected
poly.
These coefficients - 1/3 and 1/12 - effectively enable an accurate
reduced order model for the gate, reducing a large number of R and C
elements to two (or three) resistors and one capacitor.
Gate Delta Model: where a gate is described by two
positive and one negative resistors
only applicable to contacts on gate overhangs
invalid for self-aligned gate contacts, where gate contact land
directly on top of gate, not gate overhang
Some SPICE simulators have problems handling negative
resistors, that's possibly why this model did not get a wide
adoption. Some foundries and PDKs support delta gate model, while some
others don't.
Vertical component of
gate resistance
In "old" technologies (pre-16nm), gate resistance was dominated by
lateral resistance. However, in advanced technologies, multiple
interfaces between gate material layers lead to a large vertical gate
resistance.
It's very easy to check this in DSPF file - if gate instance pin is
connected directly to the center of the gate poly - vertical resistance
is not accounted for. If it is connected by a positive resistor to the
center of the gate poly - that resistors represents the vertical gate
resistance.
decap
leakage current is determined by \(R_s +
R_p\), and \(R_p \gg R_s\)
low freq: \(Z=R_s + R_p\)
high freq: \(Z=R_s\)
An example: \(R_s=200\space
\Omega\), \(R_p = 8 \space
M\Omega\) and \(C_\text{gate}=10\space
fF\)
reference
⭐ B. Razavi, Y. Ran, and K. F. Lee, “Impact of Distributed Gate
Resistance on the Performance of MOS Devices,” IEEE Trans. Circuits and
Systems, Part I, pp. 750–754, Nov. 1994.
⭐ Maxim Ershov, Diakopto. "Gate Resistance in IC design flow", [link,
pdf]
Saha, Samar K.. “FinFET Devices for VLSI Circuits and Systems.”
(2020).
Harpe, Pieter J. A., Andrea Baschirotto and Kofi A. A. Makinwa.
“Hybrid ADCs, Smart sensors for the IoT, and Sub-1V and Advanced node
analog circuit design: Advances in Analog Circuit Design 2017.”
(2018).
Chauhan, Yogesh Singh. FinFET Modeling for IC Simulation and Design:
Using the BSIM-CMG Standard. London, UK: Academic Press, 2015.
A.J.Sholten et al., "FinFET compact modelling for analogue and RF
applications", IEDM'2010, p.190.
W. Wu and M. Chan, “Gate resistance modeling of multifin MOS
devices,” IEEE Electron Device Letters, vol. 27, no. 1, pp. 68-70, Jan.
2006.
A. L. S. Loke, C. K. Lee and B. M. Leary, "Nanoscale CMOS
Implications on Analog/Mixed-Signal Design," 2019 IEEE Custom Integrated
Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-57, doi:
10.1109/CICC.2019.8780267.
The problem with sine-wave scaling is that the noise power is, on
average, evenly distributed over all FFT bins, whereas the
sine-wave power is concentrated in only a few bins. With
sine-wave scaling, the power of individual sine-wave components can be
read directly from the spectral plot, but in order to determine the
noise power, the powers of all the noise bins must be added
together.
subplot(3,1,1); for N = [162561024] wrect = rectwin(N); Wrect = fftshift(fft(wrect)); Wrect_mag = abs(Wrect)/sum(wrect); nb_rect = sum(Wrect_mag > 0.1); fprintf('Number of nonzero FFT bin(rect window N=%d): %d\n', N, nb_rect); stem(1:N, Wrect_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('rect window')
subplot(3,1,2); for N = [162561024] whann = hann(N); Whann = fftshift(fft(whann)); Whann_mag = abs(Whann)/sum(whann); nb_hann = sum(Whann_mag > 0.1); fprintf('Number of nonzero FFT bin(hann window N=%d): %d\n', N, nb_hann); stem(1:N, Whann_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('Hanning window')
subplot(3,1,3); for N = [162561024] whann2 = (1-cos(2*pi*(0:N-1)/N)).^2/2^2; Whann2 = fftshift(fft(whann2)); Whann2_mag = abs(Whann2)/sum(whann2); nb_hann2 = sum(Whann2_mag > 0.1); fprintf('Number of nonzero FFT bin(hann2 window N=%d): %d\n', N, nb_hann2); stem(1:N, Whann2_mag, LineWidth=2) hold on end grid on legend('16', '256', '1024') title('Hann2 window')
% Number of nonzero FFT bin(rect window N=16): 1 % Number of nonzero FFT bin(rect window N=256): 1 % Number of nonzero FFT bin(rect window N=1024): 1 % Number of nonzero FFT bin(hann window N=16): 3 % Number of nonzero FFT bin(hann window N=256): 3 % Number of nonzero FFT bin(hann window N=1024): 3 % Number of nonzero FFT bin(hann2 window N=16): 5 % Number of nonzero FFT bin(hann2 window N=256): 5 % Number of nonzero FFT bin(hann2 window N=1024): 5
N = 2048; cycles = 67; fs = 1000; fx = fs*cycles/N; LSB = 2/2^10; %generate signal, quantize (mid-tread) and take FFT x = cos(2*pi*fx/fs*[0:N-1]); x = round(x/LSB)*LSB; s = abs(fft(x)); s = s(1:end/2)/N*2; % calculate SNR sigbin = 1 + cycles; noise = [s(1:sigbin-1), s(sigbin+1:end)]; snr = 10*log10( s(sigbin)^2/sum(noise.^2) );
sdb = 20*log10(s);
% How to plot a series of numbers which some of them are inf? % https://www.mathworks.com/matlabcentral/answers/476643-how-to-plot-a-series-of-numbers-which-some-of-them-are-inf plot([0:N/2-1]/N, max(sdb, -120), LineWidth=4) hold on; plot([00.5], [-61.9-61.9], 'r--', LineWidth=2) plot([00.5], [-92-92], 'm--', LineWidth=2) grid on; grid minor; ylim([-1200]); xlim([00.5]); xlabel('Frequency [f/fs]'), ylabel('DFT Magnitude [dBFS]'); title('2048 point FFT, SNR=61.90dB')
DFT bin's output noise standard deviation (rms)
value is proportional to \(\sqrt{N}\),
and the DFT's output magnitude for the bin containing the signal
tone is proportional to \(N\)
signal tone power \[
P_{\text{sig}} = 2 \frac{X_{w,sig}^2}{N^2}
\]
noise power \[
P_n = \frac{X_{w,n}^2}{N}
\]
The displayed SNR\[
\mathrm{SNR} = \mathrm{SNR}' - 10\log_{10}(2/N)
\] If we increase a DFT's size from \(N\) to \(2N\), the DFT's output SNR increased by
3dB. So we say that a DFT's processing gain increases
by 3dB whenever \(N\) is doubled.
1 2 3 4 5 6
for N=[2^62^82^102^12] wd = rectwin(N); nbw = enbw(wd)/N; snr_shift = 10*log10(nbw * 2); disp(snr_shift); end
output:
1 2 3 4 5 6 7
-15.0515
-21.0721
-27.0927
-33.1133
How spectrum analyzer work?
We tried to plot a power spectral density together with
something that we want to interpret as a power spectrum
spectrum of a periodic signal
spectral density of a broadband signal such as noise
Sine-wave components are located in individual FFT bins, but
broadband signals like noise have their power spread over all FFT
bins!
The noise floor depends on the length of the
FFT
PS and PSD
The spectral density format is appropriate for random or noise
signals but inappropriate for discrete frequency components because the
latter theoretically have zero bandwidth
Amplitude Correction
A finite-duration window \(w[n]\)
DTFT is \(W[e^{j\omega}]\) and the
maximum magnitude is is at DC frequency, which \(\sum_n w_n\)
Sinusoidal signal \(x[n]\)
DFS is \(X_k\), and DTFT shall be
\(\frac{2\pi}{N}X_k(e^{j\omega})\)
the windowed sequence \(v[n] =
x[n]w[n]\)
with multiplication property, DTFT of \(v[n]\) shall be \(\frac{X_k(e^{j\omega})}{N}\sum_n w_n\)
As we know, DFT of \(v[n]\) is
samples of its DTFT, that is \[
\frac{X_k(e^{j\omega})}{N}\sum_n w_n = X_v[k]
\] Therefore, \[
\frac{X_k(e^{j\omega})}{N} = \frac{X_v[k]}{\sum_n w_n}
\]
Effective Noise BandWidth
(ENBW)
General derivation
The relationship between a power spectrum (\(PS, V^2\)) and a power spectral
density (\(PSD, V^2/Hz\)) is given
by the effective noise bandwidth (ENBW), which
can easily be determined at the time when the DFT is computed.
ENBW should always be recorded when a spectrum or spectral density is
computed, such that the result can be converted to the other form at a
later stage, when the information about the frequency resolution \(f_{res}\) and the window that was used is
normally not easily available any more.
The normalized equivalent noise bandwidth (NENBW) of
the window is given by
\[
\text{NENBW} = \frac{NS_2}{S_1^2}
\] where \(S_1 = \sum
_{k=0}^{N-1}w_k\) and \(S_2 = \sum
_{k=0}^{N-1}w_k^2\)
Equivalent noise bandwidth (ENBW) compares a window to an
ideal, rectangular time-window. It is the bandwidth of the
rectangular window's frequency-domain shape that passes the same
amount of white noise energy as the frequency-domain
shape defined by the other window.
Therefore, the equivalent noise bandwidth \(B_{enbw}\) is given by
Assuming the windowed sequence \(v[n] =
x[n]w[n]\)
\(W[k]\): Fourier Transform of
finite sequence window
\(X_{sig}\): Fourier Transform
of signal
\(X_{n}\): Fourier Transform of
noise
\(X_{v,sig}\): Fourier Transform
of windowed signal
\(X_{v,n}\): Fourier Transform
of windowed noise
From Fig. 6,, we observe that the amplitude of the harmonic estimate
at a given frequency is biased by the accumulated broad-band noise
included in the bandwidth of the window.
In this sense, the window behaves as a filter, gathering
contributions for its estimate over its bandwidth
The Fourier Transform of windowed signal can be expressed as
%Clear variables. clear command window, close all figures: clc; clear all; close all; %%%Setup and define variables f0=10; %frequency of sinusoidal signal (Hz) fs=100; %sampling frequency (Hz) Ts=1/fs; %sampling period (seconds) N0=3000; %number of samples t=[0:Ts:Ts*(N0-1)]; %Sample times noise_PSD=.5; %This is the desired noise power spectral density in W/Hz. variance=noise_PSD*fs;% Variance = sigma^2 sigma=sqrt(variance); noise=transpose(sigma*randn(N0,1));%create sampled white Gaussian noise. xsignal=20*sin(2*pi*f0*t); %create sampled sinusoidal signal x=xsignal+noise; %Add signal to noise figure(1) histogram(noise,30) %plot histogram set(gca,'FontSize',14) %set font size of axis tick labels to 18 xlabel('Noise amplitude','fontsize',14) ylabel('Frequency of occurance','fontsize',14) title('Simulated histogram of white Gaussian noise','fontsize',14) SNR_try1=snr(xsignal,noise); %calculate SNR using built in "snr" function. SNR_try2=10*log10(sum(xsignal.^2)/sum(noise.^2)); %manually calculate SNR. %If everything is correct, the two SNR calculations above should agree. %Plot noise in time-domain figure(2) plot(t,x) set(gca,'FontSize',14) %set font size of axis tick labels to 18 xlabel('Time (s)','fontsize',14) ylabel('Amplitude','fontsize',14) title('Noisey sinusoid','fontsize',14) grid on %Plot power spectral density (PSD) of noise using three different methods: % %Method 1. Calcululate PSD from amplitude spectrum N=2^16; %Number of discrete points in the FFT y=fft(x,N)/fs; %fft of noise z=fftshift(y);%center noise spectrum f_vec=[0:1:N-1]*fs/N-fs/2; %designate sample frequencies amplitude_spectrum=abs(z); %compute two-sided amplitude spectrum ESD1=amplitude_spectrum.^2; %ESD = |F(w)|^2; PSD1=ESD1/((N0-1)*Ts);% PSD=ESD/T where T = total time of sample figure(3) plot(f_vec,10*log10(PSD1)); xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 1','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight %calculate average power using PSD calclated from method 1: Average_power_method_1=sum(PSD1)*fs/N; % Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Method 2 - Calculate PSD from autocorrelation time_lag=((-length(x)+1):1:(length(x)-1))*Ts; auto_cor=xcorr(x,x)/fs; %Use xcorr function to find PSD y=1/fs*fft(auto_cor,N); %fft of auto correlation function PSD2=abs(1/(N0-1)*fftshift(fft(auto_cor,N))); figure(4) plot(f_vec,10*log10(PSD2));%use convolution xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 2','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight %calculate average power using PSD calclated from method 1: Average_power_method_2=sum(PSD2)*fs/N; %Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Method 3 - Calculate PSD using built in pwelch function figure(5) PSD3=periodogram(x,[],N,fs,'centered'); plot(10*log10(PSD3)) xlabel('Frequency [Hz]','fontsize',14) ylabel('dB/Hz','fontsize',14) title('Power spectral density - method 3','fontsize',14) grid on set(gcf,'color','w'); %set background color from grey (default) to white axis tight Average_power_method_3=sum(PSD3)*fs/N; %Pav=sum(PSD)*delta_f where delta_f=fs/N; % %Calculate mean and average PSD of noise: PSD_noise=periodogram(noise,[],N,fs,'centered'); Average_noise_PSD=mean(PSD_noise); Mean_noise=mean(noise);
The power spectral density plots for methods 2 and 3 exactly match
that for method 1 (shown above).
A finite-length data record = an infinite record multiplied by a
rectangular window
Windowing is unavoidable
Applying the Hanning window (or any window) to a periodic
signal creates leakage.
leakage:
The component at one frequency leaks into the vicinity of another
compnent owing to the spectral smearing introdued by
window.
Notice side lobes adding out of phase can reduce
the heights of the peaks
Windowed Signal
Short transient signals in the time domain produce high, broadband
frequency content.
To reduce leakage, a mathematical function called a
window is applied to the data. Windows are designed to
reduce the sharp transient in the re-created signal as much as
possible.
Because the sharp transients are reduced and smoothed, the broadband
frequency of the spectral leakage is also reduced.
Periodic versus
Non-Periodic Background
When performing a Fourier Transform on measurement data, a window
affects periodic and non-periodic data differently:
Periodic (No Window needed): A signal captured
in a periodic manner does not require a window, and a resulting Fourier
Transform has no leakage. Applying a window alters the resulting Fourier
transform, and even creates spectral leakage where there would have been
no leakage otherwise.
Non-periodic (Window needed): Windows are used
on signals that are captured in a non-periodic manner to reduce spectral
leakage and get closer to the periodic results. A window can minimize
the leakage present in a non-periodic signal, but cannot eliminate
it.
The signal is repeated and appended mathematically because the
measured data is assumed to be representative of the entire original
signal
Periodic
When a measurement signal is captured in a periodic manner, the
Fourier Transform of the captured signal will have no
leakage in the frequency domain.
A window is not recommended for a periodic signal as it will distort
the signal in an unnecessary manner, and actually creates
spectral leakage.
Maloberti, F. Data Converters. Dordrecht, Netherlands:
Springer, 2007.
Non-periodic
The same sine wave, with a different measurement time, results in a
non-periodic captured signal. Here, when the captured signal is
repeated, the original sine wave signal is not re-created.
In fact, several broadband transient events (circled in red) are
introduced. These transients create a broadband response, or
leakage.
Windows are used to minimize this leakage effect in
the frequency domain.
Hanning
When doing operational noise and vibration measurements, the Hanning
window is commonly used.
Random data has spectral leakage due to the abrupt cutoff at
the beginning and end of the time block. It is
non-periodic.
There is no way to ensure that the captured random
signal is periodic by varying the measurement time.
Hanning windows are often used with random data
because they have moderate impact on the frequency resolution and
amplitude accuracy of the resulting frequency spectrum.
The maximum amplitude error of a Hanning window is
15%
In the cited article, all spectral data had an amplitude
correction factor applied.
while the frequency leakage is typically confined to 1.5
spectral lines to each side of the original sine wave
signal
periodic signal
Applying the Hanning window (or any window) to a periodic signal
creates leakage.
The periodically captured sine wave with the Hanning window
(blue) is wider in frequency than the original signal (red)
In the figure, the sine wave with the Hanning window (blue) is
wider in frequency than the original signal (red).
non-periodic signal
When a Hanning window is applied to a non-periodic signal, the
leakage is greatly reduced and the amplitude is higher.
A non-periodically captured sine wave (magenta) has a
spectral leakage over the entire bandwidth, applying a Hanning window
minimized the leakage (green)
RMS calculation
A RMS calculationsums up the energy within a
frequency range.
both the RMS of the periodic and non-periodic signals with a
Hanning window are equal to the RMS of the leakage-free sine
wave.
Only the RMS of the non-periodic sine wave without a window
applied is not equal to the others
With the leakage spread over a smaller frequency range, doing
analysis calculations like RMS yields more accurate
results.
Flattop
The Flattop window has a better amplitude accuracy in
frequency domain compared to the Hanning window,
The maximum amplitude error of a Flattop window is less than
0.01%. By contrast, the Hanning window maximum amplitude error is
15%.
A Flattop window confines leakage to 3.43 spectral lines
to each side of the original signal.
amplitude errors
These maximum amplitude errors assume that amplitude correction
factors are applied to the frequency spectrums. These amplitude
correction factors compensate for any reduction caused by applying a
window.
leakage
The frequency accuracy of the Flattop window is more coarse compared
to a Hanning window. As a result, the Flattop window is typically
employed on data where frequency peaks are distinct and well separated
from each other.
When the frequency peaks are not guaranteed to be well separated, the
Hanning window is preferred because it is less likely to cause
individual peaks to be lost in the spectrum
Spectrum of two periodically captured tones that are \(4Hz\) apart with a \(1Hz\) frequency resolution. The spectrum
with a Hanning window (green) shows two peaks while the spectrum with a
Flattop window (blue) shows one peak.
Note that at the original frequencies of the tones the amplitude is
correct and equal to one for both windows.
One common application for a flattop window is performing
calibration. For example, a sound pistonphone only produces
one single and distinct frequency during microphone
calibration.
Uniform
A Uniform window has a value of 1.0 across the entire
measurement time. In reality, a Uniform window could be
called no window.
Depending on the data acquisition system used, sometimes the term
Rectangular window is also used.
A Uniform window creates no frequency or amplitude distortion
when the measured signal is periodic.
When a measured signal is not periodic, the amplitude is reduced
by a maximum of 36% and the frequency content is spread over
the entire bandwidth of the measurement.
This is due to sharp transients that are created by
repeating and appending the measured signal.
Whenever a measurement signal is periodic, a Uniform window is
preferred.
Applying a Hanning or Flattop window to a periodic signal will
actually create amplitude and frequency distortion.
Benefit of Reducing Leakage
The benefit is not that the captured signal is
perfectly replicated.
The main benefit is that the leakage is now confined over a
smaller frequency range, instead of affecting the entire
frequency bandwidth of the measurement.
With the leakage spread over a smaller frequency range, doing
analysis calculations like RMS yields more accurate results.
It is impossible to calculate the proper RMS amplitude estimate over
a limited frequency range of the un-windowed sine wave, since
the leakage is over the full frequency range. Therefore the RMS
amplitude is not correct.
Two tones
In the case of two closely spaced sine tones, without a window being
applied, two tones frequencies would leak into each other, which make
determining the true amplitude of individual peaks very difficult.
The window makes it easier to separate and distinguish each tone so a
proper analysis could be performed.
window function in
frequency domain
The transfer function \(a(f)\) of a
window \(w_j, j \in [0, N-1]\)
expresses the response of the window to a sinusoidal signal at an offset
of \(f\) frequency bins, i.e. DFT .
real part:\[
a_r(f)=\sum_{j=0}^{N-1}w_j\cos (2\pi f j/N)
\]
imaginary part:\[
a_i(f)=\sum_{j=0}^{N-1}w_j\sin (2\pi f j/N)
\]
frequency response can be obtained as \[
a(f) = \frac{\sqrt{a_r^2+a_i^2}}{S_1}
\] where \(S_1 = \sum
_{k=0}^{N-1}w_k\)
Rectangular window example
aka. Uniform window, "Rectangular" window, "no window"
Whenever a measurement signal is periodic, a Uniform window is
preferred. Applying a Hanning or Flattop window to a periodic signal
will actually create amplitude and frequency distortion.
When \(f=0\)
\[
a_r(f) + ja_i(f) = \sum_{k=0}^{N-1}w_k = N
\]
When \(f \neq 0\)
\[\begin{align}
a_r(f) + ja_i(f) &= \sum_{k=0}^{N-1} e^{\frac{j2\pi k f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} + e^{\frac{j2\pi (k+N/2)
f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} + e^{j\pi}
e^{\frac{j2\pi k f}{N}} \\
&= \sum_{k=0}^{N/2} e^{\frac{j2\pi k f}{N}} - e^{\frac{j2\pi k
f}{N}} \\
&= 0
\end{align}\]
A Uniform window creates no frequency or amplitude distortion when
the measured signal is periodic.
However, if the signal cannot be guaranteed to be periodic, a Uniform
window should be avoided.
Window Properties
There is no possibility of trade-off between
main-lobe width and sied-lobe amplitude, since the
window length is the only variable parameter.
The rectangular window has the narrowest main lobe for a given
length, i.e. \(\Delta
_{ml}=4\pi/L\)
Other windows include the Bartlett, Hann, and Hamming windows. The
DTFTs of all these windows have main-lobe width \(\Delta _{ml}=8\pi/(L-1)\), which is
approximately twice that of the rectangular window, but they have
significantly smaller side-lobe amplitudes.
figure(1) plot(ff, X, 'r-o', ff, X_rect, 'b-s'); xlabel('Frequency(Hz)'); ylabel('|X|') title('Amplitude spectrum of periodically captured sine wave'); legend('w/ hanning', 'w/ rect'); grid on grid minor % rectangular window provide higher frequency resolution % hanning window induce leakage for the periodically captured sine wave
% fin - 0.5fres fin_lkg0d5 = fin - 0.5*fres; wv_lkg0d5 = cos(2*pi*fin_lkg0d5*tt); power_lkg0d5 = periodogram(wv_lkg0d5, whan, N, fs, 'power'); X_lkg0d5 = (power_lkg0d5).^0.5*2^0.5; psd_lkg0d5 = periodogram(wv_lkg0d5, whan, N, fs, 'psd'); rms_lkg0d5 = sum(psd_lkg0d5*fres)^0.5; fprintf('RMS@-0.5fres & hanning: %.5f\n', rms_lkg0d5);
Basic idea: use of mean of \(v'(t)\) to approximate
median of \(v'(t)\)
Elmore delay approximates the median of \(h(t)\) by the mean of
\(h(t)\)
Distributed RC-Line
Lumped approximations
\(rc\)-models
If your simulator does not support a distributed \(rc\)-model, or if the computational
complexity of these models slows down your simulation too much, you can
construct a simple yet accurate model yourself by approximating the
distributed \(rc\) by a lumped RC
network with a limited number of elements
The accuracy of the model is determined by the number of stages. For
instance, the error of the \(\Pi -3\)
model is less than 3%, which is generally sufficient.
Why use "\(\Pi\)
Model"
examples
Wire Inductive Effect
RC delay increases quadratically with length
LC delay (speed of light flight time) increases linearly with
length
Inductance will only be important to the delay of low-resistance
signals such as wide clock lines
wave
Signal propagates over the wire as a wave (rather
than diffusing as in \(rc\) only models)
Signal propagates by alternately transferring energy from capacitive
to inductive modes
A glitch is an unwanted pulse at the output of a
combinational logic network – a momentary change in an
output that should not have changed
A circuit with the potential for a glitch is said to have a
hazard
In other words a hazard is something intrinsic about a circuit; a
circuit with hazard may or may not have a glitch depending on input
patterns and the electric characteristics of the circuit.
When do circuits have hazards
?
Hazards are potential unwanted transients that occur in the output
when different paths from input to output have different propagation
delays
Isolation cells are additional cells
inserted by the synthesis tools for isolating the buses/wires crossing
from power-gated domain of a circuit to its always-on
domain (AON).
To prevent corruption of always-on domain, we clamp the nets crossing
the power domains to a value depending upon the design.
A simple circuit having a switchable (or gated) power
domain
The circuit shown in Figure 1, after isolation cells are
inserted
Clock Gating is defined as: "Clock gating is a
technique/methodology to turn off the clock to certain parts of the
digital design when not needed".
AND gate-based clock gating
In simplest form a clock gating can be achieved by using an
AND gate as shown in picture below
However, this simplest form of clock gating technique has some
problem of generating glitches in the clock provide to
the FF, which are not desirable.
Glitches in enable/gated clock
Latch based clock gating
These glitches can be removed by introducing a negative edge
triggered FF (assuming downstream FFs are positive edge) or low-level
sensitive latch at the output of the clock enable signal.
This will make sure that any glitch in the clock enable signal will
not be visible to the gated clock output. The Latch output will only be
updated during the negative clock cycle and thus input to AND gate will
be stable high.
Glitch Free Gated Clock
OCV Derating With AOCV
Genus Attribute Reference 22.1
Innovus Text Command Reference 22.10
Article (20416394) Title: Analysis with Advanced On-chip Variation
(AOCV) derating in EDI system and ETS URL:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050NxEAI
When set to aocv_multiplicative, the derating factor
will be calculated as AOCV derating * OCV derating, which is set using
the set_timing_derate command.
When set to aocv_additive, the derating factor will be
calculated as AOCV derating + OCV derating values.
When you use this global variable, the report_timing
command shows the total_derate column in the timing report
output, which allows you to view and cross-check the calculated total
derate factor.
To set this global variable, use the set_global
command.
Gildenblat, G. S. (2010). Compact modeling : principles, techniques
and applications. Springer.
VDS Effect On Channel Noise
\[
\color{red} \overline{i^2_d} \propto V_{DS}
\]
K. Ohmori and S. Amakawa, "Direct White Noise Characterization of
Short-Channel MOSFETs," in IEEE Transactions on Electron
Devices, vol. 68, no. 4, pp. 1478-1482, April 2021 [pdf,
slides]
⭐ where \(S_{x_n}^T=\frac{\partial
T}{\partial x_n}\frac{x_n}{T}\) is relative
sensitivity
relative sensitivity connect \(\frac{dx_n}{x_n}\) with total relative
variation \(\frac{dT}{T}\)
And \(dT\) can be expressed as \[
dT =\sum_{n=1}^N S_{x_n}^T T\cdot \frac{dx_n}{x_n} = \sum_{n=1}^N
x_n'\cdot \frac{dx_n}{x_n}
\] ⭐ where \(x_n'= S_{x_n}^T
T\) is the contribution of \(x_n\) in \(T\)
⭐ For parallel or series resistors, it can prove \(\sum_{n=1}^N S_{x_n}^T = 1\) and \(\sum_{n=1}^N x_n'=T\)
Here \(T= R_1 \parallel R_2 =
\frac{R_1R_2}{R_1+R_2}\), and \(T|_{R_1=8000, R_2=2000} = 1600\)
The contribution of \(R_1\) and
\(R_2\) to \(T\)\[\begin{align}
R_1' &= S_{R_1}^T T | _{R_1=8000, R_2=2000} = 320 \\
R_2' &= S_{R_2}^T T | _{R_1=8000, R_2=2000} = 1280
\end{align}\]
Any dc current flowing through a diode generates the
so-called "shot noise" due to the random nature of the hole and
electron transitions across the pn junction
Shot noise is not relevant in CMOS devices since it
is only present in bipolar transistors and junction diodes
If \(V_{DS}\) is slightly
greater than \(V_{GS} - V_{TH}\), then
the inversion layer stops at \(x \leq
L\), and we say the channel is "pinched
off"
Upon passing the pinchoff point, the electrons simply shoot through
the depletion region near the drain junction and arrive at the drain
terminal
\(L^{'}\) is the function of
\(V_{DS}\)
with \(\frac{1}{L^{'}} =
\frac{1}{L-\Delta L}=\frac{L+\Delta L}{L^2-\Delta L^2}\approx
\frac{1}{L}\left(1+\frac{\Delta L}{L}\right)\), we have \[
I_D \approx \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(1+\frac{\Delta
L}{L}\right)(V_{GS}-V_{TH})^2 = \frac{1}{2}\mu_n
C_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2 (1+\lambda V_{DS})
\] assuming \(\frac{\Delta L}{L} =
\lambda V_{DS}\)
\(\lambda\) represents the
relative variation in length for a given increment in \(V_{DS}\). Thus, for longer channels, \(\lambda\) is smaller
In reality, however, \(r_O\) varies
with \(V_{DS}\). As \(V_{DS}\)increases and the
pinch-off point moves toward the source, the rate at which the
depletion region around the source becomes wider decreases,
resulting in a higher incremental output impedance.
The dependence of offset voltage and current mismatches upon the
overdrive voltage is similar to our observations for corresponding
noise quantities
differential pair
In reality, since mismatches are independent statistical
variables
Above shows that the input transistors must be designed for high
gain (\(g_mr_o =
\frac{2}{V_{OV}\lambda}\)), which means they must be designed for
small\(V_{GS}-V_{TH}\).
It is desirable to minimize \(V_{GS}-V_{TH}\) by lowering the tail
current or increasing the transistor widths
Then, we get \[
V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m)
\] Due to \(V_o=V_m\) and \(V_o'=V_m'\)\[
V_{os}=(1/A+1)\Delta{V_m}
\] or \[
V_{os}=(1/A+1)\Delta{V_o}
\] if \(A \gg 1\)\[
V_{os}=\Delta{V_o}
\]
we get \[
V_{os}=\frac{V_o'-V_o}{A}+(V_m'-V_m)
\] or \[
V_{os}=\frac{\Delta V_o}{A}+\beta \Delta V_o
\] if \(A \gg 1\)\[
V_{os}=\beta \Delta V_o
\] or \[
V_{os}=\Delta V_m
\]
Lecture 22 Variability and Mismatch of Dr. Hesham A. Omran's
Analog IC Design
M. Coelho et al., "Is There a ZTC Biasing Point in the
Leading-Edge FET Intrinsic Gain gmrDS?," 2025 9th International
Young Engineers Forum on Electrical and Computer Engineering
(YEF-ECE), Caparica / Lisbon, Portugal, 2025
zero temperature coefficient (ZTC)
MOM cap of wo_mx
Monte Carlo model:
\(C_{pa}=C_{pa1}\), \(C_{pb}=C_{pb1}\) for each iteration during
Process Variation
different variation is applied to \(C_{ab}\) and \(C_{a1b1}\) each iteration during
Mismatch Variation, though \(C_{pa}\), \(C_{pb}\), \(C_{pa1}\) and \(C_{pb1}\) remain constant
\(C_\text{eq}\) and \(R_\text{eq}\) are obtained \[\begin{align}
C_\text{eq} &= \frac{1+|A|^2-2A_r}{1-A_r}\cdot C_f \\
R_\text{eq} &= \frac{A_i}{1+|A|^2-2A_r}\cdot \frac{1}{\omega C_f}
\end{align}\]
D/S small signal model
The Drain and Source of MOS are determined
in DC operating point, i.e. large signal.
That is, top of \(M_2\) is
drain and bottom is source, \[\begin{align}
R_\text{eq2} &= \frac{r_\text{o2}+R_L}{1+g_\text{m2}r_\text{o2}} \\
& \simeq \frac{1}{g_\text{m2}}
\end{align}\]
PMOS small signal model
polarity
The small-signal models of NMOS and PMOS transistors are
identical
A negative \(\Delta V_\text{GS}\)
leads to a negative \(\Delta I_D\).
Recall that \(I_D\), in the
direction shown here, is negative because the actual current of holes
flows from the source to the drain.
Conversely, a positive \(\Delta
V_\text{GS}\) produces a positive \(\Delta I_D\), as is the case for an NMOS
device.
Leakage in MOS
Subthreshold leakage
Drain-Induced Barrier Lowering (DIBL)
Reverse-bias Source/Drain junction leakages
Gate leakage
two other leakage mechanisms
Gate Induced Drain Leakage (GIDL)
Punchthrough
W. M. Elgharbawy and M. A. Bayoumi, "Leakage sources and possible
solutions in nanometer CMOS technologies," in IEEE Circuits and Systems
Magazine, vol. 5, no. 4, pp. 6-17, Fourth Quarter 2005, doi:
10.1109/MCAS.2005.1550165.
X. Qi et al., "Efficient subthreshold leakage current optimization -
Leakage current optimization and layout migration for 90- and 65- nm
ASIC libraries," in IEEE Circuits and Devices Magazine, vol. 22, no. 5,
pp. 39-47, Sept.-Oct. 2006, doi: 10.1109/MCD.2006.272999.
P. Monsurró, S. Pennisi, G. Scotti and A. Trifiletti, "Exploiting the
Body of MOS Devices for High Performance Analog Design," in IEEE
Circuits and Systems Magazine, vol. 11, no. 4, pp. 8-23, Fourthquarter
2011, doi: 10.1109/MCAS.2011.942751.
Andrea Baschirotto, ISSCC2015 "ADC Design in Scaled Technologies"
As a result of DIBL, threshold voltage is reduced
with shorter channel lengths and, consequently, the subthreshold leakage
current is increased
impact on output impedance
The principal impact of DIBL on circuit design is the degraded output
impedance.
In short-channel devices, as \(V_{DS}\) increases further, drain-induced
barrier lowering becomes significant, reducing the threshold
voltage and increasing the drain current
Impact Ionization and GIDL are different, however both
increase drain current, which flowing from the drain into the
substrate
Gate induced drain leakage
(GIDL)
The large current flows from the drain to bulk and this
drain leakage current is named gate-induced drain leakage
(GIDL) since it is due to a gate-induced high electric
field present in the gate-to-drain overlap region
gate-induced drain leakage (GIDL) increases exponentially due to the
reduced gate oxide thickness
Chauhan, Yogesh Singh, et al. FinFET modeling for IC simulation
and design: using the BSIM-CMG standard. Academic Press, 2015.
\[
\frac{g_m}{I_D} = \frac{2}{V_{GS}-V_{TH}}
\] Decrease of gm/Id results from decrease in VT.
GIDL (Gate induced drain leakage) as at weak
inversion may results in a weak lateral electric field causing leakage
current between drain and bulk, which degrade the efficiency of the
transistor (gm/ID).
REF: D. A. Yokoyama-Martin et al., "A Multi-Standard Low Power
1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS," IEEE Custom Integrated
Circuits Conference 2006, 2006, pp. 401-404, doi:
10.1109/CICC.2006.320970.
Power/Ground and I/O Pins
Power / Ground Pin
Information
In both digital and analog I/O, power and ground pins appear at the
sub-circuit definiton, allowing user to use the I/O in voltage islands.
They follow certain naming conventions.
digital I/O sub-circuit
VDD: pre-driver core voltage (supplied by PVDD1CDGM)
VSS: pre-driver ground and also global ground (supplied by
PVDD1CDGM)
VDDPST: I/O post-driver voltage, i.e. 1.8V (supplied by PVDD2CDGM or
PVDD2POCM)
VSSPOST: I/O post-driver ground (supplied by PVDD2CDGM or
PVDD2POCM)
POCCTRL: POCCTRL signal (supplied by PVDD2POCM)
analog I/O placed in a core voltage domain, the convention is
TACVDD: analog core voltage (supplied by PVDD3ACM)
TACVSS: analog core ground (supplied by PVDD3ACM)
VSS: global core ground
analog I/O placed in an I/O voltage domain, the convention is:
TAVDD: analog I/O voltage, i.e. 1.8V (supplied by PVDD3AM)
TAVSS: analog I/O ground (supplied by PVDD3AM)
VSS: global core ground
Power/Ground Combo Cells
power/ground combo pad cell
pins to be connected to bump
to core side pin name
PVDD1CDGM
VDD VSS
VDD VSS
PVDD2CDGM PVDD2POCM
VDDPST VSSPST
N/A
PVDD3AM
TAVDD TAVSS
AVDD AVSS
PVDD3ACM
TACVDD TACVSS
AVDD AVSS
Note for the retention mode
At initial state, IRTE must be 0 when VDD is
off.
IRTE must be kept >= 10us after VDD turns on again (from the
retention mode to the normal operation mode).
IRTE can be switched only when both VDD and VDDPST are on.
When the rention function is needed, IRTE signal must come from an
"always-on" core power domain. If you don't need the rention function,
it is required to tie IRTE to ground. In other words, no matter
the rention feature is needed or not, it is required to have PCBRTE in
each domain.
Note: PCBRTE does not need PAD
connection.
Internal Pins
There are 3 internal global pins, i.e. ESD,
POCCTRL, RTE, in all digital domain
cells.
In real application,
ESD pin is an internal signal and
active in ESD event happening
POCCTRL is an internal signal and active in
Power-on-control event.
However, these special events (i.e. ESD event and Power-on-control
event) are not modeled in NLDM kit (.lib), only normal function is
covered, so ESD and POCCTRL pins are
simply defined as ground in NLDM kit (.lib).
These 3 global pins will be connected automatically after
cell-to-cell abutting in physical layout.
Power-Up sequence in
Digital Domain
Power up the I/O power (VDDPST) first, then the core power (VDD)
PVDDD2POCM cell would generate Power-On-Control signal (POCCTRL) to
have the post-driver NMOS and PMOS off, so that the crowbar current
would not occur in the post-driver fingers when the I/O voltage is on
while the core voltage remains off. As such, I/O cell would be in the
Hi-Z state. when POCCTRL is on, the pll-up/down resistor is disabled and
C is 0.
The POCCTRL signal is transmitted to I/O cells through cell
abutment. There is no need to have routing for POCCTTRL nor
give a control signal to the POCCTRL pin any of I/O cells. Note that the
POCCTRL signal would be cut if inserting a power-cut (PRCUT) cell.
Power-Down sequence in
Digital Domain
It's the reverse of power-up sequence.
Use model in Innovus
1 2 3 4 5 6 7 8 9 10 11 12
set init_gnd_net "vss_core vss DUMMY_ESD DUMMY_POCCTRL"
M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for
small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17,
no. 1, pp. 31-41, Jan. 2001, doi: 10.1109/101.900125.
Ali Sheikholeslami, Circuit Intuitions: Thevenin and Norton
Equivalent Circuits, Part 3 IEEE Solid-State Circuits Magazine, Vol. 10,
Issue 4, pp. 7-8, Fall 2018.
—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part
2 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 3, pp. 7-8, Summer
2018.
—, Circuit Intuitions: Thevenin and Norton Equivalent Circuits, Part
1 IEEE Solid-State Circuits Magazine, Vol. 10, Issue 2, pp. 7-8, Spring
2018.
—, Circuit Intuitions: Miller's Approximation IEEE Solid-State
Circuits Magazine, Vol. 7, Issue 4, pp. 7-8, Fall 2015.
The most accurate method to calculate the degradation of transistors
is the SPICE-level simulation of the whole netlist with application
programming interface (API) and industry-standard stress process
models
MOSRA: MOSFET reliability analysis Synopsys
RelXpert: Cadence
TMI: TSMC Model Interface, TSMC
OMI: Open Model Interface, Si2 standard,
The Silicon Integration Initiative (Si2) Compact Model Coalition has
released the Open Model Interface, an Si2 standard, C-language
application programming interface that supports SPICE compact model
extensions.OMI allows circuit designers to simulate and analyze such
important physical effects as self-heating and aging,
and perform extended design optimizations. It is based on TMI2, the TSMC
Model Interface, which was donated to Si2 by TSMC in 2014.
TDDB: Time-Dependent Dielectric Breakdown
HCI: Hot Carrier injection
BTI: Bias Temperature Instability
NBTI: Negative Bias Temperature Instability
PBTI: Positive Bias Temperature Instability
SHE: Self-Heating Effect
Aging & SHE in FinFET
SHE
Self-Heating & EM
Heat Sink (HS)
guard ring
closer OD help reduce dT
extended gate
source/drain metal stack
Bias Temperature Instability
(BTI)
BTI occurs predominantly in PMOS (or p-type or p channel)
transistors and causes an increase in the transistor's absolute
threshold voltage.
Stress in the case of NBTI means that the PMOS transistor is
in inversion; that means that its gate to
body potential is substantially below 0 V for analogue circuits
or at VGB = −VDD for digital circuits
Higher voltages and higher temperatures both have
an exponential impact onto the degradation, induced by NBTI.
NBTI will be accelaerated with thinner gate oxide, at a high
temperature and at a high electric field across the oxide region.
During recovery phase where the gate voltage of pMOS is high and
stress is removed, the H atoms in the gate oxiede diffuse back to
Si-SiO2 interface and the recombination of Si-H bonds reduces the
threshold voltage of pMOS.
The net result is an increase in the magnitude of the device
threshold voltage |Vt|, and a degradation of the
channel carrier mobility.
Caution: The aging model provided by fab may
NOT contain recovry effect
PBTI
Hot Carrier Degradation (HCI)
Short-channel MOSFETs may exprience high lateral electric
fields if the drain-source voltage is large. while the average
velocity of carriers saturate at high fields, the instantaneous velocity
and hence the kinetic energy of the carriers continue to increase,
especially as they accelerate toward the drain. These are called
hot carriers.
In nanometer technologies, hot carrier effects have
subsided. This is because the energy required to create
an electron-hole pair, \(E_g \simeq 1.12
eV\), is simply not available if the supply voltage is around
1V.
\[
F_E= E \cdot q
\]
\[\begin{align}
E_k &= F_E \cdot s \\
&= E \cdot q \cdot s
\end{align}\]
Electrons and holes gaining high kinetic energies in
the electric field (hot carriers) may be injected into
the gate oxide and cause permanent changes in the
oxide-interface charge distribution, degrading the current-voltage
characteristics of the MOSFET.
The channel hot-electron (CHE) effect is caused by electons flowing
in the channel region, from the source to the drain. This effect is more
pronounced at large drain-to-source voltage, at which the lateral
electric field in the drain end of the channel accelerates the
electrons.
Four different hot carrier injectoin mechanisms can be distinguished:
- channel hot electron (CHE) injection - drain avalanche hot carrier
(DAHC) injection - secondary generated hot electron (SGHE) injection -
substrate hot electron (SHE) injection
HCI is more of a drain-localized mechanism, and is
primarily a carrier mobility degradation (and a Vt
degradation if the device is operated bi-directionally).
For smaller transistor dimensions, CHE dominates the hot
carrier degradation effect
The hot-carrier induced damage in nMOS transistors has been found to
result in either trapping of carriers on defect sites in the oxide or
the creation of interface states at the silicon-oxide interface, or
both.
The damage caused by hot-carrier injection affects the transistor
characteristics by causing a degradation in transconductance, a shift in
the threshold voltage, and a general decrease in the drain current
capability.
HCI seems to have just a weak temperature
dependency. Unlike BTI, it seems to be no or just little recovery. As
holes are much "cooler" (i.e. heavier) than electrons, the channel hot
carrier effect in nMOS devices is shown to be more significant than in
pMOS devices.
Degradation saturation
effect
HCI model can reproduce the saturation effect if stress time is long
enough
K. Yang, R. Zhang, T. Liu, D. -H. Kim and L. Milor, "Optimal
Accelerated Test Regions for Time- Dependent Dielectric Breakdown
Lifetime Parameters Estimation in FinFET Technology," 2018 Conference on
Design of Circuits and Integrated Systems (DCIS), Lyon, France, 2018 [https://par.nsf.gov/servlets/purl/10104486]
waveform-dependent nature
The figure below illustrates the waveform-dependent nature of these
mechanisms – as described earlier, BTI and HCI depend upon the region of
active device operation. The slew rate of the circuit inputs and output
will have a significant impact upon these mechanisms, especially
HCI.
Negative bias temperature instability (NBTI). This
is caused by constant electric fields degrading the dielectric,
which in turn causes the threshold voltage of the transistor to degrade.
That leads to lower switching speeds. This effect depends on the
activity level of the circuits, with heavier impact on parts of the
design that don’t switch as often, such as gated clocks,
control logic, and reset, programming and test circuitry.
Hot carrier injection (HCI). This is caused by
fast-moving electrons inserting themselves into the gate and
degrading performance. It primarily occurs on higher-voltage modes and
fast switching signals.
longer channel length help both BTI and HCI
larger\(V_{ds}\) help
BTI, but hurt HCI
lower temperature help BTI of core device, but hurt that of
IO device for 7nm FinFET
MOSRA
MOSRA is a 2-step simulation: 1) Age computation, 2) Post-age
analysis
TMI
BTI recovery effect NOT included for N7
Stochastic Nature
of Reliability Mechanisms
A fraction of devices will fail
Circuit Simulations
Heat transfer, thermal
resistance
Burn-in &
High-temperature operating life (HTOL)
HTOL:
characterization test
characterize the life expectancy
Burn-in:
production test
weed out defective products
HTOL and Burn-in Testing capture the two ends of the reliability
characterization graph known as the "bathtub curve"
Tanya Nigam and Andreas Kerber. Global Foundaries. CICC2014 Session
15 - Challenges for Analog Nanoscale Technologies: Reliability
challenges and modeling of HK MG Technologies
Spectre Tech Tips: Device Aging? Yes, even Silicon wears out -
Analog/Custom Design (Analog/Custom design) - Cadence Blogs - Cadence
Community https://shar.es/afd31p
A. Zhang et al., "Reliability variability simulation methodology for
IC design: An EDA perspective," 2015 IEEE International Electron Devices
Meeting (IEDM), Washington, DC, USA, 2015, pp. 11.5.1-11.5.4, doi:
10.1109/IEDM.2015.7409677.
W. -K. Lee et al., "Unifying self-heating and aging simulations with
TMI2," 2014 International Conference on Simulation of Semiconductor
Processes and Devices (SISPAD), Yokohama, Japan, 2014, pp. 333-336, doi:
10.1109/SISPAD.2014.6931631.
Article (20482350) Title: Measure the Impact of Aging in Spectre
Technology URL:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESBFUA4
Karimi, Naghmeh, Thorben Moos and Amir Moradi. “Exploring the Effect
of Device Aging on Static Power Analysis Attacks.” IACR Trans. Cryptogr.
Hardw. Embed. Syst. 2019 (2019): 233-256.[link]
Y. Zhao and Y. Qu, "Impact of Self-Heating Effect on Transistor
Characterization and Reliability Issues in Sub-10 nm Technology Nodes,"
in IEEE Journal of the Electron Devices Society, vol. 7, pp. 829-836,
2019, doi: 10.1109/JEDS.2019.2911085.
