KNOW-HOW

Reference Ripple

C-H Chan (U. of Macau) "Extreme SAR ADCs - Exploring New Frontiers" Online Course (2024) : Reference Buffer in SAR ADC [https://youtu.be/vj98B7AaC9E]

C. Li, C. -H. Chan, Y. Zhu and R. P. Martins, "Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 82-93, Jan. 2019 [https://ime.um.edu.mo/wp-content/uploads/magazines/961546494e705f6fd16b9f785a121030.pdf]

J. Zhong, Y. Zhu, S. -W. Sin, S. -P. U and R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 9, pp. 2196-2206, Sept. 2015 [https://sci-hub.st/10.1109/TCSI.2015.2452331]

C. -H. Chan et al., "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2576-2588, Oct. 2017 [https://ime.um.edu.mo/wp-content/uploads/magazines/407e580ac0218605bcf9b9bbd0ea1109.pdf]

TODO 📅

Sampling Front-End (SFE) Pulse Response

sweep the setup time between ideal pulse input and clock, sample the output of SFE at falling edge

sample-by-sample

3rd harmonic

bit-by-bit

The amplitude of the reference ripple is code-dependent as it is correlated with switching energy in each bit cycling

Redundancy

decision level

final digital output for an \(N\)-bit \(M\)-step ADC can be calculated \[ D_{out} = s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0] -1)\cdot s(1) \]

track the decision level

For \(N\)-bit binary weighted algorithm,\(N=M\) and \(s(i)=2^{i-1}\), where \(i\in \{N, N-1,...,2,1 \}\)

\[\begin{align} D_{out} &= s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0] -1) \\ &= 2^{N-1} + \sum_{i=1}^{N-1}2^i\cdot b[i] - \sum_{i=0}^{N-2}2^{i} + (b[0] -1) \\ &= \sum_{i=0}^{N-1} b[i] \cdot 2^i \end{align}\]

alternative method for d2a & CDAC equivalent weight

\[\begin{align} D_{out} &= \sum_{i=1}^{M-1}(2b_i -1)w_{i-1} + (b_0-1)w_0 \\ &= \sum_{i=1}^{M-1}b_i\cdot 2w_{i-1} + b_0\cdot w_0 -\sum_{i=1}^{M-1}w_{i-1} -w_0 \\ &= \left[\sum_{i=1}^{M-1}b_i\cdot 2w_{i-1} + b_0\cdot w_0\right] - \frac{1}{2}\left[\sum_{i=1}^{M-1}2w_{i-1} +w_0 + w_0\right] \\ &= \sum_{i=0}^{M-1}b_i\cdot W_i - \frac{1}{2}\left[\sum_{i=0}^{M-1}W_i + W_0\right] \end{align}\]

where \(W_i = 2w_{i-1}\) for \(i\in [M-1,1]\) and \(W_0 = w_0\)

Error Tolerance Window

\[ \varepsilon_t(n) = \sum_{i=1}^{n-2} s(i) - s(n-1) \]

where \(n\in [1, N]\), and \(N\)-bit SAR

For the \(n\)th output bit, once a decision is made, the next decision level will either move up or down by the step size of \(s(n − 1)\)

If this decision is erroneous, then the sum of the follow-on step sizes, \(s(n − 2)\), \(s(n − 3)\), ..., \(s(1)\), must be large enough and exceed the value of the current step size to counteract this mistake

The exceeded amount is the tolerance window for that decision level

sub-binary search

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import numpy as np
import matplotlib.pyplot as plt


def sar(xi, ss):
    M = ss.size
    th = ss[0]
    oob = []
    for i in range(M):
        ocur = 1 if xi >= th else 0
        oob.append(ocur)
        if i + 1 < M:
            th += (2 * ocur - 1) * ss[i + 1]
        else:
            break

    binstr = ''.join([str(s) for s in oob])
    decval = int(binstr, 2)
    return binstr, decval


def sar_plot(ss, Npts=10000):
    ss = np.asarray(ss)
    ssum = np.sum(ss)
    xilist = np.linspace(0, ssum + 1, Npts)
    outlist = []
    for i in range(Npts):
        _, decval = sar(xilist[i], ss)
        outlist.append(decval)
    outmax = np.max(outlist)
    plt.figure(figsize=(16,8))
    plt.plot(xilist, outlist, '-', linewidth=4)
    plt.xticks(range(0, ssum + 2))
    plt.yticks(range(0, outmax + 2, 2))
    plt.title('search step: {}'.format(ss), fontsize=20)
    plt.xlabel('analog out', fontsize=20); plt.ylabel('digital out', fontsize=20)

    plt.grid(True)

ss = [8, 4, 2, 1]
sar_plot(ss)

ss = [8, 2, 2, 2, 1]
sar_plot(ss)

plt.show()

ENOB vs. fixed radix

When the ADC is designed with a fixed radix, \(\alpha\) and the required number of conversion steps, \(M\)

the sum of all the step sizes \(s_{tot}\) \[ s_{tot} = \sum_{k=0}^{M-1} s_0 \alpha^k = s_0\frac{\alpha^M-1}{\alpha-1} \]

where \(s(i)\) is step size and \(i \in [0, 1, 2, M-1]\)

The effective number of bits, \(N\), can be calculated \[ N \leq \log 2\left(\frac{s_{tot} + s_0}{s_0}\right) = \frac{\alpha^M+\alpha-2}{\alpha-1} \]

Speed Benefit

TODO 📅

MSB with noise simualtion

SAR ADC Noise Analysis

kT/C Noise in sampling

DAC Noise in conversion

T. Miki et al., "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015 [https://sci-hub.jp/10.1109/JSSC.2015.2417803]

Comparator Noise in conversion

noise analysis for dynamic integrator

noise analysis for latch phase

P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008

CDAC

The charge redistribution capacitor network is used to sample the input signal and serves as a digital-to-analog converter (DAC) for creating and subtracting reference voltages

sampling charge \[ Q = V_{in} C_{tot} \] conversion charge \[ Q = -C_{tot}V_c + V_{ref}C_\Delta \] That is \[ V_c = \frac{C_\Delta}{C_{tot}}V_{ref} - V_{in} \]

CDAC is actually working as a capacitive divider during conversion phase, the charge of internal node retain (charge conservation law)

assuming \(\Delta V_i\) is applied to series capacitor \(C_1\) and \(C_2\)

\[ (\Delta V_i - \Delta V_x) C_1 = \Delta V_x \cdot C_2 \] Then \[ \Delta V_x = \frac{C_1}{C_1+C_2}\Delta V_i \]

\(V_x= V_{x,0} + \Delta V_x\)

CDAC settling accuracy

\[\begin{align} V_x(s) &= \frac{C_1+C_2}{RC_1C_2}\cdot \frac{1}{s+\frac{C_1+C_2}{RC_1C_2}}\cdot V_i(s) \\ &= \frac{1}{\tau}\cdot \frac{1}{s+\frac{1}{\tau}}\cdot \frac{1}{s}\\ &= \frac{1}{\tau}\cdot \tau(\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}})=\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}} \end{align}\]

inverse Laplace Transform is \(V_x(t) = 1 - e^{-t/\tau}\)

\[\begin{align} V_y(s) &= V_x\frac{C_1}{C_1+C_2} \\ &= \frac{C_1}{C_1+C_2} \left(\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}}\right)\\ \end{align}\]

inverse Laplace Transform is \(V_y(t) = \frac{C_1}{C_1+C_2}\left(1 - e^{-t/\tau}\right)\)

\(V_x(t)\) and \(V_y(t)\) prove that the settling time is same

\(\tau = R\frac{C_1C_2}{C_1+C_2}\), which means usually worst for MSB capacitor (largest)

both \(\tau\) and \(\Delta V\) are the maximum

A popular way to improve the settling behavior, again, is to employ unit-element DACs that statistically reduce the switching activities, which, unfortunately, exhibits unnecessary complications to the power, area and speed tradeoffs of the design

CDAC Energy Consumption

\[ E_{Vref} = \int P(t)dt = \int V_{ref} I(t) dt = V_{ref}\int I(t)dt = V_{ref}\cdot \Delta Q \]

Given \(V_{c,0}=\frac{1}{2}V_{ref}-V_{in}\) and \(V_{c,1}=\frac{3}{4}V_{ref}-V_{in}\) \[\begin{align} Q_{b0,0} &= \left(V_{ref} - V_{c,0} \right)\cdot 2C = \left(\frac{1}{2}V_{ref}+V_{in} \right)\cdot 2C \\ Q_{b1,0} &= (0 - V_{c,0})\cdot C = \left(-\frac{1}{2}V_{ref}+V_{in} \right)\cdot C \\ Q_{b0,1} &= \left(V_{ref} - V_{c,1} \right)\cdot 2C = \left(\frac{1}{4}V_{ref}+V_{in} \right)\cdot 2C \\ Q_{b1,1} &= \left(V_{ref} - V_{c,1} \right)\cdot C = \left(\frac{1}{4}V_{ref}+V_{in} \right)\cdot C \end{align}\]

Therefore \[ E_{Vref} = V_{ref}\cdot (Q_{b0,1}+Q_{b1,1} - Q_{b0,0}-Q_{b1,0}) = \frac{1}{4}C V_{ref}^2 \]

CDAC total energy change \[\begin{align} \Delta E_{tot} &= \frac{1}{2}\cdot 2C \cdot (U_{2c,1}^2 - U_{2c,0}^2) + \frac{1}{2}\cdot C \cdot (U_{c,1}^2 - U_{c,0}^2) + \frac{1}{2}\cdot C \cdot (U_{c1,1}^2 - U_{c1,0}^2) \\ &= \left(-\frac{3}{16}V_{ref}^2 - \frac{1}{2}V_{ref}V_{in} - \frac{3}{32}V_{ref}^2+\frac{3}{4}V_{ref}V_{vin} + \frac{5}{32}V_{ref}^2-\frac{1}{4}V_{ref}V_{in}\right)C \\ &= -\frac{1}{8}CV_{ref}^2 \end{align}\]

alternative method

\[ \Delta E_{tot} = \frac{1}{2}\cdot\frac{3}{4}C\cdot V_{ref}^2 - \frac{1}{2}\cdot C\cdot V_{ref}^2 = -\frac{1}{8}CV_{ref}^2 \]

The total energy decreases by \(-\frac{1}{8}CV_{ref}^2\), though \(V_{ref}\) provides \(\frac{1}{4}C V_{ref}^2\)

The charge redistribution change the CDAC energy

\[ E_{c,0} = \frac{1}{2}CV^2 \] After charge redistribution \[ E_{c,1} = \frac{1}{2}\cdot 2C\cdot \left(\frac{1}{2}V\right)^2 = \frac{1}{4}CV^2 \]

That make sense, charge redistribution consume energy

CDAC structure

CDAC with constant common-mode voltage

Comparator

Comparator input cap effect

\[ -V_{in}\cdot 2^N C = V_c (2^N C + C_p) \] Then \(V_c = -\frac{2^N C}{2^N C + C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude by the factor

During conversion \[\begin{align} V_c &= -\frac{2^N C}{2^N C + C_p}V_{in} +V_{ref}\sum_{n=0}^{N-1} \frac{b_n\cdot2^n C}{2^N C + C_p} \\ &= \frac{2^N C}{2^N C + C_p}\left(-V_{in} + V_{ref}\sum_{n=0}^{N-1}\frac{b_n }{2^{N-n}} \right) \end{align}\]

That is, it does not change the sign

Comparator offset effect

Synchronous SAR ADC

It also divides a full conversion into several comparison stages in a way similar to the pipeline ADC, except the algorithm is executed sequentially rather than in parallel as in the pipeline case.

However, the sequential operation of the SA algorithm has traditionally been a limitation in achieving high-speed operation

• a clock running at least \((N + 1) \cdot F_s\) is required for an \(N\)-bit converter with conversion rate of \(F_s\)
• every clock cycle has to tolerate the worst case comparison time
• every clock cycle requires margin for the clock jitter

The power and speed limitations of a synchronous SA design comes largely from the high-speed internal clock

Split Arrary CDAC

Split capacitor, double-array cap

attenuation capacitance \(C_a\)

\[\begin{align} \Delta V_{dac} &= \frac{1}{2}b_3+\frac{1}{4}b_2+\frac{1}{4}\left(\frac{1}{2}b_1+\frac{1}{4}b_0 \right) \\ &= \frac{1}{2}b_3+\frac{1}{4}b_2 + \frac{1}{8}b_1+\frac{1}{16}b_0 \end{align}\]

Asynchronous SAR ADC

The comparator itself trigger the next bit-conversion cycle as soon as the present bit decision has been taken

The maximum resolving time reduction between synchronous and asynchronous case is two fold

comparator metastable state

when the input is sufficiently small. The time needed for the comparator outputs to fully resolve may take arbitrarily long

In this case, the ready signal generator should still set the flag and the decision result is simply taken from the previous value stored in the SR latch

both outputs (\(Q_p\) and \(Q_n\)) will drop together, NAND is inverter actually

The transition point of this NAND gate is skewed to eliminate metastability issues arising when the input differential voltage level is small (comparator)

reference

Andrea Baschirotto, "T6: SAR ADCs" ISSCC2009

Pieter Harpe, ISSCC 2016 Tutorial: "Basics of SAR ADCs Circuits & Architectures"

Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006 [pdf, slides]

—. "Power Efficient System and A/D Converter Design for Ultra-Wideband Radio" [http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-71.pdf]

—. "Asynchronous SAR ADC: Past, Present and Beyond" [https://viterbi-web.usc.edu/~swchen/index_files/async_sar_tutorial_chen_final.pdf]

C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010 [https://sci-hub.se/10.1109/JSSC.2010.2042254]

L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021 [pdf]

W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011 [https://sci-hub.st/10.1109/JSSC.2011.2163556]

Andrew Yu. Understanding Metastability in SAR ADCs: Part II: Asynchronous [https://github.com/phonon/sar-adc-metastability] [pdf]

Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023)

Figures of Merit (FoMs)

B. Murmann, "ADC Performance Survey 1997-2022," [Online]. Available: [https://github.com/bmurmann/ADC-survey]

Carsten Wulff, "Advanced Integrated Circuits 2025" [http://analogicus.com/aic2025/2025/02/20/Lecture-6-Oversampling-and-Sigma-Delta-ADCs.html#high-resolution-fom]

Walden FoM unit: J/conv-step

For Scherier FoM (DR, SNDR)

Offset & Gain Error

Kwantae Kim, Integrated Analog Systems D - Lecture 10 (ADC) [https://youtu.be/IEdbLNJb9wQ]

Testing

Kent H. Lundberg "Analog-to-Digital Converter Testing" [https://www.mit.edu/~klund/A2Dtesting.pdf]

Tai-Haur Kuo, Da-Huei Lee "Analog IC Design: ADC Measurement" [http://msic.ee.ncku.edu.tw/course/aic/202309/ch13%20(20230111).pdf] [http://msic.ee.ncku.edu.tw/course/aic/aic.html]

ESE 6680: Mixed Signal Design and Modeling "Lec 20: April 10, 2023 Data Converter Testing" [https://www.seas.upenn.edu/~ese6680/spring2023/handouts/lec20.pdf]

Degang Chen. "Distortion Analysis" [https://class.ece.iastate.edu/djchen/ee435/2017/Lecture25.pdf]

TODO 📅

ADCToolbox

L. Jie and Z. Zhang. ADCToolbox [https://github.com/Arcadia-1/ADCToolbox]

SNR vs NSD — full-scale noise spread over the Nyquist band

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## https://github.com/Arcadia-1/ADCToolbox/blob/main/python/src/adctoolbox/examples/02_spectrum/exp_s01_analyze_spectrum_simplest.py

import numpy as np
import matplotlib.pyplot as plt
from adctoolbox import analyze_spectrum, amplitudes_to_snr, snr_to_nsd

N_fft = 2**13
Fs = 100e6
Fin = 123/N_fft * Fs  # Coherent frequency
t = np.arange(N_fft) / Fs
A = 0.5
noise_rms = 10e-6
signal = 0.5 * np.sin(2*np.pi*Fin*t) + np.random.randn(N_fft) * noise_rms

# --- My own manual cross-check (not in exp_s01_analyze_spectrum_simplest.py) ---
# Hand-derived from first principles to sanity-check the amplitudes_to_snr /
# snr_to_nsd helpers below:
#   SNR = 10*log10( signal_power / noise_power ) = 10*log10( (A^2/2) / noise_rms^2 )
#   NSD = -SNR - 10*log10(Fs/2)  (full-scale noise spread over the Nyquist band)
snr_theroretical = 10*np.log10(A**2/2/noise_rms**2)
print(f"Theoretical SNR: {snr_theroretical:.2f} dB")
nsd_theoretical = -snr_theroretical - 10*np.log10(Fs/2)
print(f"Theoretical NSD: {nsd_theoretical:.2f} dBFS/Hz")
# --- end of my addition ---

snr_ref = amplitudes_to_snr(sig_amplitude=A, noise_amplitude=noise_rms)
nsd_ref = snr_to_nsd(snr_ref, fs=Fs, osr=1)

result = analyze_spectrum(signal, fs=Fs)

print(f"\n[setting] Noise RMS=[{noise_rms*1e6:.2f} uVrms], Theoretical SNR=[{snr_ref:.2f} dB], Theoretical NSD=[{nsd_ref:.2f} dBFS/Hz]")
print(f"[results] ENoB=[{result['enob']:.2f} b], SNDR=[{result['sndr_dbc']:.2f} dB], SFDR=[{result['sfdr_dbc']:.2f} dB], SNR=[{result['snr_dbc']:.2f} dB], NSD=[{result['nsd_dbfs_hz']:.2f} dBFS/Hz]\n")

plt.show()

# Theoretical SNR: 90.97 dB
# Theoretical NSD: -167.96 dBFS/Hz

# [setting] Noise RMS=[10.00 uVrms], Theoretical SNR=[90.97 dB], Theoretical NSD=[-167.96 dBFS/Hz]
# [results] ENoB=[14.82 b], SNDR=[90.99 dB], SFDR=[116.37 dB], SNR=[91.25 dB], NSD=[-168.24 dBFS/Hz]

reference

Aaron Buchwald, ISSCC2010 T1: "Specifying & Testing ADCs"

Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in ADCs

Boris Murmann, ISSCC2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications

—， ISSCC2012 SC3: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications

—， A/D Converter Figures of Merit and Performance Trends

Quantization Noise

Quantization Error

Notice \(e_q\in (0, \Delta)\) and its average is \(\Delta/2\). To calculate SNDR, DC component shall be excluded

Don't confuse resolution \(\Delta\) with Bounded Quantization Noise \(-\Delta/2 \sim \Delta/2\)

Quantization Noise Spectrum

Quantization noise is less with higher resolution as the input range is divided into a greater number of smaller ranges

This error can be considered a quantization noise with RMS

ADC Input Noise

Walt Kester, ADC Input Noise: The Good, The Bad, and The Ugly­. Is No Noise Good Noise? [link] [pdf]

—, MT-004: The Good, the Bad, and the Ugly Aspects of ADC Input Noise-Is No Noise Good Noise? [https://www.analog.com/media/en/training-seminars/tutorials/mt-004.pdf]

Understanding ADC Noise for Small and Large Signal Inputs for Receiver Applications [https://www.analog.com/en/resources/technical-articles/understanding-adc-noise-for-small-and-large-signal-inputs-for-receiver-applications.html]

The LSB determines the ADC code resolution, but the minimum reliably detectable input voltage is determined by the total noise floor, including quantization noise

[https://share.google/aimode/aA1V4uj3GofKbBojl]

ADC quantization noise is considered a "deterministic error" rather than random thermal noise because it correlates with the input signal, creating a saw-tooth error waveform rather than random Gaussian noise. While it cannot be reduced by averaging a static signal, it can be reduced through averaging if the signal is oversampled, or if dither (random noise) is added to decorrelate it.

Quantization is NOT Noise

N. Blachman, "The intermodulation and distortion due to quantization of sinusoids," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 33, no. 6, pp. 1417-1426, December 1985 [https://sci-hub.st/10.1109/TASSP.1985.1164729]

Carsten Wulff, Oversampling and Sigma-Delta ADCs [https://analogicus.com/aic2026/oversampling_and_sigma-delta_adcs] [video] [slides]

N. Blachman, "The intermodulation and distortion due to quantization of sinusoids," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 33, no. 6, pp. 1417-1426, December 1985

The quantization noise is an infinite sum of input signal odd harmonics, where the amplitude of the harmonics is determined by a sum of a Bessel function

"Quantization noise is white", because for a high number of bits, it looks white in the FFT

The quantization noise is odd harmonics of the input signal [Gist link]

[Gist link]

Sampling Noise in ADC

Kwantae Kim, Integrated Analog Systems D - Lecture 12 (ADC) [https://youtu.be/NkSitVkPNig]

In the power domain, \(\color{red}v_{nS,RMS}/3 \lt \sigma_{q,RMS}\) ensures that sampling noise power is nearly an order of magnitude smaller than the quantization noise

ADC SNR & clock jitter

Akkaya, A. (2021). High-Speed ADC Design and Optimization for Wireline Links (Publication No. 8453) [PhD thesis, EPFL; Supervised by Y. Leblebici]. [https://doi.org/10.5075/epfl-thesis-8453]

CC Chen, Why Absolute Jitter Matters for ADCs & DACs? [https://youtu.be/jBgDDFFDq30]

Thomas Neu, TIPL 4704. Jitter vs SNR for ADCs [https://www.ti.com/content/dam/videos/external-videos/en-us/2/3816841626001/5529003238001.mp4/subassets/TIPL-4704-Jitter-vs-SNR.pdf]

Walt Kester , MT-007: Aperture Time, Aperture Jitter, Aperture Delay Time [https://www.analog.com/media/en/training-seminars/tutorials/MT-007.pdf]

cyclostationary random process

\[\begin{align} \text{SNR}_\text{ADC}[\text{dB}] &= -20\cdot \log \sqrt{\left(10^{-\frac{\text{SNR}_\text{Quantization Noise}}{20}}\right)^2 + \left(10^{-\frac{\text{SNR}_\text{Jitter}}{20}}\right)^2} \\ &= -10\cdot \log \left(\left(10^{-\frac{\text{SNR}_\text{Quantization Noise}}{20}}\right)^2 + \left(10^{-\frac{\text{SNR}_\text{Jitter}}{20}}\right)^2\right) \\ &= -10\cdot \log \left(\left(10^{-\frac{10\log(\frac{3\times2^{2N}}{2})}{20}}\right)^2 + \left(10^{-\frac{-20\log{(2\pi f_\text{in}\sigma_\text{jitter})}}{20}}\right)^2\right) \\ &= -10\cdot \log \left( \frac{2}{3\times 2^{2N}} + (2\pi f_\text{in}\sigma_\text{jitter})^2 \right) \end{align}\]

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import numpy as np
import matplotlib.pyplot as plt

N = 12  # ADC bit
fin = 100e6 # the frequency of the sinusoidal input signal
jrms = np.linspace(0, 10, 1000)*1e-12 #ps

# ADC (SNR) with Quantization Noise & Jitter degradation
SNR_ADC = -10 * np.log10(10**(-np.log10(3*2**(2*N)/2)) + (2*np.pi*fin*jrms)**2)
ENOB = (SNR_ADC - 1.76) / 6.02

plt.plot(jrms*1e12, ENOB, label='100 MHZ input')
plt.plot([0, 10], [12, 12], '--', label='12-bit limit')
plt.plot([0, 10], [6, 6], '--', label='6-bit limit')

plt.xscale('linear')
plt.xlim([0, 10])
plt.ylim([5, 15])
plt.xlabel('RMS Jitter (ps)')
plt.ylabel('Effective Number of Bits (ENOB')
plt.grid(which='both')
plt.title('ENOB vs. RMS Clock Jitter (100 MHz)')
plt.legend()
plt.show()

Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data Converters. July, 2006 [pdf]

Chembian Thambidurai, "SNR of an ADC in the presence of clock jitter" [https://www.linkedin.com/posts/chembiyan-t-0b34b910_adcsnrjitter-activity-7171178121021304833-f2Wd/]

Unlike the quantization noise and the thermal noise, the impact of the clock jitter on the ADC performance depends on the input signal properties like its PSD

The error between the ideal sampled signal and the sampling with clock jitter can be treated as noise and it results in the degradation of the SNR of the ADC

For sinusoid input:

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import numpy as np
import matplotlib.pyplot as plt

ENOB = 8
fin = np.logspace(8, 11, 60)

# quantization noise: SNR = 6.02*ENOB + 1.76 dB
Ps_PnQ = 10**((6.02*ENOB + 1.76)/10)
PnQ = 1/Ps_PnQ

# jitter noise: SNR = 6 - 20log10(2*pi*fin*Jrms) dB @ref. Chembiyan T
Jrms_list = [25e-15, 50e-15, 100e-15, 250e-15, 500e-15, 1000e-15]
for Jrms in Jrms_list:
    # Ps_PnJ_lcl = 10**((6-20*np.log10(2*np.pi*fin*Jrms))/10)     # ref. Chembiyan T
    Ps_PnJ_lcl = 10**((0 - 20 * np.log10(2 * np.pi * fin * Jrms)) / 10)  # ref. Nicola Da Dalt
    PnJ_lcl = 1/Ps_PnJ_lcl
    SNR_lcl = 10*np.log10(1/(PnQ+PnJ_lcl))
    plt.plot(fin, SNR_lcl, label=r'$\sigma_{jitter}$'+'='+str(int(Jrms*1e15))+'fs')

plt.xscale('log')
plt.ylim([0, 55])
plt.xlabel(r'$f_{in}$ [Hz]')
plt.ylabel(r'SNR [dB]')
plt.grid(which='both')
# plt.title(r'ref. Chembiyan T')
plt.title(r'ref. Nicola Da Dalt')
plt.legend()
plt.show()

K. Tyagi and B. Razavi, "Performance Bounds of ADC-Based Receivers Due to Clock Jitter," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 5, pp. 1749-1753, May 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/KT_TCAS_2023.pdf]

N. Da Dalt, M. Harteneck, C. Sandner and A. Wiesbauer, "On the jitter requirements of the sampling clock for analog-to-digital converters," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002 [https://sci-hub.se/10.1109/TCSI.2002.802353]

M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of high-speed sampling systems," in IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, Feb. 1990 [https://sci-hub.se/10.1109/4.50307]

Akkaya, A. (2021). High-Speed ADC Design and Optimization for Wireline Links (Publication No. 8453) [PhD thesis, EPFL; Supervised by Y. Leblebici]. [https://doi.org/10.5075/epfl-thesis-8453]

待学芯. ADC量化结果反推采样时钟抖动（Jitter） [https://mp.weixin.qq.com/s/55xfVQMe_N8zUGpI8ZvmsQ]

—. 关于时钟抖动(Jitter)与ADC的一些讨论 [https://mp.weixin.qq.com/s/GW1keHhfq7zrd036lyG0CQ]

DAC SNR & clock jitter

Boris Murmann ISSCC 2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [pdf]

S. Kim, K. -Y. Lee and M. Lee, "Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2832-2841, Sept. 2018 [https://sci-hub.se/10.1109/TCSI.2018.2821198]

Martin Clara. High-Performance D/A-Converters - Application to Digital Transceivers, 2013 [pdf]

Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data Converters. July, 2006 [pdf]

ampling Jitter Effects for ADC/DAC

• In both DAC or ADC cases, doubling the timing jitter doubles the noise level
• Also, doubling the frequency or amplitude doubles the jitter induced noise - SNR is not improved

ADC Linearity (DNL/INL)

missing code

TODO 📅

• Endpoint method
• BestFit method

INL/DNL Measurements for High-Speed Analog-to Digital Converters (ADCs) [https://picture.iczhiku.com/resource/eetop/sYKTSqLfukeHSmMB.pdf]

Code Density Test

Apply a linear ramp to ADC input

Jungwirth, Patrick. Sampling Theory and Analog-to-Digital Conversion. Independently published, 2018.

DAC Linearity (DNL/INL)

The worst INL of three DAC Architecture is same

DAC DNL

One difference between ADC and DAC is that DAC DNL can be less than -1 LSB

In a DAC, DNL < -1LSB implies non-monotonicity

DAC INL

• \(A = \sum_{j=1}^k I_j\), \(B=\sum_{j=k+1}^N I_j\)
• A and B are independent with \(\sigma_A^2 = k\sigma_u^2\) and \(\sigma_B^2=(N-k)\sigma_u^2\)

Therefore \[ \mathrm{Var}\left(\frac{X}{Y}\right)\approx \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{\mathrm{cov}(X,Y)}{kNI_u^2}\right) \] and \[\begin{align} \mathrm{cov}(X,Y) &= E[XY] - E[X]E[Y] = E[A(A+B)] - kNI_u^2 \\ &= E[A^2]+E[A]E[B] - kNI_u^2= \sigma_A^2+E[A]^2 + k(N-k)I_u^2 - kNI_u^2\\ &= k\sigma_i^2 + k^2I_u^2+ k(N-k)I_u^2 - kNI_u^2 \\ &= k\sigma_i^2 \end{align}\]

Finally, \[ \mathrm{Var}\left(\frac{X}{Y}\right)\approx \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{k\sigma_i^2}{kNI_u^2}\right) = \frac{k^2}{N^2}\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 \] i.e. \[ \boxed{\mathrm{Var(INL(k))} = k^2\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 = k\left(1- \frac{k}{N}\right)\sigma_u^2} \]

Standard deviation of INL is maximum at mid-scale (k=N/2)

INL/DNL analysis of current steering DAC

Spectral Metrics

SNR, SNDR (SINAD)

Understanding Key Parameters for RF-Sampling Data Converters White Paper (WP509) [https://docs.amd.com/v/u/en-US/wp509-rfsampling-data-converters]

ENOB

Qasim Chaudhari, On Analog-to-Digital Converter (ADC), 6 dB SNR Gain per Bit, Oversampling and Undersampling [https://wirelesspi.com/on-analog-to-digital-converter-adc-6-db-snr-gain-per-bit-oversampling-and-undersampling/]

The quantization noise power \(P_Q\) for a uniform quantizer with step size \(\Delta\) is given by \[ P_Q = \frac{\Delta ^2}{12} \] For a full-scale sinusoidal input signal with an amplitude equal to \(V_{FS}/2\), the input signal is given by \(x(t) = \frac{V_{FS}}{2}\sin(\omega t)\)

Then input signal power \(P_s\) is \[ P_s = \frac{V_{FS}^2}{8} \] Therefore, the signal-to-quantization noise ratio (SQNR) is given by \[ \text{SQNR} = \frac{P_s}{P_Q} = \frac{V_{FS}^2/8}{\Delta^2/12}=\frac{V_{FS}^2/8}{V_{FS}^2/(12\times 2^{2N})} = \frac{3\times 2^{2N}}{2} \] where \(N\) is the number of quantization bits

When represented in dBs \[ \text{SQNR(dB)} = 10\log(\frac{P_s}{P_Q}) = 10\log(\frac{3\times 2^{2N}}{2})= 20N\log(2) + 10\log(\frac{3}{2})= 6.02N + 1.76 \]

the maximum achievable SNR of N-bit ADC — theoretical SNR limit

Dan Boschen, GRCon25: Quantifying Signal Quality: Practical Tools for High-Fidelity Waveform Analysis

[linkedin GRCon25]

SDR, THD

Understanding Key Parameters for RF-Sampling Data Converters White Paper (WP509) [https://docs.amd.com/v/u/en-US/wp509-rfsampling-data-converters]

Walt Kester. Evaluating High Speed DAC Performance [https://www.analog.com/media/en/training-seminars/tutorials/mt-013.pdf]

via other definition

THD: signal to distortion

SINAD: noise and distortion to signal

SFDR & INL

Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input signal frequency

Dynamic Range (DR)

Noise Spectral Density (NSD)

Understanding Key Parameters for RF-Sampling Data Converters White Paper (WP509) [https://docs.amd.com/v/u/en-US/wp509-rfsampling-data-converters]

Spectral Leakage

Two ways to deal with spectral leakage: Ensure integer number of periods or Windowing

Coherent Sampling

Choosing M/N non-prime repeats the signal quantization periodically and fewer quantization steps are measured. The quantization repeats periodically and creates a line spectrum that can obscure real frequency lines (e.g. the red lines in the images below, created by non-linearities of the ADC).[https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple]

\[ \frac{f_{\text{in}}}{f_{\text{s}}}=\frac{M_C}{N_R} \]

• \(f_\text{in}\) and \(f_s\) must be incommensurate (\(f_s/f_\text{in}\) is irrational number. btw, co-prime is sufficient but not necessary)

• \(M_C\) and \(N_R\) must be co-prime

• Samples must include integer # of cycles of input signal

An irreducible ratio ensures identical code sequences not to be repeated multiple times.

Given that \(\frac{M_C}{N_R}\) is irreducible, and \(N_R\) is a power of 2, an odd number for \(M_C\) will always produce an irreducible ratio

Assuming there is a common factor \(k\) between \(M_C\) and \(N_R\), i.e. \(\frac{M_C}{N_R}=\frac{k M_C'}{k N_R'}\)

The samples (\(n\in[1, N_R]\))

\[ y[n] = \sin\left( \omega_{\text{in}} \cdot t_n \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_s} \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_{\text{in}}}\frac{M_C}{N_R} \right) = \sin\left( 2\pi n\frac{M_C}{N_R} \right) \]

Then

\[ y[n+N_R'] = \sin\left( 2\pi (n+N_R')\frac{M_C}{N_R} \right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{M_C}{N_R}\right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{kM_C'}{kN_R'} \right) = \sin\left( 2\pi n \frac{M_C}{N_R}\right) \]

So, the samples is repeated \(\color{red}y[n] = y[n+N_R']\)

\(N_R\) & \(M_C\) irreducible ratio (mutually prime)

• Periodic sampling points result in periodic quantization errors
• Periodic quantization errors result in harmonic distortion

GCD(2048, 67)=1

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N = 2048;
cycles = 67;
fs = 1000;
fx = fs*cycles/N;
LSB = 2/2^10;
%generate signal, quantize (mid-tread) and take FFT
xc = cos(2*pi*fx/fs*[0:N-1]);
x = round(xc/LSB)*LSB;
s = abs(fft(x));
s = s(1:end/2)/N*2;
% calculate SNR
sigbin = 1 + cycles;
noise = [s(1:sigbin-1), s(sigbin+1:end)];
snr = 10*log10( s(sigbin)^2/sum(noise.^2) );

% frequency vector
f = [0:N/2-1]/N;
subplot(1,3,1)
stem(f, s);
 
% some FFT bins for "noise" to be exactly zero, empty plot
subplot(1,3,2)
plot(f, 20*log10(s))

% Use a small offset to avoid -Inf
subplot(1,3,3)
plot(f, 20*log10(s + 1e-6))
ylim([-120, 0])

Periodic Quantization Noise if N and cycles are not mutually prime, i.e. cycles=64 then GCD(2048, 64)=64, then \(N_R' = 2048/64=32\), so quantization noise manifests as odd harmonics \(n/32\mid n = 2k + 1, k \in \mathbb{Z}\) because of Half Wave Symmetry

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N = 2048;
cycles = 64;
fs = 1000;
fx = fs*cycles/N;
LSB = 2/2^10;
%generate signal, quantize (mid-tread) and take FFT
xc = cos(2*pi*fx/fs*[0:N-1]);
x = round(xc/LSB)*LSB;

% frequency vector
f = [0:N/2-1]/N;
nq = x - xc;
NTn = N / gcd(N, cycles);

subplot(2,1,1)
plot(nq(1:NTn/2), '-s')
hold on
plot(nq(1+NTn/2:NTn), '-o')
xticks(1:1:16); grid on

sn  = abs(fft(nq));
sn = sn(1:end/2)/N*2;
subplot(2,1,2)
plot(f, 20*log10(sn))

Using FFT in Cadence Spectre [https://www.eecis.udel.edu/~vsaxena/courses/ece614/f14/Homeworks/fft_calculation.pdf]

Hideo Okawara's Mixed Signal Lecture Series, DSP-Based Testing - Fundamentals 6 - Spectrum Analysis – FFT [https://www3.advantest.com/documents/11348/8c5e06b8-85b8-407d-b253-b671ca9ac85c]

—, DSP-Based Testing - Fundamentals 7 - Coherent Condition [https://www3.advantest.com/documents/11348/7f5f00bb-f5f0-41da-b154-fc1d974ad201]

Kwantae Kim, ELEC-E3530 [https://github.com/KwantaeKim/ELEC-E3530/blob/main/CAD8.ipynb]

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import numpy as np
from matplotlib.ticker import EngFormatter

def coherent_sampling(fin, Fs, N):
    """
    Returns the adjusted input frequency for coherent sampling.

    Parameters:
        fin  : input frequency (Hz)
        Fs   : sample rate (Hz)
        N    : number of samples

    Returns:
        Adjusted fin (Hz) such that M/N = fin/Fs, where M is the nearest prime to N*fin/Fs.
    """
    x = int(np.ceil(N * fin / Fs))
    primes = [n for n in range(2, x*2) if all(n % i for i in range(2, n))]
    M = primes[np.argmin(np.abs(np.array(primes) - x))]
    return Fs * M / N

fmt = EngFormatter(places=6)
print(f"Adjusted f_in: {fmt(coherent_sampling(10, 100, 2**6))}Hz")

# adjusted f_in: 10.937500Hz

Midrise and Midtread Quantizers

\(\Gamma_x\) is no-overload range

Top-Plate vs Bottom-Plate Sampling

[https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf]

Bottom-Plate Sampling

Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling

The capacitor voltage is defined as

\[ V_C = V_{\text{out}}-V_X \]

Before \(M_2\) turns off, \(M_1\) and \(M_2\) are both ON, so approximately

\[ V_{\text{out}}=V_{\text{in}},\qquad V_X=0 \]

and therefore

\[ V_C=V_{\text{in}} \]

When \(M_2\) turns off first, the slide writes

\[ V_C=V_{\text{in}}+\frac{\Delta Q_2}{C} \]

At this moment \(M_1\) is still ON, so the top plate is still held at

\[ V_{\text{out}}\approx V_{\text{in}} \]

Hence

\[\begin{aligned} V_X &=V_{\text{out}}-V_C\\ &=V_{\text{in}} -\left(V_{\text{in}}+\frac{\Delta Q_2}{C}\right)\\ &=\boxed{-\frac{\Delta Q_2}{C}}. \end{aligned}\]

[https://indico.cern.ch/event/1064521/contributions/4475393/attachments/2355793/4078773/esi_sampling_and_converters2022.pdf]

EE 435 Spring 2024 Analog VLSI Circuit Design - Switched-Capacitor Amplifiers Other Integrated Filters, https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf

Top-Plate Sampling

TODO 📅

Maintain constant common-mode during conversion

D. Pfaff et al., "7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024 [https://iccircle.com/static/upload/img20240529101747.pdf]

—, "A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited)," 2025 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-8, doi: 10.1109/CICC63670.2025.10983461.

E. Swindlehurst et al., "An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch," IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, 2021, [https://sci-hub.se/10.1109/JSSC.2021.3057372]

Tracking Settling Accuracy

Finite Acquisition Time - Consider a sinusoidal input

\[\begin{align} V_\text{in}(t)=\cos(\omega t+\theta) & \overset{\mathcal{L}}{\Rightarrow} \frac{s\cos \theta-\omega \sin \theta}{s^2+\omega^2} \\ h(t) & \overset{\mathcal{L}}{\Rightarrow} \frac{\frac{1}{\tau}}{s+\frac{1}{\tau}} \end{align}\]

Then,

\[\begin{align} V_\text{out}(s) &= V_\text{in}(s)\cdot H(s) \\ &= \frac{s\cos \theta-\omega \sin \theta}{s^2+\omega^2} \cdot \frac{\frac{1}{\tau}}{s+\frac{1}{\tau}} \\ &= \frac{A}{s+\frac{1}{\tau}} + \frac{Bs+C}{s^2+\omega^2} \end{align}\]

Obtain,

\[ A = -\frac{\cos(\theta - \phi)}{\sqrt{ \omega^2\tau ^2 +1}} \qquad\qquad B = -A \qquad\qquad C = -\frac{\omega \sin(\theta - \phi)}{\sqrt{\omega^2\tau ^2 +1}} \]

That is \[ \boxed{V_\text{out}(s) = -\frac{\cos(\theta - \phi)}{\sqrt{\omega^2\tau ^2 +1}} \frac{1}{s+\frac{1}{\tau}} + \frac{1}{\sqrt{\omega^2\tau ^2 +1}}\frac{s\cos(\theta - \phi) - \omega \sin(\theta - \phi)}{s^2+\omega^2}} \]

where \(\phi = \arctan(\omega \tau)\)

The relation \(V_\text{out}(s) = H(s)\,V_\text{in}(s)\) is the zero-state response only. The transfer function is defined under the assumption \(V_\text{out}(0^-) = 0\), so you can't recover the natural response from it. You have to go back one step, to the differential equation.

For the RC (track) network with \(\tau = RC\):

\[ \tau \dot{V}_\text{out} + V_\text{out} = V_\text{in} \]

Transform with the full derivative rule \(\mathcal{L}\{\dot{V}_\text{out}\} = s V_\text{out}(s) - V_0\), where \(V_0 \equiv V_\text{out}(0^-)\) (the capacitor voltage is continuous, so \(0^-\) and \(0^+\) agree): \[ \tau\big(s V_\text{out}(s) - V_0\big) + V_\text{out}(s) = V_\text{in}(s) \]

\[ \boxed{\;V_\text{out}(s) = \underbrace{\frac{V_\text{in}(s)}{\tau s + 1}}_{\text{zero-state}} + \underbrace{\frac{\tau V_0}{\tau s + 1}}_{\text{zero-input}} = H(s)\,V_\text{in}(s) + \frac{V_0}{s + \frac{1}{\tau}}\;} \]

Then the Complete Laplace Expression is \[ \boxed{V_\text{out}(s) = -\frac{\cos(\theta - \phi)}{\sqrt{\omega^2\tau ^2 +1}} \frac{1}{s+\frac{1}{\tau}} + \frac{1}{\sqrt{\omega^2\tau ^2 +1}}\frac{s\cos(\theta - \phi) - \omega \sin(\theta - \phi)}{s^2+\omega^2} + \frac{V_\text{out}(0)}{s + \frac{1}{\tau}} } \] The Total Time-Domain Solution \[ \boxed{V_{\text{out}}(t) = \underbrace{V_{\text{out}}(0)e^{-\frac{t}{\tau}}}_{\text{Pure Natural Response}} + \underbrace{\frac{1}{\sqrt{\omega^2\tau^2 + 1}} \left[ \cos(\omega t + \theta - \phi) - \cos(\theta - \phi) e^{-\frac{t}{\tau}} \right]}_{\text{Forced Response (Transient + Steady-State)}} } \] And grouped by transient vs. steady-state components: \[ \boxed{V_{\text{out}}(t) = \underbrace{\left[ V_{\text{out}}(0) - \frac{\cos(\theta - \phi)}{\sqrt{\omega^2\tau^2 + 1}} \right] e^{-\frac{t}{\tau}}}_{\text{Total Transient Response}} + \underbrace{\frac{\cos(\omega t + \theta - \phi)}{\sqrt{\omega^2\tau^2 + 1}}}_{\text{Steady-State Response}}} \]

Tracking Nonlinearity

Wei Yu, Subhajit Sen and B. H. Leung, "Distortion analysis of MOS track-and-hold sampling mixers using time-varying Volterra series," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 2, pp. 101-113, Feb. 1999 [https://sci-hub.ru/10.1109/82.752910]

B. Murmann, EE315B VLSI-Data-Conversion-Circuits [https://dl.sabzdanesh.com/Electronic/VLSI-Data-Conversion-Circuits_(WWW.SabzElco.IR).pdf]

\[\begin{align} HD_2 &\approx \frac{1}{2}\omega C V_m \frac{\mathcal{d} R_{on}}{\mathcal{d}v_{in}}\bigg\rvert_{v_{in}=0}=\frac{1}{2}\omega C V_m\frac{R_{ON}}{V_{OV}} = \frac{1}{2}\frac{\omega}{\omega_c}\frac{V_m}{V_{OV}} \\ HD_3 &\approx \frac{1}{4}\omega C V_m^2 \frac{\mathcal{d}^2 R_{on}}{\mathcal{d}v_{in}^2}\bigg\rvert_{v_{in}=0}=\frac{1}{4}\omega C V_m^2\frac{R_{ON}}{V_{OV}^2} = \frac{1}{2}\frac{\omega}{\omega_c}\left(\frac{V_m}{V_{OV}}\right)^2 \end{align}\]

where \(V_{OV}=V_{DD}-V_{IN}-V_t\), \(R_{ON}=\frac{1}{\mu C_{ox}W/LV_{OV}}\) and \(\omega_c=1/R_{ON}C\)

Even-order distortion products cancel in perfectly symmectrical circuits; But phase and amplitude imbalances lead to finite \(HD_2\) in practice

DAC Settling Accuracy

In a SAR conversion the DAC doesn't move by full scale — the MSB trial is the largest single step, and it is exactly half of full scale. Subsequent trials step by \(V_{FS}/4\), \(V_{FS}/8\), … So the MSB transition (\(\color{red}0 \to V_{FS}/2\)) is the worst case, and if it settles in the allotted per-bit time, every later trial does too.

The accuracy criterion

The settling error must stay below half an LSB, where \(\text{LSB} = V_{FS}/2^{n}\):

\[ \frac{V_{FS}}{2} - V_{DAC}(t_{settle}) \;\le\; \frac{1}{2}\cdot\frac{V_{FS}}{2^{n}} = \frac{V_{FS}}{2^{\,n+1}} \]

Rearranged \[ V_{DAC}(t_{settle}) \ge V_{FS}\left(\frac{1}{2}-\frac{1}{2^{n+1}}\right) \]

Solving for the time \[ \frac{V_{FS}}{2}e^{-t_{settle}/\tau} \le \frac{V_{FS}}{2^{\,n+1}} \;\Longrightarrow\; e^{-t_{settle}/\tau} \le 2^{-n} \]

\[ \boxed{\;t_{settle} \ge n\,\tau\ln 2 \approx 0.693\,n\,\tau\;} \]

Redundancy

Max tolerance of comparator offset is \(\pm V_{FS}/4\)

1. \(b_j\) error is \(\pm 1\)
2. \(b_{j+1}\) error is \(\pm 2\) , wherein \(b_{j+1}\): \(0\to 2\) or \(1\to -1\)

i.e. complementary analog and digital errors cancel each other, \(V_o +\Delta V_{o}\) should be in over-/under-range comparators (\(-V_{FS}/2 \sim 3V_{FS}/2\))

\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{V_{out,j}+\Delta V_{out,j}}{2} \\ V_{in,{j+1}} &= (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \end{align}\]

with \(V_{in,j+1} = V_{out,j}+\Delta V_{out,j}\)

\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2} \left\{ (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \right\} \\ &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2}(b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2}+ \frac{1}{2}\frac{V_{in,j+2}}{2} \\ &=\tilde{b_j} \cdot \frac{V_{FS}}{2}+ \tilde{b_{j+1}}\cdot \frac{V_{FS}}{4}+ \frac{1}{4}V_{in,j+2} \end{align}\]

where \(b_j\) is 1-bit residue without redundancy and \(\tilde{b_j}\) is redundant bits

Uniform Sub-Radix-2 SAR ADC

Minimal analog complexity, no additional decoding effort

Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." (2013). [https://dspace.mit.edu/bitstream/handle/1721.1/82177/861702792-MIT.pdf]

Kuttner, Franz. "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS." 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 1 (2002): 176-177 vol.1. [https://sci-hub.se/10.1109/ISSCC.2002.992993]

T. Ogawa, H. Kobayashi, et. al., "SAR ADC Algorithm with Redundancy and Digital Error Correction." IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A (2010): 415-423. [paper, slides]

B. Murmann, “On the use of redundancy in successive approximation A/D converters,” International Conference on Sampling Theory and Applications (SampTA), Bremen, Germany, July 2013. [https://www.eurasip.org/Proceedings/Ext/SampTA2013/papers/p556-murmann.pdf]

Krämer, M. et al. (2015) High-resolution SAR A/D converters with loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].

sarthak, "Visualising redundancy in a 1.5 bit pipeline ADC“ [https://electronics.stackexchange.com/a/523489/233816]

Thermometer to Binary encoder

Pipeline ADC

CMP reference voltage is 0.5vref, DAC output is 0.5vref or 0

residual error \[ V_{r,n} = (V_{r,n-1}-\frac{1}{2}b_{n})\cdot 2 \] and \(V_{r,-1}=V_i\) \[ V_{r,n-1} = 2^{n}V_i -\sum_{k=0}^{n-1}2^{n-k-1}b_k = 2^{n}\left(V_i - \sum_{k=0}^{n-1}\frac{b_k}{2^{k+1}}\right) \]

here, \(b_0\) is first stage and MSB

It divides the process into several comparison stages, the number of which is proportional to the number of bits

Due to the pipeline structure of both analog and digital signal path, inter-stage residue amplification is needed which consumes considerable power and limits high speed operation

Vishal Saxena, "Pipelined ADC Design - A Tutorial"[https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20NonIdealities%20Slides%20v1_0.pdf] [https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20Slides%20v1_2.pdf]

Bibhu Datta Sahoo, Analog-to-Digital Converter Design From System Architecture to Transistor-level [http://smdpc2sd.gov.in/downloads/IGF/IGF%201/Analog%20to%20Digital%20Converter%20Design.pdf]

Bibhu Datta Sahoo, Associate Professor, IIT, Kharagpur, [https://youtu.be/HiIWEBAYRJY]

Multiplying DACs (MDAC)

Phase 1: sample the input

• \(C_S\) has \(V_{\text{in}}\) on its left plate and 0 V on its right plate, so it stores the input as charge.
• Both ends of \(C_F\) are grounded, resetting its voltage to zero.
• The small ADC samples the same input and determines a digital code.

At the end of sampling:

\[ Q_{x,\text{sample}}=-C_SV_{\text{in}} \]

Phase 2: subtract and amplify

• Switching (C_S)’s left plate from (V_{}) to zero disturbs node (x).
• Switching the DAC bottom plate from zero to (V_D) produces an opposing disturbance.
• The amplifier changes (V_{}), through (C_F), to balance the remaining charge.

After amplification settles, both ends of \(C_S\) are approximately zero:

\[ Q_{x,\text{amp}}=-C_FV_{\text{out}}-C_{\text{DAC}}V_D \]

Equating them:

\[ \boxed{ V_{\text{out}} = \frac{C_S}{C_F}V_{\text{in}} - \frac{C_{\text{DAC}}}{C_F}V_D } \]

If \(C_S=C_{\text{DAC}}\), this becomes:

\[ \boxed{V_{\text{out}}=G(V_{\text{in}}-V_D)}, \qquad G=\frac{C_S}{C_F} \]

R-2R & C-2C

\(N_b\) bit binary + \(N_t\) bit thermometer DAC

\(N_b\) bit binary can be simplified with Thevenin Equivalent \[ V_B = \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_b-n}} \] with thermometer code

\[\begin{align} V_o &= V_B\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R}+\sum_{n=0}^{2^{N_t}-2}T_n\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R} \\ &= \frac{V_B}{2^{N_t}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \\ &= \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_t+N_b-n}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \end{align}\]

B. Razavi, "The R-2R and C-2C Ladders [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 10-15, Summer 2019 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2019.pdf]

4bit binary R2R DAC with Ru=1kOhm

RVB equivalent R

Binary-Weighted (BW) DAC

During \(\Phi_1\), all capacitor are shorted, the net charge at \(V_x\) is 0

During \(\Phi_2\), the charge at bottom plate of CDAC \[ Q_{DAC,btm} = \sum_{i=0}^{N-1}(b_i\cdot V_R - V_x)\cdot 2^{i}C_u = C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x \] the charge at the internal plate of integrator \[ Q_{intg} = V_x C_p + (V_x - V_o)2^NC_u \] and we know \(-V_x A = V_o\) and \(Q_{DAC,btm} = Q_{intg}\) \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x = V_x C_p + (V_x - V_o)2^NC_u \] i.e. \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i = (2^N-1)C_uV_x + V_x C_p + (V_x - V_o)2^NC_u \] therefore \[ -V_o = \frac{2^N C_u}{\frac{(2^{N+1}-1)C_u+C_p}{A}+2^NC_u}\sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right)\approx \sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right) \]

Midscale (MSB Transition) often is the largest DNL error

\(C_4\) and \(C_1+C_2+C_3\) are independent (can't cancel out) and their variance is two largest (\(16\sigma_u^2\), \(15\sigma_u^2\), ), the total standard deviation is \(\sqrt{16\sigma_u^2+15\sigma_u^2}=\sqrt{31}\sigma_u\)

reference

Maloberti, F. Data Converters. Dordrecht, Netherlands: Springer, 2007.

Ali, Ahmed M. A. High Speed Data Converters. The Institution of Engineering and Technology, 2016.

Razavi B. Analysis and Design of Data Converters. Cambridge University Press; 2025.

Aaron Buchwald, ISSCC2010 T1: "Specifying & Testing ADCs"

Ahmed M. A. Ali. CICC 2018: High Speed Pipelined ADCs: Fundamentals and Variants

John P. Keane, ISSCC2020 T5: "Fundamentals of Time-Interleaved ADCs"

Yun Chiu, ISSCC2023 T3: "Fundamentals of Data Converters" [https://personal.utdallas.edu/~yxc101000/courses/7327/handout/isscc2023_tutorial.pdf]

—， "Design and Calibration Techniques for SAR and Pipeline ADCs" [http://formation-old.in2p3.fr/microelectronique15/IN2P3_ADC.pdf]

—， Radiation-Tolerant SAR ADC Architecture and Digital Calibration Techniques [https://indico.cern.ch/event/385097/attachments/768706/1054353/CERN_May15.pdf]

—， Recent Advances in Multistep Nyquist ADC's [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Recent%20Advances%20in%20Nyquist%20rate%20ADCs.pdf]

Aaron Buchwald, ISSCC 2008 T2 Pipelined A/D Converters: The Basics

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis

Jan Mulder Broadcom. ISSCC2015 T5: High-Speed Current-Steering DACs

Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023)

V. Chen, "Tutorial: High-Speed Analog-to-Digital Converters," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, pp. 1-1, doi: 10.1109/ISSCC49661.2025.11076112.

S. Su, "Principles and Practices of High-Speed DAC Design: From Conversion Fundamentals to Layout-Aware Implementation," in IEEE Solid-State Circuits Magazine, vol. 18, no. 3, pp. 26-43, Summer 2026, doi: 10.1109/MSSC.2026.3704105

M. Gu, Y. Tao, Y. Zhong, L. Jie and N. Sun, "Timing-Skew Calibration Techniques in Time-Interleaved ADCs," in IEEE Open Journal of the Solid-State Circuits Society [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623]

everynanocounts. Memos on FFT With Windowing. URL: https://a2d2ic.wordpress.com/2018/02/01/memos-on-fft-with-windowing/

How to choose FFT depth for ADC performance analysis (SINAD, ENOB). URL:https://dsp.stackexchange.com/a/38201

Computation of Effective Number of Bits, Signal to Noise Ratio, & Signal to Noise & Distortion Ratio Using FFT. URL:https://cdn.teledynelecroy.com/files/appnotes/computation_of_effective_no_bits.pdf

Kester, Walt. (2009). Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor. URL:https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

T. C. Hofner: Dynamic ADC testing part I. Defining and testing dynamic ADC parameters, Microwaves & RF, 2000, vol. 39, no. 11, pp. 75-84,162

—: Dynamic ADC testing part 2. Measuring and evaluating dynamic line parameters, Microwaves & RF, 2000, vol. 39, no. 13, pp. 78-94

AN9675: A Tutorial in Coherent and Windowed Sampling with A/D Converters https://www.renesas.com/us/en/document/apn/an9675-tutorial-coherent-and-windowed-sampling-ad-converters

APPLICATION NOTE 3190: Coherent Sampling Calculator (CSC) https://www.stg-maximintegrated.com/en/design/technical-documents/app-notes/3/3190.html

Coherent Sampling (Very Brief and Simple) https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple

Signal Chain Basics #160: Making sense of coherent and noncoherent sampling in data-converter testing https://www.planetanalog.com/signal-chain-basics-160-making-sense-of-coherent-and-noncoherent-sampling-in-data-converter-testing/

Signal Chain Basics #104: Understanding noise in ADCs https://www.planetanalog.com/signal-chain-basics-part-104-understanding-noise-in-adcs/

Signal Chain Basics #101: ENOB Degradation Analysis Over Frequency Due to Jitter https://www.planetanalog.com/signal-chain-basics-part-101-enob-degradation-analysis-over-frequency-due-to-jitter/

Clock jitter analyzed in the time domain, Part 1, Texas Instruments Analog Applications Journal (slyt379), Aug 2010 https://www.ti.com/lit/an/slyt379/slyt379.pdf

Clock jitter analyzed in the time domain, Part 2 https://www.ti.com/lit/slyt389

Measurement of Total Harmonic Distortion and Its Related Parameters using Multi-Instrument [pdf]

Application Note AN-4: Understanding Data Converters' Frequency Domain Specifications [pdf]

Belleman, J. (2008). From analog to digital. 10.5170/CERN-2008-003.131. [pdf]

HandWiki. Coherent sampling [link]

Luis Chioye, TI. Leverage coherent sampling and FFT windows when evaluating SAR ADCs (Part 1) [link]

Coherent Sampling vs. Window Sampling | Analog Devices https://www.analog.com/en/technical-articles/coherent-sampling-vs-window-sampling.html

Understanding Effective Number of Bits https://robustcircuitdesign.com/signal-chain-explorer/understanding-effective-number-of-bits/

ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise? [https://www.analog.com/en/resources/analog-dialogue/articles/adc-input-noise.html]

Walt Kester, Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care [https://www.analog.com/media/en/training-seminars/tutorials/MT-001.pdf]

Dan Boschen, "How to choose FFT depth for ADC performance analysis (SINAD, ENOB)", [https://dsp.stackexchange.com/a/38201]

B. Razavi, "A Tale of Two ADCs - Pipelined Versus SAR" IEEE Solid-State Circuits Magazine, Volume. 7, Issue. 30, pp. 38-46, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15ADC.pdf)]

Dr. Tai-Haur Kuo (郭泰豪 教授) Analog IC Design (類比積體電路設計) [http://msic.ee.ncku.edu.tw/course/aic/aic.html]

Converter Passion for data-converter professionals sharing thoughts on ADCs and DACs [https://converterpassion.wordpress.com/]

Boris Murmann, EE315B VLSI Data Conversion Circuits, Autumn 2013

MPScholar Analog-to-Digital Converters (ADCs) [https://www.monolithicpower.com/en/learning/mpscholar/analog-to-digital-converters]

tomverbeure. List of Analog Devices Tutorials [https://tomverbeure.github.io/2021/02/15/Analog-Devices-Tutorials.html]

replica biasing

TODO 📅

noise in current mirror

Noise of ref MOS is amplified by the current mirror's gain

Due to M0 is biased by current source, we probe gate voltage instead of current

result browser of instance show noise contribution, which is same with noise summary

current mirror with source follower

source follower alleviate gate leakage impact on reference current

constant-gm

aka. Beta-multiplier reference

\(I_\text{out}\) is PTAT in case temperature coefficient of \(R_s\) is less than that of \(\mu_n\)

Body effect of M2

Boris Murmann, Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables

S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias Circuits," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022

S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver , May 2004

Why MOS in saturation ?

\(g_m\), \(g_\text{ds}\) at fixed \(V_\text{GS}\)

\(g_{ds}\) is constant in saturation region

in triode region \[ g_{ds} = \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS}) \]

Interestingly, \(g_m\) in the saturation region is equal to the inverse of \(R_\text{on}\) in the deep triode region.

\(g_m\), \(g_\text{ds}\) at fixed \(I_d\), \(V_G\)

In triode region \[ I_D = \frac{1}{2}\mu_nC_{ox}\frac{W}{L}[2(V_{GS}-V_{TH})V_{DS}-V_{DS}^2] \] where \(I_D\) and \(V_G\) is fixed

Then \(V_S\) can be expressed with \(V_D\), that is \[ V_S = V_{GT} - \sqrt{(V_{GT}-V_D)^2+V_{dsat}^2} \] where \(V_{GT}=V_G-V_{TH}\), \(V_{dsat}\) is \(V_{DS}\) saturation voltage \[ g_m = \mu_nC_{ox}\frac{W}{L}\left(V_D-V_{GT}+\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}\right) \] Then \[ \frac{\partial g_m}{\partial V_D} \propto 1 - \frac{V_{GT}-V_D}{\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}} \gt 0 \]

That is, \(g_m \propto V_D\)​

\[\begin{align} g_{ds} &= \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS}) \\ &= \mu_nC_{ox}\frac{W}{L}(V_{GT}-V_{D}) \end{align}\]

That is, \(g_{ds} \propto -V_D\)

Both gain and speed degrade once entering triode region, though Id is constant

Cascode MOS

The low threshold voltage of cascode MOS don't help decrease the minimum output voltage

Poor Man's Cascode

\[ V_{DS1} = V_{GS2} - V_{GS1} \qquad V_{GS1} = V_{OV1} + V_\text{th1} \] with $V_{GS2} - V_V_{DS1} $ \[ V_{GS2} - V_\text{th2} \lt V_{GS2} - V_{GS1} \to V_{GS1} \lt V_\text{th2} \to \color{green}\boxed{V_{OV1} \lt V_\text{th2} - V_\text{th1}} \]

Channel-length modulation

❗ There it not channel-length modulation in the triode region

\[\begin{align} I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\frac{\Delta L}{L}) \\ I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\lambda V_{DS}) \\ I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\frac{V_{DS}}{V_A}) \end{align}\]

where \(\frac{\Delta L}{L}=\lambda V_{DS}\) and \(V_A=\frac{1}{\lambda}\)

\(\lambda\) is channel length modulation parameter

\(V_A\), i.e. Early voltage is equal to inverse of channel length modulation parameter

The output resistance \(r_o\)

\[\begin{align} r_o &= \frac{\partial V_{DS}}{\partial I_D} \\ &= \frac{1}{\partial I_D/\partial V_{DS}} \\ &= \frac{1}{\lambda I_D} \\ &= \frac{V_A}{I_D} \end{align}\]

Due to \(\lambda \propto 1/L\), i.e. \(V_A \propto L\) \[ r_o \propto \frac{L}{I_D} \]

The output resistance is almost doubled using Stacked FET in saturation region

\(V_t\) and mobility \(\mu_{n,p}\) are sensitive to temperature

• \(V_t\) decreases by 2-mV for every 1\(^oC\) rise in temperature
• mobility \(\mu_{n,p}\) decreases with temperature

Overall, increase in temperature results in lower drain currents

current mirror mismatch

The current mismatch consists of two components.

• The first depends on threshold voltage mismatch and increases as the overdrive \((V_{GS} − V_t)\) is reduced.
• The second is geometry dependent and contributes a fractional current mismatch that is independent of bias point.

\[ \Delta I_D = g_m\cdot \Delta V_{TH}+I_D\cdot \frac{\Delta(W/L)}{W/L} \]

where mismatches in \(\mu_nC_{ox}\) are neglected

\[\begin{align} \Delta V_{TH} &= \frac{A_{VTH}}{\sqrt{WL}} \\ \frac{\Delta(W/L)}{W/L} &= \frac{A_{WL}}{\sqrt{WL}} \end{align}\]

summary:

Current mirror mismatch analysis

Art Zirger, Random Offset in CMOS IC Design [https://designers-guide.org/forum/Attachments/mismatch_presentation.pdf]

Another solution is to view the mirror branch as a whole

In source branch self mismatch \(\sigma_{vth,src} = \frac{A_{vt}}{\sqrt{2WL}}\) and mirror branch self-mismatch \(\sigma_{vth,mir} = \frac{A_{vt}}{\sqrt{2kWL}}\), then mutual mismatch is \[ \sigma_{vth} = \sqrt{\sigma_{vth,src}^2 + \sigma_{vth,mir}^2} = \sigma_{vth,src}\sqrt{1+\frac{1}{k}} \] mirror current variation \(\sigma_{I_k} = k g_m \sigma_{vth}\), relative variation of mirror current is \[ \frac{\sigma_{I_k}}{I_k} = \frac{k g_m \sigma_{vth}}{kI} = \frac{g_m \sigma_{vth,src}}{I}\sqrt{1+\frac{1}{k}}=\color{red}\frac{\sigma_{I}}{I}\sqrt{1+\frac{1}{k}} \]

Biasing current source and global variation Monte Carlo

iwl: biased by mirror

iwl_ideal: biased by vdc source, whose value is typical corner

For local variation, constant voltage bias (vb_const in schematic) help reduce variation from \(\sqrt{2}\Delta V_{th}\) to \(\Delta V_{th}\)

For global variation, all device have same variation, mirror help reduce variation by sharing same \(V_{gs}\)

1. global variation + local variation (All MC)

2. local variation (Mismatch MC)

3. global variation (Process MC)

We had better bias mos gate with mirror rather than the vdc source while simulating sub-block.

This is real situation due to current source are always biased by mirror and vdc biasing don't give the right result in global variation Monte Carlo simulation (542.8n is too pessimistic, 13.07p is right result)

Small gain theorem

Dr. Degang Chen, EE 501: CMOS Analog Integrated Circuit Design [https://class.ece.iastate.edu/djchen/ee501/2020/References.ppt]

For any given constant values of u and v, the constant values of variables that solve the the feed back relationship are called the operating points, or equilibrium points.

Operating points can be either stable or unstable.

An operating point is unstable if any or some small perturbation near it causes divergence away from that operating point.

If the loop gain evaluated at an operating point is less than one, that operating point is stable.

This is a sufficient condition

With \(m_{1\to 2} = 1\) \[ \text{Loop Gain} \simeq \frac{V_{BN}-V_{T2}}{V_{BN}-V_{T2} + V_R} \tag{$LG_0$} \] Assuming all MOS in strong inv operation, \(I\), \(V_{BN}\) and \(V_R\) is obtain \[\begin{align} I &= \frac{2\beta _1 + 2\beta _2 - 4\sqrt{\beta _1 \beta _2}}{R^2\beta _1 \beta _2} \\ V_{BN} &= V_{T2} + \frac{2}{R\beta _2}(1- \sqrt{\frac{\beta _2}{\beta _1}}) \\ IR &= \frac{2}{R}\left( \frac{1}{\sqrt{\beta_2}} - \frac{1}{\sqrt{\beta_1}} \right) \end{align}\]

Substitute \(V_{BN}\) and \(V_R\) of \(LG_0\) \[\begin{align} \text{Loop Gain} & \simeq \frac{1-\sqrt{\frac{\beta_2}{\beta_1}}}{\frac{\beta_2}{\beta_1} - 3\sqrt{\frac{\beta_2}{\beta_1}}+2} \\ &= \frac{1}{2-\sqrt{\frac{\beta_2}{\beta_1}}} \tag{$LG_1$} \end{align}\]

Alternative approach for Loop Gain

using derivation of large signal

❗❗❗ R should not be on the other side

Self-Biasing Cascode

reference

B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 6-16, Summer 2021, [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2021.pdf]

Shanthi Pavan, IIT Madras, India , ISSCC 2026: Circuit Insights Voltage and Current Reference Generation [https://youtu.be/i1bKJvtiXmY], [slides]

Correlated Double Sampling (CDS)

TODO 📅

Dynamic Element Matching (DEM)

TODO 📅

Galton, Ian. (2010). Why dynamic-element-matching DACs work. Circuits and Systems II: Express Briefs, IEEE Transactions on. 57. 69 - 74. 10.1109/TCSII.2010.2042131. [https://sci-hub.se/10.1109/TCSII.2010.2042131]

KHIEM NGUYEN. Analog Devices Inc, "Practical Dynamic Element Matching Techniques for 3-level Unit Elements" [https://picture.iczhiku.com/resource/eetop/shihEDaaoJjFdCVc.pdf]

E. Alvarez-Fontecilla, P. S. Wilkins and S. C. Rose, "Understanding High-Resolution Dynamic Element Matching DACs [Feature]," in IEEE Circuits and Systems Magazine, vol. 23, no. 4, pp. 34-43, Fourthquarter 2023

E. Alvarez-Fontecilla and P. S. Wilkins, "Linearity Through Democracy [Feature]," in IEEE Circuits and Systems Magazine, vol. 25, no. 1, pp. 58-69, Firstquarter 2025

Autozeroing

offset is sampled and then subtracted from the input

Measure the offset somehow and then subtract it from the input signal

low gain comparator

Residual Noise of Auto-zeroing

P. Bruschi, Dynamic techniques for the rejection of the offset and low frequency noise [https://docenti.ing.unipi.it/~a008309/mat_stud/MIXED/2023/Lecture_notes/Chap_2_2_Offset_Flicker_Reduction.pdf] [slides]

\[ \color{blue}\boxed{ v_{\rm out}(t)=v_t(t)+v_h(t) } \] where: \[ \boxed{ v_t(t):\ \text{track-phase noise, RC low-pass shaped} } \] and \[ \boxed{ v_h(t):\ \text{sampled/held } kT/C \text{ noise, pulse-shape sinc shaped} } \]

pnosie Noise Type: timeaverage

\(\Pi\)-Capacitor

\[\begin{align} (V_a-V_{a0})C_0 + (\overline{V_a - V_b} - \overline{V_{a0} - V_{b0}})C_1 &= \Delta Q_a \\ (V_b-V_{b0})C_0 + (\overline{V_b - V_a} - \overline{V_{b0} - V_{a0}})C_1 &= \Delta Q_b \end{align}\]

therefore we obtain \[\begin{align} V_a + V_b &= \frac{\Delta Q_a + \Delta Q_b}{C_0} + V_{a0} + V_{b0} \\ V_a - V_b &= \frac{\Delta Q_a - \Delta Q_b}{C_0+2C_1} + V_{a0} - V_{b0} \end{align}\] Then \[\begin{align} V_a &= \frac{\Delta Q_a(C_0+C_1)+\Delta Q_b C_1}{C_0(C_0+2C_1)} + V_{a0} \\ V_b &= \frac{\Delta Q_aC_1+\Delta Q_b (C_0+C_1)}{C_0(C_0+2C_1)} + V_{b0} \end{align}\]

rearrange the above equation \[\begin{align} V_a &= \frac{\Delta Q_a}{C_0} + \frac{\Delta Q_b-\Delta Q_a}{C_0(\frac{C_0}{C_1}+2)} + V_{a0} \\ V_b &= \frac{\Delta Q_b}{C_0} + \frac{\Delta Q_a-\Delta Q_b}{C_0(\frac{C_0}{C_1}+2)} + V_{b0} \end{align}\]

The difference between \(V_a\) and \(V_b\) \[ V_a - V_b = \frac{I_a-I_b}{C_0+2C_1}t + V_{a0} - V_{b0} \]

\(C_1\) save total capacitor area while retaining the same \(V_a - V_b\) due to \(\Delta I_{a,b}\), in comparison to \(C_0\)

at autozero phase \[\begin{align} I_{a0} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{a0} - V_{TH})^2 \\ I_{Rb} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{b0} - V_{TH})^2 \end{align}\]

then \[ \Delta I_0 = \frac{1}{2}(V_{a0} - V_{b0})(g_{m,a0}+g_{m,b0}) \] where \(g_{m,a0}+g_{m,b0} = \mu C_{OX}\frac{W}{L}(V_{a0}+V_{b0} - 2V_{TH})\)

at comparison phase \[\begin{align} I_{a1} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{a1} - V_{TH})^2 \\ I_{b1} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{b1} - V_{TH})^2 \end{align}\]

then \[ \Delta I_1 = \frac{1}{2}(V_{a1} - V_{b1})(g_{m,a1}+g_{m,b1}) \] That is, \(g_{m,a1}+g_{m,b1} = \mu C_{OX}\frac{W}{L}(V_{a1}+V_{b1} - 2V_{TH})\)

To minimize the difference between \(\Delta I_1\) and \(\Delta I_0\), the drift of both differential and common mode between \(V_a\) and \(V_b\) shall be alleviated

Chopping

offset is modulated away from the signal band and then filtered out

Modulate the offset away from DC and then filter it out

Good: Magically reduces offset, 1/f noise, drift

Bad: But creates switching spikes, chopper ripple and other artifacts …

Chopping in the Frequency Domain

Square-wave Modulation

definition of convolution \(y(t) = x(t)*h(t)= \int_{-\infty}^{\infty} x(\tau)h(t-\tau)d\tau\)

for real signal \(H(j\omega)^*=H(-j\omega)\)​

\[ H(j\hat{\omega})*H(j\hat{\omega}) = \int_{-\infty}^{\infty}H(j\omega)H(j(\hat{\omega}-\omega))d\omega \]

The Fourier Series of squarewave \(x(t)\) with amplitudes \(\pm 1\), period \(T_0\)

\[ C_n = \left\{ \begin{array}{cl} 0 &\space \ n=0 \\ 0 &\space \ n=\text{even} \\ |\frac{2}{n\pi}| &\space n=\pm 1,\pm 5,\pm9, ... \\ -|\frac{2}{n\pi}| &\space n=\pm 3,\pm 7,\pm11, ... \end{array} \right. \]

The Fourier transform of \(s(t)=x(t)x(t)\), and we know \[\begin{align} S(j2n\omega_0) &= \frac{1}{2\pi}\int X(j(2n\omega_0 -\omega))X(j\omega) d\omega\\ &= \frac{1}{2\pi}\int X(j(\omega-2n\omega_0))X(j\omega) d\omega \end{align}\]

Therefore \(n=0\) \[ S(j0) = \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}2\sum_{n=0}^{+\infty}\frac{1}{(2n+1)^2} \delta(\omega) = 2\pi \delta(\omega) \]

if \(n=1\)

\[\begin{align} S(j2\omega_0) &= \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}\left(1 - 2\sum_{n=0}^{+\infty}\frac{1}{(2n+1)(2n+3)} \right) \\ &= \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}\left(1 - 2\sum_{n=0}^{+\infty}\frac{1}{2}\left[\frac{1}{2n+1}- \frac{1}{2n+3}\right] \right) \\ &= 0 \end{align}\]

\(n=2\) \[\begin{align} \sum &= -\frac{2}{3} + 2\left(\frac{1}{1\times 5}+ \frac{1}{3\times 7}+ \frac{1}{5\times 9} + \frac{1}{7\times 11}+...\right) \\ &= -\frac{2}{3} + 2\cdot \frac{1}{4}\left(\frac{1}{1}-\frac{1}{5}+ \frac{1}{3}- \frac{1}{7}+ \frac{1}{5} - \frac{1}{9} +\frac{1}{7}-\frac{1}{11}+...\right) \\ &= -\frac{2}{3} + 2\cdot \frac{1}{4}\frac{4}{3} = 0 \end{align}\]

That is, the input signal remains the same after chopping or squarewave up/down modulation

EXAMPLE 2.7 in R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

Prove that \(\pi^2/8 = 1 + 1/3^2 + 1/5^2 + 1/7^2 + \cdots\) [https://math.stackexchange.com/a/2348996]

Bandwidth & Gain Accuracy

• lower effective gain: DC level at the output of the amplifiers is a bit less than what it should be

• chopping artifacts at the even harmonics: frequency of output is \(2f_{ch}\)

Below we justify \(A_\text{eff} = A(1-4\tau/T_\text{ch})\) \[ V_o(t) = A + (V_0-A)e^{-t/\tau} \qquad V_o(T/2) = -V_0 \]

then \[ V_0 = -A\frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}} \] Then DC level is \[ A_\text{eff} = \frac{1}{T/2}\int_0^{T/2} V_o(t)dt = A\left(1-\frac{4\tau}{T}\cdot \frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}}\right)\approx A\left(1-\frac{4\tau}{T}\right) \]

where assuming \(\tau \ll T\)

REF. [https://raytroop.github.io/2023/01/01/insight/#rc-charge-discharge]

[https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/57799/very-low-dc-gain-of-pstb-simulation/1392299]

Residual Offset of Chopping

assume input spikes can be expressed as \[ V_\text{spike}(t) = V_o e^{-\frac{t}{\tau}} \]

Then, residual offset is

\[\begin{align} \overline{V_\text{os}} &= \frac{2\int_0^{T_{ch}/2}V_\text{spike}(t)dt}{T_{ch}} = 2f_{ch}V_o\int_0^{T_{ch}/2} e^{-\frac{t}{\tau}}dt = 2f_{ch}V_o\tau\int_0^{T_{ch}/2\tau} e^{-\frac{t}{\tau}}d\frac{t}{\tau}\\ &\approx 2f_{ch}V_o\tau \end{align}\]

Chopping Simulation

EE 501: CMOS Analog Integrated Circuit Design — Chopping for Offset reduction [https://class.ece.iastate.edu/djchen/ee501/2016/Chopper_design_EE501.pptx]

• Run transient simulation to ensure the amp output can settle into a steady-state and offset ripple is small
• Run PAC/ Pnoise to verify the ac and noise performance with chopping on

Ripple Cancellation after Chopping

On-chip analog filter is not good enough due to limited cutoff frequency

at \(\Phi_+\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[n] &= \frac{I_l[n]-I_r[n-1]}{G_m} \\ \left(I_0+\frac{V_\text{os0}-\Delta V_\text{os}[n]}{R_E}\right)\beta &= I_l[n]+I_r[n-1] \end{array} \right. \] Then \[ \left\{ \begin{array}{cl} I_r[n-1] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] at \(\Phi_-\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[n] &= \frac{I_l[n-1]-I_r[n]}{G_m} \\ \left(I_0+\frac{-V_\text{os0}+\Delta V_\text{os}[n]}{R_E}\right)\beta &= I_l[n-1]+I_r[n] \end{array} \right. \] Then \[ \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n-1] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] \(\Phi_+ \to \Phi_-\) state transformation \[ \left\{ \begin{array}{cl} I_r[n-1] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \to \left\{ \begin{array}{cl} I_r[n+1] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] Two \(I_l[n]\) shall be equal, that is \[ \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 = \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \] Rearrange the above equation \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \] \(\Phi_- \to \Phi_+\) state transformation \[ \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n-1] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \to \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n+1] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] Two \(I_r[n]\) shall be equal, that is \[ \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 = \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \] Rearrange the above equation \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \]

Both State-transition equations are same \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \] With geometric progression sum formula \[ \Delta V_\text{os}[n] = \left(\frac{G_mR_E-\beta}{G_mR_E+\beta}\right)^n\cdot \Delta V_\text{os}[0] + \left[1-\left(\frac{G_mR_E-\beta}{G_mR_E+\beta}\right)^n\right]\cdot V_\text{os0} \] during \(n \to \infty\) \[ \lim_{n\to \infty} \Delta V_\text{os}[n] = V_\text{os0} \] As expected \[ \lim_{n\to \infty} V_\text{os}[n] =\lim_{n\to \infty} V_\text{os0}-\Delta V_\text{os}[n] = 0 \]

Assuming that begainning from \(\Phi_+\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[0] &= \frac{I_l[0]-I_r[-1]}{G_m} \\ \left(I_0+\frac{V_\text{os0}-\Delta V_\text{os}[0]}{R_E}\right)\beta &= I_l[0]+I_r[-1] \end{array} \right. \overset{\mathcal{I_r[-1]=0}}{\Longrightarrow} \Delta V_\text{os}[0]=\frac{(I_0R_E+V_\text{os0})\beta}{G_mR_E+\beta} \] With \(I_0=10\mu A\), \(R_E=5k \Omega\), \(V_\text{os0}=20mV\), \(G_m=500\mu S\), \(\beta=0.5\) \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[0] &= 167mV \\ \frac{G_mR_E-\beta}{G_mR_E+\beta} &= 0.667 \end{array} \right. \]

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DVos0 = 167;  % mV
Vos0 = 20; % mV
Rr = 0.667;

n = 1:1:50;
DVosn_DVos0 = Rr.^n*DVos0;
DVosn_Vos0 = (1-Rr.^n)*Vos0;
DVosn = DVosn_DVos0 + DVosn_Vos0;

plot(n, DVosn_DVos0,'--r', LineWidth=2);
hold on
plot(n, DVosn_Vos0, '--g', LineWidth=2);
plot(n, DVosn, 'b', LineWidth=3);
plot(-5:1:55, ones(1,61)*Vos0, '--k', LineWidth=2)

grid on;
xlim([-5, 55]);ylim([-5, 120]);
xlabel('n', FontSize=16); ylabel('mV', FontSize=16);
legend('$\Delta V_{os}[0]$ decaying','$V_{os0}$ decaying','$\Delta V_{os}[n]$', '$V_{os0}$', 'Interpreter','latex', fontsize=16)

reference

P. Bruschi, Dynamic techniques for the rejection of the offset and low frequency noise [https://docenti.ing.unipi.it/~a008309/mat_stud/MIXED/2023/Lecture_notes/Chap_2_2_Offset_Flicker_Reduction.pdf] [slides]

C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," in Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996, doi: 10.1109/5.542410. [http://www2.ing.unipi.it/~a008309/mat_stud/MIXED/archive/2019/Articles/Offset_canc_Enz_Temes_96.pdf]

R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. Wiley-Interscience, 1986

Christian-Charles Enz. "High precision CMOS micropower amplifiers"

Kofi Makinwa. Precision Analog Circuit Design: Coping with Variability, [https://youtu.be/nA_DZtRqrTQ] [https://youtu.be/uwRpP20Lprc]

—, ISSCC 2007 Dynamic-Offset Cancellation Techniques in CMOS

—, Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise? [https://youtu.be/y7TzJtHE7IA]

Qinwen Fan, 2022 SSCS webinar: Evolution of precision amplifiers

—. IEEE Sensors 2018: Capacitively-Coupled Chopper Instrumentation Amplifiers : an Overview [https://youtu.be/NoGHJfCFCks]

Axel Thomsen, Silicon Laboratories ISSCC2012 T8: "Managing Offset and Flicker Noise"

CC Chen. Why Dynamic Offset or Mismatch Cancellation with Auto-zeroing Technique? [https://youtu.be/PQJwzd1tyO0]

—. Why Dynamic Offset or Mismatch Cancellation with Chopping Technique? [https://youtu.be/x5FS8jEKu_g]

—. Why Design Challenge in Chopping Offset & Flicker Noise? [https://youtu.be/ydjca2KrXgc]

—. Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise? [https://youtu.be/y7TzJtHE7IA]

Modulation of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: [Modulation of Random Processes]

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

modulated with small perturbation

Nicola Da Dalt , Understanding Jitter and Phase Noise: 3.1.3 Voltage to Excess Phase Transformations: Random Noise

Given \(\color{blue}\phi(t)\ll 1\), the autocorrelation still depends on absolute time \(t\). Therefore \(v(t)\) is cyclostationary, and they must take a time average over one carrier period.

Chembiyan T. Jitter and Phase Noise in Phase Locked Loops [link]

\[ y(t) = A\cos(2\pi f_0t+\phi_n(t)) \approx A \cos(2\pi f_0 t) - A \phi_n (t)\sin(2\pi f_0 t) \]

\[ R_x(\tau) = \frac{A^2}{2}\cos(2\pi f_0\tau) + \frac{A^2}{2}R_\phi(\tau)\cos(2\pi f_0\tau) \] The PSD of the signal \(x(t)\) is given by \[ S_x(f) = \mathcal{F}\{R_x(\tau)\} = \frac{P_c}{2}\left[\delta(f+f_0)+\delta(f-f_0)+S_\phi(f+f_0)+S_\phi(f-f_0)\right] \] where \(P_c = A^2/2\) is the carrier power of the signal

modulated with full-cycle random

Given \(\color{blue}\Theta\sim U[0,2\pi]\), after ensemble averaging, the autocorrelation becomes WSS

Haykin, Simon S., and Michael Moher. Communication Systems. 5th ed. John Wiley & Sons, 2009. - Mixing of a Random Process with a Sinusoidal Process

Assume \(\Theta\sim \mathcal U[0,2\pi)\) is a single random phase that remains constant for all \(t\): \[ \color{blue}\boxed{X(t)=A\cos(\omega_0t+\Theta).} \]

Mean \[ \begin{aligned} m_X(t) &=\mathbb E[X(t)]\\ &=\frac{A}{2\pi}\int_0^{2\pi} \cos(\omega_0t+\theta)\,d\theta\\ &=0. \end{aligned} \]

Thus, the mean is independent of \(t\).

Autocorrelation

For \(t_1\) and \(t_2\), \[ R_X(t_1,t_2) = \mathbb E[X(t_1)X(t_2)]. \] Using \(\cos a\cos b=\frac{1}{2}\left[\cos(a-b)+\cos(a+b)\right],\)

we obtain \[ \begin{aligned} R_X(t_1,t_2) &= \frac{A^2}{2} \mathbb E\left[ \cos\big(\omega_0(t_1-t_2)\big) + \cos\big(\omega_0(t_1+t_2)+2\Theta\big) \right]. \end{aligned} \] Since \(\Theta\) is uniform, \[ \mathbb E\left[ \cos\big(\omega_0(t_1+t_2)+2\Theta\big) \right]=0. \] Therefore, \[ \boxed{ R_X(t_1,t_2) = \frac{A^2}{2} \cos\big(\omega_0(t_1-t_2)\big) } \] or, defining \(\tau=t_1-t_2\), \[ \boxed{ R_X(\tau)=\frac{A^2}{2}\cos(\omega_0\tau) }. \] The autocorrelation depends only on the time difference \(\tau\).

Is it WSS?

Yes. The two WSS conditions are satisfied: \[ m_X(t)=0, \] which is constant, and \[ R_X(t_1,t_2)=R_X(t_1-t_2). \] Thus, \[ \boxed{X(t)\text{ is wide-sense stationary.}} \] In fact, because a time shift simply changes the uniformly distributed phase, \[ X(t+t_0) = A\cos\left(\omega_0t+\underbrace{\Theta+\omega_0t_0}_{\text{still uniform modulo }2\pi}\right), \] the process is also strict-sense stationary.

Power spectral density

Using the angular-frequency Fourier-transform convention \[ S_X(\omega) = \int_{-\infty}^{\infty} R_X(\tau)e^{-j\omega\tau}\,d\tau, \] and \[ \mathcal F\{\cos(\omega_0\tau)\} = \pi\left[ \delta(\omega-\omega_0)+\delta(\omega+\omega_0) \right], \] we get \[ \boxed{ S_X(\omega) = \frac{\pi A^2}{2} \left[ \delta(\omega-\omega_0) + \delta(\omega+\omega_0) \right] }. \] Thus, the PSD consists of two spectral lines at \(\omega=\pm\omega_0\).

The total average power is \[ R_X(0)=\frac{A^2}{2}, \] and equivalently, \[ \frac{1}{2\pi}\int_{-\infty}^{\infty}S_X(\omega)\,d\omega = \frac{A^2}{2}. \] For frequency \(f\), where \(f_0=\omega_0/(2\pi)\), \[ \color{blue}\boxed{ S_X(f) = \frac{A^2}{4} \left[ \delta(f-f_0)+\delta(f+f_0) \right] }. \] The random phase makes the ensemble stationary; a sinusoid with a fixed deterministic phase is not normally regarded as a stationary random process because it contains no random ensemble.

modulated with deterministic cosine

the carrier phase/time origin is fixed, not randomized, it not WSS but cyclostationary

Hayder Radha, ECE 458 Communications Systems Laboratory Spring 2008: Lecture 7 - EE 179: Introduction to Communications - Winter 2006–2007 Energy and Power Spectral Density and Autocorrelation

\(g(t) = i_n(t)\sin\omega_0 t\) is not WSS (it's cyclostationary), but its time-averaged PSD is white

the solution silently performs the time-averaging step

Assume zero-mean white noise \(n(t)\) is multiplied by a sinusoid:

\[ y(t)=n(t)\cos(\omega_0 t) \]

Let the two-sided white-noise PSD be

\[ S_n(f)=\frac{N_0}{2} \]

so

\[ R_n(\tau)=\frac{N_0}{2}\delta(\tau) \]

Because the sinusoid is deterministic and time-varying, \(y(t)\) is generally cyclostationary, not WSS.

Using the symmetric autocorrelation definition,

\[ R_y(t,\tau) = E\left[ y\left(t+\frac{\tau}{2}\right) y\left(t-\frac{\tau}{2}\right) \right] \]

we get

\[\begin{aligned} R_y(t,\tau) &= R_n(\tau) \cos\left(\omega_0 t+\frac{\omega_0\tau}{2}\right) \cos\left(\omega_0 t-\frac{\omega_0\tau}{2}\right) \\ &= \frac{R_n(\tau)}{2} \left[ \cos(\omega_0\tau)+\cos(2\omega_0t) \right] \end{aligned}\]

Therefore, for white noise,

\[ \boxed{ R_y(t,\tau) = \frac{N_0}{4} \left[ \cos(\omega_0\tau)+\cos(2\omega_0t) \right]\delta(\tau) } \]

If you average over one modulation period, then

\[ \overline{R_y}(\tau) = \frac12 R_n(\tau)\cos(\omega_0\tau) \]

For general stationary noise this corresponds to

\[ \boxed{ \overline{S_y}(f) = \frac14 \left[ S_n(f-f_0)+S_n(f+f_0) \right] } \]

where \(f_0=\frac{\omega_0}{2\pi}\)

For ideal white noise,

\[ S_n(f-f_0)=S_n(f+f_0)=\frac{N_0}{2} \]

so

\[ \boxed{ \overline{S_y}(f)=\frac{N_0}{4} } \]

Thus an important result is: multiplying ideal white noise by a sinusoid does not change the shape of its time-averaged PSD—it remains white—but its average PSD is reduced by a factor of 2, because

\[ \overline{\cos^2(\omega_0t)}=\frac12 \]

For colored noise, however, the sinusoidal multiplication creates two shifted copies:

\[ S_n(f) \rightarrow \frac14S_n(f-f_0)+\frac14S_n(f+f_0) \]

Quadrature-Modulated Processes

Haykin, Simon S., and Michael Moher. Communication Systems. 5th ed. John Wiley & Sons, 2009.

Dr. Vishal Saxena, ECE518 Memory/Clock Synchronization IC Design: Oscillator Phase Noise [https://www.eecis.udel.edu/~vsaxena/courses/ece504/Handouts/Oscillator%20Phase%20Noise.pdf]

Sampling of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: Impulse sampling of Random Processes

DT sequence \(x[n]\)

Owing to \(\phi[0] = \phi_c(0)\), the average power of the sampled version \(x[n]\) is the same as its input \(x_c(t)\)

impulse train \(x_s(t)\)

That is \[ P_{x_s x_s} (f)= \frac{1}{T_s^2}P_{xx}(f) \] where \(x[n]\) is sampled discrete-time sequence, \(x_s(t)\) is sampled impulse train

Noise Aliasing

apply foregoing observation

Pulsed Noise Signals

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

Above, the output of the multiplier be \(y(t)\) is passed through a ideal brick wall low pass filter with a bandwidth of \(f_0/2\)

When a random signal is multiplied by a pulse function, the resulting signal becomes a cyclo-stationary random process.

As rule of thumb, the spectrum of such a pulsed noise signal

• thermal noise is multiplied by \(\color{red}D\)

• flicker noise is multiplied by \(\color{red}D^2\),

where \(D\) is the duty cycle of the pulse signal

banlimited input (no aliasing)

wideband white noise input

flicker noise input

with \(S_x(f)=\frac{K_f}{f}\)

Assuming \(\Delta f \ll f_0\)

Rectangular Pulse Sampling

Balu Santhanam. ece439 Introduction to Digital Signal Processing. Example: Rectangular Pulse Sampling [http://ece-research.unm.edu/bsanthan/ece439/recsamp.pdf]

reference

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]

R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

John G. Proakis and Masoud Salehi, Fundamentals of communication systems 2nd ed [pdf]

Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007

Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers, oscillators, samplers, and logic: an introduction to cyclostationary noise." Proceedings of the IEEE 2000 Custom Integrated Circuits Conference. [pdf, slides]

Antoni, J., "Cyclostationarity by examples", Mechanical Systems and Signal Processing, vol. 23, no. 4, pp. 987–1036, 2009 [https://docente.unife.it/docenti/dleglc/a-a-2010-2011-dmsm/ciclostazionarieta.pdf]

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF. URL:https://designers-guide.org/analysis/sc-filters.pdf

STEADY-STATE AND CYCLO-STATIONARY RTS NOISE IN MOSFETS [https://ris.utwente.nl/ws/portalfiles/portal/6038220/thesis-Kolhatkar.pdf]

Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]

L.W. Couch, Digital and Analog Communication Systems, 8th Edition, Pearson, 2013. [pdf]

Tran options for VCO

[https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/15832/how-to-run-the-simulaiton-for-1-ns-step-interval]

cmin is a small artificial capacitance that the simulator adds from every circuit node to ground during transient simulation. Cadence recommends it mainly as a convergence aid because it smooths abrupt/discontinuous behavior that can force extremely small timesteps

This is not a physical capacitor in your schematic. It is a numerical stabilization parameter.

undo sorting in ADE

Noise Analysis

The % / Total column in the noise summary table always displays values in \(V^{2}\) contribution, regardless of whether noise unit option is set to V or V^2

result browser of instance show noise contribution, which is same with noise summary

res isnoisy default yes

layout porting

streamout in old process -> streamin in new process with layermap, format in below

Modulation index in Virtuoso

indq, capq

The inductor with Q works in all the analyses except for shooting.

The capacitor with Q

Pole Zero (PZ) Analysis

Pole Zero (PZ) Analysis with Spectre/SpectreX Rapid Adoption Kit (RAK)

Note: poles/zeros in simulation log are in Hz instead of rad/s

STB and PSTB in Spectre/RF

F. Wiedmann, "Loop gain simulation, [https://sites.google.com/site/frankwiedmann/loopgain]

M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17, no. 1, pp. 31-41, Jan. 2001 [https://kenkundert.com/docs/cd2001-01.pdf]

Open loop gain analysis and "STB" method [https://www.linkedin.com/pulse/open-loop-gain-analysis-stb-method-jean-francois-debroux]

刘堃. Middlebrook环路测量方法讨论，STB原理 [https://bbs.eetop.cn/thread-985438-1-1.html]

STB analysis

Spectre stb's "loopgain" is negative of "T" in paper \[ T = \frac{2(AD-BC) - A + D}{2(AD-BC)-A+D-1} \]

AC simulation testbench, shown as below,

1. \(I_{inj}\) = 0, \(V_{inj}\) = 1

   B = if, D = ve

2. \(I_{inj}\) = 1, \(V_{inj}\) = 0

   A = if, C = ve

PSTB analysis

Spectre pstb is similar to stb, just set pac as 1 instead of ac in current source and voltage source.

This analysis just use harmonic 0 transfer function in pac analysis, which has limitation.

psf_utils

PSF Utilities — Read Spectre Data Files [https://github.com/KenKundert/psf_utils]

m-factor devices correlation

community.cadence, Understanding underlying statistical assumptions in Monte Carlo simulations [link]

Hesham Omran, Why Using The Device Multiplier Can Make Your Monte Carlo Simulations Wrong [https://www.linkedin.com/pulse/why-using-device-multiplier-can-make-your-monte-carlo-hesham-omran/]

cadence support, How is mismatch applied in array/parallel devices in Spectre Monte Carlo?

—, How does spectre apply correlation between m-factor devices during Monte Carlo simulation?

nullmfactorcorrelation=no/yes

differential R/C simulation

The left testbench is better choice for differential R/C extraction. because the right testbench may have uncontrolled AC common stimulus, which is undesired

changing Library Reference

TODO 📅

Net Tracer

Virtuoso(Layout XL)高亮神器 Net Tracer功能介绍及使用方法 [https://www.kaixinspace.com/virtuosolayout-xl-net-tracer-highlight/#:~:text=1.%20%E8%83%8C%E6%99%AF%E8%AF%B4%E6%98%8E,IC%20Virtuoso]

Virtuoso Studio IC 23.1: Using Net Tracer for Design Review [https://community.cadence.com/cadence_blogs_8/b/cic/posts/virtuoso-studio-using-net-tracer-for-design-review-]

ACMatch

ACMatch analysis linearizes the circuit about the DC operating point and computes the variations of AC responses due to statistical parameters defined in statistics blocks.

Only mismatch parameters are considered. The analysis skips the process parameters.

Imag 1-Sigma \[ \sqrt{50.2^2 + 57.9^2} = 76.6 \]

ViVA Marker Table

Window->Assistants->Vert Marker Table

Window->Assistants->Horiz Marker Table

[https://community.cadence.com/cadence_blogs_8/b/cic/posts/things-you-didn-t-know-about-virtuoso-delta-markers-in-viva]

Layout XL

IC61电路新添加器件XL更新（两种方法）

①　重新Layout XL后→Connectivity→Generate→Selected From Source（先去原理图选择新器件再操作）

②　重新Layout XL后→Connectivity→update→Components And Nets→OK

IC61 Net飞线关系

Connectivity→Nets→Show/Hide All Incomplete Nets

IC61加线名

Connectivity→Nets→Assign→F3

Layout XL里面的黄色框框 已有 1109 次阅读| 2021-9-7 17:25 |系统分类:芯片设计

在使用layout XL的时候，有些器件的连线没有按照生成的对应关系连线，当update connectivity information when design is modifed ON，就会出现很多黄色的框框，在菜单栏里点击Verify->Markers->Delete All即可一键删除。

[https://blog.eetop.cn/home.php?mod=space&uid=1542900&do=blog&id=6947553]

[https://blog.eetop.cn/blog-1768341-6947567.html]

s-Domain Controlled Source

Layout XL pointing to new schematic

Connectivity(Menu in Layout View) ---> Update ---> Connectivity Reference

Hide Muti-Pattern Color

noiseon & noiseoff

Options -> Analog...

only work in presimu simulation (excluding lpe.spi)

vsource with noisefile

1. both rise/fall edge are added the noisefile
2. noise between rise and fall edge are partially correlated

Pnoise sampled(jitter) with Sampled Phase

vsource output is applied with noise all the time

Loockup Table vs Equations Model in Verilog-A

Solar Cell Verilog Model for Cadence [https://miscircuitos.com/solar-cell-verilog-model-for-cadence/]

How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-A [https://miscircuitos.com/how-to-create-a-model-in-verilog-a-with-a-lockup-table/]

with Equation

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/////////////////////////////////////////////////////////////////////////////
//
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell IXYS
//
// Change history: 1/7/2018
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"

module SolarCell( EN, Vsolar, GND);

input EN;
electrical EN;

output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

parameter real vdd = 1.2;
parameter real vthreshold = 0.6;
parameter real fc = 10M;
parameter real light = 6;

//Curve parameters
real gm;
real A;
real factor;
real Vop;
real vcp;

integer light_i;
integer en;
analog begin

    @(initial_step)    begin 
        en = 0;
        A = 1;    
        Vop = 1;
        factor = 10;
    end
//Enable digitalization
    @(cross(V(EN)-vthreshold,1)) begin
        if(V(EN)>=vthreshold) en = 1;
        else en = 0;
    end
        
    case(light):
            0: begin A = 0; Vop = 0; end
            1: begin A = -1.2; Vop = 1.71; end
            2: begin A = -0.8; Vop = 1.64; end
            3: begin A = -0.4; Vop = 1.50; end
            4: begin A = 0.1; Vop = 1.43; end
            5: begin A = 0.7; Vop = 1.36; end
            6: begin A = 1.1; Vop = 1.22; end
            default: begin A = -1.2; Vop = 1.71; end
        endcase

    //gm = A + atan(factor*(Vop-V(Vsolar))); //Transconductance

    vcp=laplace_nd(V(Vsolar,GND),{1},{1,1/(6.28*fc)});

    I(Vsolar,GND) <+  (A + atan(factor*(vcp -Vop)))/1000;

end //analog
endmodule

with lookup table

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///////////////////////////////////////////////////////////////////////////
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell photodiode
//
// Change history: 11/Sept/2019
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"
 
module SolarCell_Table( EN, Vsolar, GND);
 
input EN;
electrical EN;
 
output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

 
//Curve parameters
parameter real light =1;
parameter real vthreshold = 0.6;

real Vcp;
real iout, itemp;
real i1,i2, i3, i4, i5;
integer en;
analog begin
 
    @(initial_step)    begin 
        en = 0;
    end

//Enable function
    @(cross(V(EN) -vthreshold,1)) begin
        if(V(EN)>=vthreshold) en = 1;
        else en = 0;
    end

    Vcp = V(Vsolar,GND)*1000;

    i1 =  -$table_model (Vcp, "ph4_1.tbl", "1C")/1000000;
    i2 =  -$table_model (Vcp, "ph4_2.tbl", "1C")/1000000;
    i3 =  -$table_model (Vcp, "ph4_3.tbl", "1C")/1000000;
    i4 =  -$table_model (Vcp, "ph4_4.tbl", "1C")/1000000;
    i5 =  -$table_model (Vcp, "ph4_5.tbl", "1C")/1000000;

//    if(itemp <0 ) iout = itemp;
//    else iout = 0;
    case (light)
        1: iout = i1;
        2: iout = i2;
        3: iout = i3;
        4: iout = i4;
        5: iout = i5;
        default: iout = 0;
    endcase
    
    if(en== 0) iout = 0;

    I(Vsolar,GND) <+  iout;
 
end //analog
endmodule

PEX LAYER_MAP

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// *LAYER_MAP
// *1 POLY
// *2 CONT
// *3 M1
...
*RES
8 ENL:30 ENL:34 0.525075 // $lvl=3
9 ENL ENL:30 0.07 // $lvl=3

[https://picture.iczhiku.com/resource/eetop/wYItYWLPleWrpvNV.pdf]

nodeset & initial condition

• A nodeset steers the convergence in a particular direction - useful to speed up DC convergence

• An initial condition is useful when you want to force the circuit to start a transient in a particular condition

[https://community.cadence.com/cadence_technology_forums/f/rf-design/29843/ade--difference-between-node-set-and-initial-condition/1335460]

Remove prefix from multiple files in Linux console

Bash

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for file in prefix*; do mv "$file" "${file#prefix}"; done;

The for loop iterates over all files with the prefix. The do removes from all those files iterated over the prefix.

Here is an example to remove "bla_" form the following files:

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bla_1.txt
bla_2.txt
bla_3.txt
blub.txt

Command

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for file in bla_*; do mv "$file" "${file#bla_}";done;

Result in file system:

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1.txt
2.txt
3.txt
blub.txt

[https://gist.github.com/guisehn/5438bbc22138435665c6e996493fe02b]

remove .cdslck

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 #!/bin/sh
tree -if | grep 'cdslck' > txt
var=`cat txt`
for i in $var; do
	rm -i $i
done
rm -i txt

[https://wikis.ece.iastate.edu/vlsi/index.php?title=Tips_%26_Tricks#Locked_Files_in_Cadence]

Custom Bindkey

schBindKeys.il

schematic

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alias bk hiSetBindKey
when ( isCallable('schGetEnv')
bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")")
bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")")
bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")")
bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()")
bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)")
)
unalias bk

leBindKeys.il

layout

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alias bk hiSetBindKey
when ( isCallable('leGetEnv)
    bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" )
    ; M1-VIA1-M2
    bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" )
    ; M2-VIA2-M3
    bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" )
    ; M3-VIA3-M4
    bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" )
    ; M4-VIA4-M5
	; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them
    bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" )
    ; all visiable
    bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" )
)
unalias bk

Design Variable in vpwlf

PWL File as Design Var? parameter in vpwlf cell is convenient for sweep simulation or corner simulation, wherein there are multiple pwl files .

The file path should be surrounded with double-quotes to be protected from evaluation.

save option

Using Spectre Save Effectively RAK

none:

​ Does not save any data (currently does save one node chosen at random)

selected:

​ Saves only signals specified with save statements. The default setting.

lvlpub:

Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.

lvl:

​ Saves all signals up to nestlvl deep in the subcircuit hierarchy. This option is relevant for subcircuits.

allpub:

​ Saves only signals that are normally useful.

all:

​ Saves all signals.

Signals that are "normally useful" include the shared node voltages and currents through voltage sources and iprobes, and exclude the internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain, source on a FET, and so on). It also excludes currents through inductors, controlled sources, transmission lines, transformers, etc.

If you use lvl or all instead of lvlpub or allpub, you will also get internal node voltages and currents through other components that happen to compute current.

Thus, using *pub excludes internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain and source on a FET, etc). It also excludes the currents through inductors, controlled sources, transmission lines, transformers, etc.

nestlvl

This variable is used to save groups of signals as results and when signals are saved in subcircuits. The nestlvl parameter also specifies how many levels deep into the subcircuit hierarchy you want to save signals.

virtuoso "dlopen failed to open 'libdl.so'"

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$ sudo yum install glibc-devel  

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Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST.                                                         
Dependencies resolved.
=========================================================================================================================================
 Package                            Architecture              Version                                    Repository                 Size
=========================================================================================================================================
Installing:
 glibc-devel                        x86_64                    2.28-189.5.el8_6                           baseos                     78 k
Installing dependencies:
 glibc-headers                      x86_64                    2.28-189.5.el8_6                           baseos                    482 k
 kernel-headers                     x86_64                    4.18.0-372.26.1.el8_6                      baseos                    9.4 M
 libxcrypt-devel                    x86_64                    4.1.1-6.el8                                baseos                     24 k

Transaction Summary
=========================================================================================================================================
Install  4 Packages

SpiceIn foundary's standard cell's spice netlist

use SpiceIn GUI feature to map MOS parameter correctly in generated schematic

Input

The mos's total width (parameter name "w") value will update during SpiceIn trigger CDF callback automatically

Output

Device Map

User Prop Mapping is significant setup, both xxx.spi and Edit CDF provide the essential information.

The map syntax is spice_para0 cdf_para0 spice_para1 cdf_para01 ... spice_paraN cdf_paraN

reference

Article (20488179) Title: How to use SpiceIn GUI feature to map MOS parameter correctly in generated schematic

Article (11724692) Title: SpiceIn maps the netlist parameter to the CDF parameter incorrectly on the generated schematic devices (e.g. w to wf)

Model Library Setup

In order to set up model files automatically in the Model Library Setup form for Spectre or AMS simulator in ADE Explorer or ADE Assembler

Add the following line in your .cdsinit

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envSetVal( "spectre.envOpts" "modelFiles" 'string "<path_to model_file>/myModels.scs")

or

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envSetVal("spectre.envOpts" "modelFiles" 'string "moreModels;ff mymodels;tt")

DSPF for each corner

Create a new file with an extension scs like myDSPF_Files.scs

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* DSPF files to use with Corner Definitions
* This is an example file showing how to define different dspf files for different corners
* using model files for individual components as the
* building blocks.
simulator lang=spectre
library dspf_files_corners

section rctyp_25
dspf_include "DSPF_RC_TYPNOM25.spf"
endsection rctyp_25

section rctyp_125
dspf_include "DSPF_RC_TYP125.spf"
endsection rctyp_125

section rcworst_25
dspf_include "DSPF_RC_WORSE25.spf"
end section rcworst_25

section rcworst_125
dspf_include "DSPF_RC_WORSE125.spf"
end section rcworst_125

endlibrary dspf_files_corners

Add the file created above ‘myDSPF_File.scs’ in ‘Add/Edit Model Files’ of Corners setup form

split pins in dspf_emir

dspf extract using starrc

multiple label and rectangle in vssa net

• general dspf

  SHORT_PINS: YES

  

  other pin are short together

• dspf for emir analysis

It seems that dspf_emir don't contain the rectangle pin information.

only label is necessary

shortPins="yes" is preferred default option for dspf_emir, which has split pins

DSPF Syntax

• ::=*|P ? describes pins in the net. Multiple pin descriptions can be listed in one line.

• ::=( {}?) represents the name of the pin. represents the type of the pin. It can be any of the following: I (Input), O (Output),

  ​ B (Bidirectional), X (don’t care), S (Switch), and J (Jumper). ​ represents the capacitance value associated with the pin. ​ is optional. It represents the location of the pin. Multiple pin locations are allowed

split pins

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*|P (avss_1 O 0 207.7555 59.9170)
*|P (avss_10 O 0 181.1610 151.1130)
*|P (avss_11 O 0 186.6330 151.1130)
*|P (avss_12 O 0 192.1050 151.1130)
*|P (avss_13 O 0 197.5770 151.1130)

reference

Article (20467964) Title: Difference in result on running Spectre APS with EMIR and without EMIR analysis

StarRC User Guide and Command Reference Version O-2018.06, June 2018

DSPF Options

Case Sensitivity

For a dspf format, it will be treated as a spice netlist format, which is by default case insensitive

Pay attention to VerilogIn block, which may contain upper case / lower case net name, e.g NET1 and net1.

The extracted DSPF using extraction tool also contain NET1 and net1, which shall not be shorted together.

Port Order

If you use .dspf_include, the following rules apply:

• The subcircuit description is taken from the DSPF file even if the same subcircuit description is available in the schematic netlist.
• Depending on the port_order option, the port order of the subcircuit definition is taken from the pre-layout schematic netlist or from the DSPF file subcircuit definition, as shown below.
  • port_order=sch – (Default). The port order is taken from schematic subcircuit definition. The same port number and names are required. If the schematic subcircuit definition is not available, a warning is issued in the log file, and DSPF port order is used.
  • port_order=spf – The port order is taken from the DSPF subcircuit definition.

SPICE_SUBCKT_FILE of StarRC

The StarRC tool reads the files specified by the SPICE_SUBCKT_FILE command to obtain port ordering information. The files control the port ordering of the top cell as well. The port order and the port list members read from the .subckt for a skip cell are preserved in the output netlist.

The file usually is the cdl netlist of extracted cell, this way, port order is not problem

CDF termOrder

DSPF same order

DSPF

input.scs

different order

manual change DSPF's pin order shown as below

port_order=sch

dspf port is mapping to schematic by name, and the simulation result is right

port_order=spf

dspf pin order is retained, and no mapping between spectre netlist and dspf.

The simulation result is wrong

bus_delim="_ <>"

The way this works is that the first part of bus_delim is the "schematic" delimiter (i.e. what's in the spectre netlist), and the other part is the DSPF delimiter

reference

Article (20502176) Title: How does Spectre understand case-sensitive net names when using various post-layout netlists such as dspf, av_extracted view, or smart view?

spf in cadence https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31326/spf-in-cadence/1342278#1342278

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1

StarRC™ User Guide and Command Reference Version O-2018.06, June 2018

Virtual Connectivity

Normally, if the layout connectivity extractor finds disjoint, unconnected geometries with the same net name text attached, the extractor will view this as an open circuit.

• Virtual connection results in the extraction of a single net from two or more disjoint physical nets when the physical net segments share the same name.
• Virtual connectivity is triggered by the rule file VIRTUAL CONNECT COLON and VIRTUAL CONNECT NAME specification statements.
• Virtual connectivity can also be specified through the Calibre Interactive GUI.

Virtual connectivity is of primary interest in LVS applications

connect all nets by name: VIRTUAL CONNECT NAME "?"

VIRTUAL CONNECT COLON

Virtual Connect Colon is used to virtually connect nets that share a common prefix before a colon, like VDD:1, VDD:2, and so forth.

If you specify YES, then the connectivity extractor first strips off all characters from the first colon to the end of the label names.

Next, the extractor forms a virtual connection between any two labels that have the same name and that originally contained a colon.

Colons can appear anywhere in the name with the exception that a colon at the beginning of a name is treated as a regular character (that is, it has no special effect).

up to the first colon character encountered

The colon is discarded in the extracted net name

VIRTUAL CONNECT NAME

Virtual Connect Name virtually connects nets that share the same name

Each name is a net name and can be optionally enclosed in quotes.

The connectivity extractor forms a virtual connection between any two labels having the same name such that the label name appears in a Virtual Connect Name specification statement in the rule file.

VIRTUAL CONNECT NAME ? == Connect all nets by name

Note that if Virtual Connect Colon YES is also specified, then Virtual Connect Name operates on names after all colon suffixes have been stripped off.

Calibre Fundamentals: Performing DRC/LVS Student Workbook

Calibre Verification User’s Manual Software Version 2019.3 Document Revision 7

Y.Liu. PDK Training - Calibre user guide [https://picture.iczhiku.com/resource/eetop/SyKTloquGiZeHMbx.pdf]

Calibre Runsets

Calibre Interactive stores a list of your most recently opened runsets in your home directory as .cgidrcdb or .cgilvsdb for Calibre Interactive DRC or LVS, respectively.

When invoked, the Calibre DRC and LVS windows automatically load the runset used when the last session was closed.

Runsets are ASCII files that set up Calibre Interactive for a Calibre run. They contain only information that differs from the default configuration of Calibre Interactive. There is a one-to-one correspondence between entry lines in the runset file and fields and button items in the Calibre Interactive user interface. Here is as example of a DRC runset:

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*drcRulesFile: rule_file *drcRulesFileLastLoad: 1009224452 *drcLayoutPaths: ./lab3.gds *drcLayoutPrimary: lab3 *drcResultsFile: ./lab3.db *drcSummaryFile: drc_report *drcRunTurbo: 0 *drcRunRemoteOn: Cluster *drcRemoteLICENSEFILEName: MGLS_LICENSE_FILE *drcRemoteLICENSEFILEValue: /scratch1/mgls/mgclicenses *drcDontWaitForLicense: 0

The runset filename opened at startup (if no runset is specified on the command line) can also be specified by setting the MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC, and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable for LVS. If these environment variables are set, they take precedence over all other runset opening behavior options.

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setenv RUNSET_DIR ../calibre
setenv MGC_CALIBRE_DRC_RUNSET_FILE $RUNSET_DIR/tsmc180nm_drc_runset
setenv MGC_CALIBRE_LVS_RUNSET_FILE $RUNSET_DIR/tsmc180nm_lvs_runset
setenv MGC_CALIBRE_PEX_RUNSET_FILE $RUNSET_DIR/tsmc180nm_pex_runset
setenv CALIBRE_DISABLE_RHEL5_WARNING 1

reference

tsmc_template. https://github.com/lnis-uofu/tsmc_template/tree/main

Calibre Verification User’s Manual

DC sweep & parametric sweep

swpuseprevic

swpuseprevic shall be yes when Hysteresis Sweep

variables with statistical distribution

Specifying Parameter Distributions Using Statistics Blocks

• process: generate random number once per MC run
• mismatch : generate a random number per instance

Article (20498356) Title: How to vary design variables with statistical distribution to be used with Monte Carlo analysis

Spectre Circuit Simulator Reference

DC operating points during TRANSIENT

Andrew Beckettover 11 years ago

Two approaches:

1. On the transient options form, there's a field called "infotimes" - specify the times at which you want it to output the dc operating point data. You can then annotate the "transient operating points" from any of these times after the simulation, or access them via the results browser.
2. Or you could get the operating point data to be continuously saved during the transient for selected devices - if so, create a file called (say) "save.scs" (make sure it has a ".scs" suffix), and put: save M1:oppoint or save M*:oppoint sigtype=dev in this file, and then reference the file via Setup->Model Libraries or as a "definition file" on Setup->Simulation Files. With this approach you can then find the operating point data for the selected devices in the results browser and plot it versus time (be cautious of saving too much though because this can generate a lot of data if you're not careful)

Regards,

Andrew.

transient options form

setup

access 1

right-click \(\to\) Annotate \(\to\) Transient Operating Points

access 2

tranOpTimed

save.scs

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save M0:oppoint

How to Save Node in DSPF?

DSPF Semantics

*|DIVIDER <divider>

<divider> represents the hierarchical pathname divider. The default hierarchical character is forward slash (/).

*|DELIMITER <delimiter>

• <delimiter> represents the delimiter character used to concatenate an instance name and pin name to form an instance pin name.
• It is also represents the delimiter character used to concatenate a net name and subnode number to form a subnode name. The default character is colon (:)

*|BUSBIT <left_busbit_char><right_busbit_char>

<left_busbit_char> and <right_busbit_char> are used at the end of an identifier of an array to select a single object of the array.

Objects which may be indexed include nets, primary pins, and instance pins

*|NET <netName> <netCap>

• <netName> represents the name of a net. It can be a user-provided net name, the name of the driving pin, or the name of the driving instance pin.
• <netCap> represents the total capacitance value in farads associated with the net. This may be comprised of capacitances to ground and capacitances to nearby wires.

*|P <pinName> <pinType> <pinCap> {<coord>}

• <pinName> represents the name of the pin.
• <pinType> represents the type of the pin. It can be any of the following: I (Input), O (Output), B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
• <pinCap> represents the capacitance value associated with the pin.
• <coord> is optional. It represents the location of the pin. Multiple pin locations are allowed.

*|S <subNodeName> {<coord>}

subnodes in the net

• <subNodeName> represents the name of the subnode. A subnode name is obtained by concatenating the net name and a subnode number using the delimiter specified in the DELIMITER statement. The default delimiter is colon (:).
• <coord> represents the location of the subnode.

*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}

describes instance pins in the net

• <instPinName> represents the name of the instance pin. An instance pin name is obtained by concatenating the <instName> and the <pinName> with a delimiting character which is specified by the DELIMITER statement
• <instName> represents the name of the instance

*|DeviceFingerDelim "@"

MOS finger delimiter

For example, M8's finger is 4, then split into 4 Devices in DSPF

MM8, MM8@2, MM8@3, MM8@4

its drain terminal will be

MM8:d, MM8@2:d, MM8@3:d, MM8@4:d

DSPF Syntax

DSPF has two sections:

• a net section

  The net section consists of a series of net description blocks. Each net description block corresponds to a net in the physical design. A net description block begins with a net statement followed by pins, instance pins, subnodes, and parasitic resistor/capacitor (R/C) components that characterize the electrical behavior of the net.

• an instance section

  The instance section consists of a series of SPICE instance statements. SPICE instance statements begin with an X.

Each file consists of hierarchical cells and interconnects only.

The DSPF format is as generic and as much like SPICE as possible. While native SPICE statements describe the R/C sections, some non-native SPICE statements complete the net descriptions. These non-native SPICE statements start with the notation "*|" to differentiate them from native SPICE statements. For native SPICE statements, a continuation line begins with the conventional "+" sign in the first column.

The native SPICE statements used by the DSPF format are listed below:

• .SUBCKT represents a subcircuit statement.
• .ENDS represents the end of a subcircuit statement.
• R represents a resistor element.
• C represents a capacitor element.
• E represents a voltage-controlled voltage sources element.
• X represents an instance of a cell;
• * represents a comment line unless it is *| or *+.
• .END is an optional statement that represents the end of a simulation session

spectre netlist

hier_delimiter="."

Used to set hierarchical delimiter. Length of hier_delimiter should not be longer than 1, except the leader escape character

spfbusdelim = busdelim_schematic [busdelim_parasitic]

This option maps the bus delimiter between schematic netlist and parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus delimiter in the schematic netlist, and optionally the bus delimiter in the parasitic file. By default, the bus delimiter of the parasitic file is taken from the parasitic file header (i.e. |BUSBIT [], |BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not defined in the parasitic file header, you need to specify it by using the spfbusdelim option in schematic netlist.

Exampel

• spfbusdelim=<> - A<1> in the schematic netlist is mapped to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is "_".
• spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1] in the DSPF file (the bus delimiter in DSPF header will be ignored).

How to Save Net voltage in DSPF

!!! follow the name of net section in DSPF - prepend to top-level devices in the schematic with X

Assume node n1...n4 are named as below in DSPF file (prefix X)

• n1

  XXosc/zip:1

• n2

  XXosc/zip:2

• n3

  XXosc/zip:3

• n4

  XXosc/zip:4

To save these nodes, you can add follow code in Definition Files

saveopt.scs

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save Xwrapper.Xvco.XXosc\/zip\:1
save Xwrapper.Xvco.XXosc\/zip\:2
save Xwrapper.Xvco.XXosc\/zip\:3
save Xwrapper.Xvco.XXosc\/zip\:4

• Escape character \ is used for hierarchical pathname divider / and subnode :

• By the way, . is hierarchical delimiter of Spectre

• Calibre always prepend one X to instance name of schematic in generated DSPF file

• The DSPF design is flatten, the DIVIDER character indicate the hierarchy

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save Xwrapper.Xvco.XXosc\/zip

The above save voltage, however I'm NOT sure which node it save.

To avoid this unsure problem, the MOS terminal may be better choice to save.

But keep in mind

• OD resistance is lumped in the FEOL model
• M0OD and above layer resistances are extracted by RC tool

How to Save Current in DSPF

!!! follow the name of instance section of DSPF - prepend to top-level devices in the schematic with XX

MOS in schematic: Xsupply.M4

MOS related information in DSPF (prefix XX in instance section):

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...
// net section
*|I XXsupply/MM4:d XXsupply/MM4 d B 0.0 

...
//instance section
XXXsupply/MM4 XXsupply/MM4:d XXsupply/MM4:g XXsupply/MM4:s XXsupply/MM4:b pch_svt_mac
+ L=... W=... nfin=...
+ ...

To save drain current:

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save Xvco.XXXsupply\/MM4:d

<instName> in *|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?} which has prefix X corresponding to schematic is NOT the instance name in DSPF. The instance name is in instance section and has prefix XX

!!! Only work for MOS terminal current. Fail to apply to block pin

Thinking about voltage and current save

• MOS device always prepend with M
• To save net voltage, take account of the prefix X of top-level device
• To save MOS terminal, take account of the prefix XX of top-level device

Post-layout netlists are created by layout extraction tools - Mentor Calibre

Differences Between DSPF and Schematic Names

• MOS Terminal Mismatch ( ‘s’ vs ‘1’)
  • Schematic: number '1' ,'2', '3','4'
  • DSPF: 'd', 'g', 's','b'

.simrc file

If DSPF files show such differences, you can set options in the .simrc file to update the save statement in the netlist so that the device names match with those in the DSPF file

Additionally, dspf_include reads all the DSPF lines starting with * (|NET, |I, *|P,*|S), while include considers all related lines as comments.

Only verified to DSPF output of Mentor Calibre

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; ensure that the netlist is recreated each time
nlReNetlistAll=t

dspfFileEnvOptions = '(
        nil
        spfFileNameMappingFormat "cdl“
        spfFileTermDelimiter “:”
        spfFileHierDelimiter “/”
        spfFileFingerDelimiter “@”
        spfFileNetMapping “mixed”
        spfFileTerminalMapping “lower”
        spfFileAddPrefixToDevice t
        spfFileAddContextSensitivePrefix t
        spfFileDeviceDefaultPrefix “X”
        spfFileDevicePrefixForTermCurrent “X”
        spfFileDevicePrefixForOppoints “X“
        
)

spfFileDevicePrefixForTermCurrent and spfFileDevicePrefixForOppoints are applicable to MOS devices only.

Both @ and __ have been observed as Finger Delimiter in single DSPF . wired...

signal name saved using wildcard operator

How to find the signal name saved using wildcard operator with save statement in spectre?

method 1

From ADE L or ADE XL Test Editor, you can use menu Simulation → Options → Analog→ Miscellaneous → Addition arguments field:dump_wildcard_info=yes

method 2

add below in netlist file or Simulation Files → Definition Files:saveopt.scs

saveopt.scs

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wcOption options dump_wildcard_info=yes

saved file

After running simulation, saved wildcard summary is save into file <netlist_file_name>.wildcard.out*

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Wildcard match summary:

save * nodes: 68
    0
    vdd!
    I0.net10
    I0.net15
    I0.I8.net30

Save and Plot terminal voltage in ADE Explorer and Assembler

.cdsinit

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envSetVal("auCore.selection" "terminalSelectionType" 'cyclic "current")

Available options are current, voltage, both or prompt and the default is current which matches the default behavior in previous releases.

• The schematic will have an ellipse annotation where a current probe has been saved,
• a V annotation for a voltage probe,
• and both annotations for both.

NOTE: Starting with IC 6.1.8 ISR5, you can now set this from Options->Plotting/Printing

Interpreting _noxref Entries

You enable gate recognition in the Calibre nmLVS-H tool. Normally, the _noxref names are internal to the gate

Saving net with hierarchy delimiter and colon (:) in net name gives WARNING (SPECTRE-8282) during simulation

Problem

I am running simulation using an spf/spef file which has a net name definition as shown in the below example:

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// input.scs
simulator lang=spice
.subckt pi_rc a z
r1 a x1a 1k
r2 x1a x1/x1:DRN 1k
cb x1/x1:DRN z 200f
.ends

xpi1 in 0 pi_rc
vdd in 0 pwl (0 0 1n 0 1.1n 10)

simulator lang=spectre
myopt options hier_ambiguity=lower
tran tran stop=2u

save xpi1.x1\/x1:DRN

The net name is x1/x1:DRN. During the simulation, the following warning is reported:

Warning from spectre during initial setup.

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WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name.
WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.

How can I save this net for plotting and measurements?

Solution

The colon (:) in the save statement specifies terminal current. So, the save statement used above is for terminal current and, hence, the warning messages are reported.

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save xpi1.x1\/x1:DRN

You need to modify the save statement as below:

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save xpi1.x1\/x1\:DRN

Now, run the simulation and the issue will be resolved.

DSPF r vs rcc

rcc

c

only c dspf give the lumped capacitance

EMIR via Voltus-Fi

general terminology

DC related

Imax in T*'s DRC document is the maximum allowed DC current, which depends on Length and Width only

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to Imax rules \[ I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau} \] Similarly, Iabsavg rules are identical to Imax rules, too \[ I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau} \]

rms

Irms is the root-mean-square of the current through a metal line, which depends w(in um), the drawn width of the metal line and \(\Delta T\), the temperature rise due to Joule heating. \[ I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2} \]

peak current

Ipeak in T*'s DRC document is the current at which a metal line undergoes excessive Joule heating and can begin to melt. Ipeak is corresponding to EM Current Analysis: max in Voltus-Fi Analysis Setup \[ I_{\text{peak}}=\max(|I(t)|) \] The limit for the peak current is \[ I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r } } \] where r is the duty ratio

The relationship between Ipeak and Ipeak_DC is merged in DRC document so that there is only Ipeak equation in document

\(I_{\text{peak,limit}}\) depends on \(t_D\), r, width and length

\[ r=\frac{t_D}{\tau} \]

where \(t_D\) is equivalent duration \[ t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}} \] or \[ r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}} \]

where the drawn width is 1um, r is 0.1

\[ 9.37*(1-0.004)/\sqrt0.1 = 29.512 \]

acpeak/pwc

It's same with max EM Current Analysis in Voltus-Fi

dynamicACPeak

This option affect how duty ratio r is computed in max and acpeak/pwc EM current Analysis

When the dynamicACPeak variable is set to true or multiPeak \[ r=\frac{T_d}{T_{\text{total}}} \]

​ where \(T_{\text{total}} = \text{EMIR time window}\)

​ \(T_d\) = the time duration in microsecond of the total "On Time" period based on IPWC

Pulse-Wise Constant EM current calculation (IPWC)

where Tau is \(T_d\) in above formula

!!! It seems that t*'s PDK don't support dynamicACPeak=true

IR drop filter layers

EM techfile (qrcTechFile) may take diffusion contact (n_odtap, p_odtap in DSPF file) into account during IR drop analysis. And these segment often dominate IR drop, but we as IC designer can NOT improve them. In general, the IR drop to M1 layer is enough and feasible.

Regular analysis statements in emir configuration

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net name=[I0.vdd I0.vss] analysis=[vmax vavg]
net name=[I0.*] analysis =[imax ivavg irms]

emirreport command

Creating reports for specific nets after simulation using emirreport

Create a new config file as shown below:

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** test.conf**
net name=[I1.VDD I1.VSS] analysis=[iavg]
net name=[I1.VBIAS] analysis=[imax]

Run emirreport on the command line using the emirdatabase (emir*.bin) and test.conf created above in

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% emirreport -64 -c test.conf -db <emirdatabase> -outdir newreport

database

simulation result

• input.emir0_bin: The first EMIR Analysis which is DC or Transient, which depends on Analyses order

• input_tran.emir0_bin: EMIR Analysis in Transient simulation

• input_dcOp.emir0_bin: EMIR Analysis in DC simulation

For example

Two results are generated input.emir0_bin and input_dcOp.emir0_bin and their reports respectly

Fix Electromigration

• Iavg

  The average value of the current, which is the effective DC current

• Irms

  Irms rule relates to the heat or Joule-heating of metal lines

• Ipeak

  The main goal of the Ipeak limits is to ensure that no thermal breakdown could occur on single overshoot events. If the signal may not have a high current density but if it has a very large peak current density, then, local melting will happen and cause failures

QA

1. Q. Why “length” column in EM results form doesn’t show extracted length, it shows “NA”.

   A. Voltus-Fi reports the “length” column only when length rules are present in the emDataFile.

2. Seeing different port currents with and without emir simulations for same dspf included in EMIR Direct method using dspf_include.

   Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the regular spectre flow. Islands patching is only performed in EMIR only

3. Setting temperature for EM analysis

   By Default, Voltus-FI and VPS pick up the current density limit for temperature at which simulation has been performed.

   By the way, Design Variables - temperature will override the temperature in Setup toolbar which is gray in ADE Explorer

   

4. AC Peak EM analysis - Voltus-Fi

   The available options within the EM current analysis section in the EMIR Analysis Setup form are:

   max / avg / avgabs / rms.

   In order to enable the AC Peak based information when loading the EM results, both max and avg should be selected when setting up the EMIR Analysis Setup.

   With this configuration, the AC Peak option becomes available and can be used.

5. How to print average, rms, and peak current of device tap in Spectre/Voltus FI EMIR analysis

   The following option enables you to save the average, rms, and peak tap currents in the emir0bin file and report it in the input.rpt_tapi file.

   1	solver report_tapi=true

   Add this option in emir.conf to enable the reporting of tap current after the Spectre EMIR simulation. The input.rpt_tapi file will be saved in the psf/raw directory.

   Note: This feature is supported in SPECTRE20.1 ISR14 and later versions.

6. emir.conf file

   emir.conf file is generated automaticaly after configure EM/IR Analysis in ADE, which is in netlist directory.

   

7. Setting default path for EM rules file in APS EMIR analysis

   • set the following environment variable in your terminal

     1	setenv EMDATAFILE < path to EM rules file>

   • or set in .cdsinit

     1	setShellEnvVar("EMDATAFILE=<path to EM rules file>")

8. Print node names and length associated with parasitic resistors in EM report file

   export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME

   • Printing the parasitic resistor length in the EM report

     1	emirutil reportLength=true

   • Printing nodes that are associated with the parasitic resistor

     1	emirutil reportNodeName=true

     Once these are enabled, you will have the Length, Node_1, and Node_2 columns printed in the EM report file, as shown below:

     

9. Is it possible to run RMS IR Drop analysis using Voltus-Fi?

   Typically, in a simulation, Power/Ground nets are always biased with a constant DC source. Hence, at present, Voltus-Fi only supports Average and Maximum (Peak) IR Drop analysis.

   For a net to have data for IR analysis(vmax/vavg), the net/node must be connected to a DC vsource or a vsource which is constant within the emir time window.

10. Can we change the time window of EM computation after the simulation completed ?

    It is not possible to modify the EM time window without re-running the full simulation.

    However you can specify several time window in the emir conf file for instance for 2 time window [0 to 10n] and [10n 20n]

    1	time window=[0 10n 10n 20n]

    In that case it will create 2 emir_bin files and then 2 different em report files according to the 2 different time windows.

11. How to print segment_W values being used to compute EM limits

    You can use the following option to print segment_W to the report:

    1	emirutil reportSegmentWidth=[true]

    This would print a Segment_w column in the report containing the segment width values used for computing the limit:

    Pass/Fail %	Resistor	layer	Current	Width	PathLength	I limit	X1	Y1	X2	Y2	J/JMAX	Res	ViaArea	No of needed vias	width/#via	J limit	Segment_w
    			(mA)	(um)	(um)		(um)	(um)	(um)	(um)			(nm^2)		(um/#)	(A/um)
    pass-100.0	Rj3292	Met1	9.02376e-12	0.1	42.72	1.10067	0.350	11.568	0.350	11.376	8.19843e-12	0.7382	NA	NA	0.0001	0.0110067	0.1

12. pathLength vs Length in EM report file

    • Length: parasitic resistor length, which is set by emirutil reportLength=true

    • pathlength: Blech length is also known as "Short length" or "Path length", and can be explained as : The longest and continuous centerline path from edge to edge among the connected wire shapes on the same metal layer.

      • For all resistors falling on this shape, same pathLength is reported.
      • After the longest path in shape has been determined the tool applies the same blech length to all the resistor falling on that shape.
      • This resistor length is NOT used in EM analysis because EM rules consider Blech length of the resistor.

      

      where W is the wire width and L is the Blech length.

      • By default the tool will sum all branches of a given metal layer. In other words the path length that will be used to look up the EM density limit is :

        Bl = $l(R1) + $l(R2) + $l(R3) + $l(R4) + $l(R5) + $l(R6) + $l(R7) + $l(R8)

        

13. How to enable EMIR analysis in PSS simualtion ?

    To enable EMIR in PSS, you have to enable DC and/or Tran simulation simultaneously. Two or more binary results file should be generated and select the file based file name or configure text file in psf directory.

    (given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)

StarRC

NETLIST_CONNECT_OPENS

Connector resistors - non-physical resistors (well or substrate layer, that is not extracted for resistance)

Maxim Ershov, Diakopto. Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why? [https://diakopto.marsdm.com/wp-content/uploads/Bizarre_results_for_P2P_resistance_and_current_density.pdf]

TRANSLATE_RETAIN_BULK_LAYERS

Behind the scenes of the SPICE Circuit Simulator

Adam Teman. Behind the Scenes of the SPICE Circuit Simulator [youtube, slides]

reference

AC Peak Analysis Using IPWC Rapid Adoption Kit (RAK) Product Version: IC6.1.8 ISR10, SPECTRE19.1 ISR5 April 2020

Posser, Gracieli & Sapatnekar, Sachin & Reis, Ricardo. (2017). Electromigration Inside Logic Cells. 10.1007/978-3-319-48899-8.

A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts of electromigration awareness," 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp. 527-532, doi: 10.1109/ASPDAC.2013.6509650.

Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling of electromigration in SRAMs.” (2014).

N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical approach to static signal electromigration analysis," Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 572-577, doi: 10.1109/DAC.1998.724536.

Blaauw, David & Oh, Chanhee & Zolotov, Vladimir & Dasgupta, Aurobindo. (2003). Static electromigration analysis for on-chip signal interconnects. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 22. 39 - 48. 10.1109/TCAD.2002.805728.

Rotaing Phasor

phasor in time domain as time elapses

A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC Oscillator," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 45-59, 2025 [pdf]

—, 30 January, SSCS Technical Webinars, [https://resourcecenter.sscs.ieee.org/education/webinars/sscs_edu_web_abidi_013026]

The oscillation \(\color{red}V_0\cos\omega_0 t\) is represented by the horizontal phasor of magnitude \(\color{red}V_0\)

\[ \boxed{\color{blue}\begin{equation} \left. \begin{aligned} C_{+} &= V_{AM} + V_{PM} \\ C_{-} &= \overline{V}_{AM} - \overline{V}_{PM} \end{aligned} \right\} \quad\Longrightarrow\quad \begin{aligned} V_{AM} &= \tfrac{1}{2}\left(C_{+} + \overline{C}_{-}\right) \\ V_{PM} &= \tfrac{1}{2}\left(C_{+} - \overline{C}_{-}\right) \end{aligned} \end{equation}} \]

AM \[ e^{j\omega_0 t}(V_0 + V_{AM}e^{jy_A}+V_{AM}e^{-jy_A}) = V_0 e^{j\omega_0 t}\cdot \left(1+\frac{2V_{AM}}{V_0}\cos y_A\right) \] modulate amplitude of the oscillation sinusoidally with frequency \(\omega_m\) and depth \(m=\frac{2V_A}{V_0}\)

PM \[ e^{j\omega_0 t}(V_0 + V_{PM}e^{jy_P}-V_{PM}e^{-jy_P})=V_0e^{j\omega_0 t}\left(1 + j\frac{2V_{PM}}{V_0}\sin y_P\right) \approx V_0e^{j\omega_0 t}\cdot e^{j\frac{2V_{PM}}{V_0}\sin y_P} \] modulate the phase of the oscillation with an index of approximately \(\frac{2V_{PM}}{V_0}\) rad

Darabi H. Radio Frequency Integrated Circuits and Systems. 2nd ed. Cambridge University Press; 2020.

"I" is the in-phase or real axis and "Q" is the quadrature or imaginary axis

• phasor rotating counter-clockwise represents the upper sideband (USB) \(e^{j(\omega_o+\omega_m )t} = e^{j\omega_o t}\color{red}e^{j\omega_m t}\)

• phasor rotating clockwise represents the lower sideband (LSB) \(e^{j(\omega_o-\omega_m )t} = e^{j\omega_o t}\color{red}e^{-j\omega_m t}\)

AM modulation

\[\begin{align} x(t)&= (1+2k\cos(\omega_m t)) \cos(\omega_0 t) = \cos(\omega_0 t) + 2k \cos(\omega_m t) \cos(\omega_0 t) \\ &=\mathcal{Re}\{e^{j\omega_0t}+k(e^{j\omega_0t}e^{j\omega_mt}+e^{j\omega_0t}e^{-j\omega_mt})\} =\mathcal{Re}\{e^{j\omega_0t}(\color{red}1+k(e^{j\omega_mt}+e^{-j\omega_mt})\color{black})\} \end{align}\]

PM modulation with incidental AM

Phasors, Modulation & Sidebands [https://www.rfinsights.com/concepts/modulation-and-sidebands/]

Single Sideband Modulation (SSB)

Phase Noise 101: Basics, Applications and Measurements [https://www.qsl.net/ab4oj/test/docs/20180720_KEE7_PhaseNoise.pdf]

Marcelino Lazaro, Communication Theory, Chapter 2 Analog Modulations [https://ocw.uc3m.es/pluginfile.php/7097/mod_page/content/15/OCW-CT-C2.pdf] [video]

Real & Complex Modulation

J OHN M. C IOFFI. Complex AWGN and Other Channels [https://cioffi-group.stanford.edu/ee379a/Lectures/L4.pdf]

Matt Guibord. TIPL 4: Real and Complex Modulation [https://www.ti.com/content/dam/videos/external-videos/en-us/2/3816841626001/5576277660001.mp4/subassets/TIPL4708-Real-and-Complex-Modulation.pdf]

\[\begin{align} X_{bb,AM,USB}(t) &= e^{j\omega_m t} = \cos(\omega_m t) + j\sin(\omega_m t)\\ X_{bb,AM,LSB}(t) &= e^{-j\omega_m t} = \cos(\omega_m t) - j\sin(\omega_m t) \end{align}\]

where \(X_{I,AM,USB}(t)=\cos(\omega_m t)\) and \(X_{Q,AM,USB}(t)=\sin(\omega_m t)\); \(X_{I,AM,USB}(t)=\cos(\omega_m t)\) and \(X_{Q,AM,USB}(t)=-\sin(\omega_m t)\);

\(X_{I,AM,USB} = X_{I,AM,LSB}\) and \(X_{Q,AM,USB} = -X_{Q,AM,LSB}\)

\[\begin{align} X_{bb,PM,USB}(t) &= e^{j\omega_m t} = \cos(\omega_m t) + j\sin(\omega_m t)\\ X_{bb,PM,LSB}(t) &= -e^{-j\omega_m t} = -\cos(\omega_m t) + j\sin(\omega_m t) \end{align}\]

where \(X_{I,PM,USB}(t)=\cos(\omega_m t)\) and \(X_{Q,PM,USB}(t)=\sin(\omega_m t)\); \(X_{I,PM,USB}(t)=-\cos(\omega_m t)\) and \(X_{Q,PM,USB}(t)=\sin(\omega_m t)\);

\(X_{I,PM,USB} = -X_{I,PM,LSB}\) and \(X_{Q,PM,USB} = X_{Q,PM,LSB}\)

Amplitude Noise

Deog-Kyoon Jeong. Topics in IC Design: 1.1 Introduction to Jitter [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%201%20-%20Jitter%20and%20Phase%20Noise.pdf]

with \(x(t) = A_0\sin (2\pi f_0 t +\phi _0)\), then \(y(t) = x(t) + n_v(t)\)

\[\begin{align} R_y(\tau) &= \mathrm{E}[y(t)y(t+\tau)] \\ &= \mathrm{E}[x(t)x(t+\tau)] + \mathrm{E}[x(t)]\mathrm{E}[n_v(t+\tau)] + \mathrm{E}[x(t+\tau)]\mathrm{E}[n_v(t)] + \mathrm{E}[n_v(t)n_v(t+\tau)]\\ &= \mathrm{E}[x(t)x(t+\tau)] + \mathrm{E}[n_v(t)n_v(t+\tau)] = R_x(\tau) + R_{n_v}(\tau) \end{align}\]

P.E. Allen - 2003. ECE 6440 - Frequency Synthesizers: Lecture 160 – Phase Noise - II [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L160-PhNoII(2UP).pdf]

PM & FM

Dan Boschen What is the difference between phase noise and frequency noise? [https://dsp.stackexchange.com/a/38230/59253]

Phase Noise and Frequency Noise are not two different noise sources, they are artifacts of the same noise, it is just a matter of what units you want to use

AM & PM Sidebands

The spectrum of the narrowband FM signal is very similar to that of an amplitude modulation (AM) signal but has the phase reversal for the other sideband component

Assume the modulation frequency of PM and AM are same, \(\omega_m\)

\[\begin{align} x(t) &= (1+A_m\cos{\omega_m t})\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= \cos(\omega_0 t + P_m \sin\omega_m t) + A_m\cos{\omega_m t}\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= X_{pm}(t) + X_{apm}(t) \end{align}\]

\(X_{pm}(t)\), PM Only \[ X_{pm}(t) = \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{P_m}{2}\cos(\omega_0 + \omega_m)t \] \(X_{apm}(t)\), AM & PM \[\begin{align} X_{apm}(t) &= A_m \cos{\omega_m t} (\cos\omega_0 t-P_m\sin\omega_m t\sin\omega_0 t) \\ &= \frac{A_m}{2}[\cos(\omega_0 + \omega_m)t + \cos(\omega_0 -\omega_m)t] - \frac{A_mP_m}{2}\sin(2\omega_m t)\sin(\omega_0 t) \\ &= \frac{A_m}{2}\cos(\omega_0 + \omega_m)t + \frac{A_m}{2}\cos(\omega_0 -\omega_m)t - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]

That is \[\begin{align} x(t) &= \cos\omega_0 t + \frac{A_m-P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{A_m+P_m}{2}\cos(\omega_0 + \omega_m)t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]

For general case, \(x(t) = (1+A_m\cos{\omega_{am} t})\cos(\omega_0 t + P_m \sin\omega_{pm} t)\), i.e., PM is \(\omega_{pm}\), AM is \(\omega_{am}\)

\[\begin{align} x(t) &= \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_{pm})t + \frac{P_m}{2}\cos(\omega_0 + \omega_{pm})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_m}{2}\cos(\omega_0 - \omega_{am})t + \frac{A_m}{2}\cos(\omega_0 + \omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}-\omega_{am})t + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}+\omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}-\omega_{am})t - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}+\omega_{am})t \end{align}\]

Therefore, sideband is asymmetric if \(\omega_{pm} = \omega_{am}\) same

Asymmetrical Linear System

Golara, S. (2015). Identifying Mechanisms of AM-PM Distortion in Large Signal Amplifiers. UCLA [https://escholarship.org/uc/item/4jp786z8]

Bob Nelson. Phase Noise 101: Basics, Applications and Measurements [[https://www.qsl.net/ab4oj/test/docs/20180720_KEE7_PhaseNoise.pdf])https://www.qsl.net/ab4oj/test/docs/20180720_KEE7_PhaseNoise.pdf]

Hegazi, Emad, Asad Abidi, and Jacob Rael. The Designer's Guide to High-purity Oscillators. [New York]: Kluwer Academic Publishers, 2005. [pdf]

Equipartition theorem

Carlo Samori, Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-VCO-short.pdf]

Enrico Rubiola. The Measurement of AM-PM Noise, and the Origin of Noise in Oscillators [https://rubiola.org/pdf-slides/2010T-ANL-Noise-and-oscillators.pdf]

Stationary noise can also be decomposed into AM and PM components, but there will always be equal amounts of both.

Narrowband Noise

in-phase & quadrature component

\[\begin{align} n(t)\cdot 2\cos(\omega_c t) &= n_I(t) + n_I(t)\cos(2\omega_c t) - n_Q(t)\sin(2\omega_c t) \\ n(t)\cdot -2\sin(\omega_c t) &= n_Q(t) - n_I(t)\sin(2\omega_c t) - n_Q(t)\cos(2\omega_c t) \end{align}\]

[https://arnabiitk.wordpress.com/wp-content/uploads/2013/02/solution-manual-for-communication-systems-haykin.pdf]

If the narrowband noise \(n(t)\) is Gaussian and its power spectral density \(S_N (t )\) is symmetric about the mid-band frequency \(f_c\), then the in-phase component \(n_I(t)\) and quadrature component \(n_Q(t)\) are statistically independent

envelope and phase components

AN-PN Conversion

G. Giust, Influence of Noise Processes on Jitter and Phase Noise Measurements [https://www.signalintegrityjournal.com/articles/800-influence-of-noise-processes-on-jitter-and-phase-noise-measurements]

—. "Methodologies for PCIe5 Refclk Jitter Analysis,", PCI-SIG Electrical Workgroup Meeting (Jan. 19, 2018)

—. How to Identify the Source of Phase Jitter through Phase Noise Plots [https://www.sitime.com/company/newsroom/blog/how-identify-source-phase-jitter-through-phase-noise-plots]

AN10072 Determine the Dominant Source of Phase Noise, by Inspection [https://www.sitime.com/support/resource-library/application-notes/an10072-determine-dominant-source-phase-noise-inspection]

• AM alone doesn't introduce jitter (e.g., doesn't change zero-crossings) nor impact phase

• AM changes slew rate, and so influences the conversion of amplitude noise to jitter when amplitude noise (BB) is present

additive & parametric noise

Enrico Rubiola. The Measurement of AM-PM Noise, and the Origin of Noise in Oscillators [https://rubiola.org/pdf-slides/2010T-ANL-Noise-and-oscillators.pdf]

—, February 7, 2025. Phase Noise - Art, Science and Experimental Methods [https://rubiola.org/pdf-lectures/Scient-Instrum-Files/!-Phase-noise.pdf]

AM & PM Noise Separation

Ken Kundert. Introduction to RF Simulation and its Application [https://designers-guide.org/analysis/rf-sim.pdf]

[https://designers-guide.org/analysis/am-pm-conv.pdf]

For AM & pacphase=90deg, complex exponentials with frequency \(\omega_m\) \[ \alpha_+(t) = je^{j\omega_m t} = e^{j(\omega_mt+\pi/2)} \] where \(A_+=j\)

Then, the complex exponentials with frequency \(-\omega_m\) shall be \[ \alpha_-(t) = [\alpha_+(t)]^* = -je^{-j\omega_m t} = e^{-j(\omega_mt+\pi/2)} \] where \(A_-=A_+^* =-j\)

\(\phi_c=0\) in above simulation

Ken Kundert. Re: Question about phase noise simulation result [https://designers-guide.org/forum/YaBB.pl?num=1309258199/15#15]

Spectre Circuit Simulator RF Analysis Theory — Measuring AM, PM and FM Conversion

sine wave + white noise

equal amounts of AM and PM noise in both USB and LSB