Reference Spur

spurs are carrier or clock frequency spectral imperfections measured in the frequency domain just like phase noise. However, unlike phase noise they are discrete frequency components.

• Spurs are deterministic

• Spur power is independent of bandwidth

• Spurs contribute bounded peak jitter in the time domain

Sources of Spurs:

• External (coupling from other noisy block) Supply, substrate, bond wires, etc.
• Internal (int-N/fractional-N operation)
  • Frac spur: Fractional divider (multi-modulus and frequency accumulation)
  • Ref. spur: PFD/charge pump/analog loop filter non-idealities, clock coupling

LPF gate leakage

For the sake of simplicity, \(V_{ctr}\) looks like a rectangular pulse with an amplitude of \(I_{CP}R_1\) and a duty ratio of (\(I_{leak}/I_{CP}\)), whose first coefficient of Fourier series is

where \(I_\text{leak} \ll I_{CP}\) is assumed

Then, the peak frequency deviation \(\Delta f\) \[ \Delta f = a_1 \cdot K_v = 2I_\text{leak}R_1 K_v \] using narrowband FM approximation, we have \[ P_\text{spur} = 20\log\left(\frac{\Delta f}{2f_\text{ref}}\right) = 20\log\left(\frac{I_\text{leak}R_1 K_v}{f_\text{ref}}\right) \]

W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]

—. Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons

[https://lpsa.swarthmore.edu/Fourier/Series/ExFS.html]

Fractional Spur

TODO 📅

Non-ideal Effects in Charge Pump

The periodic signal on VCTRL modulates the VCO, giving rise to deterministic jitter

• Timing Offsets Between Up and Dn Pulses
• Mismatch Between Charge-Pump Current Sources
• Incomplete Settling of Charge-Pump Currents
• Finite Output Resistance of the Charge Pump

Up/Dn Timing Offset

If Dn pulse arrives \(\Delta T\) after the Up pulse, the steady-state VCTRL will be slightly lower than it would be without the \(\Delta T\) mismatch so as to return the VCO's phase to match the reference clocks.

Vice versa, if If Up pulse arrives \(\Delta T\) after the Dn pulse, the steady-state VCTRL will be slightly higher than without \(\Delta T\) mismatch

Current Sources Mismatch

Incomplete Settling

W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 545-548 vol.2 [pdf]

Cowan G. Mixed-Signal CMOS for Wireline Communication: Transistor-Level and System-Level Design Considerations. Cambridge University Press; 2024

cycle slip

TODO 📅

frequency divider & phase margin

type-I PLLs

frequency divider weakens the feedback and increases the phase margin

type-II PLLs

frequency divider weakens the feedback and decrease the phase margin

Injection Locking

TODO 📅

"Topics in IC(Wireline Transceiver Design): Lec 4 - Injection Locked Oscillators" [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%204%20-%20Injection%20Locked%20Oscillators.pdf]

Cowan, Glenn. (2024). Mixed-Signal CMOS for Wireline Communication: Transistor-Level and System-Level Design Considerations. 10.1017/9781108779791.

PFD Deadzone

Dead zone induced by incomplete settling of charge-pump currents

This situation can be avoided by adding additional delay to the AND gate in the PFD

Sam Palermo, "Lecture 4: Phase Detector Circuit" [https://people.engr.tamu.edu/spalermo/ecen620/lecture04_ee620_phase_detectors.pdf]

Temperature compensation for VCO

Temperature compensation for the VCO oscillation frequency is a critical issue

TODO 📅

DCC & IQ Calibration

TODO 📅

Bob Lefferts, Navraj Nandra. SNUG Israel 2007 [https://picture.iczhiku.com/resource/eetop/whKYwQorwYoPUVbm.pdf]

multi-modulus divider

TODO 📅

Duty-cycle correction circuit

The amount of correction can be set by intentional injection of an offset current into the summing input node of INV, threshold-adjustable inverter

Note that the change to the threshold is opposite in direction to the change to INV

increasing DC of input signal is equivalent to lower down the threshold of INV

voltage at INV1 will increased by: \[ \frac{\Delta V_{DAC} - \Delta {INV1}}{R_{DAC}} = \frac{\Delta {INV1} +A_0 \Delta {INV1}}{R_{F}} \] therefore \[ \Delta {INV1} = \Delta V_{DAC} \cdot \frac{R_F}{R_F+(A_0+1)R_{DAC}} \approx \Delta V_{DAC} \cdot \frac{R_F}{A_0R_{DAC}} \]

If \(R_{DAC} = R_F\) \[ \Delta {INV1}\approx \frac{\Delta V_{DAC}}{A_0} \]

C. Menolfi et al., "A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS," 2018 IEEE International Solid-State Circuits Conference - (ISSCC) [https://sci-hub.se/https://doi.org/10.1109/ISSCC.2018.8310205]

Auto-tracking high-Q BPF

The PLL is the only device that performs auto-tracking band-pass filtering with high-quality factor Q and wide tunability

charge pump with amplifier

Young, I.A., Greason, J.K., Wong, K.L.: A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors. IEEE Journal of Solid-State Circuits 27(11), 1599– 1607 (1992) [https://people.engr.tamu.edu/spalermo/ecen620/pll_intel_young_jssc_1992.pdf]

Johnson, M., Hudson, E.: A variable delay line PLL for CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits 23(10), 1218–1223 (1988) [https://sci-hub.se/10.1109/4.5947]

Sam Palermo, Lecture 5: Charge Pump Circuits, ECEN620: Network Theory Broadband Circuit Design Fall 2024 [https://people.engr.tamu.edu/spalermo/ecen620/lecture05_ee620_charge_pumps.pdf]

"gain" of the PFD

Fractional-N

1. Dither Feedback Divider Ratio by a delta-sigma modulator

2. Frequency Accumulation

Charge Pump Current noise

consider only thermal noise in the analysis that follows

Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]

M.H. Perrott, M.D. Trott, C.G. Sodini, "A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis", JSSC, vol 38, no 8, pp 1028-1038, Aug 2002. [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]

why 2nd loop filter ?

PI (proportional - integral) Loop Filter

Switched Capacitor Banks

Q: why \(R_b\) ?

A: TODO 📅

Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in RF/millimeter-wave oscillators for 5G communications." PhD diss., 2019.

S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010, pp. 1903-1906

SSC intuition

Due to \(f= K_{vco}V_{ctrl}\), its derivate to \(t\) is

\[ \frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt} \]

For chargepump PLL, \(dV_{ctrl} = \frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[ \frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C} \]

Phase Interpolator (PI)

!!! Clock Edges

And for a phase interpolator, you need those reference clocks to be completely the opposite. Ideally they would be triangular shaped

four input clocks given by the cyan, black, magenta, red

John T. Stonick, ISSCC 2011 tutorial. "DPLL Based Clock and Data Recovery" [https://www.nishanchettri.com/isscc-slides/2011%20ISSCC/TUTORIALS/ISSCC2011Visuals-T5.pdf]

kink problem

B. Razavi, "The Design of a Phase Interpolator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 15, Issue. 4, pp. 6-10, Fall 2023.(https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2023.pdf)

DIV 1.5

TODO 📅

Xu, Haojie & Luo, Bao & Jin, Gaofeng & Feng, Fei & Guo, Huanan & Gao, Xiang & Deo, Anupama. (2022). A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs. 69. 4238 - 4242. [https://www.researchgate.net/publication/382240520_A_Flexible_073-155_GHz_Single_LC_VCO_Clock_Generator_in_12_nm_CMOS]

False locking

TODO 📅

• divider failure
• even-stage ring oscillator ( multipath ring oscillators)
• DLL: harmonic locking, stuck locking

clock edge impact

ck1 is div2 of ck0

• edge of ck0 is affected differently by ck1

• edge of ck1 is affected equally by ck0

clock distribution

TODO 📅

X. Mo, J. Wu, N. Wary and T. C. Carusone, "Design Methodologies for Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021

Feedback Dividers

• Large values of N lowers the loop BW which is bad for jitter

Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF, Analog and Mixed Signal Circuits and Systems. Aalborg: River Publishers, 2017.

VCO varactor

Two methods: 1. pss + pac; 2. pss+psp

PSS + PAC

pss time domain

using the 0-harmonic

PSS + PSP

using Y11 of psp

results

which are same

clock gating

PLL Type & Order

Type: # of integrators within the loop

Order: # of poles in the closed-loop transfer function

Type \(\leq\) Order

Why Type 2 PLL ?

1. That is, to have a wide bandwidth, a high loop gain is required
2. More importantly, the type 1 PLL has the problem of a static phase error for the change of an input frequency

Type 1 PLL with input phase step \(\Delta \phi \cdot u(t)\) \[\begin{align} \Delta \phi\cdot u(t) - K\int_0^{t}\phi _e (\tau)d\tau &= \phi _e (t) \\ \phi _e (0) &= \Delta \phi \end{align}\]

we obtain \(\phi _e (t) = \Delta \phi \cdot e^{-Kt}\cdot u(t)\)

and \(\phi _e(\infty) = 0\)

AC-coupled buffer

Since duty-cycle error is high frequency component, the high-pass filter suppresses the duty-cycle error propagating to the output

• The AC-coupling capacitor blocks the low-frequency component of the input
• The feedback resistor sets common mode voltage to the crossover voltage

Bae, Woorham; Jeong, Deog-Kyoon: 'Analysis and Design of CMOS Clocking Circuits for Low Phase Noise' (Materials, Circuits and Devices, 2020)

Casper B, O’Mahony F. Clocking analysis, implementation and measurement techniques for high-speed data links: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers. 2009;56(1):17–39

Divider phase noise & jitter

• Multiplying the frequency of a signal by a factor of N using an ideal frequency multiplier increases the phase noise of the multiplied signal by \(20\log(N)\) dB.
• Similarly dividing a signal frequency by N reduces the phase noise of the output signal by \(20\log(N)\) dB

The sideband offset from the carrier in the frequency multiplied/divided signal is the same as for the original signal.

The 20log(N) Rule

If the carrier frequency of a clock is divided down by a factor of \(N\) then we expect the phase noise to decrease by \(20\log(N)\).The primary assumption here is a noiseless conventional digital divider.

The \(20\log(N)\) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same.

What About Phase Jitter?

We integrate SSB phase noise L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for “brick wall” integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.

Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise, L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant.

Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.

[Timing 101: The Case of the Jitterier Divided-Down Clock, Silicon Labs]

[How division impacts spurs, phase noise, and phase]

[Phase Noise Theory: Ideal Frequency Multipliers and Dividers]

PLL bandwidth test

A step response test is an easy way to determine the bandwidth.

Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected response at the output of the loop filter as shown in this block diagram

a first order loop \[ BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)} \] Where \(BW\) is the 3 dB bandwidth in Hz and \(𝑡\)​ is the 10%/90% rise or fall time.

For second order loops with a typical damping factor of 0.7 this relationship is closer to: \[ BW = \frac{0.33}{t}\space\space\space\space \text{(second order system, damping factor = 0.7)} \]

[How can I experimentally find the bandwidth of my PLL?, https://dsp.stackexchange.com/a/73654/59253]

reference

Dennis Fischette, Frequently Asked PLL Questions [https://www.delroy.com/PLL_dir/FAQ/FAQ.htm]

Ian Galton, ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]

Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T6Visuals.pdf]

The Problem of "Sinusoids Running Around Loops"

The representative of Fourier transform \(\frac{1}{j\omega+j\omega_0}\) back in the time domain \(e^{-j\omega_0 t}\) is infinite extent in time

Running around a loop, chasing one's tail — these are thought pictures that only work in a discretized, time-sequenced conceptual framework that has a beginning and an end

Fix in your mind that oscillations are a type of resonance

Dawson, Joel L. A Guide to Feedback Theory. Cambridge: Cambridge University Press, 2021.

Nyquist's Stability Criterion

TODO 📅

[Michael H. Perrott, High Speed Communication Circuits and Systems, Lecture 15 Integer-N Frequency Synthesizers]

RMS for non-sinusoidal periodic function

Nyquist rate & Nyquist frequency

• Nyquist rate

  The Nyquist rate is the minimum sample rate required to accurately measure a signal's highest frequency. It's equal to twice the highest frequency of the signal

• Nyquist frequency

  The Nyquist frequency is the highest frequency that can be represented without aliasing in a discrete signal. It's equal to half the sampling frequency

Oversampling Ratio (OSR) is defined as the ratio of the Nyquist frequency \(f_s/2\) to the signal bandwidth \(B\) given by \(\text{OSR}=f_s/2B\)

Summation & Integration

both are NOT stable

sinc function

where \(W\) is sampling frequency in Hz

sinc function is square integrable but not absolutely integrable

Zero-order hold (ZOH)

\[ h_{ZOH}(t) = \text{rect}(\frac{t}{T} - \frac{1}{2}) = \left\{ \begin{array}{cl} 1 & : \ 0 \leq t \lt T \\ 0 & : \ \text{otherwise} \end{array} \right. \] The effective frequency response is the continuous Fourier transform of the impulse response \[ H_{ZOH}(f) = \mathcal{F}\{h_{ZOH}(t)\} = T\frac{1-e^{j2\pi fT}}{j2\pi fT}=Te^{-j\pi fT}\text{sinc}(fT) \] where \(\text{sinc}(x)\) is the normalized sinc function \(\frac{\sin(\pi x)}{\pi x}\)

The Laplace transform transfer function of the ZOH is found by substituting \(s=j2\pi f\) \[ H_{ZOH}(s) = \mathcal{L}\{h_{ZOH}(t)\}=\frac{1-e^{-sT}}{s} \]

frequency convention

• radian frequency \(\omega_0\) in rad/s
• cyclic frequency \(f_0\) in Hz

Energy signals vs Power signal

Topic 5 Energy & Power Signals, Correlation & Spectral Density [https://www.robots.ox.ac.uk/~dwm/Courses/2TF_2021/N5.pdf]

modulation & demodulation

Hossein Hashemi, RF Circuits, [https://youtu.be/0f3yZMvD2Jg?si=2c1Q4y6WJq8Jj8oN]

channel loss

• skin effect loss
• dielectric loss

phase delay & group delay

• Phase delay directly measures the device or system time delay of individual sinusoidal frequency components in the steady-state conditions.
• In the ideal case the envelope delay is equal to the phase delay
• envelope delay is a more sensitive measure of aberrations than phase delay

phase delay

If the phase delay peaks (exceeds the low-frequency value) you can expect to see high-frequency components late in the step response. This causes ringing.

group delay

steady-state at this frequency is a polarity flip; a 180 degrees phase shift; which is a transfer function of H(s)=-1. \[ H(s) = e^{j\pi} \] That is \(\phi(\omega) = \pi\) \[ \tau_p = \frac{\pi}{\omega} \] and \[ \tau_g = \frac{\partial \pi}{\partial \omega}=0 \]

Hollister, Allen L. Wideband Amplifier Design. Raleigh, NC: SciTech Pub., 2007.

Pupalaikis, Peter. (2006). Group Delay and its Impact on Serial Data Transmission and Testing. [https://cdn.teledynelecroy.com/files/whitepapers/group_delay-designcon2006.pdf]

[Pupalaikis et al., “Eye Patterns in Scopes”, DesignCon, Santa Clara CA, 2005https://cdn.teledynelecroy.com/files/whitepapers/eye_patterns_in_scopes-designcon_2005.pdf]

Starič, P. & Margan, E.. (2006). Wideband Amplifiers. 10.1007/978-0-387-28341-8.

Alan V. Oppenheim, Alan S. Willsky, and S. Hamid Nawab. 1996. Signals & systems (2nd ed.). Prentice-Hall, Inc., USA.

Phase delay vs group delay: Common misconceptions. [https://audiosciencereview.com/forum/index.php?threads/phase-delay-vs-group-delay-common-misconceptions.39591/]

Feedback Rearrange

The closed loop transfer function of \(Y/X\) and \(Y_1/X_1\) are almost same, except sign

\[\begin{align} \frac{Y}{X} &= +\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \\ \frac{Y_1}{X_1} &= -\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \end{align}\]

define \(-Y_1=Y_n\), then \[ \frac{Y_n}{X_1} = \frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \]

Saurabh Saxena, IIT Madras. CICC2022 Clocking for Serial Links - Frequency and Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery

Convolution of probability distributions

The probability distribution of the sum of two or more independent random variables is the convolution of their individual distributions.

Thermal noise

Thermal noise in an ideal resistor is approximately white, meaning that its power spectral density is nearly constant throughout the frequency spectrum.

When limited to a finite bandwidth and viewed in the time domain, thermal noise has a nearly Gaussian amplitude distribution

Barkhausen criteria

Barkhausen criteria are necessary but not sufficient conditions for sustainable oscillations

it simply "latches up" rather than oscillates

NRZ Bandwidth

Maxim Integrated,NRZ Bandwidth - HF Cutoff vs. SNR [https://pdfserv.maximintegrated.com/en/an/AN870.pdf]

\(0.35/T_r\)

\(0.5/T_r\)

TODO 📅

System Type

Control of Steady-State Error to Polynomial Inputs: System Type

control systems are assigned a type number according to the maximum degree of the input polynominal for which the steady-state error is a finite constant. i.e.

• Type 0: Finite error to a step (position error)
• Type 1: Finite error to a ramp (velocity error)
• Type 2: Finite error to a parabola (acceleration error)

The open-loop transfer function can be expressed as \[ T(s) = \frac{K_n(s)}{s^n} \]

where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),

The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform is \[ R(s) = \frac{1}{s^{k+1}} \]

Then the equation for the error is simply \[ E(s) = \frac{1}{1+T(s)}R(s) \]

Application of the Final Value Theorem to the error formula gives the result

\[\begin{align} \lim _{t\to \infty} e(t) &= e_{ss} = \lim _{s\to 0} sE(s) \\ &= \lim _{s\to 0} s\frac{1}{1+\frac{K_n(s)}{s^n}}\frac{1}{s^{k+1}} \\ &= \lim _{s\to 0} \frac{s^n}{s^n + K_n}\frac{1}{s^k} \end{align}\]

• if \(n > k\), \(e=0\)
• if \(n < k\), \(e\to \infty\)
• if \(n=k\)
  • \(e_{ss} = \frac{1}{1+K_n}\) if \(n=k=0\)
  • \(e_{ss} = \frac{1}{K_n}\) if \(n=k \neq 0\)​

where we define \(K_n(0) = K_n\)

Spectral content of NRZ

Lecture 26 Autocorrelation Functions of Random Binary Processes [https://bpb-us-w2.wpmucdn.com/sites.gatech.edu/dist/a/578/files/2003/12/ECE3075A-26.pdf]

Lecture 32 Correlation Functions & Power Density Spectrum, Cross-spectral Density [https://bpb-us-w2.wpmucdn.com/sites.gatech.edu/dist/a/578/files/2003/12/ECE3075A-32.pdf]

sinusoidal steady-state and frequency response

Due to KCL and \(u(t)=e^{j\omega t}\) and \(y(t)=H(j\omega)e^{j\omega t}\), we have ODE:

\[\begin{align} \frac{u(t) - y(t)}{R} = C \frac{dy(t)}{dt} \\ e^{j\omega t} - H(j\omega) e^{j\omega t} = H(j\omega)\cdot j\omega e^{j\omega t} \\ \end{align}\]

\(H(j\omega)\) is obtained as below \[ H(j\omega) = \frac{1}{1+j\omega} \]

Different Variants of the PSD Definition

In the practice of engineering, it has become customary to use slightly different variants of the PSD definition, depending on the particular application or research field.

• Two-Sided PSD, \(S_x(f)\)

  this is a synonym of the PSD defined as the Fourier Transform of the autocorrelation.

• One-Sided PSD, \(S'_x(f)\)

  this is a variant derived from the two-sided PSD by considering only the positive frequency semi-axis.

  To conserve the total power, the value of the one-sided PSD is twice that of the two-sided PSD \[ S'_x(f) = \left\{ \begin{array}{cl} 0 & : \ f \geq 0 \\ S_x(f) & : \ f = 0 \\ 2S_x(f) & : \ f \gt 0 \end{array} \right. \]

Note that the one-sided PSD definition makes sense only if the two-sided is an even function of \(f\)

If \(S'_x(f)\) is even symmetrical around a positive frequency \(f_0\), then two additional definitions can be adopted:

• Single-Sideband PSD, \(S_{SSB,x}(f)\)

  This is obtained from \(S'_x(f)\) by moving the origin of the frequency axis to \(f_0\) \[ S_{SSB,x}(f) =S'_x(f+f_0) \] This concept is particularly useful for describing phase or amplitude modulation schemes in wireless communications, where \(f_0\) is the carrier frequency.

  Note that there is no difference in the values of the one-sided versus the SSB PSD; it is just a pure translation on the frequency axis.

• Double-Sideband PSD, \(S_{DSB,x}(f)\)

  this is a variant of the SSB PSD obtained by considering only the positive frequency semi-axis.

  As in the case of the one-sided PSD, to conserve total power, the value of the DSB PSD is twice that of the SSB \[ S_{DSB,x}(f) = \left\{ \begin{array}{cl} 0 & : \ f \geq 0 \\ S_{SSB,x}(f) & : \ f = 0 \\ 2S_{SSB,x}(f) & : \ f \gt 0 \end{array} \right. \]

Note that the DSB definition makes sense only if the SSB PSD is even symmetrical around zero

Poles and Zeros of transfer function

poles

\[ H(s) = \frac{1}{1+s/\omega_0} \]

magnitude and phase at \(\omega_0\) and \(-\omega_0\) \[\begin{align} H(j\omega_0) &= \frac{1}{1+j} = \frac{1}{\sqrt{2}}e^{-j\pi/4} \\ H(-j\omega_0) &= \frac{1}{1-j} = \frac{1}{\sqrt{2}}e^{j\pi/4} \end{align}\]

system response \(y(t)\) of input \(\cos(\omega_0 t)\), note \(\cos(\omega_0t) = \frac{1}{2}(e^{j\omega_0 t} + e^{-j\omega_0 t})\) \[\begin{align} y(t) &= H(j\omega_0)\cdot \frac{1}{2}e^{j\omega_0 t} + H(-j\omega_0)\cdot \frac{1}{2}e^{-j\omega_0 t} \\ &= \frac{1}{\sqrt{2}}\cos(\omega_0t-\pi/4) \end{align}\]

\(\cos(\omega_0 t)\), with frequency same with pole DON'T have infinite response

That is, pole indicate decrease trending

zeros

similar with poles, \(\cos(\omega_0 t)\), with frequency same with zero DON'T have zero response

\[ H(s) = 1+s/\omega_0 \]

magnitude and phase at \(\omega_0\) and \(-\omega_0\) \[\begin{align} H(j\omega_0) &= 1+j = \sqrt{2}e^{j\pi/4} \\ H(-j\omega_0) &= 1-j = \sqrt{2}e^{-j\pi/4} \end{align}\]

system response \(y(t)\) of input \(\cos(\omega_0 t)\), note \(\cos(\omega_0t) = \frac{1}{2}(e^{j\omega_0 t} + e^{-j\omega_0 t})\) \[\begin{align} y(t) &= H(j\omega_0)\cdot \frac{1}{2}e^{j\omega_0 t} + H(-j\omega_0)\cdot \frac{1}{2}e^{-j\omega_0 t} \\ &= \sqrt{2}\cos(\omega_0t+\pi/4) \end{align}\]

baud rate

symbol rate, modulation rate or baud rate is the number of symbol changes per unit of time.

• Bit rate refers to the number of bits transmitted between two devices per unit of time
• The baud or symbol rate refers to the number of symbols that can be sent in the same amount of time

reference

Stephen P. Boyd. EE102 Lecture 10 Sinusoidal steady-state and frequency response [https://web.stanford.edu/~boyd/ee102/freq.pdf]

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018. Feedback Control of Dynamic Systems (8th Edition) (8th. ed.). Pearson.

Inter-Symbol Interference (or Leaky Bits) [http://blog.teledynelecroy.com/2018/06/inter-symbol-interference-or-leaky-bits.html]

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization. URL:[https://www.controlpaths.com/articles/an001_designing_iir_biquad_filter_bilinear/]

Frequency warping using the bilinear transform. URL:[https://www.controlpaths.com/2022/05/09/frequency-warping-using-the-bilinear-transform/]

Digital control loops. Theoretical approach. URL:[https://www.controlpaths.com/2022/02/28/digital-control-loops-theoretical-approach/]

Simulation of DSP algorithms in Verilog. URL:[https://www.controlpaths.com/2023/05/20/simulation-of-dsp-algorithms-in-verilog/]

Implementing a digital biquad filter in Verilog. URL:[https://www.controlpaths.com/2021/04/19/implementing-a-digital-biquad-filter-in-verilog/]

Implementing a FIR filter using folding. URL:[https://www.controlpaths.com/2021/05/17/implementing-a-fir-filter-using-folding/]

Oppenheim, Alan V. and Cram. “Discrete-time signal processing : Alan V. Oppenheim, 3rd edition.” (2011).

Extras: PID Compensator with Bilinear Approximation URL:[https://ctms.engin.umich.edu/CTMS/index.php?aux=Extras_PIDbilin]

noise power at filter output

Chembian Thambidurai, "Comparison Of Noise Power At Lowpass Filter Output" [link]

—, "On Noise Power At The Bandpass Filter Output" [link]

—, "Integrated Power of Thermal and Flicker Noise" [link]

TODO 📅

Pulsed Noise Signals

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

Above, the output of the multiplier be \(y(t)\) is passed through a ideal brick wall low pass filter with a bandwidth of \(f_0/2\)

When a random signal is multiplied by a pulse function, the resulting signal becomes a cyclo-stationary random process.

As rule of thumb, the spectrum of such a pulsed noise signal

• thermal noise is multiplied by \(D\)

• flicker noise is multiplied by \(D^2\),

where \(D\) is the duty cycle of the pulse signal

banlimited input

wideband white noise input

flicker noise input

with \(S_x(f)=\frac{K_f}{f}\)

Assuming \(\Delta f \ll f_0\)

Sampling Noise

Chembian Thambidurai, "Noise, Sampling and Zeta Functions" [link]

A random signal \(v_n(t)\) is sampled using an ideal impulse sampler

TODO 📅

Aperture Jitter & ADC SNR

Chembian Thambidurai, "SNR of an ADC in the presence of clock jitter" [https://www.linkedin.com/posts/chembiyan-t-0b34b910_adcsnrjitter-activity-7171178121021304833-f2Wd?utm_source=share&utm_medium=member_desktop]

Unlike the quantization noise and the thermal noise, the impact of the clock jitter on the ADC performance depends on the input signal properties like its PSD

The error between the ideal sampled signal and the sampling with clock jitter can be treated as noise and it results in the degradation of the SNR of the ADC

For sinusoid input:

K. Tyagi and B. Razavi, "Performance Bounds of ADC-Based Receivers Due to Clock Jitter," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 5, pp. 1749-1753, May 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/KT_TCAS_2023.pdf]

N. Da Dalt, M. Harteneck, C. Sandner and A. Wiesbauer, "On the jitter requirements of the sampling clock for analog-to-digital converters," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002 [https://sci-hub.se/10.1109/TCSI.2002.802353]

M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of high-speed sampling systems," in IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, Feb. 1990 [https://sci-hub.se/10.1109/4.50307]

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import numpy as np
import matplotlib.pyplot as plt

ENOB = 8
fin = np.logspace(8, 11, 60)

# quantization noise: SNR = 6.02*ENOB + 1.76 dB
Ps_PnQ = 10**((6.02*ENOB + 1.76)/10)
PnQ = 1/Ps_PnQ

# jitter noise: SNR = 6 - 20log10(2*pi*fin*Jrms) dB @ref. Chembiyan T
Jrms_list = [25e-15, 50e-15, 100e-15, 250e-15, 500e-15, 1000e-15]
for Jrms in Jrms_list:
    # Ps_PnJ_lcl = 10**((6-20*np.log10(2*np.pi*fin*Jrms))/10)     # ref. Chembiyan T
    Ps_PnJ_lcl = 10**((0 - 20 * np.log10(2 * np.pi * fin * Jrms)) / 10)  # ref. Nicola Da Dalt
    PnJ_lcl = 1/Ps_PnJ_lcl
    SNR_lcl = 10*np.log10(1/(PnQ+PnJ_lcl))
    plt.plot(fin, SNR_lcl, label=r'$\sigma_{jitter}$'+'='+str(int(Jrms*1e15))+'fs')

plt.xscale('log')
plt.ylim([0, 55])
plt.xlabel(r'$f_{in}$ [Hz]')
plt.ylabel(r'SNR [dB]')
plt.grid(which='both')
# plt.title(r'ref. Chembiyan T')
plt.title(r'ref. Nicola Da Dalt')
plt.legend()
plt.show()

i.e. N. Da Dalt's

Ayça Akkaya, "High-Speed ADC Design and Optimization for Wireline Links" [https://infoscience.epfl.ch/server/api/core/bitstreams/96216029-c2ff-48e5-a675-609c1e26289c/content]

ISF for Oscillators

TODO 📅

Sampled Thermal Noise

The aliasing of the noise, or noise folding, plays an important role in switched-capacitor as it does in all switched-capacitor filters

Assume for the moment that the switch is always closed (that there is no hold phase), the single-sided noise density would be

\(v_s[n]\) is the sampled version of \(v_{RC}(t)\), i.e. \(v_s[n]= v_{RC}(nT_C)\) \[ S_s(e^{j\omega}) = \frac{1}{T_C} \sum_{k=-\infty}^{\infty}S_{RC}(j(\frac{\omega}{T_C}-\frac{2\pi k}{T_C})) \cdot d\omega \] where \(\omega \in [-\pi, \pi]\), furthermore \(\frac{d\omega}{T_C}= d\Omega\) \[ S_s(j\Omega) = \sum_{k=-\infty}^{\infty}S_{RC}(j(\Omega-k\Omega_s)) \cdot d\Omega \]

The noise in \(S_{RC}\) is a stationary process and so is uncorrelated over \(f\) allowing the \(N\) rectangles to be combined by simply summing their noise powers

where \(m\) is the duty cycle

Below analysis focus on sampled noise

• Calculate autocorrelation function of noise at the output of the RC filter
• Calculate the spectrum by taking the discrete time Fourier transform of the autocorrelation function

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF [https://designers-guide.org/analysis/sc-filters.pdf]

Pavan, Schreier and Temes, "Understanding Delta-Sigma Data Converters, Second Edition" ISBN 978-1-119-25827-8

Boris Murmann, EE315B VLSI Data Conversion Circuits, Autumn 2013

- Noise Analysis in Switched-Capacitor Circuits, ISSCC 2011 / tutorials [slides, transcript]

Tania Khanna, ESE568 Fall 2019, Mixed Signal Circuit Design and Modeling URL: https://www.seas.upenn.edu/~ese568/fall2019/

Matt Pharr, Wenzel Jakob, and Greg Humphreys. 2016. Physically Based Rendering: From Theory to Implementation (3rd. ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.

Bernhard E. Boser . Advanced Analog Integrated Circuits Switched Capacitor Gain Stages [https://people.eecs.berkeley.edu/~boser/courses/240B/lectures/M05%20SC%20Gain%20Stages.pdf]

R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. Wiley-Interscience, 1986

Trevor Caldwell, Lecture 9 Noise in Switched-Capacitor Circuits [http://individual.utoronto.ca/trevorcaldwell/course/NoiseSC.pdf]

Christian-Charles Enz. High precision CMOS micropower amplifiers [pdf]

reference

David Herres, The difference between signal under-sampling, aliasing, and folding URL: https://www.testandmeasurementtips.com/the-difference-between-signal-under-sampling-aliasing-and-folding-faq/

Pharr, Matt; Humphreys, Greg. (28 June 2010). Physically Based Rendering: From Theory to Implementation. Morgan Kaufmann. ISBN 978-0-12-375079-2. Chapter 7 (Sampling and reconstruction)

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition

活塞环(Piston Ring)

马力 vs 扭矩

扭矩 = 力 x 力臂 (T=FL)

悬挂 (vehicle suspension)

变速箱 (transmission)

变速箱实现转速和扭矩的转换：低档扭矩大，转速慢； 高档扭矩小，转速慢

发动机小齿轮和变速箱大齿轮啮合处的力相同（力的作用是相互的），但是力臂不同，于是实现了扭矩转换

阿克曼转向几何 (Ackerman steering geometry)

缸内直喷 (direct injection)

• 歧管喷油
• 缸内直喷
  • 省油
  • 动力更强
  • 喷油时间自由度大

This cascode compensation topology is popularly known as ahuja compensation

The cause of the positive zero is the feedforward current through \(C_m\).

To abolish this zero, we have to cut the feedforward path and create a unidirectional feedback through \(C_m\).

1. Adding a resistor(nulling resistor) is one way to mitigate the effect of the feedforward current.

2. Another approach uses a current buffer cascode to pass the small-signal feedback current but cut the feedforward current

People name this approach after the author Ahuja

The benefits of Ahuja compensation over Miller compensation are severa

• better PSRR

• higher unity-gain bandwidth using smaller compensation capacitor

• ability to cope better with heavy capacitive and resistive loads

Miller's approximation

Right-Half-Plane Zero

\[ \left[(v_i - v_o)sC_c - g_m v_i\right]R_o = v_o \] Then \[ \frac{v_o}{v_i} = -g_mR_o\frac{1-s\frac{C_c}{g_m}}{1+sR_oC_c} \] right-half-plane Zero \(\omega _z = \frac{g_m}{C_c}\)

Equivalent cap

The amplifier gain magnitude \(A_v = g_m R_o\) \[ I_\text{c,in} = (v_i - v_o)sC_c \] Then \[\begin{align} I_\text{c,in} &= (v_i + A_v v_i)sC_c \\ & = v_i s (1+A_v)C_c \end{align}\]

we get \(C_\text{in,eq}= (1+A_v)C_c\simeq A_vC_c\)

Similarly \[\begin{align} I_\text{c,out} &= (v_o - v_i)sC_c \\ & = v_o s (1+\frac{1}{A_v})C_c \end{align}\]

we get \(C_\text{out,eq}= (1+\frac{1}{A_v})C_c\simeq C_c\)

cascode compensation

Of course, , if the capacitance at the gate of \(M_1\) is taken into account, pole splitting is less pronounced.

including \(r_\text{o2}\)

\[ \frac{V_{out}}{I_{in}} \approx \frac{-g_{m1}R_SR_L(g_{m2}+C_Cs)}{\frac{R_S+r_\text{o2}}{r_\text{o2}}R_LC_LC_Cs^2+g_{m1}g_{m2}R_LR_SC_Cs+g_{m2}} \] The poles as

\[\begin{align} \omega_{p1} &\approx \frac{1}{g_{m1}R_LR_SC_c} \\ \omega_{p2} &\approx \frac{g_{m2}R_Sg_{m1}}{C_L}\frac{r_\text{o2}}{R_S+r_\text{o2}} \end{align}\]

and zero is not affected, which is \(\omega_z =\frac{g_{m2}}{C_C}\)

the above model simulation result is shown below

the zero is located between two poles

take into the capacitance at the gate of \(M_1\) and all other second-order effect

intuitive analysis of zero

miller compensation

• zero in the right half plane \[ g_\text{m1}V_P = sC_c V_P \]

cascode compensation

• zero in the left half plane \[ g_\text{m2}V_X = - sC_c V_X \]

How to Mitigate Impact of Zero

dominant pole \[ \omega_\text{p,d} = \frac {1} {R_\text{eq}g_\text{m9}R_{L}C_{c}} \] first nondominant pole \[ \omega_\text{p,nd} = \frac {g_\text{m4}R_\text{eq}g_\text{m9}} {C_L} \] zero \[ \omega_\text{z} = (g_\text{m4}R_\text{eq})(\frac {g_\text{m9}} {C_c}) \] a much greater magnitude than \(g_\text{m9}/C_C\)

Lectures

EE 240B: Advanced Analog Circuit Design, Prof. Bernhard E. Boser [OTA II, Multi-Stage]

Papers

B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers," in IEEE Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983, doi: 10.1109/JSSC.1983.1052012.

D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range," in IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984, doi: 10.1109/JSSC.1984.1052246.

Abo, Andrew & Gray, Paul. (1999). A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter.

Book's chapters

Design of analog CMOS integrated circuits, Behzad Razavi

• 10.5 Compensation of Two-Stage Op Amps
• 10.7 Other Compensation Techniques

Analog Design Essentials, Willy M.C. Sansen

• chapter #5 Stability of operational amplifiers - Compensation of positive zero

Analysis and Design of Analog Integrated Circuits 5th Edition, Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer

• 9.4.3 Two-Stage MOS Amplifier Compensation

CMOS Analog Circuit Design 3rd Edition, Phillip E. Allen, Douglas R. Holberg

• 6.2.2 Miller Compensation of the Two-Stage Op Amp

reference

B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers," IEEE 1. Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983.

U. Dasgupta, "Issues in "Ahuja" frequency compensation technique", IEEE International Symposium on Radio-Frequency Integration Technology, 2009.

R. 1. Reay and G. T. A. Kovacs, "An unconditionally stable two-stage CMOS amplifier," IEEE 1. Solid-State Circuits, vol. 30, no. 5, pp. 591- 594, May 1995.

A. Garimella and P. M. Furth, "Frequency compensation techniques for op-amps and LDOs: A tutorial overview," 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp. 1-4, doi: 10.1109/MWSCAS.2011.6026315.

H. Aminzadeh, R. Lotfi and S. Rahimian, "Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers," 2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 264-267, doi: 10.1109/ICECS.2006.379776.

H. Aminzadeh and K. Mafinezhad, "On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers," Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), Bangalore, India, 2008, pp. 283-288, doi: 10.1145/1393921.1393995.

Stabilizing a 2-Stage Amplifier URL:https://a2d2ic.wordpress.com/2016/11/10/stabilizing-a-2-stage-amplifier/

overview

\(\omega_d\) called damped natural frequency

closed loop frequency response

\[\begin{align} A &= \frac{\frac{A_0}{(1+s/\omega_1)(1+s/\omega_2)}}{1+\beta \frac{A_0} {(1+s/\omega_1)(1+s/\omega_2)}} \\ &= \frac{A_0}{1+A_0 \beta}\frac{1}{\frac{s^2}{\omega_1\omega_2(1+A_0\beta)}+\frac{1/\omega_1+1/\omega_2}{1+A_0\beta}s+1} \\ &\simeq \frac{A_0}{1+A_0 \beta}\frac{1}{\frac{s^2}{\omega_u\omega_2}+\frac{1}{\omega_u}s+1} \\ &= \frac{A_0}{1+A_0 \beta}\frac{\omega_u\omega_2}{s^2+\omega_2s+\omega_u\omega_2} \end{align}\]

That is \(\omega_n = \sqrt{\omega_u\omega_2}\) and \(\zeta = \frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\)

where \(\omega_u\) is the unity gain bandwidth

where \(f_r\) is resonant frequency, \(\zeta\) is damping ratio, \(P_f\) maximum peaking, \(P_t\) is the peak of the first overshoot (step response)

damping factor & phase margin

• phase margin is defined for open loop system

• damping factor (\(\zeta\)) is defined for close loop system

The roughly 90 to 100 times of damping factor (\(\zeta\)​) is phase margin \[ \mathrm{PM} = 90\zeta \sim 100\zeta \] In order to have a good stable system, we want \(\zeta > 0.5\) or phase margin more than \(45^o\)

We can analyze open loop system in a better perspective because it is simpler. So, we always use the loop gain analysis to find the phase margin and see whether the system is stable or not.

additional Zero

\[\begin{align} TF &= \frac{s +\omega_z}{s^2+2\zeta \omega_ns+\omega_n^2} \\ &= \frac{\omega _z}{\omega _n^2}\cdot \frac{1+s/\omega _z}{1+s^2/\omega_n^2+2\zeta s/\omega_n} \end{align}\]

Let \(s=j\omega\) and omit factor, \[ A_\text{dB}(\omega) = 10\log[1+(\frac{\omega}{\omega _z})^2] - 10\log[1+\frac{\omega^4}{\omega_n^4}+\frac{2\omega^2(2\zeta ^2 -1)}{\omega_n^2}] \] peaking frequency \(\omega_\text{peak}\) can be obtained via \(\frac{d A_\text{dB}(\omega)}{d\omega} = 0\) \[ \omega_\text{peak} = \omega_z \sqrt{\sqrt{(\frac{\omega_n}{\omega_z})^4 - 2(\frac{\omega_n}{\omega_z})^2(2\zeta ^2-1)+1} - 1} \]

Settling Time

single-pole

\[ \tau \simeq \frac{1}{\beta \omega_\text{ugb}} \]

two poles

Rise Time

Katsuhiko Ogata, Modern Control Engineering Fifth Edition

For underdamped second order systems, the 0% to 100% rise time is normally used

For \(\text{PM}=70^o\)

• \(\omega_2=3\omega_u\), that is \(\omega_n = 1.7\omega_u\).
• \(\zeta = 0.87\)

Then \[ t_r = \frac{3.1}{\omega_u} \]

Settling Time

Gene F. Franklin, Feedback Control of Dynamic Systems, 8th Edition

As we know \[ \zeta \omega_n=\frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\cdot \sqrt{\omega_u\omega_2}=\frac{1}{2}\omega_2 \]

Then \[ t_s = \frac{9.2}{\omega_2} \]

For \(\text{PM}=70^o\), \(\omega_2 = 3\omega_u\), that is \[ t_s \simeq \frac{3}{\omega_u} \space\space \text{, for PM}=70^o \]

For \(\text{PM}=45^o\), \(\omega_2 = \omega_u\), that is \[ t_s \simeq \frac{9.2}{\omega_u} \space\space \text{, for PM}=45^o \]

Above equation is valid only for underdamped, \(\zeta=\frac{1}{2}\sqrt{\frac{\omega_2}{\omega_u}}\lt 1\), that is \(\omega_2\lt 4\omega_u\)

2 Stage RC filter

high frequency pass

Since \(1/sC_1+R_1 \gg R_0\) \[ \frac{V_m}{V_i}(s) \simeq \frac{R_0}{R_0 + 1/sC_0} = \frac{sR_0C_0}{1+sR_0C_0} \] step response of \(V_m\) \[ V_m(t) = e^{-t/R_0C_0} \] where \(\tau = R_0C_0\)

And \(V_o(s)\) can be expressed as \[\begin{align} \frac{V_o}{V_i}(s) & \simeq \frac{sR_0C_0}{1+sR_0C_0} \cdot \frac{sR_1C_1}{1+sR_1C_1} \\ &= \frac{sR_0C_0R_1C_1}{R_0C_0-R_1C_1}\left(\frac{1}{1+sR_1C_1} - \frac{1}{1+sR_0C_0}\right) \end{align}\]

Then step response of \(Vo\) \[\begin{align} Vo(t) &= \frac{R_0C_0R_1C_1}{R_0C_0-R_1C_1} \left(\frac{1}{R_1C_1}e^{-t/R_1C_1} - \frac{1}{R_0C_0}e^{-t/R_0C_0}\right) \\ &= \frac{1}{R_0C_0-R_1C_1}\left(R_0C_0e^{-t/R_1C_1} - R_1C_1e^{-t/R_0C_0}\right) \\ &\approx \frac{1}{R_0C_0-R_1C_1}\left(R_0C_0e^{-t/R_1C_1} - R_1C_1\right) \end{align}\]

where \(\tau=R_1C_1\)

Partial-fraction Expansion

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syms C0
syms R0
syms C1
syms R1
syms s

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

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>> partfrac(vm, s)
 
ans =
 
1 - (s*(C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1)
 
>> partfrac(vo, s)
 
ans =
 
1 - (s*(C0*R0 + C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1)

\[\begin{align} V_m(s) &= 1 - \frac{s(C_1R_0+C_1R_1)+1}{C_0C_1R_0R_1s^2+(C_0R_0+C_1R_0+C_1R_1)s+1} \\ V_o(s) &= 1 - \frac{s(C_0R_0+C_1R_0+C_1R_1)+1}{C_0C_1R_0R_1s^2+(C_0R_0+C_1R_0+C_1R_1)s+1} \end{align}\]

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C0 = 200e-9;
R0 = 50;
C1 = 400e-15;
R1 = 200e3;

s = tf("s");

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

vm_exp = 1 - (s*(C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1);
vo_exp = 1 - (s*(C0*R0 + C1*R0 + C1*R1) + 1)/(C0*C1*R0*R1*s^2 + (C0*R0 + C1*R0 + C1*R1)*s + 1);

figure(1)
subplot(1,2,1)
step(vm, 500e-9, 'k-o');
hold on;
step(vm_exp, 500e-9, 'r-^')
title('vm step response')
grid on;
legend()


subplot(1,2,2)
step(vo, 500e-9, 'k-o');
hold on;
step(vo_exp, 500e-9, 'r-^')
title('vo step response')
grid on;
legend()


% with approximation
figure(2)
vm_exp2 = s*R0*C0/(1+s*R0*C0);
vo_exp2 = s*R0*C0/(1+s*R0*C0) * s*R1*C1/(1+s*R1*C1);

subplot(1,2,1)
step(vm, 500e-9, 'k-o');
hold on;
step(vm_exp2, 500e-9, 'r-^')
title('vm step response')
grid on;
legend()

subplot(1,2,2)
step(vo, 500e-9, 'k-o');
hold on;
step(vo_exp2, 500e-9, 'r-^')
title('vo step response')
grid on;
legend()

spectre simulation vs matlab

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C0 = 200e-9;
R0 = 50;
C1 = 400e-15;
R1 = 200e3;

s = tf("s");

Z0 = 1/s/C1 + R1;
Z1 = R0*Z0/(R0+Z0);
vm = Z1 / (Z1 + 1/s/C0);
vo = R1/Z0 * vm;

step(vm, 500e-9);
hold on;
step(vo, 500e-9);

grid on

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>> vm

vm =
 
          1.024e-44 s^5 + 2.56e-37 s^4 + 1.6e-30 s^3
  -----------------------------------------------------------
  1.024e-44 s^5 + 2.571e-37 s^4 + 1.626e-30 s^3 + 1.6e-25 s^2
 
Continuous-time transfer function.

>> vo

vo =
 
                 8.194e-52 s^6 + 2.048e-44 s^5 + 1.28e-37 s^4
  ---------------------------------------------------------------------------
  8.194e-52 s^6 + 3.081e-44 s^5 + 3.871e-37 s^4 + 1.638e-30 s^3 + 1.6e-25 s^2
 
Continuous-time transfer function.

low frequency pass

\[ \left\{ \begin{array}{cl} \frac{V_i - V_m}{R_0} &= C_0\frac{dV_m}{dt} + C_1\frac{dV_o}{dt} \\ \frac{V_m - V_o}{R_1} &= C_1\frac{dV_o}{dt} \\ V_m(t=0) &= 1 \\ V_o(t=0) &= 0 \end{array} \right. \]

Take into initial condition account \[ \frac{dV_m}{dt} \overset{\mathcal{L}}{\longrightarrow} sV_M-V_{m0} \] where \(V_{m0} = 1\)

\[\begin{align} V_O(s) &= \frac{V_I}{s^2R_0C_0R_1C_1+s(R_0C_0+R_1C_1+R_0C_1)+1} + \frac{V_{m0}R_0C_0}{s^2R_0C_0R_1C_1+s(R_0C_0+R_1C_1+R_0C_1)+1} \\ &\approx \frac{V_I}{s^2R_0C_0R_1C_1+sR_0(C_0+C_1)+1} + \frac{V_{m0}R_0C_0}{s^2R_0C_0R_1C_1+sR_0(C_0+C_1)+1} \\ &= \frac{V_I}{R_0(C_0+C_1)}\left(\frac{R_0(C_0+C_1)}{sR_0(C_0+C_1)+1} - \frac{R_1\frac{C_0C_1}{C_0+C_1}}{sR_1\frac{C_0C_1}{C_0+C_1}+1}\right) \\ &+ \frac{C_0}{C_0+C_1}\left(\frac{R_0(C_0+C_1)}{sR_0(C_0+C_1)+1} - \frac{R_1\frac{C_0C_1}{C_0+C_1}}{sR_1\frac{C_0C_1}{C_0+C_1}+1}\right) \end{align}\]

with \(V_I = \frac{1}{s}\), using inverse Laplace transform \[\begin{align} V_o(t) &= 1 - \frac{C_1}{C_0+C_1}e^{-t/\tau_0}-\frac{C_0}{C_0+C_1}e^{-t/\tau_1} - \frac{R_1C_0C_1}{R_0(C_0+C_1)^2} \tag{Eq.0} \\ &= 1 - \frac{C_1}{C_0+C_1}e^{-t/\tau_0}-\frac{C_0}{C_0+C_1}e^{-t/\tau_1} \tag{Eq.1} \end{align}\]

where

\[\begin{align} \tau_0 &= R_0(C_0+C_1) \\ \tau_1 &= R_1C_1\cdot \frac{C_0}{C_0+C_1} \end{align}\]

and \(\tau_0 \gg \tau_1\)

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R0 = 100e3;
C0 = 200e-15;
R1 = 10e3;
C1 = 100e-15;

s = tf('s');

VI = 1/s;
Vm0 = 1;

deno = (s^2*R0*C0*R1*C1 + s*(R0*C0 + R1*C1 + R0*C1) + 1);
VO = VI/deno + (Vm0*R0*C0)/deno;
VM = (1+s*R1*C1)*VO;

t = linspace(0,40,1e3);  % ns
[vot, ~] = impulse(VO, t*1e-9);
[vmt, ~] = impulse(VM, t*1e-9);

tau0 = R0*(C0+C1)*1e9; %ns
tau1 = R1*C0*C1/(C0+C1)*1e9; %ns
y0 = 1 - C1/(C0+C1)*exp(-t/tau0) - C0/(C0+C1)*exp(-t/tau1) - R1*C0*C1/R0/(C0+C1)^2;  % Eq.0
y1 = 1 - C1/(C0+C1)*exp(-t/tau0) - C0/(C0+C1)*exp(-t/tau1);  % Eq.1

plot(t, vot, t, vmt,LineWidth=2);
hold on
plot(t,y0, t,y1, LineWidth=2, LineStyle="--" );
xlim([-10, 40])
legend('V_o(t)', 'V_m(t)','y_0(t)', 'y_1(t)', fontsize=12)
xlabel('t (ns)')
ylabel('mag (V)')
grid on;

reference

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018. Feedback Control of Dynamic Systems (8th Edition) (8th. ed.). Pearson.

Katsuhiko Ogata, Modern Control Engineering, 5th edition

Conversion Relationships

Capacitor

Inductor

Derivation

series or parallel representation

reference

Tank Circuits/Impedances [https://stanford.edu/class/ee133/handouts/lecturenotes/lecture5_tank.pdf]

Resonant Circuits [https://web.ece.ucsb.edu/~long/ece145b/Resonators.pdf]

Series & Parallel Impedance Parameters and Equivalent Circuits [https://assets.testequity.com/te1/Documents/pdf/series-parallel-impedance-parameters-an.pdf]

ES Lecture 35: Non ideal capacitor, Capacitor Q and series RC to parallel RC conversion [https://youtu.be/CJ_2U5pEB4o?si=4j4CWsLSapeu-hBo]

Are AC-Driven Circuits Linear?

\[ f(x_1 + x_2)= f(x_1)+ f(x_2) \]

Often, AC-driven circuits can be mistaken as non-linear as the basis that determines the linearity of a circuit is the relationship between the voltage and current.

While an AC signal varies with time, it still exhibits a linear relationship across elements like resistors, capacitors, and inductors. Therefore, AC driven circuits are linear.

Phasor

Phasor concept has no real physical significance. It is just a convenient mathematical tool.

Phasor analysis determines the steady-state response to a linear circuit driven by sinusoidal sources with frequency \(f\)

If your circuit includes transistors or other nonlinear components, all is not lost. There is an extension of phasor analysis to nonlinear circuits called small-signal analysis in which you linearize the components before performing phasor analysis - AC analyses of SPICE

A sinusoid is characterized by 3 numbers, its amplitude, its phase, and its frequency. For example \[ v(t) = A\cos(\omega t + \phi) \tag{1} \] In a circuit there will be many signals but in the case of phasor analysis they will all have the same frequency. For this reason, the signals are characterized using only their amplitude and phase.

The combination of an amplitude and phase to describe a signal is the phasor for that signal.

Thus, the phasor for the signal in \((1)\) is \(A\angle \phi\)

In general, phasors are functions of frequency

Often it is preferable to represent a phasor using complex numbers rather than using amplitude and phase. In this case we represent the signal as: \[ v(t) = \Re\{Ve^{j\omega t} \} \tag{2} \] where \(V=Ae^{j\phi}\) is the phasor.

\((1)\) and \((2)\) are the same

Phasor Model of a Resistor

A linear resistor is defined by the equation \(v = Ri\)

Now, assume that the resistor current is described with the phasor \(I\). Then \[ i(t) = \Re\{Ie^{j\omega t}\} \] \(R\) is a real constant, and so the voltage can be computed to be \[ v(t) = R\Re\{Ie^{j\omega t}\} = \Re\{RIe^{j\omega t}\} = \Re\{Ve^{j\omega t}\} \] where \(V\) is the phasor representation for \(v\), i.e. \[ V = RI \]

1. Thus, given the phasor for the current we can directly compute the phasor for the voltage across the resistor.

2. Similarly, given the phasor for the voltage across a resistor we can compute the phasor for the current through the resistor using \(I = \frac{V}{R}\)

Phasor Model of a Capacitor

A linear capacitor is defined by the equation \(i=C\frac{dv}{dt}\)

Now, assume that the voltage across the capacitor is described with the phasor \(V\). Then \[ v(t) = \Re\{ V e^{j\omega t}\} \] \(C\) is a real constant \[ i(t) = C\Re\{\frac{d}{dt}V e^{j\omega t}\} = \Re\{j\omega C V e^{j\omega t}\} \] The phasor representation for \(i\) is \(i(t) = \Re\{Ie^{j\omega t}\}\), that is \(I = j\omega C V\)

1. Thus, given the phasor for the voltage across a capacitor we can directly compute the phasor for the current through the capacitor.

2. Similarly, given the phasor for the current through a capacitor we can compute the phasor for the voltage across the capacitor using \(V=\frac{I}{j\omega C}\)

Phasor Model of an Inductor

A linear inductor is defined by the equation \(v=L\frac{di}{dt}\)

Now, assume that the inductor current is described with the phasor \(I\). Then \[ i(t) = \Re\{ I e^{j\omega t}\} \] \(L\) is a real constant, and so the voltage can be computed to be \[ v(t) = L\Re\{\frac{d}{dt}I e^{j\omega t}\} = \Re\{j\omega L I e^{j\omega t}\} \] The phasor representation for \(v\) is \(v(t) = \Re\{Ve^{j\omega t}\}\), that is \(V = j\omega L I\)

1. Thus, given the phasor for the current we can directly compute the phasor for the voltage across the inductor.

2. Similarly, given the phasor for the voltage across an inductor we can compute the phasor for the current through the inductor using \(I=\frac{V}{j\omega L}\)

Impedance and Admittance

Impedance and admittance are generalizations of resistance and conductance.

They differ from resistance and conductance in that they are complex and they vary with frequency.

Impedance is defined to be the ratio of the phasor for the voltage across the component and the current through the component: \[ Z = \frac{V}{I} \]

Impedance is a complex value. The real part of the impedance is referred to as the resistance and the imaginary part is referred to as the reactance

For a linear component, admittance is defined to be the ratio of the phasor for the current through the component and the voltage across the component: \[ Y = \frac{I}{V} \]

Admittance is a complex value. The real part of the admittance is referred to as the conductance and the imaginary part is referred to as the susceptance.

Response to Complex Exponentials

The response of an LTI system to a complex exponential input is the same complex exponential with only a change in amplitude

\[\begin{align} y(t) &= H(s)e^{st} \\ H(s) &= \int_{-\infty}^{+\infty}h(\tau)e^{-s\tau}d\tau \end{align}\]

where \(h(t)\) is the impulse response of a continuous-time LTI system

convolution integral is used here

\[\begin{align} y[n] &= H(z)z^n \\ H(z) &= \sum_{k=-\infty}^{+\infty}h[k]z^{-k} \end{align}\]

where \(h(n)\) is the impulse response of a discrete-time LTI system

convolution sum is used here

The signals of the form \(e^{st}\) in continuous time and \(z^{n}\) in discrete time, where \(s\) and \(z\) are complex numbers are referred to as an eigenfunction of the system, and the amplitude factor \(H(s)\), \(H(z)\) is referred to as the system's eigenvalue

Laplace transform

One of the important applications of the Laplace transform is in the analysis and characterization of LTI systems, which stems directly from the convolution property \[ Y(s) = H(s)X(s) \] where \(X(s)\), \(Y(s)\), and \(H(s)\) are the Laplace transforms of the input, output, and impulse response of the system, respectively

From the response of LTI systems to complex exponentials, if the input to an LTI system is \(x(t) = e^{st}\), with \(s\) the ROC of \(H(s)\), then the output will be \(y(t)=H(s)e^{st}\); i.e., \(e^{st}\) is an eigenfunction of the system with eigenvalue equal to the Laplace transform of the impulse response.

s-Domain Element Models

Sinusoidal Steady-State Analysis

Here Sinusoidal means that source excitations have the form \(V_s\cos(\omega t +\theta)\) or \(V_s\sin(\omega t+\theta)\)

Steady state mean that all transient behavior of the stable circuit has died out, i.e., decayed to zero

\(s\)-domain and phasor-domain

Phasor analysis is a technique to find the steady-state response when the system input is a sinusoid. That is, phasor analysis is sinusoidal analysis.

• Phasor analysis is a powerful technique with which to find the steady-state portion of the complete response.
• Phasor analysis does not find the transient response.
• Phasor analysis does not find the complete response.

The beauty of the phasor-domain circuit is that it is described by algebraic KVL and KCL equations with time-invariant sources, not differential equations of time

The difference here is that Laplace analysis can also give us the transient response

General Response Classifications

• zero-input response, zero-state response & complete response

  

  The zero-state response is given by \(\mathscr{L^1}[H(s)F(s)]\), for the arbitrary \(s\)-domain input \(F(s)\)

  where \(Z_L(s) = sL\), the inductor with zero initial current \(i_L(0)=0\) and \(Z_C(s)=1/sC\) with zero initial voltage \(v_C(0)=0\)

• transient response & steady-state response

  

• natural response & forced response

  

Transfer Functions and Frequency Response

transfer function

The transfer function \(H(s)\) is the ratio of the Laplace transform of the output of the system to its input assuming all zero initial conditions.

frequency response

An immediate consequence of convolution is that an input of the form \(e^{st}\) results in an output \[ y(t) = H(s)e^{st} \] where the specific constant \(s\) may be complex, expressed as \(s = \sigma + j\omega\)

A very common way to use the exponential response of LTIs is in finding the frequency response i.e. response to a sinusoid

First, we express the sinusoid as a sum of two exponential expressions (Euler’s relation): \[ \cos(\omega t) = \frac{1}{2}(e^{j\omega t}+e^{-j\omega t}) \] If we let \(s=j\omega\), then \(H(-j\omega)=H^*(j\omega)\), in polar form \(H(j\omega)=Me^{j\phi}\) and \(H(-j\omega)=Me^{-j\phi}\). \[\begin{align} y_+(t) & = H(s)e^{st}|_{s=j\omega} = H(j\omega)e^{j\omega t} = M e^{j(\omega t + \phi)} \\ y_-(t) & = H(s)e^{st}|_{s=-j\omega} = H(-j\omega)e^{-j\omega t} = M e^{-j(\omega t + \phi)} \end{align}\]

By superposition, the response to the sum of these two exponentials, which make up the cosine signal, is the sum of the responses \[\begin{align} y(t) &= \frac{1}{2}[H(j\omega)e^{j\omega t} + H(-j\omega)e^{-j\omega t}] \\ &= \frac{M}{2}[e^{j(\omega t + \phi)} + e^{-j(\omega t + \phi)}] \\ &= M\cos(\omega t + \phi) \end{align}\]

where \(M = |H(j\omega|\) and \(\phi = \angle H(j\omega)\)

This means if a system represented by the transfer function \(H(s)\) has a sinusoidal input, the output will be sinusoidal at the same frequency with magnitude \(M\) and will be shifted in phase by the angle \(\phi\)

Laplace transform & Fourier transform

• Laplace transforms such as \(Y(s)=H(s)U(s)\) can be used to study the complete response characteristics of systems, including the transient response—that is, the time response to an initial condition or suddenly applied signal
• This is in contrast to the use of Fourier transforms, which only take into account the steady-state response

Given a general linear system with transfer function \(H(s)\) and an input signal \(u(t)\), the procedure for determining \(y(t)\) using the Laplace transform is given by the following steps:

reference

Ken Kundert. Introduction to Phasors. Designer’s Guide Community. September 2011.

How to Perform Linearity Circuit Analysis [https://resources.pcb.cadence.com/blog/2021-how-to-perform-linearity-circuit-analysis]

Stephen P. Boyd. EE102 Lecture 7 Circuit analysis via Laplace transform [https://web.stanford.edu/~boyd/ee102/laplace_ckts.pdf]

Cheng-Kok Koh, EE695K VLSI Interconnect, S-Domain Analysis [https://engineering.purdue.edu/~chengkok/ee695K/lec3c.pdf]

Kenneth R. Demarest, Circuit Analysis using Phasors, Laplace Transforms, and Network Functions [https://people.eecs.ku.edu/~demarest/212/Phasor%20and%20Laplace%20review.pdf]

DeCarlo, R. A., & Lin, P.-M. (2009). Linear circuit analysis : time domain, phasor, and Laplace transform approaches (3rd ed).

Davis, Artice M.. "Linear Circuit Analysis." The Electrical Engineering Handbook - Six Volume Set (1998)

Duane Marcy, Fundamentals of Linear Systems [http://lcs-vc-marcy.syr.edu:8080/Chapter22.html]

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018. Feedback Control of Dynamic Systems (8th Edition) (8th. ed.). Pearson.

Data Register, DR:

• Bypass Register, BR
• Boundary Scan Register, BSR

Instruction Register, IR

TAP Controller

• FSM and Shift Register of DR and IR works at the posedge of the clock
• TMS, TDI, TDO and Hold Register of DR and IR changes value at the negedge of the clock

capture IR 01, the fixed is for easier fault detection

After power-up, they may not be in sync, but there is a trick. Look at the state machine and notice that no matter what state you are, if TMS stays at "1" for five clocks, a TAP controller goes back to the state "Test-Logic Reset". That's used to synchronize the TAP controllers.

It is important to note that in a typical Boundary-Scan test, the time between launching a signal from driver (at the falling edge of test clock (TCK) in the Update-DR or Update-IR TAP Controller state) and capturing that signal (at the rising edge of TCK in the Caputre-DR TAP Controller state) is no less tha 2.5 TCK cycles

Further, the time between successive launches on a driver is governed - not only by the TCk rate - but by the amount of serial data shifting needed to load the next pattern data in the concatenated Boundary-Scan Registers of the Boundary-Scan chain

Thus the effective test data rate of a driver could be thousands of the times lower than the TCK rate

1. For DC-coupled interconnect, this time is of no concern
2. For AC-coupled interconnect, the signal may easily decay partially or completely before it can be captured
3. If only partial decay occurs before capture, that decay will very likely be completed before the driver produces the next edge

AC-coupling

In general, AC-coupling can distort a signal transmitted across a channel depending on its frequency.

Figure 5

• The high frequency signal is relatively unaffected by the coupling
• The low frequency signal is severely impacted
  1. it decays to \(V_T\) after a few time constants
  2. its amplitude is double the input amplitude > transient response, before AC-coupling capacitor: \(-A_p \to A_p\); after AC-coupling capacitor \(V_T \to V_T+2A_p\) > A key item to note is that the transitions in the original signal are preserved, although their start and end points are offset > > compared to where they were in the high frequency

Test signal implementation

The test data is either the content of the Boundary-Scan Register Update latch (U) when executing the (DC) EXTEST instruction, or an "AC Signal" when an AC testing instruction is loaded into the device.

The AC signal is a test waveform suited for transmission through AC-coupling

Test signal reception

• When an AC testing instruction is loaded, a specialized test receiver detects transitoins of the AC signal seen at the input and determines if this represents a logic '0' or '1'
• When EXTEST is loaded, the input signal level is detected and sent to the output of the test receiver to the Boundary-Scan Register cell

When testing for a shorted capacitor, the test software must ensure that enough time has passed for the signal to decay before entering Capture-DR, either by stopping TCk or by spending additional TCK cycles in the Run-Test/Idle TAP Controller state

EXTEST_PULSE & EXTEST_TRAIN

The two new AC-test instructions provided by this standard differ primarily in the number and timing of transitions to provide flexibility in dealing with the specific dynamic behavior of the channels being tested

AC Test Signal essentially modulates test data so that it will propagate through AC-coupled channels, for devices that contatin AC pins

Tools should use the EXTEST_PULSE instruction unless there is a specific requirement for the EXTEST_TRAIN instruction

EXTEST_PULSE

Generate two additional driver transitions and allows a tester to vary the time between them dependent on how many TCK cycles the TAP is left in the Run-Test/Idle TAP Controller state.

This is intended to allow any undesired transient condition to decay to a DC steady-state value when that will make the final transition more reliably detectable

The duration in the Run-Test/Idle TAP Controller state should be at least three times the high-pass coupling time constant. This allows the first additional transition to decay away to the DC steady-state value for the channel, and ensures that the full amplitude of the final transition is added to or subtracted from that steady-state value

This establishes a known initial condition for the final transition and permits reliable specification of the detection threshold of the test receiver

EXTEST_TRAIN

Generate multiple additional transitions, the number dependent on how long the TAP is left in the Run-Test/Idle TAP Controller state

This is intended to allow any undesired transient condition to decay to an AC steady-state value when that will make the final transition more reliably detectable

IEEE Std 1149.6-2003

This standard is built on top of IEEE Std 1149.1 using the same Test Access Port structure and Boundary-Scan architecture.

• It adds the concept of a "test receiver" to input pins that are expected to handle differential and/or AC-coupling
• It adds two new instructions that cause drivers to emit AC waveforms that are processed by test receivers.

JTAG Instruction

Implementation

• AC mode hysteresis, detect transistion
• DC mode threshold is determined by jtag initial value

reference

IEEE Std 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, 2001

IEEE Std 1149.6-2003, IEEE Standard for BoundaryScan Testing of Advanced Digital Networks, IEEE, 2003

IEEE 1149.6 Tutorial | Testing AC-coupled and Differential High-speed Nets [https://www.asset-intertech.com/resources/eresources/ieee-11496-tutorial-testing-ac-coupled-and-differential-high-speed-nets/]

Prof. James Chien-Mo Li, Lab of Dependable Systems, National Taiwan University. VLSI Testing [http://cc.ee.ntu.edu.tw/~cmli/VLSItesting/]

K.P. Parker, The Boundary Scan Handbook, 3rd ed., Kluwer Academic, 2003.

B. Eklow, K. P. Parker and C. F. Barnhart, "IEEE 1149.6: a boundary-scan standard for advanced digital networks," in IEEE Design & Test of Computers, vol. 20, no. 5, pp. 76-83, Sept.-Oct. 2003, doi: 10.1109/MDT.2003.1232259.