proportional term (P) depends on the present error
integral term (I) depends on past errors
derivative term (D) depends on anticipated future errors
PID controller makes use of linear extrapolation of
the measured output
PI controller does not make use of any prediction of
the future state of the system
The prediction by linear extrapolation (D) can
generate large undesired control signals because measurement noise is
amplified, that's why D is not used widely
TODO 📅
reference
Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. Feedback
Control of Dynamic Systems, Global Edition (8th Edition). Pearson. [pdf]
Åström, K.J. & Murray, Richard. (2021). Feedback Systems: An
Introduction for Scientists and Engineers Second Edition [pdf]
Dawson, J. L. (2021). A guide to feedback theory. Cambridge
University Press.
charge pumps are capacitive
DC-DC converters. The two most common switched capacitor
voltage converters are the voltage inverter and the
voltage doubler circuit
We derive a recursive equation that describes the output voltage
\(V_{out,n}\) after the \(n\)th clock cycle \[
V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o}
\]
Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is
\[
\overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} -
\frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right)
\approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p}
\] which results in a simple expression for the output
voltage droop
\[
\Delta V_{out} = \frac{I_{load}}{f_{sw}C_p}
\]
The charge pump can be modeled as a voltage source with a
source resistance\(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage
drop across \(R_\text{out}\) due to the
load current:
Fourier transform of the output of the expander is a frequency-scaled
version of the Fourier transform of the input
Subsampling or Downsampling
Eqs. (4.72)
the superposition of an infinite set of amplitude-scaled copies of
\(X_c(j\Omega)\), frequency scaled
through \(\omega = \Omega T_d\) and
shifted by integer multiples of \(2\pi\)
Eq. (4.77)
the superposition of \(M\)
amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by
\(M\) and shifted by integer multiples
of \(2\pi\)
downsampled by a factor of \(M =
2\)
Upsampling or Zero Insertion
Assuming \(X(e^{j\omega_1}) =
U_f(e^{j\omega_1})\) with \(\omega_1 =
\Omega T_1\), upsampled by ratio \(L\), then obtain
Polyphase decomposition is a powerful technique used in digital
signal processing to efficiently implement multirate systems.
where \(e_k[n]=h[nM+k]\)
Polyphase Implementation of Decimation Filters &
Interpolation Filters
Decimation system
Interpolation system
sampling identity
LPTV Implementation
TODO 📅
The interpolation filter following an up-sampler
generally is time varying and cannot be represented by
a simple transfer function. The equivalent filter in a
zero-order hold is an exception, perhaps unique, that
can be represented with a time-invariant transfer function
The interpolation filter following an up-sampler generally is
time varying and cannot be represented by a simple
transfer function. The equivalent filter in a Zero-Order
Hold is an exception, perhaps unique, that can be represented
with a time-invariant transfer function
Split the \(1:LM\) hold process into
a \(1 : L\) hold followed by a \(1 : M\) hold \[
Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}}
\] then \[\begin{align}
F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\
&=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}}
\\
&= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}}
\end{align}\]
That is \(F_1(z)=F_2(z)\), i.e. they
are equivalent
In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is
\[
LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}}
\]
In (b),
Accumulate-And-Dump
(AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[
\phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}
\] Hence \[\begin{align}
\phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\
&= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot
\frac{1}{1-\eta^{-1}}
\end{align}\]
After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align}
\phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\
&=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}}
\end{align}\] i.e., \[
LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot
\frac{1-z^{-L}}{1-z^{-1}}
\]
When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx
1\)
J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]
J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery
Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of
Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]
J. Sonntag and J. Stonick, "A digital clock and data recovery
architecture for multi-gigabit/s binary links," Proceedings of the
IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]
Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority
Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR,"
in IEEE Transactions on Microwave Theory and Techniques, vol.
68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]
J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with
Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]
J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum
Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State
Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
A. Sheikholeslami, "Voltage Follower, Part III [Circuit Intuitions],"
in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp.
14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457
Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco,
CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.
Double differential Pair
\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
\]
In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end
assume input and reference common voltage are
same
Pros of (b)
larger input range i.e., \(\gt \pm
\sqrt{2}V_\text{ov}\) of (a), it works even one
differential is off due to lower voltage
larger \(g_m\) (smaller input
difference of pair)
Cons of (b)
sensitive to the difference of common voltage between \(V_\text{ip}\), \(V_\text{im}\) and \(V_\text{rp}\), \(V_\text{rm}\)
common-mode voltage
difference
copy aforementioned formula here for convenience \[
V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} -
V_\text{rm}})
\]
at sample phase\(V_\text{ip}=
V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}=
V_\text{cmr}\)
\(I_\text{ip0}= I_\text{im0} =
I_\text{i0}\)
\(I_\text{rp0}= I_\text{rm0} =
I_\text{r0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} = 0\)
at compare start
\(V_\text{ip}= V_\text{im}=
V_\text{cmi}\) and \(V_\text{rp}=
V_\text{cmr}+\Delta\), \(V_\text{rp}=
V_\text{cmr}-\Delta\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to
increase \(V_\text{ip}\) and decrease
\(V_\text{im}\).
and \(I_\text{ip0}= I_\text{im0} =
I_\text{i0}\), \(I_\text{rp0}=
I_\text{rm0} = I_\text{r0}\)
i.e. \(\overline{I_\text{ip} + I_\text{rm}}
- \overline{I_\text{im} + I_\text{rp}} = 0\)
If \(V_\text{cmr} - V_\text{cmi} =
\sqrt{2}V_{OV} + \delta\), and \(\delta
\gt 0\). one transistor carries the entire tail current
\(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\), all the time
At the end, \(V_\text{im} = V_\text{cmi} -
(\Delta - \delta)\), the error is \(\delta\)
In closing, \(V_\text{cmr} - V_\text{cmi}
\lt \sqrt{2}V_{OV}\) for normal work
Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to
limited impedance of current source and input
pair offset
In the end \[
V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS}
\]
Under the condition, every transistor of pairs are on in
equilibrium
Resistive degeneration in differential pairs serves as one
major technique for linear amplifier
The linear region for CMOS differential pair would be extended by
\(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align}
V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\
&= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2}
\end{align}\]
Byungsub Kim, ISSCC 2022, "T11: Basics of Equalization Techniques:
Channels, Equalization, and Circuits"
Minsoo Choi et al., "An Approximate Closed-Form Channel Model for
Diverse Interconnect Applications," IEEE Transactions on Circuits and
Systems-I: Regular Papers, vol. 61, no. 10, pp. 3034-3043, Oct.
2014.
In \(z\)-domain \[
\left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y
\right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y
\] That is \[
Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2
\] In time domain \[\begin{align}
y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\
&= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2]
\end{align}\]
LSB Dither
?? integer valued impulse responses
S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization
Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma
Modulators," in IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 54, no. 3, pp. 492-503, March 2007 [pdf]
stability of DSM
accumulator wordlength
Z. Ye and M. P. Kennedy, "Hardware Reduction in Digital Delta–Sigma
Modulators Via Error Masking—Part II: SQ-DDSM," in IEEE Transactions
on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp.
112-116, Feb. 2009 [https://sci-hub.se/10.1109/TCSII.2008.2010188]
—, "Hardware Reduction in Digital Delta-Sigma Modulators Via Error
Masking - Part I: MASH DDSM," in IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 56, no. 4, pp. 714-726, April 2009
[https://sci-hub.se/10.1109/TCSI.2008.2003383]
Truncation DAC
accumulator is implicit quantizer
with \(\frac{y}{2^{m_2}} + q= v\),
where \(v =
\lfloor\frac{y}{2^{m_2}}\rfloor\)
\[
\left\{ \begin{array}{cl}
Y + 2^{m_2} Q &= 2^{m_2}V \\
U - z^{-1}2^{m_2}Q &= Y
\end{array} \right.
\]
The STF & NTF is shown as below \[
V = \frac{1}{2^{m_2}}U + (1-z^{-1})Q
\]
To avoid accumulator overflow, stable input range is only
of a fraction of the full scale ( \(2^{m_1+m_2}-1\)) \[
u \leq = 2^{m_1+m_2} - 2^{m_2}
\]
i.e. \[
\tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL}
\]
where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV},
desired}\)
\(\Delta\Sigma\) noise in PLL
Impulse Train Modulator (ITM)
M. H. Perrott, M. D. Trott and C. G. Sodini, "A modeling approach for
/spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing
straightforward noise analysis," in IEEE Journal of Solid-State
Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002 [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]
Sigma-Delta DAC
The spectrum of the high resolution digital signal \(u_1\) contains the original
baseband portion and its replicas located at integer
multiples of \(f_{s1}\), plus
a small amount of quantization noise shown as
a solid line
Sigma-delta digital-to-analog converters (SD DAC’s) are often used
for discrete-time signals with sample rate much higher than
their bandwidth
Because of the high sample rate relative to signal bandwidth,
a very simple DAC reconstruction filter (Analog
lowpass filter) suffices, often just a one-pole RC
lowpass
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R= 4.7e3; % ohms resistor value C= .01e-6; % F capacitor value fs= 1e6; % Hz DAC sample rate % input signal x= [zeros(1,20) .9*ones(1,200) .1*ones(1,200)]; % find output y of SD DAC and output y_filt of RC filter [y,y_filt]= sd_dacRC(x,R,C,fs);
t = linspace(0,length(x)-1, length(x))*1/fs*1e3; subplot(3,1,1) plot(t, x, '.'); title('x'); grid on subplot(3,1,2) plot(t, y, '.'); title('y'); grid on subplot(3,1,3) plot(t, y_filt); title('y_{filt}'); xlabel('t(ms)'); grid on
% https://www.dsprelated.com/showarticle/1642.php % Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter
% function [y,y_filt] = sd_dacRC(x,R,C,fs) 2/5/24 Neil Robertson % 1-bit sigma-delta DAC with RC filter % Model does not include a zero-order hold. % % x = input signal vector, 0 <= x < 1 % R = series resistor value, Ohms. Normally R > 1000 for 3.3 V logic. % C = shunt capacitor value, Farads % fs = sample frequency, Hz % y = DAC output signal vector, y(n) = 0 or 1 % y_filt = RC filter output signal vector % function[y,y_filt] = sd_dacRC(x,R,C,fs) N= length(x); x= fix(x*2^16)/2^16; % quantize x to 16 bits %I 1-bit Sigma-delta DAC s= [x(1) zeros(1,N-1)]; for n= 2:N u= x(n) + s(n-1); s(n)= mod(u,1); % sum y(n)= fix(u); % carry end
%II One-pole RC filter model % Matched z-Transform https://ocw.mit.edu/courses/2-161-signal-processing-continuous-and-discrete-fall-2008/cc00ac6d468dc9dcf2238fc1d1a194d4_lecture_19.pdf Ts= 1/fs; Wc= 1/(R*C); % rad -3 dB frequency fc= Wc/(2*pi); % Hz -3 dB frequency a1= -exp(-Wc*Ts); b0= 1 + a1; % numerator coefficient a= [1 a1]; % denominator coeffs y_filt= filter(b0,a,y); % filter the DAC's output signal y
DAC ZOH
The last D2C is in human vision, which connect discrete time \(y(m)\) with line, implicitly
—. "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 54,
no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]
Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016.
Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.
Rhee, W. (2020). Phase-locked frequency generation and clocking :
architectures and circuits for modern wireless and wireline
systems. The Institution of Engineering and Technology
Kaveh Hosseini, Michael Peter Kennedy. Springer 2011. Minimizing
Spurious Tones in Digital Delta-Sigma Modulators
"Quantizers" and "truncators",
and "integrators" and "accumulators"
are used in delta-sigma ADCs and DACs,
respectively
P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma
DACS," 2003 IEEE International Symposium on Circuits and Systems
(ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]
plot(w1/2/pi, abs(h1), LineWidth=3) hold on plot(w2/2/pi, abs(h2), LineWidth=3) grid on legend('MOD1', 'MOD2') xlabel('fs') ylabel('mag') title('NTF of MOD1 & MOD2')
SQNR improvement
In general, for an \(l\)th order
modulator with \(\text{NTF}(z) = (1 −
z^{−1})^l\), the SQNR increases by \((6l + 3)\) dB for every
doubling of the OSR, which provides \(l+0.5\)extra bits
resolution
where \(N\) is the number of bits in
the output, \(M\) is known as the
over-sampling ratio, \(L\) is loop
orders
quantizer levels
The greater the number of quantizer levels, the
smaller quantization error
quantizer overload
\(\Delta \Sigma\) vs. \(\Delta\) modulation
\(\Delta \Sigma\) modulators,
and other noise-shaping modulators, change the spectrum of the
noise but leave the signal unchanged
\(\Delta\) modulators and other
signal-predicting modulators shape the spectrum of the
modulated signal but leave the quantization noise unchanged at the
receiver
output vs.
error-feedback
The error-feedback architecture is
problematic for analog implementation, since it is
sensitive to variations of its parameters (subtractor realization)
The error-feedback structure is thus of limited utility in \(\Delta \Sigma\)ADCs
The error-feedback structure is very useful and applied in
digital loops required in \(\Delta \Sigma\)DACs
ADC
DAC
P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma
DACS," 2003 IEEE International Symposium on Circuits and Systems
(ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]
always @(*) i_func_extended = {i_func[15],i_func[15],i_func[15],i_func[15],i_func}; always @(posedge i_clk ornegedge i_res) begin if (i_res==0) begin DAC_acc_1st<=16'd0; DAC_acc_2nd<=16'd0; this_bit = 1'b0; end elseif(i_ce == 1'b1) begin if(this_bit == 1'b1) begin DAC_acc_1st = DAC_acc_1st + i_func_extended - (2**15); DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st - (2**15); end else begin DAC_acc_1st = DAC_acc_1st + i_func_extended + (2**15); DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st + (2**15); end // When the high bit is set (a negative value) we need to output a 0 and when it is clear we need to output a 1. this_bit = ~DAC_acc_2nd[19]; end end endmodule
an interpolation filter effectively
up-samples its low-rate input and
lowpass-filters the resulting high-rate data
to produce a high-rate output devoid of images
Any such physically feasible device will take
a finite time to operate – in other words, the
quantized output will only be available a small time
after the quantizer has "looked" at the input - insert a one-sample
delay
there cannot be a "delay free loop" is a
common idea in sequential digital state machine design
Both integrator and quantizer are delay free
NTF realizability criterion: No delay-free loops in the modulator
linear settling & GBW of
amplifier
TODO 📅
Switched capacitor has been the common realization technique of
discrete-time (DT) modulators, and in order to achieve a
linear settling, the sampling frequency used
in these converters needs to be significantly lower than the gain
bandwidth product (GBW) of the amplifiers.
P. M. Aziz, H. V. Sorensen and J. vn der Spiegel, "An overview of
sigma-delta converters," in IEEE Signal Processing Magazine, vol. 13,
no. 1, pp. 61-84, Jan. 1996 [https://sci-hub.st/10.1109/79.482138]
V. Medina, P. Rombouts and L. Hernandez-Corporales, "A Different View
of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation
[Feature]," in IEEE Circuits and Systems Magazine, vol. 24, no.
2, pp. 80-97, Secondquarter 2024
This simplified version of LMS algorithm is identical to the
zero-forcing algorithm which minimizes the ISI at data
samples
Sign-Sign LMS (SS-LMS)
T11: Basics of Equalization Techniques: Channels, Equalization, and
Circuits, 2022 IEEE International Solid-State Circuits Conference
V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link
transceiver with adaptive equalization and data recovery," in IEEE
Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April
2005, doi: 10.1109/JSSC.2004.842863.
Jinhyung Lee, Design of High-Speed Receiver for Video Interface with
Adaptive Equalization; Phd thesis, August 2019. thesis
link
Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical
Implementation, 5th edition
E. -H. Chen et al., "Near-Optimal Equalizer and Timing Adaptation for
I/O Links Using a BER-Based Metric," in IEEE Journal of Solid-State
Circuits, vol. 43, no. 9, pp. 2144-2156, Sept. 2008
DFE h0 Estimator
summer output \[
r_k =
a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=1}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right)
\] error slicer analog output \[
e_k=r_k-\hat{a}_k \hat{h}_0
\] error slicer digital output \[
\hat{e}_k=|e_k|
\] It's NOT possible to implement \(e_k\), which need to determine \(\hat{a}_k=|r_k|\) in no time. One method to
approach this problem is calculate \(e_k^{a_k=1}=r_k-\hat{a}_k \hat{h}_0\) and
\(e_k^{a_k=-1}=r_k+\hat{a}_k
\hat{h}_0\), then select the right one based on \(\hat{a}_k\)
The update equation based on Sign-Sign-Least Mean square (SS-LMS) and
loss function \(L(\hat{h}_{\text{0~ntap}})=E(e_k^2)\)\[
\hat{h}_n(k+1) = \hat{h}_n(k)+\mu \cdot |e_k|\cdot \hat{a}_{k-n}
\] Where \(n \in
[0,...,\text{ntap}]\). This way, we can obtain \(\hat{h}_0\), \(\hat{h}_1\), \(\hat{h}_2\), ...
\(\hat{h}_0\) is used in AFE
adaptation
We may encounter difficulty if the first tap of DFE is unrolled, its
\(e_k\) is modified as follow \[
r_k =
a_kh_0+\left(\sum_{n=-\infty,n\neq0}^{+\infty}a_{k-n}h_n-\sum_{n=2}^{\text{ntap}}\hat{a}_{k-n}\hat{h}_n\right)
\] Where there is NO \(\hat{h}_1\)
To find \(\hat{h}_1\), we shall use
different pattern for even and odd error slicer
MLSD (Maximum
Likelihood Sequence Detection)
The process is also referred to as Maximum Likelihood
Sequence Estimator (MLSE)
M. Emami Meybodi, H. Gomez, Y. -C. Lu, H. Shakiba and A.
Sheikholeslami, "Design and Implementation of an On-Demand
Maximum-Likelihood Sequence Estimation (MLSE)," in IEEE Open Journal of
Circuits and Systems, vol. 3, pp. 97-108, 2022, doi:
10.1109/OJCAS.2022.3173686.
Zaman, Arshad Kamruz (2019). A Maximum Likelihood Sequence Equalizing
Architecture Using Viterbi Algorithm for ADC-Based Serial Link.
Undergraduate Research Scholars Program. Available electronically from
[https://hdl.handle.net/1969.1/166485]
There are several variants of MLSD (Maximum Likelihood Sequence
Detection), including:
S. Song, K. D. Choo, T. Chen, S. Jang, M. P. Flynn and Z. Zhang, "A
Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link," in
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65,
no. 7, pp. 2269-2278, July 2018
MMPD infers the channel response from baud-rate samples of the
received data, the adaptation aligns the sampling clock such that
pre-cursor is equal to the post-cursor in the pulse
response
F. Spagna et al., "A 78mW 11.8Gb/s serial link transceiver
with adaptive RX equalization and baud-rate CDR in 32nm CMOS," 2010
IEEE International Solid-State Circuits Conference - (ISSCC), San
Francisco, CA, USA, 2010, pp. 366-367, doi:
10.1109/ISSCC.2010.5433823.
K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of
PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open
Journal of Circuits and Systems, vol. 3, pp. 216-227, 2022 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9910561]
\(s_{011}\) & \(s_{110}\) are approaching to each
other
\(s_{100}\) & \(s_{001}\) are approaching to each
other
Then, \(h_{-1}\) and \(h_1\) are same, which is desired
Bang-Bang CDR
alexander PD or !!PD
The alexander PD locks that edge clock (clkedge) is located at zero
crossings of the data. The \(h_{-0.5}\)
and \(h_{0.5}\) are
equal at the lock point, where the \(h_{-0.5}\) and \(h_{0.5}\) are the cursors located at -0.5
UI and 0.5 UI.
Stojanovic, Vladimir & Ho, A. & Garlepp, B. & Chen, Fred
& Wei, J. & Alon, Elad & Werner, C. & Zerbe, J. &
Horowitz, M.A.. (2004). Adaptive equalization and data recovery in a
dual-mode (PAM2/4) serial link transceiver. IEEE Symposium on VLSI
Circuits, Digest of Technical Papers. 348 - 351.
10.1109/VLSIC.2004.1346611.
A. A. Bazargani, H. Shakiba and D. A. Johns, "MMSE Equalizer Design
Optimization for Wireline SerDes Applications," in IEEE Transactions
on Circuits and Systems I: Regular Papers, doi:
10.1109/TCSI.2023.3328807.
A. Sharif-Bakhtiar, A. Chan Carusone, "A Methodology for Accurate DFE
Characterization," IEEE RFIC Symposium, Philadelphia,
Pennsylvania, June 2018. [PDF]
[Slides
– PDF]
S. Kiran, S. Cai, Y. Zhu, S. Hoyos and S. Palermo, "Digital
Equalization With ADC-Based Receivers: Two Important Roles Played by
Digital Signal Processingin Designing Analog-to-Digital-Converter-Based
Wireline Communication Receivers," in IEEE Microwave Magazine,
vol. 20, no. 5, pp. 62-79, May 2019 [https://sci-hub.se/10.1109/MMM.2019.2898025]
K. K. Parhi, "Design of multigigabit multiplexer-loop-based decision
feedback equalizers," in IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 13, no. 4, pp. 489-493, April 2005
[http://sci-hub.se/10.1109/TVLSI.2004.842935]
T. Toifl et al., "A 3.5pJ/bit 8-tap-feed-forward
8-tap-decision feedback digital equalizer for 16Gb/s I/Os," ESSCIRC
2014 - 40th European Solid State Circuits Conference (ESSCIRC),
Venice Lido, Italy, 2014 [https://sci-hub.se/10.1109/ESSCIRC.2014.6942120]
Comparator Output SNR during sampling region and decision region go
up
Comparator Output SNR during regeneration region is
constant, where noise is critical
Transient Noise Method
Noise Fmax sets the bandwidth of the random noise
sources that are injected at each time point in the transient
analysis
We can identify the RMS noise value easily by looking at 15.9% or
84.1% of CDF (\(1\sigma\)), the
input-referred noise in the RMS is 0.9mV
Thus, if \(V_S\) is chosen so as to
reduce the probability of zeros to 16%, then \(V_S = 1\sigma\), which is also the total
root-mean square (rms) noise referred to the input.
Comparison of two methods
here, fundamental frequency = fclk; integrated noise (0 ~
0.5fclk)
E. Gillen, G. Panchanan, B. Lawton and D. O'Hare, "Comparison of
transient and PNOISE simulation techniques for the design of a dynamic
comparator," 2022 33rd Irish Signals and Systems Conference (ISSC),
Cork, Ireland, 2022, pp. 1-5
J. Conrad, J. Kauffman, S. Wilhelmstatter, R. Asthana, V. Belagiannis
and M. Ortmanns, "Confidence Estimation and Boosting for
Dynamic-Comparator Transient-Noise Analysis," 2024 22nd IEEE
Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada,
2024, pp. 1-5
There are some ambiguity in formula in ADC Verification Rapid
Adoption Kit (RAK)(Product Version: IC 6.1.8, SPECTRE 18.1 March,
2019)
Transient Noise Analysis: \(\sqrt{2}\sigma\), why ratio \(\sqrt{2}\) ???
If the input referred offset follows a normal distribution than it is sufficient to apply a single offset voltage to calculate the offset voltage. See details in Razavi, B., The StrongARM Latch [A Circuit for All Seasons], IEEE Solid-State Circuits Magazine, Volume:7, Issue: 2, Spring 2015
Omran, Hesham. (2019). Fast and accurate technique for comparator
offset voltage simulation. Microelectronics Journal. 89.
10.1016/j.mejo.2019.05.004.
Kickback noise trades with the dimensions of the input
transistors and hence with the offset voltage
affects the comparator's own decision
corrupts the input voltage while it is sensed by other circuits
Tetsuya Iizuka,VLSI2021_Workshop3 "Nyquist A/D Converter Design in
Four Days"
Figueiredo, Pedro & Vital, João. (2006). Kickback noise reduction
techniques for CMOS latched comparators. Circuits and Systems II:
Express Briefs, IEEE Transactions on. 53. 541 - 545.
10.1109/TCSII.2006.875308. [https://sci-hub.se/10.1109/TCSII.2006.875308]
P. M. Figueiredo and J. C. Vital, "Low kickback noise techniques for
CMOS latched comparators," 2004 IEEE International Symposium on Circuits
and Systems (ISCAS), Vancouver, BC, Canada, 2004, pp. I-537 [https://sci-hub.se/10.1109/ISCAS.2004.1328250]
Current mirrors are used between stages to reduce
charge kick back from the logic level swing of the
latch onto the small comparator input capacitors
Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW
Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006 [pdf,
slides]
K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in
1-mm/sup 2/," in IEEE Journal of Solid-State Circuits, vol. 32, no. 12,
pp. 1887-1895, Dec. 1997 [https://sci-hub.st/10.1109/4.643647]
W. Liu, P. Huang and Y. Chiu, "A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS
SAR ADC achieving over 90dB SFDR," 2010 IEEE International
Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA,
2010 [https://sci-hub.se/10.1109/ISSCC.2010.5433830]
Math Background
Relating \(\Phi\) and erf
Error Function (Erf) of the
standard Normal distribution \[
\text{Erf}(x) = \frac{2}{\sqrt{\pi}}\int_0^x e^{-t^2} \mathrm{d}t.
\]Cumulative Distribution Function
(CDF) of the standard Normal distribution \[
\Phi(x) = \frac{1}{\sqrt{2\pi}}\int_{-\infty}^x e^{-z^2/2} \mathrm{d}z.
\]
P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise
Analysis of Regenerative Comparators for Reconfigurable ADC
Architectures," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008 [https://picture.iczhiku.com/resource/eetop/SYirpPPPaAQzsNXn.pdf]
J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity
function analysis of periodic circuits," 2008 IEEE/ACM International
Conference on Computer-Aided Design, 2008, pp. 386-391, doi:
10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]
Y. Luo, A. Jain, J. Wagner and M. Ortmanns, "Input Referred
Comparator Noise in SAR ADCs," in IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 66, no. 5, pp. 718-722, May 2019. [https://sci-hub.se/10.1109/TCSII.2019.2909429]
X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating
Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55,
no. 4, pp. 1011-1022, April 2020 [https://sci-hub.se/10.1109/JSSC.2019.2960485]
C. Mangelsdorf, "Metastability: Deeply misunderstood [Shop Talk: What
You Didn’t Learn in School]," in IEEE Solid-State Circuits Magazine,
vol. 16, no. 2, pp. 8-15, Spring 2024
Rabuske, Taimur & Fernandes, Jorge. (2014). Noise-aware
simulation-based sizing and optimization of clocked comparators. Analog
Integr. Circuits Signal Process.. 81. 723-728.
10.1007/s10470-014-0428-4. [https://sci-hub.se/10.1007/s10470-014-0428-4]
Rabuske, Taimur & Fernandes, Jorge. (2016). Charge-Sharing SAR
ADCs for Low-Voltage Low-Power Applications.
10.1007/978-3-319-39624-8.
Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, "A
low-noise self-calibrating dynamic comparator for high-speed ADCs,"
2008 IEEE Asian Solid-State Circuits Conference, Fukuoka,
Japan, 2008 [slides,
paper]
where \(H(j\omega)\), \(H(e^{j\hat{\omega}})\) is frequency
response of continuous-time systems and
discrete-time systems, which is the function of \(\omega\) and \(\hat{\omega}\)\[\begin{align}
H(j\omega) &= \int_{-\infty}^{+\infty}h(t)e^{-j\omega t}dt \\ \\
H(e^{j\hat{\omega}}) &=
\sum_{n=-\infty}^{+\infty}h[n]e^{-j\hat{\omega} n}
\end{align}\]
The frequency response of discrete-time LTI systems
is always a periodic function of the frequency variable
\(\hat{\omega}\) with period \(2\pi\)
Sampling Theorem
time-sampling theorem: applies to bandlimited
signals
spectral sampling theorem: applies to
timelimited signals
Aliasing
The frequencies \(f_{\text{sig}}\)
and \(Nf_s \pm f_{\text{sig}}\) (\(N\) integer), are
indistinguishable in the discrete time
domain.
Given below sequence \[
X[n] =A e^{j\omega T_s n}
\]
\[\begin{align}
A e^{j(\omega_s + \Delta \omega) T_s n} &= A e^{j(k\omega_s + \Delta
\omega) T_s n} \\
A e^{j(\omega_s - \Delta \omega) T_s n} &= A e^{j(k\omega_s - \Delta
\omega) T_s n}
\end{align}\]
CTFS & CTFT
Fourier transform of a periodic signal with Fourier series
coefficients \(\{a_k\}\) can be
interpreted as a train of impulses occurring at the
harmonically related frequencies and for which the area of the impulse
at the \(k\)th harmonic frequency \(k\omega_0\) is \(2\pi\) times the \(k\)th Fourier series coefficient \(a_k\)
inverse CTFT & inverse DTFT
time domain
frequency domain
inverse CTFT
\(\delta(t)\)
\(\int_{\infty}d\omega\)
inverse DTFT
\(\delta[n]\)
\(\int_{2\pi}d\hat{\omega}\)
inverse CTFT shall integral from \(-\infty\) to \(+\infty\) to obtain \(\delta(t)\) in time domain, e.g., \(x_s(t)\) impulse train
spectral sampling
spectral sampling by \(\omega_0\),
and \(\frac{2\pi}{\omega_0} \gt \tau\)\[
X_{n\omega_0}(\omega) =
\sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega - n\omega_0)
\] Periodic repetition of \(x(t)\) is \[
x_{n\omega_0}(t) = \frac{1}{\omega_0}\sum_{n=-\infty}^{\infty}x(t
-n\frac{2\pi}{\omega_0})=\frac{T_0}{2\pi}\sum_{n=-\infty}^{\infty}x(t
-nT_0)
\]
Then, if \(x_{T_0} (t)\), a periodic
signal formed by repeating \(x(t)\)
every \(T_0\) seconds (\(T_0 \gt \tau\)), its CTFT is \[
X_{T_0}(\omega) = \frac{2\pi}{T_0} \cdot X_{n\omega_0}(\omega) =
\frac{2\pi}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega -
n\omega_0)
\] Then \(x_{T_0} (t)\) can be
expressed with inverse CTFT as \[\begin{align}
x_{T_0} (t) &=
\frac{1}{2\pi}\int_{-\infty}^{\infty}X_{T_0}(\omega)e^{j\omega t}d\omega
\\
&= \frac{1}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)e^{jn\omega_0
t} =\sum_{n=-\infty}^{\infty}\frac{1}{T_0}X(n\omega_0)e^{jn\omega_0 t}
\end{align}\]
i.e. the coefficients of the Fourier series for \(x_{T_0} (t)\) is \(D_n =\frac{1}{T_0}X(n\omega_0)\)
alternative method by direct Fourier series
Why DFT ?
We can use DFT to compute DTFT samples and CTFT samples
\[
\overline{x}(t) = \sum_{n=0}^{N_0-1}x(nT)\delta(t-nT)
\] applying the Fourier transform yieds \[
\overline{X}(\omega) = \sum_{n=0}^{N_0-1}x[n]e^{-jn\omega T}
\] But \(\overline{X}(\omega)\),
the Fourier transform of \(\overline{x}(t)\) is \(X(\omega)/T\), assuming negligible
aliasing. Hence, \[
X(\omega) = T\overline{X}(\omega) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn\omega
T}
\] and \[
X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\omega_0 T}
\] with \(\hat{\omega}_0 = \omega_0
T\)\[
X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\hat{\omega}_0}
\]i.e. the relationship between CTFT and DFT is \(X(k\omega_0) = T\cdot X[k]\), DFT is a tool
for computing the samples of CTFT
C/D
Sampling with a periodic impulse train, followed by conversion to a
discrete-time sequence
The periodic impulse train is \[
s(t) = \sum_{n=-\infty}^{\infty}\delta(t-nT)
\]\(x_s(t)\) can be expressed
as \[
x_s(t) = \sum_{n=-\infty}^{\infty}x_c(nT)\delta(t-nT)
\] i.e., the size (area) of the impulse at sample time
\(nT\) is equal to the value of the
continuous-time signal at that time.
\(x_s(t)\) is, in a sense, a
continuous-time signal (specifically, an impulse train)
samples of \(x_c(t)\) are represented by
finite numbers in \(x[n]\)
rather than as the areas of impulses, as with \(x_s(t)\)
Frequency-Domain
Representation of Sampling
The relationship between the Fourier transforms of the input and the
output of the impulse train modulator \[
X_s(j\omega) = \frac{1}{T}\sum_{k=-\infty}^{\infty}X_c(j(\omega
-k\omega_s))
\] where \(\omega_s\) is the
sampling frequency in radians/s
\(X(e^{j\hat{\omega}})\), the
discrete-time Fourier transform (DTFT) of the sequence \(x[n]\), in terms of \(X_s(j\omega)\) and \(X_c(j\omega)\)
yield \[
x[n] = A e^{j\omega_0 n} = A e^{j\Omega_0 nT_s}
\]
1 2 3 4 5 6 7 8 9
import numpy as np x = np.linspace(0,1,10000) y = np.cos(2*np.pi*1*x) rms = np.sqrt(np.power(y, 2).sum()/x.size) print(rms) print(1/2**0.5)
# 0.7071421356417675 # 0.7071067811865475
Example 4.1 impulse scaling \(\delta(\omega/T)=T\delta(\omega)\)
\[
\int \delta(\frac{\omega}{T})d\omega = \int T \delta(\omega)d\omega =
\int T\delta(\frac{\omega}{T})d\frac{\omega}{T} = T
\]
D/C
zero padding
This option increases \(N_0\), the
number of samples of \(x(t)\), by
adding dummy samples of 0 value. This addition of dummy
samples is known as zero padding
We should keep in mind that even if the fence were transparent, we
would see a reality distorted by aliasing.
Zero padding only allows us to look at more samples of that
imperfect reality
A remarkable fact of linear systems is that the complex
exponentials are eigenfunctions of a linear
system, as the system output to these inputs equals the input multiplied
by a constant factor.
Both amplitude and phase may change
but the frequency does not change
For an input \(x(t)\), we can
determine the output through the use of the convolution integral, so
that with \(x(t) = e^{st}\)\[\begin{align}
y(t) &= \int_{-\infty}^{+\infty}h(\tau)x(t-\tau)d\tau \\
&= \int_{-\infty}^{+\infty} h(\tau) e^{s(t-\tau)}d\tau \\
&= e^{st}\int_{-\infty}^{+\infty} h(\tau) e^{-s\tau}d\tau \\
&= e^{st}H(s)
\end{align}\]
Take the input signal to be a complex exponential of the form \(x(t)=Ae^{j\phi}e^{j\omega t}\)
The real cosine signal is actually composed of two
complex exponential signals: one with positive
frequency and the other with negative \[
cos(\omega t + \phi) = \frac{e^{j(\omega t + \phi)} + e^{-j(\omega t +
\phi)}}{2}
\]
The sinusoidal response is the sum of the complex-exponential
response at the positive frequency \(\omega\) and the response at the
corresponding negative frequency \(-\omega\) because of LTI systems's
superposition property
input: \[\begin{align}
x(t) &= A cos(\omega t + \phi) \\
&= \frac{1}{2}Ae^{\phi}e^{\omega t} +
\frac{1}{2}Ae^{-\phi}e^{-\omega t}
\end{align}\]
J. Zhong, Y. Zhu, S. -W. Sin, S. -P. U and R. P. Martins, "Thermal
and Reference Noise Analysis of Time-Interleaving SAR and
Partial-Interleaving Pipelined-SAR ADCs," in IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 62, no. 9, pp. 2196-2206,
Sept. 2015 [https://sci-hub.st/10.1109/TCSI.2015.2452331]
The amplitude of the reference ripple is code-dependent as it is
correlated with switching energy in each bit cycling
quantization error &
quantization noise
Notice \(e_q\in (0, \Delta)\) and
its average is \(\Delta/2\). To
calculate SNDR, DC component shall be excluded
Don't confuse resolution\(\Delta\) with Bounded Quantization
Noise\(-\Delta/2 \sim
\Delta/2\)
Redundancy
decision level
final digital output for an \(N\)-bit \(M\)-step ADC can be calculated \[
D_{out} = s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0]
-1)\cdot s(1)
\]
i
M
M-1
M-2
...
2
1
0
b[i]
b[M-1]
b[M-2]
...
b[2]
b[1]
b[0]
s[i]
s(M)
s(M-1)
s(M-2)
...
s(2)
s(1)
track the decision level
For \(N\)-bit binary weighted
algorithm,\(N=M\) and \(s(i)=2^{i-1}\), where \(i\in \{N, N-1,...,2,1 \}\)
For the \(n\)th output bit, once a
decision is made, the next decision level will either move up or down by
the step size of \(s(n − 1)\)
If this decision is erroneous, then the sum of the follow-on step
sizes, \(s(n − 2)\), \(s(n − 3)\), ..., \(s(1)\), must be large enough and exceed the
value of the current step size to counteract this mistake
The exceeded amount is the tolerance window for that decision
level
When the ADC is designed with a fixed radix, \(\alpha\) and the required number of
conversion steps, \(M\)
the sum of all the step sizes \(s_{tot}\)\[
s_{tot} = \sum_{k=0}^{M-1} s_0 \alpha^k = s_0\frac{\alpha^M-1}{\alpha-1}
\]
where \(s(i)\) is step size and
\(i \in [0, 1, 2, M-1]\)
The effective number of bits, \(N\),
can be calculated \[
N \leq \log 2\left(\frac{s_{tot} + s_0}{s_0}\right) =
\frac{\alpha^M+\alpha-2}{\alpha-1}
\]
Speed Benefit
TODO 📅
CDAC
The charge redistribution capacitor network is used to
sample the input signal and serves as a digital-to-analog converter
(DAC) for creating and subtracting reference voltages
inverse Laplace Transform is \(V_y(t) =
\frac{C_1}{C_1+C_2}\left(1 - e^{-t/\tau}\right)\)
\(V_x(t)\) and \(V_y(t)\) prove that the settling time is
same
\(\tau = R\frac{C_1C_2}{C_1+C_2}\),
which means usually worst for MSB capacitor (largest)
both \(\tau\) and \(\Delta V\) are the maximum
A popular way to improve the settling behavior, again, is to employ
unit-element DACs that statistically reduce the switching activities,
which, unfortunately, exhibits unnecessary complications to the power,
area and speed tradeoffs of the design
That make sense, charge redistribution consume
energy
Comparator
Comparator input cap effect
\[
-V_{in}\cdot 2^N C = V_c (2^N C + C_p)
\] Then \(V_c = -\frac{2^N C}{2^N C +
C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude
by the factor
During conversion \[\begin{align}
V_c &= -\frac{2^N C}{2^N C + C_p}V_{in} +V_{ref}\sum_{n=0}^{N-1}
\frac{b_n\cdot2^n C}{2^N C + C_p} \\
&= \frac{2^N C}{2^N C + C_p}\left(-V_{in} +
V_{ref}\sum_{n=0}^{N-1}\frac{b_n }{2^{N-n}} \right)
\end{align}\]
That is, it does not change the sign
Comparator offset effect
Synchronous SAR ADC
It also divides a full conversion into several comparison stages in a
way similar to the pipeline ADC, except the algorithm is
executed sequentially rather than in parallel
as in the pipeline case.
However, the sequential operation of the SA algorithm has
traditionally been a limitation in achieving high-speed
operation
a clock running at least \((N + 1) \cdot
F_s\) is required for an \(N\)-bit converter with conversion rate of
\(F_s\)
every clock cycle has to tolerate the worst case comparison
time
every clock cycle requires margin for the clock jitter
The power and speed limitations of a synchronous SA design comes
largely from the high-speed internal clock
The comparator itself trigger the next bit-conversion cycle as soon
as the present bit decision has been taken
The maximum resolving time reduction between synchronous and
asynchronous case is two fold
comparator metastable state
when the input is sufficiently small. The time needed for
the comparator outputs to fully resolve may take arbitrarily
long
In this case, the ready signal generator should still set the
flag and the decision result is simply taken from the previous
value stored in the SR latch
both outputs (\(Q_p\) and \(Q_n\)) will drop together, NAND is
inverter actually
The transition point of this NAND gate is skewed to
eliminate metastability issues arising when the input differential
voltage level is small (comparator)
reference
Andrea Baschirotto, "T6: SAR ADCs" ISSCC2009
Pieter Harpe, ISSCC 2016 Tutorial: "Basics of SAR ADCs Circuits &
Architectures"
Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW
Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006 [pdf,
slides]
C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit
50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in
IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp.
731-740, April 2010 [https://sci-hub.se/10.1109/JSSC.2010.2042254]
L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From
Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State
Circuits Society, vol. 1, pp. 149-161, 2021 [pdf]
W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant
Successive-Approximation-Register Analog-to-Digital Converter With
Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46,
no. 11, pp. 2661-2672, Nov. 2011 [https://sci-hub.st/10.1109/JSSC.2011.2163556]
