KNOW-HOW

Specifying Parameter Distributions Using Statistics Blocks

• process: generate random number once per MC run
• mismatch : generate a random number per instance

reference

Article (20498356) Title: How to vary design variables with statistical distribution to be used with Monte Carlo analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009ErHHEA0

Spectre Circuit Simulator Reference

Rational Fit

Matlab/rationalfit

To resolve the convergence problem of s-parameter in Spectre simulator - rationalfit and write Verilog-A

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filename  = 'touchstone/ISI.S4P';
s4p = read(rfdata.data, filename);
sdd_params = s2sdd(s2p.S_Parameters, 2);
sdd21 = squeeze(sdd_params(2, 1, :));   % s21
freq = s4p.Freq;

% rational fitting
weight = ones(size(sdd21));
weight(floor(end*3/4):end) = 0.2;
weight(2:10) = 0;

[hfit, errb] = rationalfit(freq, sdd21, 'IterationLimit', [4, 16], 'Delayfactor', 0.98, ...
    'Weight', weight, 'Tolerance', -38, 'NPoles', 32);
[sdd21_fit, ff] = freqresp(hfit, freq);

figure(1)
plot(freq/1e9, db(sdd21), 'b-'); hold on;
plot(ff/1e9, db(sdd21_fit), 'r-'); hold off; grid on;
legend('sdd21', 'sdd21\_fit');
xlabel('Freq (GHz)');
ylabel('magnitude (dB)');


ts = 1e-12;
n = 2^18;
trise = 4e-14;
[yout, tout] = stepresp(hfit, ts, n, trise);
figure(2)
plot(tout*1e12, yout, 'b-'); grid on;
xlabel('Time (ps)');
ylabel('V');
title('Step Response');


% write verilog-A
writeva(hfit, 'channel_32poles.va');

Z0

Remember, S-parameters don't mean much unless you know the value of the reference impedance (it's frequently called Z0).

simulator will read sp file's Z0 parameter

The default Z0 exported by EMX is 50

reference

microwaves101, S-parameters (https://www.microwaves101.com/encyclopedias/s-parameters)

Pupalaikis, P. (2020). S-Parameters for Signal Integrity. Cambridge: Cambridge University Press. doi:10.1017/9781108784863

Coelho, C. P., Phillips, J. R., & Silveira, L. M. (n.d.). Robust rational function approximation algorithm for model generation. Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). doi:10.1109/dac.1999.781313

Cadence IEEE IMS 2023, Introducing the Spectre S-Parameter Quality Checker and Rational Fit Model Generator [https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009lplhEAA]

The Complex Art Of Handling S-Parameters: The importance of extraction and fitting to circuit simulation involving S-parameters [https://semiengineering.com/the-complex-art-of-handling-s-parameters]

Rational Fit

Matlab/rationalfit

To resolve the convergence problem of s-parameter in Spectre simulator - rationalfit and write Verilog-A

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filename  = 'touchstone/ISI.S4P';
s4p = read(rfdata.data, filename);
sdd_params = s2sdd(s2p.S_Parameters, 2);
sdd21 = squeeze(sdd_params(2, 1, :));   % s21
freq = s4p.Freq;

% rational fitting
weight = ones(size(sdd21));
weight(floor(end*3/4):end) = 0.2;
weight(2:10) = 0;

[hfit, errb] = rationalfit(freq, sdd21, 'IterationLimit', [4, 16], 'Delayfactor', 0.98, ...
    'Weight', weight, 'Tolerance', -38, 'NPoles', 32);
[sdd21_fit, ff] = freqresp(hfit, freq);

figure(1)
plot(freq/1e9, db(sdd21), 'b-'); hold on;
plot(ff/1e9, db(sdd21_fit), 'r-'); hold off; grid on;
legend('sdd21', 'sdd21\_fit');
xlabel('Freq (GHz)');
ylabel('magnitude (dB)');


ts = 1e-12;
n = 2^18;
trise = 4e-14;
[yout, tout] = stepresp(hfit, ts, n, trise);
figure(2)
plot(tout*1e12, yout, 'b-'); grid on;
xlabel('Time (ps)');
ylabel('V');
title('Step Response');


% write verilog-A
writeva(hfit, 'channel_32poles.va');

Z0

Remember, S-parameters don't mean much unless you know the value of the reference impedance (it's frequently called Z0).

simulator will read sp file's Z0 parameter

The default Z0 exported by EMX is 50

reference

microwaves101, S-parameters (https://www.microwaves101.com/encyclopedias/s-parameters)

Pupalaikis, P. (2020). S-Parameters for Signal Integrity. Cambridge: Cambridge University Press. doi:10.1017/9781108784863

Coelho, C. P., Phillips, J. R., & Silveira, L. M. (n.d.). Robust rational function approximation algorithm for model generation. Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). doi:10.1109/dac.1999.781313

Cadence IEEE IMS 2023, Introducing the Spectre S-Parameter Quality Checker and Rational Fit Model Generator [https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009lplhEAA]

The Complex Art Of Handling S-Parameters: The importance of extraction and fitting to circuit simulation involving S-parameters [https://semiengineering.com/the-complex-art-of-handling-s-parameters]

impulse2pulse

serdes/impulse2pulse.m

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function P = impulse2pulse(I, N, dt)

impulseSize = size(I);

%Convert to Pulse by shifting and adding
P = zeros(impulseSize,'like',I);

for indx=1:N
    P = P + circshift(I, indx,1);
end

P = P*dt;  % `dt` is the width of area

\[ P_k = \Delta t \times \sum_j I_j \]

impulse2step

serdes/impulse2step.m

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function S = impulse2step(I,dt)

[nr,nn] = size(I);

S = zeros(nr,nn,'like',I);
for indx=2:nr
    S(indx,:) = S(indx-1,:) + I(indx-1,:)*dt;
end

\[ S_k = S_{k-1} + I_{k-1}\times \Delta t \]

step2impulse

serdes/step2impulse.m

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function I = step2impulse(S,dt)

I = diff(S)/dt;

\[ I_k = \frac{S_{k+1}- S_{k}}{\Delta t} \]

pulse2impulse

serdes/pulse2impulse.m

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function I = pulse2impulse(P, N, dt )

%   The algorithm computes the step response from the pulse response and
%   then take the derivative to get the impulse response. The derivative
%   calculation has zero delay and is reasonably accurate up to one half
%   the Nyquist rate but then diverges rapidly back to zero at the Nyquist
%   rate.

%Size input waveform
[nr,nc] = size(P);

%Remove DC component of waveform
dcValues = P(1,:);
P = P - repmat(dcValues,nr,1);

% Convert to step response. No circshift here
step = zeros( nr, nc,'like',P );
for jj = 1:nc
    for indx = 1:N:nr
        step(indx:nr,jj) = step(indx:nr,jj) + P(1:nr-indx+1,jj);
    end
end

% Take the derivative
a1 = 0.59;
a3 = -0.03;
stepExt = zeros( nr+6, nc, 'like',P );
I = coder.nullcopy(P);
for jj = 1:nc    
    stepExt(1:3,jj) = step(1,jj);
    stepExt(4:nr+3,jj) = step(:,jj);
    stepExt(nr+4:nr+6,jj) = step(nr,jj);
    I(:,jj) = (a1*(stepExt(5:nr+4,jj) - stepExt(3:nr+2,jj)) + ...
        a3*(stepExt(7:nr+6,jj) - stepExt(1:nr,jj))) / dt;
end

pulse2wave

serdes/pulse2wave.m

% The algorithms utilizes circular convolution to project the pulse

% response onto the data pattern.

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close all;
clear all;
clc;

load('PulseResponseReflective100ps.mat');

P1 = pulse(:,1) - pulse(1,1);
P1 = P1(1:2000);
% P1 = P1 + 0.2;  % dc offset

figure('Name','pulse')
plot(P1)
grid on;

order = 10;
data =zeros(1,512);
data(1, 8) = 1;
data(1, 256) = -1;

figure('Name','input sequence');
stem(data);



W1 = pulse2wave(P1,data,SamplesPerSymbol); 

figure('Name','waveform')
plot(W1)
grid on;

pulse2pda

B. K. Casper, M. Haycock and R. Mooney, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes," 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), Honolulu, HI, USA, 2002, pp. 54-57, doi: 10.1109/VLSIC.2002.1015043.

Chang, Wei-Ju and Ruey-Beei Wu. “Eye diagram estimation and equalizer design method for PAM4.” 2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) (2018): 1-4.

Three fast time-domain system simulation techniques:

• single-bit response method
• double-edge response method
• multiple-edge response method

Single-Bit Response (SBR) Method

Overlapping portions of a pulse response from neighboring bits are referred to as intersymbol interference (ISI). A received waveform is formed by superimposing, in time, the pulse responses of each bit in the sequence, as illustrated in Figure 9, assuming symmetric positive and negative pulses are transmitted for 1s and 0s

To avoid spurious glitches between consecutive ones, rising and falling edge responses shall be symmetric. This is the limitation of SBR method.

Let \(p(t)\) be the SBR of the channel, \(t_s\) be the data sampling phase, \(T\) be the bit time, \(N_c\) is the number of UI in stored pulse response and \(b_m\) be the \(m\)th transmitted symbol. The voltage seen by the receiver's data sampler at the \(m\)th data sample is determined by \[ y_m = \sum_{k=m-N_c+1}^{m}b_kp(t_s+(m-k)T) \] where \(b_k \in [0, 1]\) and \(p(t) \ge 0\)

We always prepend \(Nc-1\) 0s in random bit stream for consistency.

For computation convenient, the pulse need to be positive. For differential signal and amplitude \(V_{peak}\), the peak to peak is \(-V_{peak}\) to \(+V_{peak}\). After pulse added by \(V_{peak}\), peak to peak is \(0\) to \(+2V_{peak}\).

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hold on;

yy_sum = zeros(OSR*Ns, Ns);
for idxBit = 1:Ns
    bs_split = zeros(1, Ns+Nc-1);
    bs_split(idxBit) = bs(idxBit);
    yy = zeros(OSR, Ns);
    for ii = Nc:Nc+Ns-1
        bb = bs_split(ii:-1:ii-Nc+1);
        yy(:,ii-Nc+1) = sum(bb.*yrps, 2);
    end
    yy_cont2 = reshape(yy, [], 1);
    h = plot(yy_cont2);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
    yy_sum(:, idxBit) = yy_cont2;
end
yy_sum = sum(yy_sum, 2);    % merge
plot(yy_sum, 'k--');
plot(yy_cont, 'm-.');
grid on;
legend('sum', 'syn');
title('merge all single bit');
ylabel('mag');
xlabel('Time (\times Ts)');

The pulse response contain rising and falling edge. The 1 bit first rise from -1 to 1, then fall to -1; The 0 bit just do nothing for synthesized waveform with the help of falling edge of 1 bit.

The DC shift help deal with continuous 0 bits.

another SBR example

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A = zeros(10,21);
n = [1:10];

% post cursor
for m = 1:3
    A(m, 11+n(m)) = 0.5;
    A(m, 11-n(m)) = 0.5;
end

% one
for m = 4:10
    A(m, 11) = 1;
end

% h0 or main cursor
h0 = zeros(1, 21);
h0(1, 1) = 0.5;
h0(1, 21) = 0.5;
out = h0;

for m = 1:10
    out = conv(out, A(m, :), "full");
end


stem(out)

Double-Edge Response (DER) Method

To handle the more general cases, with asymmetric rising and falling edges, the system response can be constructed in terms of edge transitions instead of bit responses.

The DER method decomposes the input data pattern, in terms of rising and falling edge transitions. The system response can be calculated by superimposing the shifted versions of the rising and falling edge responses : \[ y_m = \sum_{k=m-N_c+1}^{m}(b_k-b_{k-1})s_k(t_s+(m-k)T) + y_{int} \] where

\[\begin{align} s_i(t) &= r(t) -V_{low} \quad \text{if} \: (b_i\gt b_{i-1}) \\ &= V_{high}-f(t) \quad \text{otherwise} \end{align}\]

\(r(t)\) and \(f(t)\) are the rising and falling edge responses,respectively. \(V_{high}\) and \(V_{low}\) are the steady state DC levels, in response to a constant stream of ones and zeros, respectively. \(y_{int}\) is the initial DC state (either \(V_{high}\) or \(V_{low}\) ).

We always prepend \(Nc\) 0s in random bit stream for consistency.

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figure(1)
subplot(3, 1, 1)
plot(yrc);
hold on;
plot(yfc);
hold off;
legend('rising', 'falling')
grid on;
ylabel('mag');
xlabel('Time (\times Ts)');
title('step response');

subplot(3, 1, 2)
stem(bs, 'k'); grid on;
hold on;
stem((idxPreRspStart:idxPreRspEnd), bs(idxPreRspStart:idxPreRspEnd), "filled", 'r');
stem(idxPreRspStart, bs(idxPreRspStart), 'go');
stem(idxCurData, bs(idxCurData), "filled", 'm');
stem((idxPreRspStart:idxPreRspEnd)+0.5, 0.1.*bd(idxPreRspStart:idxPreRspEnd), 'bd-.');
hold off;
legend('', 'Nc bits', 'y_{int}', 'Current bit', 'Edge Transitions');
ylabel('mag');
xlabel('Time (\times UI)');
title('input stream');

subplot(3, 1, 3)
yy_cont = reshape(yy, [], 1);   % continuous version
plot(yy_cont); grid on;
title('continuous yout')
ylabel('mag');
xlabel('Time (\times Ts)');

figure(2)
hold on;
for idx = idxPreRspStart+1-Nc:idxCurData+32-Nc
    ys = yy(:, idx);
    tt = ((idx-1)*OSR+1:idx*OSR);
    h = plot(tt(:), ys(:), 'LineWidth',3);
    h.Annotation.LegendInformation.IconDisplayStyle = 'off';
end
plot(yy_cont, 'm--', 'LineWidth',1);
hold off;
legend('syn')
ylabel('mag');
xlabel('Time (\times Ts)');
title('synthesize with step response');
grid on;

Reference

T. C. Carusone, "Introduction to Digital I/O: Constraining I/O Power Consumption in High-Performance Systems," in IEEE Solid-State Circuits Magazine, vol. 7, no. 4, pp. 14-22, Fall 2015

Oh, Kyung Suk Dan, and Xing Chao Chuck Yuan. High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting. Prentice Hall, 2011.

Ren, Jihong and Kyung Suk Oh. “Multiple Edge Responses for Fast and Accurate System Simulations.” IEEE Transactions on Advanced Packaging 31 (2008): 741-748.

Shi, Rui. “Off-chip wire distribution and signal analysis.” (2008).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

Matlab - pulse2stateye

Due to this function only output PDF of eye, postprocessing is needed which cumulative sum PDF.

Probability Density Function(PDF) plot

Bit Error Rate(BER) plot

pulse response

DC shift don't affect pulse2stateye function normally

Both pulse [0 0 0 0 .. 0 1 0 0 0 0 0 ...] and [1 1 1 1 ... 1 0 1 1 1 1 ...] can be fed into

pulse2stateye function

CAUTION: the 0 don't mean common voltage but bit 0 , which is -Vpeak in differential link

postprocessing function

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% REF: https://www.mathworks.com/help/serdes/ref/pulse2stateye.html
load('PulseResponseReflective100ps.mat');
modulation = 2;
pulsewave = zeros(size(pulse, 1), 1);
pulsewave = pulse(:, 1);
pulsewave(:,1) = pulsewave - pulsewave(1);  % DC shift, although `pulse2stateye` shift internally

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
%stateye(1:200, 1:200) = 10000;
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')

[ysize, xsize] = size(stateye);
ymid = floor((ysize+1)/2);
upperEyePDF = stateye(ymid:end,:);
lowerEyePDF = stateye(ymid:-1:1,:); % upside down

upperEyeCDF = cumsum(upperEyePDF, 1);
lowerEyeCDF = cumsum(lowerEyePDF, 1);


berlist = [1e-12, 1e-6, 0.01];
lenBer = length(berlist);
upperBERIdx = zeros(lenBer, xsize);
lowerBERIdx = zeros(lenBer, xsize);

for i = 1:lenBer
    for j = 1:xsize
        upperBERIdx(i, j) = find(upperEyeCDF(:, j) >= berlist(i), 1);
        lowerBERIdx(i, j) = find(lowerEyeCDF(:, j) >= berlist(i), 1);
    end
end

% shift idx to algin original stateye
upperBERIdx = ymid - 1 + upperBERIdx;
lowerBERIdx = ymid + 1 - lowerBERIdx;

upperBERVal = vh(upperBERIdx);
lowerBERVal = vh(lowerBERIdx);

tticks = th*SymbolTime*1e12;
figure(2);
lgd = cell(lenBer*2,1) ;
hold on;
for i = 1:lenBer% REF: https://www.mathworks.com/help/serdes/ref/pulse2stateye.html
load('PulseResponseReflective100ps.mat');
modulation = 2;
pulsewave = zeros(size(pulse, 1), 1);
pulsewave = pulse(:, 1);    % remove crosstalk pulse responses

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')

[ysize, xsize] = size(stateye);
ymid = floor((ysize+1)/2);
upperEyePDF = stateye(ymid:end,:);
lowerEyePDF = stateye(ymid:-1:1,:); % upside down

upperEyeCDF = cumsum(upperEyePDF, 1);
lowerEyeCDF = cumsum(lowerEyePDF, 1);


berlist = [1e-12, 1e-6, 0.01];
lenBer = length(berlist);
upperBERIdx = zeros(lenBer, xsize);
lowerBERIdx = zeros(lenBer, xsize);

for i = 1:lenBer
    for j = 1:xsize
        upperBERIdx(i, j) = find(upperEyeCDF(:, j) >= berlist(i), 1);
        lowerBERIdx(i, j) = find(lowerEyeCDF(:, j) >= berlist(i), 1);
    end
end

% shift idx to algin original stateye
upperBERIdx = ymid - 1 + upperBERIdx;
lowerBERIdx = ymid + 1 - lowerBERIdx;

upperBERVal = vh(upperBERIdx);
lowerBERVal = vh(lowerBERIdx);

tticks = th*SymbolTime*1e12;
figure(2);
lgd = cell(lenBer*2,1) ;
hold on;
for i = 1:lenBer
    plot(tticks, upperBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2-1} = strcat('BER=',num2str(berlist(i)));
    plot(tticks, lowerBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2} = "";
end
hold off;
legend(lgd)
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye BER')

figure(3)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave, 'k', tt*1e9, pulsewave-pulsewave(1), 'r--');
legend('original', 'dc shift');
xlim([0 10]);
ylim([-0.65 0.65])
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;
    plot(tticks, upperBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2-1} = strcat('BER=',num2str(berlist(i)));
    plot(tticks, lowerBERVal(i, :), 'Color', cmap(i*15, :));
    lgd{i*2} = "";
end
hold off;
legend(lgd)
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye BER')

figure(3)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave);
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;

pulse without ISI

Vp2p = 1V

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modulation = 2;
SamplesPerSymbol = 32;
pulsewave = zeros(SamplesPerSymbol*16, 1);
pulsewave(3*SamplesPerSymbol:4*SamplesPerSymbol-1, 1) = 1;

[stateye,vh,th] = pulse2stateye(pulsewave,SamplesPerSymbol,modulation);
cmap = serdes.utilities.SignalIntegrityColorMap;
figure(1);
imagesc(th*SymbolTime*1e12,vh,stateye)
colormap(cmap)
colorbar
axis('xy')
xlabel('ps')
ylabel('V')
title('Statistical Eye PDF')


figure(2)
tt = [0:size(pulsewave, 1)-1]*dt;
plot(tt*1e9, pulsewave, 'k', tt*1e9, pulsewave-pulsewave(1), 'r--');
legend('original', 'dc shift');
xlabel('Time (ns)');
ylabel('voltage (V)');
title('pulse response');
grid on;

HSPICE - snpsSimADE

use StatEye Analysis in HSPICE

create netlist with hspiceD in Virtuoso

modify netlist

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P1 vi 0  port=1  Z0=0 LFSR (1 0 0 100p 100p 1G 1 [5,2])
P2 vo 0  port=2  Z0=1G
.stateye T=1ns trf=100p incident_port=1 probe_port=2
.probe stateye eye(2) berC(2) eyeBW(2)
.print stateye eye(2) berC(2) eyeBW(2)

Note bothZ0=0 and Z0=1G are used to remove port's effect, which is used as ideal voltage source and voltage monitor

The .probe stateye command generates netlist.stet# and netlist.stev# for following purposes:

• netlist.stet#: eye(t,v), eyeBW(t,v), eyeV(t), ber(t,v) and bathtubV(t)
• netlist.stet#: eye(t,v), eyeBW(t,v), eyeV(t), ber(t,v) and bathtubV(t)

setup

.cdsinit

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load( strcat( getShellEnvVar("HSPICE_HOME") "/hspice/interface/snpsSimADE.ile" ))

environment variable

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export CDS_LOAD_ENV=CSF
export SNPSSIMADE_LOAD_MODE=HSPICE

references

Sanders, Anthony, Michael Resso and John D'Ambrosia. “Channel Compliance Testing Utilizing Novel Statistical Eye Methodology.” (2004).

X. Chu, W. Guo, J. Wang, F. Wu, Y. Luo and Y. Li, "Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1370-1378, July 2021, doi: 10.1109/TVLSI.2021.3082208.

HSPICE® User Guide: Signal Integrity Modeling and Analysis, Version Q-2020.03, March 2020

IA Title: Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps IA # OIF-CEI-04.0 December 29, 2017 [pdf]

Chris Li Ph.D. student at the University of Toronto [pystateye repo]

Jitter measurements can be classified into three categories: cycle-to-cycle jitter, period jitter, and long-term jitter

Jitter is a key performance parameter. Need to know what matters in each case:

• PJ for digital timing
• LTJ for data converters and serial data
• Phase noise for communications (not all bandwidths matter)

The above Cycle-Cycle Jitter equation is wrong, \(\tau_1\) and \(\tau_2\) are not independent

Short Term Jitter

Period jitter, Jper is the short term variation in clock period compared to the average (mean) clock period.

Cycle-to-Cycle, Jcc is the time difference of two adjacent clock periods

Long Term Jitter (LTJ)

measuring LTJ

Jitter Calculation Examples

Jcc vs Jper

Estimating the RMS cycle-to-cycle jitter if all you have available is the RMS period jitter.

• Cycle-to-cycle jitter - The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as \(J_{CC}\), may be specified as either an RMS or peak-to-peak quantity.
• Period jitter - The short-term variation in clock period over all measured clock cycles, compared to the average clock period. This jitter measure, abbreviated here as \(J_{PER}\), may be specified as either an RMS or peak-to-peak quantity.

Let the variable below represent the variance of a single edge’s timing jitter, i.e. the difference in time of a jittery edge versus an ideal edge, \(\sigma^2_j\)

If each edge’s jitter is independent then the variance of the period jitter can be written as \[\begin{align} \sigma^2_\text{jper} &= (\sigma_\text{j(n+1)}-\sigma_\text{j(n)})^2 \\ &= \sigma_\text{j(n+1)}^2-2\sigma_\text{j(n+1)}\sigma_\text{j(n)})+\sigma_\text{j(n)})^2\\ &= \sigma_\text{j(n+1)}^2+\sigma_\text{j(n)})^2 \\ &=2\sigma^2_j \end{align}\]

In every cycle-to-cycle measurement we use one "interior" clock edge twice and therefore we must account for this

\[\begin{align} \sigma^2_\text{jcc} &= (\sigma_\text{jper(n+1)}-\sigma_\text{jper(n)})^2 \\ &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \end{align}\]

Since each edge's jitter is assumed to be independent and have the same statistical properties we can drop the cross correlation terms and write:

\[\begin{align} \sigma^2_\text{jcc} &=(\sigma_\text{j(n+2)}-2\sigma_\text{j(n+1)}+\sigma_\text{j(n)})^2 \\ &=\sigma_\text{j(n+2)}^2+4\sigma_\text{j(n+1)}^2+\sigma_\text{j(n)}^2 \\ &=6\sigma_\text{j}^2 \end{align}\]

The ratio of the variances is therefore \[ \frac{\sigma^2_\text{jcc}}{\sigma^2_\text{jper}} = \frac{6\sigma_\text{j}^2} {2\sigma_\text{j}^2}=3 \] Then \[ \sigma_\text{jcc} = \sqrt{3}\sigma_\text{per} \]

[Timing 101 #8: The Case of the Cycle-to-Cycle Jitter Rule of Thumb, Silicon Labs]

Cadence Sampled Phase Noise

How to derive edge phase noise from Output Noise in sampled Pnoise simulation, [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/56929/how-to-derive-edge-phase-noise-from-output-noise-in-sampled-pnoise-simulation]

[Shawn Logan, Summary of Study of Cadence Sampled Phase Noise and Jitter Definitions with a Comparison to Conventional Time Interval Error (TIE) for a Driven Circuit]

General relationships between variance of jitter and phase noise

Understanding jitter and phase noise : a circuits and systems perspective

references

AN10007 Clock Jitter Definitions and Measurement Methods, SiTime [pdf]

SERDES Design and Simulation Using the Analog FastSPICE Platform, Silicon Creations [pdf]

Flexible clocking solutions in advanced processes from 180nm to 5nm, Silicon Creations [pdf]

One-size-fits-all PLLs for Advanced Samsung Foundry Processes, Silicon Creations [pdf]

Circuit Design and Verification of 7nm LowPower, Low-Jitter PLLs, Silicon Creations, [pdf]

Lecture 10: Jitter, ECEN720: High-Speed Links Circuits and Systems Spring 2023 [pdf]

https://stackoverflow.com/a/9254257/8037585

As of git 1.6.2, you can use git rebase --root -i

For each commit except the first, change pick to squash.

this works find, but I had to do a forced push. be careful! git push -f

Calibre Interactive stores a list of your most recently opened runsets in your home directory as .cgidrcdb or .cgilvsdb for Calibre Interactive DRC or LVS, respectively.

When invoked, the Calibre DRC and LVS windows automatically load the runset used when the last session was closed.

Runsets are ASCII files that set up Calibre Interactive for a Calibre run. They contain only information that differs from the default configuration of Calibre Interactive. There is a one-to-one correspondence between entry lines in the runset file and fields and button items in the Calibre Interactive user interface. Here is as example of a DRC runset:

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*drcRulesFile: rule_file *drcRulesFileLastLoad: 1009224452 *drcLayoutPaths: ./lab3.gds *drcLayoutPrimary: lab3 *drcResultsFile: ./lab3.db *drcSummaryFile: drc_report *drcRunTurbo: 0 *drcRunRemoteOn: Cluster *drcRemoteLICENSEFILEName: MGLS_LICENSE_FILE *drcRemoteLICENSEFILEValue: /scratch1/mgls/mgclicenses *drcDontWaitForLicense: 0

The runset filename opened at startup (if no runset is specified on the command line) can also be specified by setting the MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC, and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable for LVS. If these environment variables are set, they take precedence over all other runset opening behavior options.

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setenv RUNSET_DIR ../calibre
setenv MGC_CALIBRE_DRC_RUNSET_FILE $RUNSET_DIR/tsmc180nm_drc_runset
setenv MGC_CALIBRE_LVS_RUNSET_FILE $RUNSET_DIR/tsmc180nm_lvs_runset
setenv MGC_CALIBRE_PEX_RUNSET_FILE $RUNSET_DIR/tsmc180nm_pex_runset
setenv CALIBRE_DISABLE_RHEL5_WARNING 1

reference

tsmc_template. https://github.com/lnis-uofu/tsmc_template/tree/main

Calibre Verification User’s Manual

A native layer (NT_N) is usually added under inductors or transformers in the nanoscale CMOS to define the non-doped high-resistance region of substrate, which decreases eddy currents in the substrate thus maintaining high Q of the coils.

For T* PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy currents

OD inside NT_N only can be used for NT_N potential pickup purpose, such as the guarding-ring of MOM and inductor

Derived Geometries

NP: N+ Source/Drain Ion Implantation

PP: P+ Source/Drain Ion Implantation

OD: Gate Oxide and Diffustion

NW: N-WELL

PW: P-WELL

CMOS Processing Technology

Four main CMOS technologies:

• n-well process
• p-well process
• twin-tub process
• silicon on insulator

Triple well, Deep N-Well (optional):

• NWell: NMOS svt, lvt, ulvt ...
• PWell: PMOS svt, lvt, ulvt ...
• DNW: For isolating P-Well from the substrate

The NT_N drawn layer adds no process cost and no extra mask

The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.

The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.

reference

Principles of VLSI Design CMOS Processing CMPE 413 [https://redirect.cs.umbc.edu/~cpatel2/links/315/lectures/chap3_lect09_processing2.pdf]

CMOS processing [http://users.ece.utexas.edu/~athomsen/cmos_processing.pdf]

The Fabrication Process of CMOS Transistor [https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/#:~:text=latch%2Dup%20susceptibility.-,N%2D%20well%2F%20P%2D%20well%20Technology,well%20it%20is%20vice%2D%20verse.]

CMOS Processing Technology [link1, link2]