1-bit DAC

TODO 📅

\(\Delta \Sigma\) ADC: Linearity

!!PD: Non-linear

Dan Boschen Why use a 1-bit ADC in a Sigma Delta Modulator?. [https://dsp.stackexchange.com/questions/53059/why-use-a-1-bit-adc-in-a-sigma-delta-modulator#comment105988_53063]

Dynamic Range

\[ \text{SNR} = 10\log\left(\frac{V_\text{in}^2/2}{\Delta^2/12}\right) \]

FoMs

B. Murmann, "ADC Performance Survey 1997-2022," [Online]. Available: [https://github.com/bmurmann/ADC-survey]

Carsten Wulff, "Advanced Integrated Circuits 2025" [http://analogicus.com/aic2025/2025/02/20/Lecture-6-Oversampling-and-Sigma-Delta-ADCs.html#high-resolution-fom]

Offset & Gain Error

Charge Injection and Clock Feedthrough

Slow Gating, Fast Gating

TODO 📅

Midrise and Midtread Quantizers

\(\Gamma_x\) is no-overload range

Top-Plate vs Bottom-Plate Sampling

[https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf]

Bottom-Plate Sampling

Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling

[https://indico.cern.ch/event/1064521/contributions/4475393/attachments/2355793/4078773/esi_sampling_and_converters2022.pdf]

EE 435 Spring 2024 Analog VLSI Circuit Design - Switched-Capacitor Amplifiers Other Integrated Filters, https://class.ece.iastate.edu/ee435/lectures/EE%20435%20Lect%2044%20Spring%202008.pdf

Top-Plate Sampling

TODO 📅

Maintain constant common-mode during conversion

D. Pfaff et al., "7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024 [https://iccircle.com/static/upload/img20240529101747.pdf]

—, "A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited)," 2025 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-8, doi: 10.1109/CICC63670.2025.10983461.

E. Swindlehurst et al., "An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch," IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, 2021, [https://sci-hub.se/10.1109/JSSC.2021.3057372]

SFDR & INL

Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input signal frequency

Track Time

Finite Acquisition Time - Consider a sinusoidal input

utilizing Laplace transform pair

\[\begin{align} V_\text{in}(t)=\cos{\omega t+\theta} & \overset{\mathcal{L}}{\Rightarrow} \frac{s\cos \theta-\omega \sin \theta}{s^2+\omega^2} \\ h(t) & \overset{\mathcal{L}}{\Rightarrow} \frac{\frac{1}{\tau}}{s+\frac{1}{\tau}} \end{align}\]

Then,

\[\begin{align} V_\text{out}(s) &= V_\text{in}(s)\cdot H(s) \\ &= \frac{s\cos \theta-\omega \sin \theta}{s^2+\omega^2} \cdot \frac{\frac{1}{\tau}}{s+\frac{1}{\tau}} \\ &= \frac{A}{s+\frac{1}{\tau}} + \frac{Bs+C}{s^2+\omega^2} \end{align}\]

Obtain,

\[\begin{align} A &= -\frac{\cos(\theta - \phi)}{\sqrt{\tau ^2 \omega^2 +1}} \\ B & = -A \\ C &= -\frac{\omega \sin(\theta - \phi)}{\sqrt{\tau ^2 \omega^2 +1}} \end{align}\]

That is \[ V_\text{out}(s) = -\frac{\cos(\theta - \phi)}{\sqrt{\tau ^2 \omega^2 +1}} \frac{1}{s+\frac{1}{\tau}} + \frac{1}{\sqrt{\tau ^2 \omega^2 +1}}\frac{s\cos(\theta - \phi) - \omega \sin(\theta - phi)}{s^2+\omega^2} \]

where \(\phi = \arctan(\omega \tau)\)

Boris Murmann, EE315B VLSI Data Conversion Circuits, Autumn 2013 [pdf]

Redundancy

Max tolerance of comparator offset is \(\pm V_{FS}/4\)

1. \(b_j\) error is \(\pm 1\)
2. \(b_{j+1}\) error is \(\pm 2\) , wherein \(b_{j+1}\): \(0\to 2\) or \(1\to -1\)

i.e. complementary analog and digital errors cancel each other, \(V_o +\Delta V_{o}\) should be in over-/under-range comparators (\(-V_{FS}/2 \sim 3V_{FS}/2\))

\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{V_{out,j}+\Delta V_{out,j}}{2} \\ V_{in,{j+1}} &= (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \end{align}\]

with \(V_{in,j+1} = V_{out,j}+\Delta V_{out,j}\)

\[\begin{align} V_{in,j} &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2} \left\{ (b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2} + \frac{V_{out,j+1}+\Delta V_{out,j+1}}{2} \right\} \\ &= (b_j + \Delta b_j)\cdot \frac{V_{FS}}{2} + \frac{1}{2}(b_{j+1} + \Delta b_{j+1})\cdot \frac{V_{FS}}{2}+ \frac{1}{2}\frac{V_{in,j+2}}{2} \\ &=\tilde{b_j} \cdot \frac{V_{FS}}{2}+ \tilde{b_{j+1}}\cdot \frac{V_{FS}}{4}+ \frac{1}{4}V_{in,j+2} \end{align}\]

where \(b_j\) is 1-bit residue without redundancy and \(\tilde{b_j}\) is redundant bits

Uniform Sub-Radix-2 SAR ADC

Minimal analog complexity, no additional decoding effort

Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." (2013). [https://dspace.mit.edu/bitstream/handle/1721.1/82177/861702792-MIT.pdf]

Kuttner, Franz. "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS." 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 1 (2002): 176-177 vol.1. [https://sci-hub.se/10.1109/ISSCC.2002.992993]

T. Ogawa, H. Kobayashi, et. al., "SAR ADC Algorithm with Redundancy and Digital Error Correction." IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A (2010): 415-423. [paper, slides]

B. Murmann, “On the use of redundancy in successive approximation A/D converters,” International Conference on Sampling Theory and Applications (SampTA), Bremen, Germany, July 2013. [https://www.eurasip.org/Proceedings/Ext/SampTA2013/papers/p556-murmann.pdf]

Krämer, M. et al. (2015) High-resolution SAR A/D converters with loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].

sarthak, "Visualising redundancy in a 1.5 bit pipeline ADC“ [https://electronics.stackexchange.com/a/523489/233816]

Testing

TODO 📅

Kent H. Lundberg "Analog-to-Digital Converter Testing" [https://www.mit.edu/~klund/A2Dtesting.pdf]

Tai-Haur Kuo, Da-Huei Lee "Analog IC Design: ADC Measurement" [http://msic.ee.ncku.edu.tw/course/aic/202309/ch13%20(20230111).pdf] [http://msic.ee.ncku.edu.tw/course/aic/aic.html]

ESE 6680: Mixed Signal Design and Modeling "Lec 20: April 10, 2023 Data Converter Testing" [https://www.seas.upenn.edu/~ese6680/spring2023/handouts/lec20.pdf]

Degang Chen. "Distortion Analysis" [https://class.ece.iastate.edu/djchen/ee435/2017/Lecture25.pdf]

ADC INL/DNL

TODO 📅

• Endpoint method
• BestFit method

INL/DNL Measurements for High-Speed Analog-to Digital Converters (ADCs) [https://picture.iczhiku.com/resource/eetop/sYKTSqLfukeHSmMB.pdf]

Code Density Test

Apply a linear ramp to ADC input

Bootstrapped Switch

A. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to Digital Converter," IEEE J. Solid-State Circuits, pp. 599, May 1999 [https://sci-hub.se/10.1109/4.760369]

Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electronics Letters, Jan. 1999. [https://sci-hub.se/10.1049/EL:19990028]

B. Razavi, "The Bootstrapped Switch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15Switch.pdf]

B. Razavi, "The Design of a bootstrapped Sampling Circuit [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 13, Issue. 1, pp. 7-12, Summer 2021. [http://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_1_2021.pdf]

Quantization Noise & its Spectrum

Quantization noise is less with higher resolution as the input range is divided into a greater number of smaller ranges

This error can be considered a quantization noise with RMS

Quantization is NOT Noise

[https://analogicus.com/aic2025/2025/02/20/Lecture-6-Oversampling-and-Sigma-Delta-ADCs.html#quantization]

N. Blachman, "The intermodulation and distortion due to quantization of sinusoids," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 33, no. 6, pp. 1417-1426, December 1985 [https://sci-hub.st/10.1109/TASSP.1985.1164729]

The quantization noise is an infinite sum of input signal odd harmonics, where the amplitude of the harmonics is determined by a sum of a Bessel function

"Quantization noise is white", because for a high number of bits, it looks white in the FFT

ENOB & SQNR

The quantization noise power \(P_Q\) for a uniform quantizer with step size \(\Delta\) is given by \[ P_Q = \frac{\Delta ^2}{12} \] For a full-scale sinusoidal input signal with an amplitude equal to \(V_{FS}/2\), the input signal is given by \(x(t) = \frac{V_{FS}}{2}\sin(\omega t)\)

Then input signal power \(P_s\) is \[ P_s = \frac{V_{FS}^2}{8} \] Therefore, the signal-to-quantization noise ratio (SQNR) is given by \[ \text{SQNR} = \frac{P_s}{P_Q} = \frac{V_{FS}^2/8}{\Delta^2/12}=\frac{V_{FS}^2/8}{V_{FS}^2/(12\times 2^{2N})} = \frac{3\times 2^{2N}}{2} \] where \(N\) is the number of quantization bits

When represented in dBs \[ \text{SQNR(dB)} = 10\log(\frac{P_s}{P_Q}) = 10\log(\frac{3\times 2^{2N}}{2})= 20N\log(2) + 10\log(\frac{3}{2})= 6.02N + 1.76 \]

DAC DNL

One difference between ADC and DAC is that DAC DNL can be less than -1 LSB

In a DAC, DNL < -1LSB implies non-monotonicity

DAC INL

The worst INL of three DAC Architecture is same

• \(A = \sum_{j=1}^k I_j\), \(B=\sum_{j=k+1}^N I_j\)
• A and B are independent with \(\sigma_A^2 = k\sigma_u^2\) and \(\sigma_B^2=(N-k)\sigma_u^2\)

Therefore \[ \mathrm{Var}\left(\frac{X}{Y}\right)\simeq \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{\mathrm{cov}(X,Y)}{kNI_u^2}\right) \] and \[\begin{align} \mathrm{cov}(X,Y) &= E[XY] - E[X]E[Y] = E[A(A+B)] - kNI_u^2 \\ &= E[A^2]+E[A]E[B] - kNI_u^2= \sigma_A^2+E[A]^2 + k(N-k)I_u^2 - kNI_u^2\\ &= k\sigma_i^2 + k^2I_u^2+ k(N-k)I_u^2 - kNI_u^2 \\ &= k\sigma_i^2 \end{align}\]

Finally, \[ \mathrm{Var}\left(\frac{X}{Y}\right)\simeq \frac{k^2}{N^2}\left(\frac{\sigma_i^2}{kI_u^2} + \frac{\sigma_i^2}{NI_u^2} -2\frac{k\sigma_i^2}{kNI_u^2}\right) = \frac{k^2}{N^2}\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 \] i.e. \[ \mathrm{Var(INL(k))} = k^2\left(\frac{1}{k}- \frac{1}{N}\right)\sigma_u^2 = k\left(1- \frac{k}{N}\right)\sigma_u^2 \]

Standard deviation of INL is maximum at mid-scale (k=N/2)

Hold Mode Feedthrough

P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 544-634

B. Sedighi, A. T. Huynh and E. Skafidas, "A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 113-116

Tania Khanna, ESE 568: Mixed Signal Circuit Design and Modeling [https://www.seas.upenn.edu/~ese5680/fall2019/handouts/lec11.pdf]

Coherent Sampling

\[ \frac{f_{\text{in}}}{f_{\text{s}}}=\frac{M_C}{N_R} \]

• \(f_\text{in}\) and \(f_s\) must be incommensurate (\(f_s/f_\text{in}\) is irrational number. btw, co-prime is sufficient but not necessary)

• \(M_C\) and \(N_R\) must be co-prime

• Samples must include integer # of cycles of input signal

An irreducible ratio ensures identical code sequences not to be repeated multiple times.

Given that \(\frac{M_C}{N_R}\) is irreducible, and \(N_R\) is a power of 2, an odd number for \(M_C\) will always produce an irreducible ratio

Assuming there is a common factor \(k\) between \(M_C\) and \(N_R\), i.e. \(\frac{M_C}{N_R}=\frac{k M_C'}{k N_R'}\)

The samples (\(n\in[1, N_R]\))

\[ y[n] = \sin\left( \omega_{\text{in}} \cdot t_n \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_s} \right) = \sin\left( \omega_{\text{in}} \cdot n\frac{1}{f_{\text{in}}}\frac{M_C}{N_R} \right) = \sin\left( 2\pi n\frac{M_C}{N_R} \right) \]

Then

\[ y[n+N_R'] = \sin\left( 2\pi (n+N_R')\frac{M_C}{N_R} \right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{M_C}{N_R}\right) = \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{kM_C'}{kN_R'} \right) = \sin\left( 2\pi n \frac{M_C}{N_R}\right) \]

So, the samples is repeated \(y[n] = y[n+N_R']\)

\(N_R\) & \(M_C\) irreducible ratio (mutually prime)

• Periodic sampling points result in periodic quantization errors
• Periodic quantization errors result in harmonic distortion

Choosing M/N non-prime repeats the signal quantization periodically and fewer quantization steps are measured. The quantization repeats periodically and creates a line spectrum that can obscure real frequency lines (e.g. the red lines in the images below, created by non-linearities of the ADC).

[https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple]

Thermometer to Binary encoder

Pipeline ADC

CMP reference voltage is 0.5vref, DAC output is 0.5vref or 0

residual error \[ V_{r,n} = (V_{r,n-1}-\frac{1}{2}b_{n})\cdot 2 \] and \(V_{r,-1}=V_i\) \[ V_{r,n-1} = 2^{n}V_i -\sum_{k=0}^{n-1}2^{n-k-1}b_k = 2^{n}\left(V_i - \sum_{k=0}^{n-1}\frac{b_k}{2^{k+1}}\right) \]

here, \(b_0\) is first stage and MSB

It divides the process into several comparison stages, the number of which is proportional to the number of bits

Due to the pipeline structure of both analog and digital signal path, inter-stage residue amplification is needed which consumes considerable power and limits high speed operation

Vishal Saxena, "Pipelined ADC Design - A Tutorial"[https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20NonIdealities%20Slides%20v1_0.pdf] [https://www.eecis.udel.edu/~vsaxena/courses/ece517/s17/Lecture%20Notes/Pipelined%20ADC%20Slides%20v1_2.pdf]

Bibhu Datta Sahoo, Analog-to-Digital Converter Design From System Architecture to Transistor-level [http://smdpc2sd.gov.in/downloads/IGF/IGF%201/Analog%20to%20Digital%20Converter%20Design.pdf]

Bibhu Datta Sahoo, Associate Professor, IIT, Kharagpur, [https://youtu.be/HiIWEBAYRJY?si=pjQnIdi03i5N7805]

R-2R & C-2C

TODO 📅

Conceptually, area goes up linearly with number of bit slices

drawback of the R-2R DAC

\(N_b\) bit binary + \(N_t\) bit thermometer DAC

\(N_b\) bit binary can be simplified with Thevenin Equivalent \[ V_B = \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_b-n}} \] with thermometer code

\[\begin{align} V_o &= V_B\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R}+\sum_{n=0}^{2^{N_t}-2}T_n\frac{\frac{2R}{2^{N_t}-1}}{\frac{2R}{2^{N_t}-1}+ 2R} \\ &= \frac{V_B}{2^{N_t}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \\ &= \sum_{n=0}^{N_b-1} \frac{B_n}{2^{N_t+N_b-n}} + \frac{\sum_{n=0}^{2^{N_t}-2}T_n}{2^{N_t}} \end{align}\]

B. Razavi, "The R-2R and C-2C Ladders [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 10-15, Summer 2019 [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_3_2019.pdf]

4bit binary R2R DAC with Ru=1kOhm

RVB equivalent R

Binary-Weighted (BW) DAC

During \(\Phi_1\), all capacitor are shorted, the net charge at \(V_x\) is 0

During \(\Phi_2\), the charge at bottom plate of CDAC \[ Q_{DAC,btm} = \sum_{i=0}^{N-1}(b_i\cdot V_R - V_x)\cdot 2^{i}C_u = C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x \] the charge at the internal plate of integrator \[ Q_{intg} = V_x C_p + (V_x - V_o)2^NC_u \] and we know \(-V_x A = V_o\) and \(Q_{DAC,btm} = Q_{intg}\) \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x = V_x C_p + (V_x - V_o)2^NC_u \] i.e. \[ C_uV_R\sum_{i=0}^{N-1}b_i2^i = (2^N-1)C_uV_x + V_x C_p + (V_x - V_o)2^NC_u \] therefore \[ -V_o = \frac{2^N C_u}{\frac{(2^{N+1}-1)C_u+C_p}{A}+2^NC_u}\sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right)\approx \sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right) \]

Midscale (MSB Transition) often is the largest DNL error

\(C_4\) and \(C_1+C_2+C_3\) are independent (can't cancel out) and their variance is two largest (\(16\sigma_u^2\), \(15\sigma_u^2\), ), the total standard deviation is \(\sqrt{16\sigma_u^2+15\sigma_u^2}=\sqrt{31}\sigma_u\)

reference

Maloberti, F. Data Converters. Dordrecht, Netherlands: Springer, 2007.

Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]

Razavi B. Analysis and Design of Data Converters. Cambridge University Press; 2025.

Aaron Buchwald, ISSCC2010 T1: "Specifying & Testing ADCs" [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Tutorials/T1.pdf]

Ahmed M. A. Ali. CICC 2018: High Speed Pipelined ADCs: Fundamentals and Variants [https://picture.iczhiku.com/resource/eetop/SyIGzGRYsHFehcnX.pdf]

John P. Keane, ISSCC2020 T5: "Fundamentals of Time-Interleaved ADCs" [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T5Visuals.pdf]

Yun Chiu, ISSCC2023 T3: "Fundamentals of Data Converters" [https://www.nishanchettri.com/isscc-slides/2023%20ISSCC/TUTORIALS/T3.pdf]

—， "Design and Calibration Techniques for SAR and Pipeline ADCs" [http://formation-old.in2p3.fr/microelectronique15/IN2P3_ADC.pdf]

—， Radiation-Tolerant SAR ADC Architecture and Digital Calibration Techniques [https://indico.cern.ch/event/385097/attachments/768706/1054353/CERN_May15.pdf]

—， Recent Advances in Multistep Nyquist ADC's [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Recent%20Advances%20in%20Nyquist%20rate%20ADCs.pdf]

Boris Murmann, ISSCC2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [https://www.nishanchettri.com/isscc-slides/2022%20ISSCC/SHORT%20COURSE/SC1.pdf]

—， ISSCC2012 SC3: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/SHORT%20COURSE/SC3Visuals.pdf]

—， A/D Converter Figures of Merit and Performance Trends [https://www.nishanchettri.com/isscc-slides/2015%20ISSCC/CIRCUIT%20INSIGHTS/Murmann.pdf]

Aaron Buchwald, ISSCC 2008 T2 Pipelined A/D Converters: The Basics [pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

Samuel Palermo, ISSCC 2018 T10: ADC-Based Serial Links: Design and Analysis [https://www.nishanchettri.com/isscc-slides/2018%20ISSCC/TUTORIALS/T10/T10Visuals.pdf]

Ahmed M. A. Ali. ISSCC2021 T5: Calibration Techniques in ADCs [https://www.nishanchettri.com/isscc-slides/2021%20ISSCC/TUTORIALS/ISSCC2021-T5.pdf]

Jan Mulder Broadcom. ISSCC2015 T5: High-Speed Current-Steering DACs [https://www.nishanchettri.com/isscc-slides/2015%20ISSCC/TUTORIALS/ISSCC2015Visuals-T5.pdf]

M. Gu, Y. Tao, Y. Zhong, L. Jie and N. Sun, "Timing-Skew Calibration Techniques in Time-Interleaved ADCs," in IEEE Open Journal of the Solid-State Circuits Society [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623]

everynanocounts. Memos on FFT With Windowing. URL: https://a2d2ic.wordpress.com/2018/02/01/memos-on-fft-with-windowing/

How to choose FFT depth for ADC performance analysis (SINAD, ENOB). URL:https://dsp.stackexchange.com/a/38201

Computation of Effective Number of Bits, Signal to Noise Ratio, & Signal to Noise & Distortion Ratio Using FFT. URL:https://cdn.teledynelecroy.com/files/appnotes/computation_of_effective_no_bits.pdf

Kester, Walt. (2009). Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor. URL:https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

T. C. Hofner: Dynamic ADC testing part I. Defining and testing dynamic ADC parameters, Microwaves & RF, 2000, vol. 39, no. 11, pp. 75-84,162

T. C. Hofner: Dynamic ADC testing part 2. Measuring and evaluating dynamic line parameters, Microwaves & RF, 2000, vol. 39, no. 13, pp. 78-94

AN9675: A Tutorial in Coherent and Windowed Sampling with A/D Converters https://www.renesas.com/us/en/document/apn/an9675-tutorial-coherent-and-windowed-sampling-ad-converters

APPLICATION NOTE 3190: Coherent Sampling Calculator (CSC) https://www.stg-maximintegrated.com/en/design/technical-documents/app-notes/3/3190.html

Coherent Sampling (Very Brief and Simple) https://www.dsprelated.com/thread/469/coherent-sampling-very-brief-and-simple

Signal Chain Basics #160: Making sense of coherent and noncoherent sampling in data-converter testing https://www.planetanalog.com/signal-chain-basics-160-making-sense-of-coherent-and-noncoherent-sampling-in-data-converter-testing/

Signal Chain Basics #104: Understanding noise in ADCs https://www.planetanalog.com/signal-chain-basics-part-104-understanding-noise-in-adcs/

Signal Chain Basics #101: ENOB Degradation Analysis Over Frequency Due to Jitter https://www.planetanalog.com/signal-chain-basics-part-101-enob-degradation-analysis-over-frequency-due-to-jitter/

Clock jitter analyzed in the time domain, Part 1, Texas Instruments Analog Applications Journal (slyt379), Aug 2010 https://www.ti.com/lit/an/slyt379/slyt379.pdf

Clock jitter analyzed in the time domain, Part 2 https://www.ti.com/lit/slyt389

Measurement of Total Harmonic Distortion and Its Related Parameters using Multi-Instrument [pdf]

Application Note AN-4: Understanding Data Converters' Frequency Domain Specifications [pdf]

Belleman, J. (2008). From analog to digital. 10.5170/CERN-2008-003.131. [pdf]

HandWiki. Coherent sampling [link]

Luis Chioye, TI. Leverage coherent sampling and FFT windows when evaluating SAR ADCs (Part 1) [link]

Coherent Sampling vs. Window Sampling | Analog Devices https://www.analog.com/en/technical-articles/coherent-sampling-vs-window-sampling.html

Understanding Effective Number of Bits https://robustcircuitdesign.com/signal-chain-explorer/understanding-effective-number-of-bits/

ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise? [https://www.analog.com/en/resources/analog-dialogue/articles/adc-input-noise.html]

Walt Kester, Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care [https://www.analog.com/media/en/training-seminars/tutorials/MT-001.pdf]

Dan Boschen, "How to choose FFT depth for ADC performance analysis (SINAD, ENOB)", [https://dsp.stackexchange.com/a/38201]

B. Razavi, "A Tale of Two ADCs - Pipelined Versus SAR" IEEE Solid-State Circuits Magazine, Volume. 7, Issue. 30, pp. 38-46, Summer 2015 [https://www.seas.ucla.edu/brweb/papers/Journals/BRSummer15ADC.pdf)]

Dr. Tai-Haur Kuo (郭泰豪 教授) Analog IC Design (類比積體電路設計) [http://msic.ee.ncku.edu.tw/course/aic/aic.html]

Converter Passion for data-converter professionals sharing thoughts on ADCs and DACs [https://converterpassion.wordpress.com/]

Boris Murmann, EE315B VLSI Data Conversion Circuits, Autumn 2013 [pdf]

MPScholar Analog-to-Digital Converters (ADCs) [https://www.monolithicpower.com/en/learning/mpscholar/analog-to-digital-converters]

tomverbeure. List of Analog Devices Tutorials [https://tomverbeure.github.io/2021/02/15/Analog-Devices-Tutorials.html]

replica biasing

TODO 📅

current mirror with source follower

source follower alleviate gate leakage impact on reference current

constant-gm

aka. Beta-multiplier reference

\(I_\text{out}\) is PTAT in case temperature coefficient of \(R_s\) is less than that of \(\mu_n\)

Body effect of M2

Boris Murmann, Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables

S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias Circuits," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022

S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver , May 2004

Why MOS in saturation ?

\(g_m\), \(g_\text{ds}\) at fixed \(V_\text{GS}\)

\(g_{ds}\) is constant in saturation region

in triode region \[ g_{ds} = \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS}) \]

Interestingly, \(g_m\) in the saturation region is equal to the inverse of \(R_\text{on}\) in the deep triode region.

\(g_m\), \(g_\text{ds}\) at fixed \(I_d\), \(V_G\)

In triode region \[ I_D = \frac{1}{2}\mu_nC_{ox}\frac{W}{L}[2(V_{GS}-V_{TH})V_{DS}-V_{DS}^2] \] where \(I_D\) and \(V_G\) is fixed

Then \(V_S\) can be expressed with \(V_D\), that is \[ V_S = V_{GT} - \sqrt{(V_{GT}-V_D)^2+V_{dsat}^2} \] where \(V_{GT}=V_G-V_{TH}\), \(V_{dsat}\) is \(V_{DS}\) saturation voltage \[ g_m = \mu_nC_{ox}\frac{W}{L}\left(V_D-V_{GT}+\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}\right) \] Then \[ \frac{\partial g_m}{\partial V_D} \propto 1 - \frac{V_{GT}-V_D}{\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}} \gt 0 \]

That is, \(g_m \propto V_D\)​

\[\begin{align} g_{ds} &= \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS}) \\ &= \mu_nC_{ox}\frac{W}{L}(V_{GT}-V_{D}) \end{align}\]

That is, \(g_{ds} \propto -V_D\)

Both gain and speed degrade once entering triode region, though Id is constant

Cascode MOS

The low threshold voltage of cascode MOS don't help decrease the minimum output voltage

Channel-length modulation

❗ There it not channel-length modulation in the triode region

\[\begin{align} I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\frac{\Delta L}{L}) \\ I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\lambda V_{DS}) \\ I_D &=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2(1+\frac{V_{DS}}{V_A}) \end{align}\]

where \(\frac{\Delta L}{L}=\lambda V_{DS}\) and \(V_A=\frac{1}{\lambda}\)

\(\lambda\) is channel length modulation parameter

\(V_A\), i.e. Early voltage is equal to inverse of channel length modulation parameter

The output resistance \(r_o\)

\[\begin{align} r_o &= \frac{\partial V_{DS}}{\partial I_D} \\ &= \frac{1}{\partial I_D/\partial V_{DS}} \\ &= \frac{1}{\lambda I_D} \\ &= \frac{V_A}{I_D} \end{align}\]

Due to \(\lambda \propto 1/L\), i.e. \(V_A \propto L\) \[ r_o \propto \frac{L}{I_D} \]

The output resistance is almost doubled using Stacked FET in saturation region

\(V_t\) and mobility \(\mu_{n,p}\) are sensitive to temperature

• \(V_t\) decreases by 2-mV for every 1\(^oC\) rise in temperature
• mobility \(\mu_{n,p}\) decreases with temperature

Overall, increase in temperature results in lower drain currents

current mirror mismatch

The current mismatch consists of two components.

• The first depends on threshold voltage mismatch and increases as the overdrive \((V_{GS} − V_t)\) is reduced.
• The second is geometry dependent and contributes a fractional current mismatch that is independent of bias point.

\[ \Delta I_D = g_m\cdot \Delta V_{TH}+I_D\cdot \frac{\Delta(W/L)}{W/L} \]

where mismatches in \(\mu_nC_{ox}\) are neglected

\[\begin{align} \Delta V_{TH} &= \frac{A_{VTH}}{\sqrt{WL}} \\ \frac{\Delta(W/L)}{W/L} &= \frac{A_{WL}}{\sqrt{WL}} \end{align}\]

summary:

Biasing current source and global variation Monte Carlo

iwl: biased by mirror

iwl_ideal: biased by vdc source, whose value is typical corner

For local variation, constant voltage bias (vb_const in schematic) help reduce variation from \(\sqrt{2}\Delta V_{th}\) to \(\Delta V_{th}\)

For global variation, all device have same variation, mirror help reduce variation by sharing same \(V_{gs}\)

1. global variation + local variation (All MC)

2. local variation (Mismatch MC)

3. global variation (Process MC)

We had better bias mos gate with mirror rather than the vdc source while simulating sub-block.

This is real situation due to current source are always biased by mirror and vdc biasing don't give the right result in global variation Monte Carlo simulation (542.8n is too pessimistic, 13.07p is right result)

Small gain theorem

Dr. Degang Chen, EE 501: CMOS Analog Integrated Circuit Design [https://class.ece.iastate.edu/djchen/ee501/2020/References.ppt]

For any given constant values of u and v, the constant values of variables that solve the the feed back relationship are called the operating points, or equilibrium points.

Operating points can be either stable or unstable.

An operating point is unstable if any or some small perturbation near it causes divergence away from that operating point.

If the loop gain evaluated at an operating point is less than one, that operating point is stable.

This is a sufficient condition

With \(m_{1\to 2} = 1\) \[ \text{Loop Gain} \simeq \frac{V_{BN}-V_{T2}}{V_{BN}-V_{T2} + V_R} \tag{$LG_0$} \] Assuming all MOS in strong inv operation, \(I\), \(V_{BN}\) and \(V_R\) is obtain \[\begin{align} I &= \frac{2\beta _1 + 2\beta _2 - 4\sqrt{\beta _1 \beta _2}}{R^2\beta _1 \beta _2} \\ V_{BN} &= V_{T2} + \frac{2}{R\beta _2}(1- \sqrt{\frac{\beta _2}{\beta _1}}) \\ IR &= \frac{2}{R}\left( \frac{1}{\sqrt{\beta_2}} - \frac{1}{\sqrt{\beta_1}} \right) \end{align}\]

Substitute \(V_{BN}\) and \(V_R\) of \(LG_0\) \[\begin{align} \text{Loop Gain} & \simeq \frac{1-\sqrt{\frac{\beta_2}{\beta_1}}}{\frac{\beta_2}{\beta_1} - 3\sqrt{\frac{\beta_2}{\beta_1}}+2} \\ &= \frac{1}{2-\sqrt{\frac{\beta_2}{\beta_1}}} \tag{$LG_1$} \end{align}\]

Alternative approach for Loop Gain

using derivation of large signal

❗❗❗ R should not be on the other side

Self-Biasing Cascode

reference

B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 6-16, Summer 2021, doi: 10.1109/MSSC.2021.3088963

Correlated Double Sampling (CDS)

TODO 📅

Dynamic Element Matching (DEM)

TODO 📅

Galton, Ian. (2010). Why dynamic-element-matching DACs work. Circuits and Systems II: Express Briefs, IEEE Transactions on. 57. 69 - 74. 10.1109/TCSII.2010.2042131. [https://sci-hub.se/10.1109/TCSII.2010.2042131]

KHIEM NGUYEN. Analog Devices Inc, "Practical Dynamic Element Matching Techniques for 3-level Unit Elements" [https://picture.iczhiku.com/resource/eetop/shihEDaaoJjFdCVc.pdf]

E. Alvarez-Fontecilla, P. S. Wilkins and S. C. Rose, "Understanding High-Resolution Dynamic Element Matching DACs [Feature]," in IEEE Circuits and Systems Magazine, vol. 23, no. 4, pp. 34-43, Fourthquarter 2023

E. Alvarez-Fontecilla and P. S. Wilkins, "Linearity Through Democracy [Feature]," in IEEE Circuits and Systems Magazine, vol. 25, no. 1, pp. 58-69, Firstquarter 2025

Autozeroing

offset is sampled and then subtracted from the input

Measure the offset somehow and then subtract it from the input signal

low gain comparator

Residual Noise of Auto-zeroing

pnosie Noise Type: timeaverage

\(\Pi\)-Capacitor

\[\begin{align} (V_a-V_{a0})C_0 + (\overline{V_a - V_b} - \overline{V_{a0} - V_{b0}})C_1 &= \Delta Q_a \\ (V_b-V_{b0})C_0 + (\overline{V_b - V_a} - \overline{V_{b0} - V_{a0}})C_1 &= \Delta Q_b \end{align}\]

therefore we obtain \[\begin{align} V_a + V_b &= \frac{\Delta Q_a + \Delta Q_b}{C_0} + V_{a0} + V_{b0} \\ V_a - V_b &= \frac{\Delta Q_a - \Delta Q_b}{C_0+2C_1} + V_{a0} - V_{b0} \end{align}\] Then \[\begin{align} V_a &= \frac{\Delta Q_a(C_0+C_1)+\Delta Q_b C_1}{C_0(C_0+2C_1)} + V_{a0} \\ V_b &= \frac{\Delta Q_aC_1+\Delta Q_b (C_0+C_1)}{C_0(C_0+2C_1)} + V_{b0} \end{align}\]

rearrange the above equation \[\begin{align} V_a &= \frac{\Delta Q_a}{C_0} + \frac{\Delta Q_b-\Delta Q_a}{C_0(\frac{C_0}{C_1}+2)} + V_{a0} \\ V_b &= \frac{\Delta Q_b}{C_0} + \frac{\Delta Q_a-\Delta Q_b}{C_0(\frac{C_0}{C_1}+2)} + V_{b0} \end{align}\]

The difference between \(V_a\) and \(V_b\) \[ V_a - V_b = \frac{I_a-I_b}{C_0+2C_1}t + V_{a0} - V_{b0} \]

\(C_1\) save total capacitor area while retaining the same \(V_a - V_b\) due to \(\Delta I_{a,b}\), in comparison to \(C_0\)

at autozero phase \[\begin{align} I_{a0} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{a0} - V_{TH})^2 \\ I_{Rb} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{b0} - V_{TH})^2 \end{align}\]

then \[ \Delta I_0 = \frac{1}{2}(V_{a0} - V_{b0})(g_{m,a0}+g_{m,b0}) \] where \(g_{m,a0}+g_{m,b0} = \mu C_{OX}\frac{W}{L}(V_{a0}+V_{b0} - 2V_{TH})\)

at comparison phase \[\begin{align} I_{a1} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{a1} - V_{TH})^2 \\ I_{b1} &= \frac{1}{2}\mu C_{OX}\frac{W}{L}(V_{b1} - V_{TH})^2 \end{align}\]

then \[ \Delta I_1 = \frac{1}{2}(V_{a1} - V_{b1})(g_{m,a1}+g_{m,b1}) \] That is, \(g_{m,a1}+g_{m,b1} = \mu C_{OX}\frac{W}{L}(V_{a1}+V_{b1} - 2V_{TH})\)

To minimize the difference between \(\Delta I_1\) and \(\Delta I_0\), the drift of both differential and common mode between \(V_a\) and \(V_b\) shall be alleviated

Chopping

offset is modulated away from the signal band and then filtered out

Modulate the offset away from DC and then filter it out

Good: Magically reduces offset, 1/f noise, drift

Bad: But creates switching spikes, chopper ripple and other artifacts …

Chopping in the Frequency Domain

Square-wave Modulation

definition of convolution \(y(t) = x(t)*h(t)= \int_{-\infty}^{\infty} x(\tau)h(t-\tau)d\tau\)

for real signal \(H(j\omega)^*=H(-j\omega)\)​

\[ H(j\hat{\omega})*H(j\hat{\omega}) = \int_{-\infty}^{\infty}H(j\omega)H(j(\hat{\omega}-\omega))d\omega \]

The Fourier Series of squarewave \(x(t)\) with amplitudes \(\pm 1\), period \(T_0\)

\[ C_n = \left\{ \begin{array}{cl} 0 &\space \ n=0 \\ 0 &\space \ n=\text{even} \\ |\frac{2}{n\pi}| &\space n=\pm 1,\pm 5,\pm9, ... \\ -|\frac{2}{n\pi}| &\space n=\pm 3,\pm 7,\pm11, ... \end{array} \right. \]

The Fourier transform of \(s(t)=x(t)x(t)\), and we know \[\begin{align} S(j2n\omega_0) &= \frac{1}{2\pi}\int X(j(2n\omega_0 -\omega))X(j\omega) d\omega\\ &= \frac{1}{2\pi}\int X(j(\omega-2n\omega_0))X(j\omega) d\omega \end{align}\]

Therefore \(n=0\) \[ S(j0) = \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}2\sum_{n=0}^{+\infty}\frac{1}{(2n+1)^2} \delta(\omega) = 2\pi \delta(\omega) \]

if \(n=1\)

\[\begin{align} S(j2\omega_0) &= \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}\left(1 - 2\sum_{n=0}^{+\infty}\frac{1}{(2n+1)(2n+3)} \right) \\ &= \frac{1}{2\pi} (2\pi)^2\cdot \frac{4}{\pi ^2}\left(1 - 2\sum_{n=0}^{+\infty}\frac{1}{2}\left[\frac{1}{2n+1}- \frac{1}{2n+3}\right] \right) \\ &= 0 \end{align}\]

\(n=2\) \[\begin{align} \sum &= -\frac{2}{3} + 2\left(\frac{1}{1\times 5}+ \frac{1}{3\times 7}+ \frac{1}{5\times 9} + \frac{1}{7\times 11}+...\right) \\ &= -\frac{2}{3} + 2\cdot \frac{1}{4}\left(\frac{1}{1}-\frac{1}{5}+ \frac{1}{3}- \frac{1}{7}+ \frac{1}{5} - \frac{1}{9} +\frac{1}{7}-\frac{1}{11}+...\right) \\ &= -\frac{2}{3} + 2\cdot \frac{1}{4}\frac{4}{3} = 0 \end{align}\]

That is, the input signal remains the same after chopping or squarewave up/down modulation

EXAMPLE 2.7 in R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

Prove that \(\pi^2/8 = 1 + 1/3^2 + 1/5^2 + 1/7^2 + \cdots\) [https://math.stackexchange.com/a/2348996]

Bandwidth & Gain Accuracy

• lower effective gain: DC level at the output of the amplifiers is a bit less than what it should be

• chopping artifacts at the even harmonics: frequency of output is \(2f_{ch}\)

Below we justify \(A_\text{eff} = A(1-4\tau/T_\text{ch})\) \[\begin{align} V_o(t) &= A + (V_0-A)e^{-t/\tau} \\ V_o(T/2) &= -V_0 \end{align}\]

then \[ V_0 = -A\frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}} \] Then DC level is \[ A_\text{eff} = \frac{1}{T/2}\int_0^{T/2} V_o(t)dt = A\left(1-\frac{4\tau}{T}\cdot \frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}}\right)\approx A\left(1-\frac{4\tau}{T}\right) \]

where assuming \(\tau \ll T\)

REF. [https://raytroop.github.io/2023/01/01/insight/#rc-charge-discharge]

Residual Offset of Chopping

assume input spikes can be expressed as \[ V_\text{spike}(t) = V_o e^{-\frac{t}{\tau}} \]

Then, residual offset is

\[\begin{align} \overline{V_\text{os}} &= \frac{2\int_0^{T_{ch}/2}V_\text{spike}(t)dt}{T_{ch}} \\ &= 2f_{ch}V_o\int_0^{T_{ch}/2} e^{-\frac{t}{\tau}}dt\\ &= 2f_{ch}V_o\tau\int_0^{T_{ch}/2\tau} e^{-\frac{t}{\tau}}d\frac{t}{\tau} \\ &\approx 2f_{ch}V_o\tau \end{align}\]​

Ripple Cancellation after Chopping

On-chip analog filter is not good enough due to limited cutoff frequency

at \(\Phi_+\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[n] &= \frac{I_l[n]-I_r[n-1]}{G_m} \\ \left(I_0+\frac{V_\text{os0}-\Delta V_\text{os}[n]}{R_E}\right)\beta &= I_l[n]+I_r[n-1] \end{array} \right. \] Then \[ \left\{ \begin{array}{cl} I_r[n-1] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] at \(\Phi_-\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[n] &= \frac{I_l[n-1]-I_r[n]}{G_m} \\ \left(I_0+\frac{-V_\text{os0}+\Delta V_\text{os}[n]}{R_E}\right)\beta &= I_l[n-1]+I_r[n] \end{array} \right. \] Then \[ \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n-1] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] \(\Phi_+ \to \Phi_-\) state transformation \[ \left\{ \begin{array}{cl} I_r[n-1] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \to \left\{ \begin{array}{cl} I_r[n+1] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] Two \(I_l[n]\) shall be equal, that is \[ \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 = \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \] Rearrange the above equation \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \] \(\Phi_- \to \Phi_+\) state transformation \[ \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n-1] &= \frac{G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \to \left\{ \begin{array}{cl} I_r[n] &= \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \\ I_l[n+1] &= \frac{G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \end{array} \right. \] Two \(I_r[n]\) shall be equal, that is \[ \frac{-G_mR_E+\beta}{2R_E}\cdot \Delta V_\text{os}[n] - \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 = \frac{-G_mR_E-\beta}{2R_E}\cdot \Delta V_\text{os}[n+1] + \frac{\beta}{2R_E}V_\text{os0}+\frac{\beta}{2}I_0 \] Rearrange the above equation \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \]

Both State-transition equations are same \[ \Delta V_\text{os}[n+1] = \frac{G_mR_E-\beta}{G_mR_E+\beta}\Delta V_\text{os}[n] + \frac{2\beta}{G_mR_E+\beta}V_\text{os0} \] With geometric progression sum formula \[ \Delta V_\text{os}[n] = \left(\frac{G_mR_E-\beta}{G_mR_E+\beta}\right)^n\cdot \Delta V_\text{os}[0] + \left[1-\left(\frac{G_mR_E-\beta}{G_mR_E+\beta}\right)^n\right]\cdot V_\text{os0} \] during \(n \to \infty\) \[ \lim_{n\to \infty} \Delta V_\text{os}[n] = V_\text{os0} \] As expected \[ \lim_{n\to \infty} V_\text{os}[n] =\lim_{n\to \infty} V_\text{os0}-\Delta V_\text{os}[n] = 0 \]

Assuming that begainning from \(\Phi_+\) phase \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[0] &= \frac{I_l[0]-I_r[-1]}{G_m} \\ \left(I_0+\frac{V_\text{os0}-\Delta V_\text{os}[0]}{R_E}\right)\beta &= I_l[0]+I_r[-1] \end{array} \right. \overset{\mathcal{I_r[-1]=0}}{\Longrightarrow} \Delta V_\text{os}[0]=\frac{(I_0R_E+V_\text{os0})\beta}{G_mR_E+\beta} \] With \(I_0=10\mu A\), \(R_E=5k \Omega\), \(V_\text{os0}=20mV\), \(G_m=500\mu S\), \(\beta=0.5\) \[ \left\{ \begin{array}{cl} \Delta V_\text{os}[0] &= 167mV \\ \frac{G_mR_E-\beta}{G_mR_E+\beta} &= 0.667 \end{array} \right. \]

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DVos0 = 167;  % mV
Vos0 = 20; % mV
Rr = 0.667;

n = 1:1:50;
DVosn_DVos0 = Rr.^n*DVos0;
DVosn_Vos0 = (1-Rr.^n)*Vos0;
DVosn = DVosn_DVos0 + DVosn_Vos0;

plot(n, DVosn_DVos0,'--r', LineWidth=2);
hold on
plot(n, DVosn_Vos0, '--g', LineWidth=2);
plot(n, DVosn, 'b', LineWidth=3);
plot(-5:1:55, ones(1,61)*Vos0, '--k', LineWidth=2)

grid on;
xlim([-5, 55]);ylim([-5, 120]);
xlabel('n', FontSize=16); ylabel('mV', FontSize=16);
legend('$\Delta V_{os}[0]$ decaying','$V_{os0}$ decaying','$\Delta V_{os}[n]$', '$V_{os0}$', 'Interpreter','latex', fontsize=16)

reference

C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," in Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996, doi: 10.1109/5.542410. [http://www2.ing.unipi.it/~a008309/mat_stud/MIXED/archive/2019/Articles/Offset_canc_Enz_Temes_96.pdf]

Kofi Makinwa. Precision Analog Circuit Design: Coping with Variability, [https://youtu.be/nA_DZtRqrTQ?si=6uyOpJhdnYm3iG9d] [https://youtu.be/uwRpP20Lprc?si=SGPta86jRCdECSob]

Chung-chun Chen, Why Design Challenge in Chopping Offset & Flicker Noise? [https://youtu.be/ydjca2KrXgc?si=2raCIB99vXriMPsq]

—, Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise? [https://youtu.be/y7TzJtHE7IA?si=kUeP_ESofVxp3IT_]

Qinwen Fan, Evolution of precision amplifiers

Kofi Makinwa, ISSCC 2007 Dynamic-Offset Cancellation Techniques in CMOS [https://picture.iczhiku.com/resource/eetop/sYkywlkpwIQEKcxb.pdf]

Axel Thomsen, Silicon Laboratories ISSCC2012 T8: "Managing Offset and Flicker Noise" [slides,transcript]

CC Chen. Why Dynamic Offset or Mismatch Cancellation with Auto-zeroing Technique? [https://youtu.be/PQJwzd1tyO0]

—. Why Dynamic Offset or Mismatch Cancellation with Chopping Technique? [https://youtu.be/x5FS8jEKu_g]

—. Why Design Challenge in Chopping Offset & Flicker Noise? [https://youtu.be/ydjca2KrXgc]

—. Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise? [https://youtu.be/y7TzJtHE7IA]

Qinwen Fan, Kofi Makinwa. IEEE Sensors 2018: Capacitively-Coupled Chopper Instrumentation Amplifiers : an Overview [https://youtu.be/NoGHJfCFCks]

AM, PM (asymmetric sideband)

The spectrum of the narrowband FM signal is very similar to that of an amplitude modulation (AM) signal but has the phase reversal for the other sideband component

Assume the modulation frequency of PM and AM are same, \(\omega_m\)

\[\begin{align} x(t) &= (1+A_m\cos{\omega_m t})\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= \cos(\omega_0 t + P_m \sin\omega_m t) + A_m\cos{\omega_m t}\cos(\omega_0 t + P_m \sin\omega_m t) \\ &= X_{pm}(t) + X_{apm}(t) \end{align}\]

\(X_{pm}(t)\), PM only part \[ X_{pm}(t) = \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{P_m}{2}\cos(\omega_0 + \omega_m)t \] \(X_{apm}(t)\), AM & PM part \[\begin{align} X_{apm}(t) &= A_m \cos{\omega_m t} (\cos\omega_0 t-P_m\sin\omega_m t\sin\omega_0 t) \\ &= \frac{A_m}{2}[\cos(\omega_0 + \omega_m)t + \cos(\omega_0 -\omega_m)t] - \frac{A_mP_m}{2}\sin(2\omega_m t)\sin(\omega_0 t) \\ &= \frac{A_m}{2}\cos(\omega_0 + \omega_m)t + \frac{A_m}{2}\cos(\omega_0 -\omega_m)t - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]

That is \[\begin{align} x(t) &= \cos\omega_0 t + \frac{A_m-P_m}{2}\cos(\omega_0 - \omega_m)t + \frac{A_m+P_m}{2}\cos(\omega_0 + \omega_m)t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - 2\omega_m)t + \frac{A_mP_m}{4}\cos(\omega_0 + 2\omega_m)t \end{align}\]

For general case, \(x(t) = (1+A_m\cos{\omega_{am} t})\cos(\omega_0 t + P_m \sin\omega_{pm} t)\), i.e., PM is \(\omega_{pm}\), AM is \(\omega_{am}\)

\[\begin{align} x(t) &= \cos\omega_0 t - \frac{P_m}{2}\cos(\omega_0 - \omega_{pm})t + \frac{P_m}{2}\cos(\omega_0 + \omega_{pm})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_m}{2}\cos(\omega_0 - \omega_{am})t + \frac{A_m}{2}\cos(\omega_0 + \omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}-\omega_{am})t + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}+\omega_{am})t \\ &\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space\space + \frac{A_mP_m}{4}\cos(\omega_0 + \omega_{pm}-\omega_{am})t - \frac{A_mP_m}{4}\cos(\omega_0 - \omega_{pm}+\omega_{am})t \end{align}\]

Therefore, sideband is asymmetric if \(\omega_{pm} = \omega_{am}\) same

Ken Kundert, Measuring AM, PM & FM Conversion with SpectreRF [https://designers-guide.org/analysis/am-pm-conv.pdf]

Emad Hegazi , Jacob Rael , Asad Abidi, 2005. The Designer's Guide to High-Purity Oscillators [https://picture.iczhiku.com/resource/eetop/whkgGLPAHoORYxbC.pdf]

AN-PN Conversion

G. Giust, Influence of Noise Processes on Jitter and Phase Noise Measurements [https://www.signalintegrityjournal.com/articles/800-influence-of-noise-processes-on-jitter-and-phase-noise-measurements]

—. "Methodologies for PCIe5 Refclk Jitter Analysis,", PCI-SIG Electrical Workgroup Meeting (Jan. 19, 2018)

—. How to Identify the Source of Phase Jitter through Phase Noise Plots [https://www.sitime.com/company/newsroom/blog/how-identify-source-phase-jitter-through-phase-noise-plots]

AN10072 Determine the Dominant Source of Phase Noise, by Inspection [https://www.sitime.com/support/resource-library/application-notes/an10072-determine-dominant-source-phase-noise-inspection]

Enrico Rubiola, February 7, 2025. Phase Noise - Art, Science and Experimental Methods [https://rubiola.org/pdf-lectures/Scient-Instrum-Files/!-Phase-noise.pdf]

Amplitude Noise

Deog-Kyoon Jeong. Topics in IC Design: 1.1 Introduction to Jitter [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%201%20-%20Jitter%20and%20Phase%20Noise.pdf]

with \(x(t) = A_0\sin (2\pi f_0 t +\phi _0)\), then \(y(t) = x(t) + n_v(t)\)

\[\begin{align} R_y(\tau) &= \mathrm{E}[y(t)y(t+\tau)] \\ &= \mathrm{E}[x(t)x(t+\tau)] + \mathrm{E}[x(t)]\mathrm{E}[n_v(t+\tau)] + \mathrm{E}[x(t+\tau)]\mathrm{E}[n_v(t)] + \mathrm{E}[n_v(t)n_v(t+\tau)]\\ &= \mathrm{E}[x(t)x(t+\tau)] + \mathrm{E}[n_v(t)n_v(t+\tau)] \\ &= R_x(\tau) + R_{n_v}(\tau) \end{align}\]

phase noise analyzer vs spectrum analyzer

TODO 📅

Phasor representation

Timing 201 #1: The Case of the Phase Noise That Wasn't - Part 1 [https://community.silabs.com/s/share/a5U1M000000knpiUAA/timing-201-1-the-case-of-the-phase-noise-that-wasnt-part-1?]

[https://en.lntwww.de/Modulation_Methods/Single-Sideband_Modulation]

Narrowband FM Approximation

\[ y(t) = A\cos(2\pi f_0t+\phi_n(t)) \approx A \cos(2\pi f_0 t) - A \phi_n (t)\sin(2\pi f_0 t) \]

\[ R_x(\tau) = \frac{A^2}{2}\cos(2\pi f_0\tau) + \frac{A^2}{2}R_\phi(\tau)\cos(2\pi f_0\tau) \] The PSD of the signal x(t) is given by \[ S_x(f) = \mathcal{F}\{R_x(\tau)\} = \frac{P_c}{2}\left[\delta(f+f_0)+\delta(f-f_0)\right]+\frac{P_c}{2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] \] where \(P_c = A^2/2\) is the carrier power of the signal

Modulation of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: Modulation of Random Processes

modulated with a random cosine

modulated with a deterministic cosine

Hayder Radha, ECE 458 Communications Systems Laboratory Spring 2008: Lecture 7 - EE 179: Introduction to Communications - Winter 2006–2007 Energy and Power Spectral Density and Autocorrelation

Sampling of WSS process

Balu Santhanam, Probability Theory & Stochastic Process 2020: Impulse sampling of Random Processes

DT sequence \(x[n]\)

Owing to \(\phi[0] = \phi_c(0)\), the average power of the sampled version \(x[n]\) is the same as its input \(x_c(t)\)

impulse train \(x_s(t)\)

That is \[ P_{x_s x_s} (f)= \frac{1}{T_s^2}P_{xx}(f) \] where \(x[n]\) is sampled discrete-time sequence, \(x_s(t)\) is sampled impulse train

Noise Aliasing

apply foregoing observation

Rectangular Pulse Sampling

Balu Santhanam. ece439 Introduction to Digital Signal Processing. Example: Rectangular Pulse Sampling [http://ece-research.unm.edu/bsanthan/ece439/recsamp.pdf]

reference

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]

R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th ed., Wiley, 2013 [pdf]

John G. Proakis and Masoud Salehi, Fundamentals of communication systems 2nd ed [pdf]

Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System Perspectives and Circuit Design Aspects. John Wiley & Sons

Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers, oscillators, samplers, and logic: an introduction to cyclostationary noise." Proceedings of the IEEE 2000 Custom Integrated Circuits Conference. [pdf, slides]

Antoni, J., "Cyclostationarity by examples", Mechanical Systems and Signal Processing, vol. 23, no. 4, pp. 987–1036, 2009 [https://docente.unife.it/docenti/dleglc/a-a-2010-2011-dmsm/ciclostazionarieta.pdf]

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF. URL:https://designers-guide.org/analysis/sc-filters.pdf

STEADY-STATE AND CYCLO-STATIONARY RTS NOISE IN MOSFETS [https://ris.utwente.nl/ws/portalfiles/portal/6038220/thesis-Kolhatkar.pdf]

Christian-Charles Enz. "High precision CMOS micropower amplifiers" [pdf]

changing Library Reference

ACMatch

ACMatch analysis linearizes the circuit about the DC operating point and computes the variations of AC responses due to statistical parameters defined in statistics blocks.

Only mismatch parameters are considered. The analysis skips the process parameters.

Imag 1-Sigma \[ \sqrt{50.2^2 + 57.9^2} = 76.6 \]

ViVA Marker Table

Window->Assistants->Vert Marker Table

Window->Assistants->Horiz Marker Table

[https://community.cadence.com/cadence_blogs_8/b/cic/posts/things-you-didn-t-know-about-virtuoso-delta-markers-in-viva]

Layout XL

IC61电路新添加器件XL更新（两种方法）

①　重新Layout XL后→Connectivity→Generate→Selected From Source（先去原理图选择新器件再操作）

②　重新Layout XL后→Connectivity→update→Components And Nets→OK

IC61 Net飞线关系

Connectivity→Nets→Show/Hide All Incomplete Nets

IC61加线名

Connectivity→Nets→Assign→F3

Layout XL里面的黄色框框 已有 1109 次阅读| 2021-9-7 17:25 |系统分类:芯片设计

在使用layout XL的时候，有些器件的连线没有按照生成的对应关系连线，当update connectivity information when design is modifed ON，就会出现很多黄色的框框，在菜单栏里点击Verify->Markers->Delete All即可一键删除。

[https://blog.eetop.cn/home.php?mod=space&uid=1542900&do=blog&id=6947553]

[https://blog.eetop.cn/blog-1768341-6947567.html]

s-Domain Controlled Source

Layout XL pointing to new schematic

Connectivity(Menu in Layout View) ---> Update ---> Connectivity Reference

Hide Color

noiseon & noiseoff

Options -> Analog...

only work in presimu simulation (excluding lpe.spi)

vsource with noisefile

1. both rise/fall edge are added the noisefile
2. noise between rise and fall edge are partially correlated

Pnoise sampled(jitter) with Sampled Phase

vsource output is applied with noise all the time

Loockup Table vs Equations Model in Verilog-A

Solar Cell Verilog Model for Cadence [https://miscircuitos.com/solar-cell-verilog-model-for-cadence/]

How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-A [https://miscircuitos.com/how-to-create-a-model-in-verilog-a-with-a-lockup-table/]

with Equation

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/////////////////////////////////////////////////////////////////////////////
//
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell IXYS
//
// Change history: 1/7/2018
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"

module SolarCell( EN, Vsolar, GND);

input EN;
electrical EN;

output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

parameter real vdd = 1.2;
parameter real vthreshold = 0.6;
parameter real fc = 10M;
parameter real light = 6;

//Curve parameters
real gm;
real A;
real factor;
real Vop;
real vcp;

integer light_i;
integer en;
analog begin

    @(initial_step)    begin 
        en = 0;
        A = 1;    
        Vop = 1;
        factor = 10;
    end
//Enable digitalization
    @(cross(V(EN)-vthreshold,1)) begin
        if(V(EN)>=vthreshold) en = 1;
        else en = 0;
    end
        
    case(light):
            0: begin A = 0; Vop = 0; end
            1: begin A = -1.2; Vop = 1.71; end
            2: begin A = -0.8; Vop = 1.64; end
            3: begin A = -0.4; Vop = 1.50; end
            4: begin A = 0.1; Vop = 1.43; end
            5: begin A = 0.7; Vop = 1.36; end
            6: begin A = 1.1; Vop = 1.22; end
            default: begin A = -1.2; Vop = 1.71; end
        endcase

    //gm = A + atan(factor*(Vop-V(Vsolar))); //Transconductance

    vcp=laplace_nd(V(Vsolar,GND),{1},{1,1/(6.28*fc)});

    I(Vsolar,GND) <+  (A + atan(factor*(vcp -Vop)))/1000;

end //analog
endmodule

with lookup table

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///////////////////////////////////////////////////////////////////////////
// Engineer: Alberto Lopez
//
// Description: Verilog model of the solar cell photodiode
//
// Change history: 11/Sept/2019
//
/////////////////////////////////////////////////////////////////////////////
`include "constants.vams"
`include "disciplines.vams"
 
module SolarCell_Table( EN, Vsolar, GND);
 
input EN;
electrical EN;
 
output Vsolar;
electrical Vsolar;
output GND;
electrical GND;

 
//Curve parameters
parameter real light =1;
parameter real vthreshold = 0.6;

real Vcp;
real iout, itemp;
real i1,i2, i3, i4, i5;
integer en;
analog begin
 
    @(initial_step)    begin 
        en = 0;
    end

//Enable function
    @(cross(V(EN) -vthreshold,1)) begin
        if(V(EN)>=vthreshold) en = 1;
        else en = 0;
    end

    Vcp = V(Vsolar,GND)*1000;

    i1 =  -$table_model (Vcp, "ph4_1.tbl", "1C")/1000000;
    i2 =  -$table_model (Vcp, "ph4_2.tbl", "1C")/1000000;
    i3 =  -$table_model (Vcp, "ph4_3.tbl", "1C")/1000000;
    i4 =  -$table_model (Vcp, "ph4_4.tbl", "1C")/1000000;
    i5 =  -$table_model (Vcp, "ph4_5.tbl", "1C")/1000000;

//    if(itemp <0 ) iout = itemp;
//    else iout = 0;
    case (light)
        1: iout = i1;
        2: iout = i2;
        3: iout = i3;
        4: iout = i4;
        5: iout = i5;
        default: iout = 0;
    endcase
    
    if(en== 0) iout = 0;

    I(Vsolar,GND) <+  iout;
 
end //analog
endmodule

PEX LAYER_MAP

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// *LAYER_MAP
// *1 POLY
// *2 CONT
// *3 M1
...
*RES
8 ENL:30 ENL:34 0.525075 // $lvl=3
9 ENL ENL:30 0.07 // $lvl=3

[https://picture.iczhiku.com/resource/eetop/wYItYWLPleWrpvNV.pdf]

nodeset & initial condition

• A nodeset steers the convergence in a particular direction - useful to speed up DC convergence

• An initial condition is useful when you want to force the circuit to start a transient in a particular condition

[https://community.cadence.com/cadence_technology_forums/f/rf-design/29843/ade--difference-between-node-set-and-initial-condition/1335460]

Remove prefix from multiple files in Linux console

Bash

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for file in prefix*; do mv "$file" "${file#prefix}"; done;

The for loop iterates over all files with the prefix. The do removes from all those files iterated over the prefix.

Here is an example to remove "bla_" form the following files:

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bla_1.txt
bla_2.txt
bla_3.txt
blub.txt

Command

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for file in bla_*; do mv "$file" "${file#bla_}";done;

Result in file system:

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1.txt
2.txt
3.txt
blub.txt

[https://gist.github.com/guisehn/5438bbc22138435665c6e996493fe02b]

remove .cdslck

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 #!/bin/sh
tree -if | grep 'cdslck' > txt
var=`cat txt`
for i in $var; do
	rm -i $i
done
rm -i txt

[https://wikis.ece.iastate.edu/vlsi/index.php?title=Tips_%26_Tricks#Locked_Files_in_Cadence]

Custom Bindkey

schBindKeys.il

schematic

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alias bk hiSetBindKey
when ( isCallable('schGetEnv')
bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")")
bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")")
bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")")
bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()")
bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)")
)
unalias bk

leBindKeys.il

layout

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alias bk hiSetBindKey
when ( isCallable('leGetEnv)
    bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" )
    ; M1-VIA1-M2
    bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" )
    ; M2-VIA2-M3
    bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" )
    ; M3-VIA3-M4
    bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" )
    ; M4-VIA4-M5
	; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them
    bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" )
    ; all visiable
    bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" )
)
unalias bk

Design Variable in vpwlf

PWL File as Design Var? parameter in vpwlf cell is convenient for sweep simulation or corner simulation, wherein there are multiple pwl files .

The file path should be surrounded with double-quotes to be protected from evaluation.

save option

Using Spectre Save Effectively RAK

none:

​ Does not save any data (currently does save one node chosen at random)

selected:

​ Saves only signals specified with save statements. The default setting.

lvlpub:

Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.

lvl:

​ Saves all signals up to nestlvl deep in the subcircuit hierarchy. This option is relevant for subcircuits.

allpub:

​ Saves only signals that are normally useful.

all:

​ Saves all signals.

Signals that are "normally useful" include the shared node voltages and currents through voltage sources and iprobes, and exclude the internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain, source on a FET, and so on). It also excludes currents through inductors, controlled sources, transmission lines, transformers, etc.

If you use lvl or all instead of lvlpub or allpub, you will also get internal node voltages and currents through other components that happen to compute current.

Thus, using *pub excludes internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain and source on a FET, etc). It also excludes the currents through inductors, controlled sources, transmission lines, transformers, etc.

nestlvl

This variable is used to save groups of signals as results and when signals are saved in subcircuits. The nestlvl parameter also specifies how many levels deep into the subcircuit hierarchy you want to save signals.

virtuoso "dlopen failed to open 'libdl.so'"

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$ sudo yum install glibc-devel  

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Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST.                                                         
Dependencies resolved.
=========================================================================================================================================
 Package                            Architecture              Version                                    Repository                 Size
=========================================================================================================================================
Installing:
 glibc-devel                        x86_64                    2.28-189.5.el8_6                           baseos                     78 k
Installing dependencies:
 glibc-headers                      x86_64                    2.28-189.5.el8_6                           baseos                    482 k
 kernel-headers                     x86_64                    4.18.0-372.26.1.el8_6                      baseos                    9.4 M
 libxcrypt-devel                    x86_64                    4.1.1-6.el8                                baseos                     24 k

Transaction Summary
=========================================================================================================================================
Install  4 Packages

SpiceIn foundary's standard cell's spice netlist

use SpiceIn GUI feature to map MOS parameter correctly in generated schematic

Input

The mos's total width (parameter name "w") value will update during SpiceIn trigger CDF callback automatically

Output

Device Map

User Prop Mapping is significant setup, both xxx.spi and Edit CDF provide the essential information.

The map syntax is spice_para0 cdf_para0 spice_para1 cdf_para01 ... spice_paraN cdf_paraN

reference

Article (20488179) Title: How to use SpiceIn GUI feature to map MOS parameter correctly in generated schematic URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdPWEAY

Article (11724692) Title: SpiceIn maps the netlist parameter to the CDF parameter incorrectly on the generated schematic devices (e.g. w to wf) URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nZ2CEAU

Model Library Setup

In order to set up model files automatically in the Model Library Setup form for Spectre or AMS simulator in ADE Explorer or ADE Assembler

Add the following line in your .cdsinit

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envSetVal( "spectre.envOpts" "modelFiles" 'string "<path_to model_file>/myModels.scs")

or

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envSetVal("spectre.envOpts" "modelFiles" 'string "moreModels;ff mymodels;tt")

DSPF for each corner

Create a new file with an extension scs like myDSPF_Files.scs

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* DSPF files to use with Corner Definitions
* This is an example file showing how to define different dspf files for different corners
* using model files for individual components as the
* building blocks.
simulator lang=spectre
library dspf_files_corners

section rctyp_25
dspf_include "DSPF_RC_TYPNOM25.spf"
endsection rctyp_25

section rctyp_125
dspf_include "DSPF_RC_TYP125.spf"
endsection rctyp_125

section rcworst_25
dspf_include "DSPF_RC_WORSE25.spf"
end section rcworst_25

section rcworst_125
dspf_include "DSPF_RC_WORSE125.spf"
end section rcworst_125

endlibrary dspf_files_corners

Add the file created above ‘myDSPF_File.scs’ in ‘Add/Edit Model Files’ of Corners setup form

split pins in dspf_emir

dspf extract using starrc

multiple label and rectangle in vssa net

• general dspf

  SHORT_PINS: YES

  

  other pin are short together

• dspf for emir analysis

It seems that dspf_emir don't contain the rectangle pin information.

only label is necessary

shortPins="yes" is preferred default option for dspf_emir, which has split pins

DSPF Syntax

• ::=*|P ? describes pins in the net. Multiple pin descriptions can be listed in one line.

• ::=( {}?) represents the name of the pin. represents the type of the pin. It can be any of the following: I (Input), O (Output),

  ​ B (Bidirectional), X (don’t care), S (Switch), and J (Jumper). ​ represents the capacitance value associated with the pin. ​ is optional. It represents the location of the pin. Multiple pin locations are allowed

split pins

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*|P (avss_1 O 0 207.7555 59.9170)
*|P (avss_10 O 0 181.1610 151.1130)
*|P (avss_11 O 0 186.6330 151.1130)
*|P (avss_12 O 0 192.1050 151.1130)
*|P (avss_13 O 0 197.5770 151.1130)

reference

Article (20467964) Title: Difference in result on running Spectre APS with EMIR and without EMIR analysis URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000679GRUAY

StarRC User Guide and Command Reference Version O-2018.06, June 2018

DSPF Options

Case Sensitivity

For a dspf format, it will be treated as a spice netlist format, which is by default case insensitive

Pay attention to VerilogIn block, which may contain upper case / lower case net name, e.g NET1 and net1.

The extracted DSPF using extraction tool also contain NET1 and net1, which shall not be shorted together.

Port Order

If you use .dspf_include, the following rules apply:

• The subcircuit description is taken from the DSPF file even if the same subcircuit description is available in the schematic netlist.
• Depending on the port_order option, the port order of the subcircuit definition is taken from the pre-layout schematic netlist or from the DSPF file subcircuit definition, as shown below.
  • port_order=sch – (Default). The port order is taken from schematic subcircuit definition. The same port number and names are required. If the schematic subcircuit definition is not available, a warning is issued in the log file, and DSPF port order is used.
  • port_order=spf – The port order is taken from the DSPF subcircuit definition.

SPICE_SUBCKT_FILE of StarRC

The StarRC tool reads the files specified by the SPICE_SUBCKT_FILE command to obtain port ordering information. The files control the port ordering of the top cell as well. The port order and the port list members read from the .subckt for a skip cell are preserved in the output netlist.

The file usually is the cdl netlist of extracted cell, this way, port order is not problem

CDF termOrder

DSPF same order

DSPF

input.scs

different order

manual change DSPF's pin order shown as below

port_order=sch

dspf port is mapping to schematic by name, and the simulation result is right

port_order=spf

dspf pin order is retained, and no mapping between spectre netlist and dspf.

The simulation result is wrong

bus_delim="_ <>"

The way this works is that the first part of bus_delim is the "schematic" delimiter (i.e. what's in the spectre netlist), and the other part is the DSPF delimiter

reference

Article (20502176) Title: How does Spectre understand case-sensitive net names when using various post-layout netlists such as dspf, av_extracted view, or smart view? URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fthoEAA

spf in cadence https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31326/spf-in-cadence/1342278#1342278

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1

StarRC™ User Guide and Command Reference Version O-2018.06, June 2018

Virtual Connectivity

Normally, if the layout connectivity extractor finds disjoint, unconnected geometries with the same net name text attached, the extractor will view this as an open circuit.

• Virtual connection results in the extraction of a single net from two or more disjoint physical nets when the physical net segments share the same name.
• Virtual connectivity is triggered by the rule file VIRTUAL CONNECT COLON and VIRTUAL CONNECT NAME specification statements.
• Virtual connectivity can also be specified through the Calibre Interactive GUI.

Virtual connectivity is of primary interest in LVS applications

connect all nets by name: VIRTUAL CONNECT NAME "?"

VIRTUAL CONNECT COLON

Virtual Connect Colon is used to virtually connect nets that share a common prefix before a colon, like VDD:1, VDD:2, and so forth.

If you specify YES, then the connectivity extractor first strips off all characters from the first colon to the end of the label names.

Next, the extractor forms a virtual connection between any two labels that have the same name and that originally contained a colon.

Colons can appear anywhere in the name with the exception that a colon at the beginning of a name is treated as a regular character (that is, it has no special effect).

up to the first colon character encountered

The colon is discarded in the extracted net name

VIRTUAL CONNECT NAME

Virtual Connect Name virtually connects nets that share the same name

Each name is a net name and can be optionally enclosed in quotes.

The connectivity extractor forms a virtual connection between any two labels having the same name such that the label name appears in a Virtual Connect Name specification statement in the rule file.

VIRTUAL CONNECT NAME ? == Connect all nets by name

Note that if Virtual Connect Colon YES is also specified, then Virtual Connect Name operates on names after all colon suffixes have been stripped off.

Calibre Fundamentals: Performing DRC/LVS Student Workbook

Calibre Verification User’s Manual Software Version 2019.3 Document Revision 7

Y.Liu. PDK Training - Calibre user guide [https://picture.iczhiku.com/resource/eetop/SyKTloquGiZeHMbx.pdf]

Calibre Runsets

Calibre Interactive stores a list of your most recently opened runsets in your home directory as .cgidrcdb or .cgilvsdb for Calibre Interactive DRC or LVS, respectively.

When invoked, the Calibre DRC and LVS windows automatically load the runset used when the last session was closed.

Runsets are ASCII files that set up Calibre Interactive for a Calibre run. They contain only information that differs from the default configuration of Calibre Interactive. There is a one-to-one correspondence between entry lines in the runset file and fields and button items in the Calibre Interactive user interface. Here is as example of a DRC runset:

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*drcRulesFile: rule_file *drcRulesFileLastLoad: 1009224452 *drcLayoutPaths: ./lab3.gds *drcLayoutPrimary: lab3 *drcResultsFile: ./lab3.db *drcSummaryFile: drc_report *drcRunTurbo: 0 *drcRunRemoteOn: Cluster *drcRemoteLICENSEFILEName: MGLS_LICENSE_FILE *drcRemoteLICENSEFILEValue: /scratch1/mgls/mgclicenses *drcDontWaitForLicense: 0

The runset filename opened at startup (if no runset is specified on the command line) can also be specified by setting the MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC, and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable for LVS. If these environment variables are set, they take precedence over all other runset opening behavior options.

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setenv RUNSET_DIR ../calibre
setenv MGC_CALIBRE_DRC_RUNSET_FILE $RUNSET_DIR/tsmc180nm_drc_runset
setenv MGC_CALIBRE_LVS_RUNSET_FILE $RUNSET_DIR/tsmc180nm_lvs_runset
setenv MGC_CALIBRE_PEX_RUNSET_FILE $RUNSET_DIR/tsmc180nm_pex_runset
setenv CALIBRE_DISABLE_RHEL5_WARNING 1

reference

tsmc_template. https://github.com/lnis-uofu/tsmc_template/tree/main

Calibre Verification User’s Manual

DC sweep & parametric sweep

swpuseprevic

variables with statistical distribution

Specifying Parameter Distributions Using Statistics Blocks

• process: generate random number once per MC run
• mismatch : generate a random number per instance

Article (20498356) Title: How to vary design variables with statistical distribution to be used with Monte Carlo analysis

Spectre Circuit Simulator Reference

DC operating points during TRANSIENT

Andrew Beckettover 11 years ago

Two approaches:

1. On the transient options form, there's a field called "infotimes" - specify the times at which you want it to output the dc operating point data. You can then annotate the "transient operating points" from any of these times after the simulation, or access them via the results browser.
2. Or you could get the operating point data to be continuously saved during the transient for selected devices - if so, create a file called (say) "save.scs" (make sure it has a ".scs" suffix), and put: save M1:oppoint or save M*:oppoint sigtype=dev in this file, and then reference the file via Setup->Model Libraries or as a "definition file" on Setup->Simulation Files. With this approach you can then find the operating point data for the selected devices in the results browser and plot it versus time (be cautious of saving too much though because this can generate a lot of data if you're not careful)

Regards,

Andrew.

transient options form

setup

access 1

right-click \(\to\) Annotate \(\to\) Transient Operating Points

access 2

tranOpTimed

save.scs

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save M0:oppoint

How to Save Node in DSPF?

DSPF Semantics

*|DIVIDER <divider>

<divider> represents the hierarchical pathname divider. The default hierarchical character is forward slash (/).

*|DELIMITER <delimiter>

• <delimiter> represents the delimiter character used to concatenate an instance name and pin name to form an instance pin name.
• It is also represents the delimiter character used to concatenate a net name and subnode number to form a subnode name. The default character is colon (:)

*|BUSBIT <left_busbit_char><right_busbit_char>

<left_busbit_char> and <right_busbit_char> are used at the end of an identifier of an array to select a single object of the array.

Objects which may be indexed include nets, primary pins, and instance pins

*|NET <netName> <netCap>

• <netName> represents the name of a net. It can be a user-provided net name, the name of the driving pin, or the name of the driving instance pin.
• <netCap> represents the total capacitance value in farads associated with the net. This may be comprised of capacitances to ground and capacitances to nearby wires.

*|P <pinName> <pinType> <pinCap> {<coord>}

• <pinName> represents the name of the pin.
• <pinType> represents the type of the pin. It can be any of the following: I (Input), O (Output), B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
• <pinCap> represents the capacitance value associated with the pin.
• <coord> is optional. It represents the location of the pin. Multiple pin locations are allowed.

*|S <subNodeName> {<coord>}

subnodes in the net

• <subNodeName> represents the name of the subnode. A subnode name is obtained by concatenating the net name and a subnode number using the delimiter specified in the DELIMITER statement. The default delimiter is colon (:).
• <coord> represents the location of the subnode.

*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}

describes instance pins in the net

• <instPinName> represents the name of the instance pin. An instance pin name is obtained by concatenating the <instName> and the <pinName> with a delimiting character which is specified by the DELIMITER statement
• <instName> represents the name of the instance

*|DeviceFingerDelim "@"

MOS finger delimiter

For example, M8's finger is 4, then split into 4 Devices in DSPF

MM8, MM8@2, MM8@3, MM8@4

its drain terminal will be

MM8:d, MM8@2:d, MM8@3:d, MM8@4:d

DSPF Syntax

DSPF has two sections:

• a net section

  The net section consists of a series of net description blocks. Each net description block corresponds to a net in the physical design. A net description block begins with a net statement followed by pins, instance pins, subnodes, and parasitic resistor/capacitor (R/C) components that characterize the electrical behavior of the net.

• an instance section

  The instance section consists of a series of SPICE instance statements. SPICE instance statements begin with an X.

Each file consists of hierarchical cells and interconnects only.

The DSPF format is as generic and as much like SPICE as possible. While native SPICE statements describe the R/C sections, some non-native SPICE statements complete the net descriptions. These non-native SPICE statements start with the notation "*|" to differentiate them from native SPICE statements. For native SPICE statements, a continuation line begins with the conventional "+" sign in the first column.

The native SPICE statements used by the DSPF format are listed below:

• .SUBCKT represents a subcircuit statement.
• .ENDS represents the end of a subcircuit statement.
• R represents a resistor element.
• C represents a capacitor element.
• E represents a voltage-controlled voltage sources element.
• X represents an instance of a cell;
• * represents a comment line unless it is *| or *+.
• .END is an optional statement that represents the end of a simulation session

spectre netlist

hier_delimiter="."

Used to set hierarchical delimiter. Length of hier_delimiter should not be longer than 1, except the leader escape character

spfbusdelim = busdelim_schematic [busdelim_parasitic]

This option maps the bus delimiter between schematic netlist and parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus delimiter in the schematic netlist, and optionally the bus delimiter in the parasitic file. By default, the bus delimiter of the parasitic file is taken from the parasitic file header (i.e. |BUSBIT [], |BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not defined in the parasitic file header, you need to specify it by using the spfbusdelim option in schematic netlist.

Exampel

• spfbusdelim=<> - A<1> in the schematic netlist is mapped to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is "_".
• spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1] in the DSPF file (the bus delimiter in DSPF header will be ignored).

How to Save Net voltage in DSPF

!!! follow the name of net section in DSPF - prepend to top-level devices in the schematic with X

Assume node n1...n4 are named as below in DSPF file (prefix X)

• n1

  XXosc/zip:1

• n2

  XXosc/zip:2

• n3

  XXosc/zip:3

• n4

  XXosc/zip:4

To save these nodes, you can add follow code in Definition Files

saveopt.scs

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save Xwrapper.Xvco.XXosc\/zip\:1
save Xwrapper.Xvco.XXosc\/zip\:2
save Xwrapper.Xvco.XXosc\/zip\:3
save Xwrapper.Xvco.XXosc\/zip\:4

• Escape character \ is used for hierarchical pathname divider / and subnode :

• By the way, . is hierarchical delimiter of Spectre

• Calibre always prepend one X to instance name of schematic in generated DSPF file

• The DSPF design is flatten, the DIVIDER character indicate the hierarchy

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save Xwrapper.Xvco.XXosc\/zip

The above save voltage, however I'm NOT sure which node it save.

To avoid this unsure problem, the MOS terminal may be better choice to save.

But keep in mind

• OD resistance is lumped in the FEOL model
• M0OD and above layer resistances are extracted by RC tool

How to Save Current in DSPF

!!! follow the name of instance section of DSPF - prepend to top-level devices in the schematic with XX

MOS in schematic: Xsupply.M4

MOS related information in DSPF (prefix XX in instance section):

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...
// net section
*|I XXsupply/MM4:d XXsupply/MM4 d B 0.0 

...
//instance section
XXXsupply/MM4 XXsupply/MM4:d XXsupply/MM4:g XXsupply/MM4:s XXsupply/MM4:b pch_svt_mac
+ L=... W=... nfin=...
+ ...

To save drain current:

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save Xvco.XXXsupply\/MM4:d

<instName> in *|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?} which has prefix X corresponding to schematic is NOT the instance name in DSPF. The instance name is in instance section and has prefix XX

!!! Only work for MOS terminal current. Fail to apply to block pin

Thinking about voltage and current save

• MOS device always prepend with M
• To save net voltage, take account of the prefix X of top-level device
• To save MOS terminal, take account of the prefix XX of top-level device

Post-layout netlists are created by layout extraction tools - Mentor Calibre

Differences Between DSPF and Schematic Names

• MOS Terminal Mismatch ( ‘s’ vs ‘1’)
  • Schematic: number '1' ,'2', '3','4'
  • DSPF: 'd', 'g', 's','b'

.simrc file

If DSPF files show such differences, you can set options in the .simrc file to update the save statement in the netlist so that the device names match with those in the DSPF file

Additionally, dspf_include reads all the DSPF lines starting with * (|NET, |I, *|P,*|S), while include considers all related lines as comments.

Only verified to DSPF output of Mentor Calibre

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; ensure that the netlist is recreated each time
nlReNetlistAll=t

dspfFileEnvOptions = '(
        nil
        spfFileNameMappingFormat "cdl“
        spfFileTermDelimiter “:”
        spfFileHierDelimiter “/”
        spfFileFingerDelimiter “@”
        spfFileNetMapping “mixed”
        spfFileTerminalMapping “lower”
        spfFileAddPrefixToDevice t
        spfFileAddContextSensitivePrefix t
        spfFileDeviceDefaultPrefix “X”
        spfFileDevicePrefixForTermCurrent “X”
        spfFileDevicePrefixForOppoints “X“
        
)

spfFileDevicePrefixForTermCurrent and spfFileDevicePrefixForOppoints are applicable to MOS devices only.

Both @ and __ have been observed as Finger Delimiter in single DSPF . wired...

signal name saved using wildcard operator

How to find the signal name saved using wildcard operator with save statement in spectre?

method 1

From ADE L or ADE XL Test Editor, you can use menu Simulation → Options → Analog→ Miscellaneous → Addition arguments field:dump_wildcard_info=yes

method 2

add below in netlist file or Simulation Files → Definition Files:saveopt.scs

saveopt.scs

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wcOption options dump_wildcard_info=yes

saved file

After running simulation, saved wildcard summary is save into file <netlist_file_name>.wildcard.out*

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Wildcard match summary:

save * nodes: 68
    0
    vdd!
    I0.net10
    I0.net15
    I0.I8.net30

Save and Plot terminal voltage in ADE Explorer and Assembler

.cdsinit

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envSetVal("auCore.selection" "terminalSelectionType" 'cyclic "current")

Available options are current, voltage, both or prompt and the default is current which matches the default behavior in previous releases.

• The schematic will have an ellipse annotation where a current probe has been saved,
• a V annotation for a voltage probe,
• and both annotations for both.

NOTE: Starting with IC 6.1.8 ISR5, you can now set this from Options->Plotting/Printing

Interpreting _noxref Entries

You enable gate recognition in the Calibre nmLVS-H tool. Normally, the _noxref names are internal to the gate

Saving net with hierarchy delimiter and colon (:) in net name gives WARNING (SPECTRE-8282) during simulation

Problem

I am running simulation using an spf/spef file which has a net name definition as shown in the below example:

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// input.scs
simulator lang=spice
.subckt pi_rc a z
r1 a x1a 1k
r2 x1a x1/x1:DRN 1k
cb x1/x1:DRN z 200f
.ends

xpi1 in 0 pi_rc
vdd in 0 pwl (0 0 1n 0 1.1n 10)

simulator lang=spectre
myopt options hier_ambiguity=lower
tran tran stop=2u

save xpi1.x1\/x1:DRN

The net name is x1/x1:DRN. During the simulation, the following warning is reported:

Warning from spectre during initial setup.

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WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name.
WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.

How can I save this net for plotting and measurements?

Solution

The colon (:) in the save statement specifies terminal current. So, the save statement used above is for terminal current and, hence, the warning messages are reported.

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save xpi1.x1\/x1:DRN

You need to modify the save statement as below:

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save xpi1.x1\/x1\:DRN

Now, run the simulation and the issue will be resolved.

DSPF r vs rcc

rcc

c

only c dspf give the lumped capacitance

EMIR via Voltus-Fi

general terminology

DC related

Imax in T*'s DRC document is the maximum allowed DC current, which depends on Length and Width only

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to Imax rules \[ I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau} \] Similarly, Iabsavg rules are identical to Imax rules, too \[ I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau} \]

rms

Irms is the root-mean-square of the current through a metal line, which depends w(in um), the drawn width of the metal line and \(\Delta T\), the temperature rise due to Joule heating. \[ I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2} \]

peak current

Ipeak in T*'s DRC document is the current at which a metal line undergoes excessive Joule heating and can begin to melt. Ipeak is corresponding to EM Current Analysis: max in Voltus-Fi Analysis Setup \[ I_{\text{peak}}=\max(|I(t)|) \] The limit for the peak current is \[ I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r } } \] where r is the duty ratio

The relationship between Ipeak and Ipeak_DC is merged in DRC document so that there is only Ipeak equation in document

\(I_{\text{peak,limit}}\) depends on \(t_D\), r, width and length

\[ r=\frac{t_D}{\tau} \]

where \(t_D\) is equivalent duration \[ t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}} \] or \[ r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}} \]

where the drawn width is 1um, r is 0.1

\[ 9.37*(1-0.004)/\sqrt0.1 = 29.512 \]

acpeak/pwc

It's same with max EM Current Analysis in Voltus-Fi

dynamicACPeak

This option affect how duty ratio r is computed in max and acpeak/pwc EM current Analysis

When the dynamicACPeak variable is set to true or multiPeak \[ r=\frac{T_d}{T_{\text{total}}} \]

​ where \(T_{\text{total}} = \text{EMIR time window}\)

​ \(T_d\) = the time duration in microsecond of the total "On Time" period based on IPWC

Pulse-Wise Constant EM current calculation (IPWC)

where Tau is \(T_d\) in above formula

!!! It seems that t*'s PDK don't support dynamicACPeak=true

IR drop filter layers

EM techfile (qrcTechFile) may take diffusion contact (n_odtap, p_odtap in DSPF file) into account during IR drop analysis. And these segment often dominate IR drop, but we as IC designer can NOT improve them. In general, the IR drop to M1 layer is enough and feasible.

Regular analysis statements in emir configuration

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net name=[I0.vdd I0.vss] analysis=[vmax vavg]
net name=[I0.*] analysis =[imax ivavg irms]

emirreport command

Creating reports for specific nets after simulation using emirreport

Create a new config file as shown below:

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** test.conf**
net name=[I1.VDD I1.VSS] analysis=[iavg]
net name=[I1.VBIAS] analysis=[imax]

Run emirreport on the command line using the emirdatabase (emir*.bin) and test.conf created above in

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% emirreport -64 -c test.conf -db <emirdatabase> -outdir newreport

database

simulation result

• input.emir0_bin: The first EMIR Analysis which is DC or Transient, which depends on Analyses order

• input_tran.emir0_bin: EMIR Analysis in Transient simulation

• input_dcOp.emir0_bin: EMIR Analysis in DC simulation

For example

Two results are generated input.emir0_bin and input_dcOp.emir0_bin and their reports respectly

Fix Electromigration

• Iavg

  The average value of the current, which is the effective DC current

• Irms

  Irms rule relates to the heat or Joule-heating of metal lines

• Ipeak

  The main goal of the Ipeak limits is to ensure that no thermal breakdown could occur on single overshoot events. If the signal may not have a high current density but if it has a very large peak current density, then, local melting will happen and cause failures

QA

1. Q. Why “length” column in EM results form doesn’t show extracted length, it shows “NA”.

   A. Voltus-Fi reports the “length” column only when length rules are present in the emDataFile.

2. Seeing different port currents with and without emir simulations for same dspf included in EMIR Direct method using dspf_include.

   Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the regular spectre flow. Islands patching is only performed in EMIR only

3. Setting temperature for EM analysis

   By Default, Voltus-FI and VPS pick up the current density limit for temperature at which simulation has been performed.

   By the way, Design Variables - temperature will override the temperature in Setup toolbar which is gray in ADE Explorer

   

4. AC Peak EM analysis - Voltus-Fi

   The available options within the EM current analysis section in the EMIR Analysis Setup form are:

   max / avg / avgabs / rms.

   In order to enable the AC Peak based information when loading the EM results, both max and avg should be selected when setting up the EMIR Analysis Setup.

   With this configuration, the AC Peak option becomes available and can be used.

5. How to print average, rms, and peak current of device tap in Spectre/Voltus FI EMIR analysis

   The following option enables you to save the average, rms, and peak tap currents in the emir0bin file and report it in the input.rpt_tapi file.

   1	solver report_tapi=true

   Add this option in emir.conf to enable the reporting of tap current after the Spectre EMIR simulation. The input.rpt_tapi file will be saved in the psf/raw directory.

   Note: This feature is supported in SPECTRE20.1 ISR14 and later versions.

6. emir.conf file

   emir.conf file is generated automaticaly after configure EM/IR Analysis in ADE, which is in netlist directory.

   

7. Setting default path for EM rules file in APS EMIR analysis

   • set the following environment variable in your terminal

     1	setenv EMDATAFILE < path to EM rules file>

   • or set in .cdsinit

     1	setShellEnvVar("EMDATAFILE=<path to EM rules file>")

8. Print node names and length associated with parasitic resistors in EM report file

   export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME

   • Printing the parasitic resistor length in the EM report

     1	emirutil reportLength=true

   • Printing nodes that are associated with the parasitic resistor

     1	emirutil reportNodeName=true

     Once these are enabled, you will have the Length, Node_1, and Node_2 columns printed in the EM report file, as shown below:

     

9. Is it possible to run RMS IR Drop analysis using Voltus-Fi?

   Typically, in a simulation, Power/Ground nets are always biased with a constant DC source. Hence, at present, Voltus-Fi only supports Average and Maximum (Peak) IR Drop analysis.

   For a net to have data for IR analysis(vmax/vavg), the net/node must be connected to a DC vsource or a vsource which is constant within the emir time window.

10. Can we change the time window of EM computation after the simulation completed ?

    It is not possible to modify the EM time window without re-running the full simulation.

    However you can specify several time window in the emir conf file for instance for 2 time window [0 to 10n] and [10n 20n]

    1	time window=[0 10n 10n 20n]

    In that case it will create 2 emir_bin files and then 2 different em report files according to the 2 different time windows.

11. How to print segment_W values being used to compute EM limits

    You can use the following option to print segment_W to the report:

    1	emirutil reportSegmentWidth=[true]

    This would print a Segment_w column in the report containing the segment width values used for computing the limit:

    Pass/Fail %	Resistor	layer	Current	Width	PathLength	I limit	X1	Y1	X2	Y2	J/JMAX	Res	ViaArea	No of needed vias	width/#via	J limit	Segment_w
    			(mA)	(um)	(um)		(um)	(um)	(um)	(um)			(nm^2)		(um/#)	(A/um)
    pass-100.0	Rj3292	Met1	9.02376e-12	0.1	42.72	1.10067	0.350	11.568	0.350	11.376	8.19843e-12	0.7382	NA	NA	0.0001	0.0110067	0.1

12. pathLength vs Length in EM report file

    • Length: parasitic resistor length, which is set by emirutil reportLength=true

    • pathlength: Blech length is also known as "Short length" or "Path length", and can be explained as : The longest and continuous centerline path from edge to edge among the connected wire shapes on the same metal layer.

      • For all resistors falling on this shape, same pathLength is reported.
      • After the longest path in shape has been determined the tool applies the same blech length to all the resistor falling on that shape.
      • This resistor length is NOT used in EM analysis because EM rules consider Blech length of the resistor.

      

      where W is the wire width and L is the Blech length.

      • By default the tool will sum all branches of a given metal layer. In other words the path length that will be used to look up the EM density limit is :

        Bl = $l(R1) + $l(R2) + $l(R3) + $l(R4) + $l(R5) + $l(R6) + $l(R7) + $l(R8)

        

13. How to enable EMIR analysis in PSS simualtion ?

    To enable EMIR in PSS, you have to enable DC and/or Tran simulation simultaneously. Two or more binary results file should be generated and select the file based file name or configure text file in psf directory.

    (given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)

StarRC

NETLIST_CONNECT_OPENS

Connector resistors - non-physical resistors (well or substrate layer, that is not extracted for resistance)

Maxim Ershov, Diakopto. Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why? [https://diakopto.marsdm.com/wp-content/uploads/Bizarre_results_for_P2P_resistance_and_current_density.pdf]

TRANSLATE_RETAIN_BULK_LAYERS

reference

AC Peak Analysis Using IPWC Rapid Adoption Kit (RAK) Product Version: IC6.1.8 ISR10, SPECTRE19.1 ISR5 April 2020

Posser, Gracieli & Sapatnekar, Sachin & Reis, Ricardo. (2017). Electromigration Inside Logic Cells. 10.1007/978-3-319-48899-8.

A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts of electromigration awareness," 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp. 527-532, doi: 10.1109/ASPDAC.2013.6509650.

Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling of electromigration in SRAMs.” (2014).

N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical approach to static signal electromigration analysis," Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 572-577, doi: 10.1109/DAC.1998.724536.

Blaauw, David & Oh, Chanhee & Zolotov, Vladimir & Dasgupta, Aurobindo. (2003). Static electromigration analysis for on-chip signal interconnects. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 22. 39 - 48. 10.1109/TCAD.2002.805728.

Cycle Slips and Hangup

Qasim Chaudhari. What are Cycle Slips and Hangup in Phase Locked Loops? [https://wirelesspi.com/what-are-cycle-slips-and-hangup-in-phase-locked-loops/]

TODO 📅

excess phase around n-th harmonic

\(\Delta t\) is same for any n-th harmonic

Spurious Tones

Spur-to-Carrier Ratio (SCR)

Nicola Da Dalt, ISSCC 2012: Jitter Basic and Advanced Concepts, Statistics and Applications [https://www.nishanchettri.com/isscc-slides/2012%20ISSCC/TUTORIALS/ISSCC2012Visuals-T5.pdf]

P.E. Allen - 2003 ECE 6440 - Frequency Synthesizers: Lecture 150 – Phase Noise-I [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L150-PhaseNoise-I(2UP).pdf]

Reference Spur

spurs are carrier or clock frequency spectral imperfections measured in the frequency domain just like phase noise. However, unlike phase noise they are discrete frequency components.

• Spurs are deterministic

• Spur power is independent of bandwidth

• Spurs contribute bounded peak jitter in the time domain

Sources of Spurs:

• External (coupling from other noisy block) Supply, substrate, bond wires, etc.
• Internal (int-N/fractional-N operation)
  • Frac spur: Fractional divider (multi-modulus and frequency accumulation)
  • Ref. spur: PFD/charge pump/analog loop filter non-idealities, clock coupling

Fractional Spur

TODO 📅

frequency divider & phase margin

type-I PLLs

frequency divider weakens the feedback and increases the phase margin

type-II PLLs

frequency divider weakens the feedback and decrease the phase margin

multi-modulus divider

TODO 📅

Integer-N PLL

integer-N PLL frequency synthesizers

• the frequency resolution, is equal to the reference frequency, meaning that only integer multiples of the reference frequency can be synthesized

• Stability requirements limit the loop bandwidth to about one tenth of the reference frequency; therefore

  • decreasing the reference frequency increases the settling time as the loop bandwidth also has to be decreased
  • a reduced loop bandwidth allows less suppression of the VCO’s inherent phase noise

• Another drawback of the integer-N PLL is the trade-off between phase noise and settling time when the divider ratio becomes large (The contributions to the output phase noise of almost all PLL building blocks, except the VCO, are multiplied by the division ratio)

  [https://people.engr.tamu.edu/spalermo/ecen620/lecture03_ee620_pll_system.pdf]

  

• if a small reference frequency is chosen, the reference spur in the output phase noise is located at a smaller offset frequency

Fractional-N

1. Dither Feedback Divider Ratio by a delta-sigma modulator

2. Frequency Accumulation

Switched Capacitor Banks

Q: why \(R_b\) ?

A: TODO 📅

Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in RF/millimeter-wave oscillators for 5G communications." PhD diss., 2019.

S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010, pp. 1903-1906

SSC intuition

Due to \(f= K_{vco}V_{ctrl}\), its derivate to \(t\) is

\[ \frac{df}{dt} = K_{vco}\frac{dV_{ctrl}}{dt} \]

For chargepump PLL, \(dV_{ctrl} = \frac{\phi_e I_{cp}}{2\pi C}dt\), that is \[ \frac{df}{dt} = K_{vco} \frac{\phi_e I_{cp}}{2\pi C} \]

DIV 1.5

TODO 📅

Xu, Haojie & Luo, Bao & Jin, Gaofeng & Feng, Fei & Guo, Huanan & Gao, Xiang & Deo, Anupama. (2022). A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs. 69. 4238 - 4242. [https://www.researchgate.net/publication/382240520_A_Flexible_073-155_GHz_Single_LC_VCO_Clock_Generator_in_12_nm_CMOS]

False locking

TODO 📅

• divider failure
• even-stage ring oscillator ( multipath ring oscillators)
• DLL: harmonic locking, stuck locking

clock edge impact

ck1 is div2 of ck0

• edge of ck0 is affected differently by ck1

• edge of ck1 is affected equally by ck0

Feedback Dividers

• Large values of N lowers the loop BW which is bad for jitter

Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF, Analog and Mixed Signal Circuits and Systems. Aalborg: River Publishers, 2017.

Tri-gate Clock MUX vs Pass-gate Clock MUX

TODO 📅

Why Type 2 PLL ?

Type: # of integrators within the loop

Order: # of poles in the closed-loop transfer function

Type \(\leq\) Order

1. That is, to have a wide bandwidth, a high loop gain is required
2. More importantly, the type 1 PLL has the problem of a static phase error for the change of an input frequency

Type 1 PLL with input phase step \(\Delta \phi \cdot u(t)\) \[\begin{align} \Delta \phi\cdot u(t) - K\int_0^{t}\phi _e (\tau)d\tau &= \phi _e (t) \\ \phi _e (0) &= \Delta \phi \end{align}\]

we obtain \(\phi _e (t) = \Delta \phi \cdot e^{-Kt}\cdot u(t)\)

and \(\phi _e(\infty) = 0\)

Daniel Boschen. GRCon24 - Quick Start on Control Loops with Python Workshop [https://events.gnuradio.org/event/24/contributions/599/attachments/187/480/Boschen%20Control%20Presentation.pdf]

Divider phase noise & jitter

• Multiplying the frequency of a signal by a factor of N using an ideal frequency multiplier increases the phase noise of the multiplied signal by \(20\log(N)\) dB.
• Similarly dividing a signal frequency by N reduces the phase noise of the output signal by \(20\log(N)\) dB

The sideband offset from the carrier in the frequency multiplied/divided signal is the same as for the original signal.

The 20log(N) Rule

If the carrier frequency of a clock is divided down by a factor of \(N\) then we expect the phase noise to decrease by \(20\log(N)\).The primary assumption here is a noiseless conventional digital divider.

The \(20\log(N)\) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same.

What About Phase Jitter?

We integrate SSB phase noise L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for “brick wall” integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.

Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise, L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant.

Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.

[Timing 101: The Case of the Jitterier Divided-Down Clock, Silicon Labs]

[How division impacts spurs, phase noise, and phase]

[Phase Noise Theory: Ideal Frequency Multipliers and Dividers]

PLL bandwidth test

A step response test is an easy way to determine the bandwidth.

Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected response at the output of the loop filter as shown in this block diagram

a first order loop \[ BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)} \] Where \(BW\) is the 3 dB bandwidth in Hz and \(𝑡\)​ is the 10%/90% rise or fall time.

For second order loops with a typical damping factor of 0.7 this relationship is closer to: \[ BW = \frac{0.33}{t}\space\space\space\space \text{(second order system, damping factor = 0.7)} \]

[How can I experimentally find the bandwidth of my PLL?, https://dsp.stackexchange.com/a/73654/59253]

reference

Dennis Fischette, Frequently Asked PLL Questions [https://www.delroy.com/PLL_dir/FAQ/FAQ.htm]

Ian Galton, ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]

Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T6Visuals.pdf]

Additive White Gaussian Noise (AWGN)

Qasim Chaudhari. Additive White Gaussian Noise (AWGN) [https://wirelesspi.com/additive-white-gaussian-noise-awgn/]

TODO 📅

Pulse Amplitude Modulation (PAM)

Qasim Chaudhari. Pulse Amplitude Modulation (PAM) [https://wirelesspi.com/pulse-amplitude-modulation-pam/]

TODO 📅

Nyquist's Stability Criterion

TODO 📅

[Michael H. Perrott, High Speed Communication Circuits and Systems, Lecture 15 Integer-N Frequency Synthesizers]

fft vs. ifft

Jason Sachs, Ten Little Algorithms, Part 2: The Single-Pole Low-Pass Filter [https://www.embeddedrelated.com/showarticle/779.php]

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import matplotlib.pyplot as plt
import numpy as np
np.random.seed(123456789)   # repeatable results

f0 = 4
t = np.arange(0,1.0,1.0/65536)
mysignal = (np.mod(f0*t,1) < 0.5)*2.0-1
mynoise = 1.0*np.random.randn(*mysignal.shape)

plt.figure(figsize=(8,6))
plt.plot(t, mysignal+mynoise, 'gray',
         t, mysignal,         'black');


def spectrum_fftovN(x):
    return np.abs(np.fft.fft(x))/len(x)

def spectrum_ifft(x):
    return np.abs(np.fft.ifft(x))


mysignal_spectrum_fftovN = spectrum_fftovN(mysignal)
mynoise_spectrum_fftovN  = spectrum_fftovN(mynoise)
mysignal_spectrum_ifft= spectrum_ifft(mysignal)
mynoise_spectrum_ifft = spectrum_ifft(mynoise)

N1 = 500
f = np.arange(N1)
plt.figure(figsize=(16,12))
plt.subplot(2,1,1)
plt.plot(f,mysignal_spectrum_fftovN[:N1], 'b-',
         f,mysignal_spectrum_ifft[:N1], 'r--', linewidth=3)
plt.legend(('fftovN','ifft'), fontsize=16, loc='upper right')
plt.title('signal', fontsize=24); plt.xlim(0,N1); plt.xlabel('frequency'); plt.ylabel('amplitude')

plt.subplot(2,1,2)
plt.plot(f,mynoise_spectrum_fftovN[:N1], 'b-',
         f,mynoise_spectrum_ifft[:N1], 'r--', linewidth=3)
plt.legend(('fftovN','ifft'), fontsize=16, loc='upper right')
plt.title('noise', fontsize=24); plt.xlim(0,N1); plt.xlabel('frequency'); plt.ylabel('amplitude')

plt.show()

Pulse Code Modulation (PCM)

John M Pauly. Lecture 13: Pulse Code Modulation [https://web.stanford.edu/class/ee179/lectures/notes13.pdf]

Pulse Code Modulation (PCM) is a method for digitally representing analog signals by sampling their amplitude at regular intervals and then encoding these samples into binary numbers

Energy/bit (pJ/b)

1mW/Gbps = 1pJ/bit

Joules are a unit of work or energy. Watts are a unit of power which is the rate at which energy is generated or consumed.

modulation depth

The modulation index (or modulation depth) of a modulation scheme describes by how much the modulated variable of the carrier signal varies around its unmodulated level

Image frequency

Antonio Liscidini, ESSCIRC 2019 Tutorials: Ultra Low Power Receivers [https://youtu.be/OJRB8g4vUZw]

Inspection of Phase Noise

a -10 dB/decade reference line can be used to pinpoint the location in a phase noise curve that dominates its integral

How to Identify the Source of Phase Jitter through Phase Noise Plots [https://www.sitime.com/company/newsroom/blog/how-identify-source-phase-jitter-through-phase-noise-plots]

AN10072 Determine the Dominant Source of Phase Noise, by Inspection [https://www.sitime.com/support/resource-library/application-notes/an10072-determine-dominant-source-phase-noise-inspection]

4-minute Clinic: Determine the Dominant Source of Jitter by Inspection of Phase Noise Plot [https://youtu.be/2elHk3v45Pk]

white noise

white noise doesn't mean it has a Gaussian/normal distribution

The only criteria for a (discrete) signal to be "white" is for each sample to be independently taken from the same probability distribution

By understanding input signal's statistical nature, we can gather more insights about certain requirements for our circuits than just from frequency domain

Kevin Zheng. The Frequency Domain Trap – Beware of Your AC Analysis [https://circuit-artists.com/the-frequency-domain-trap-beware-of-your-ac-analysis/]

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fs = 1;
N = 2^20;
Nhist = 100;
segmentLength = 512;

x_norm = randn(1, N,1); % Generate random data (e.g., Gaussian white noise)
[pxx_norm, f] = pwelch(x_norm, segmentLength, [], [], fs);

x_uniform = 2*rand(N,1) - 1; % uniform random -1 ~ 1;
[pxx_uniform, ~] = pwelch(x_uniform, segmentLength, [], [], fs);

x_sin = sin(2*pi*(rand(N,1) - 0.5)); % sinusoidal-like
[pxx_sin, ~] = pwelch(x_sin, segmentLength, [], [], fs);

x_bin = 2*randi(2,N,1) -3; % binomial distribution, -1, 1
[pxx_bin, ~] = pwelch(x_bin, segmentLength, [], [], fs);

subplot(2, 4, 1)
histogram(x_norm, Nhist);
title('normal distribution')

subplot(2, 4, 5)
plot(f, 10*log10(pxx_norm));
xlabel('Frequency (Hz)');
ylabel('dB');
title('PSD of normal distribution')

%% 
subplot(2, 4, 2)
histogram(x_uniform, Nhist);
title('uniform distribution')

subplot(2, 4, 6)
plot(f, 10*log10(pxx_uniform));
xlabel('Frequency (Hz)');
ylabel('dB');
title('PSD of uniform distribution')

%% 
subplot(2, 4, 3)
histogram(x_sin, Nhist);
title('sinusoidal-like distribution')

subplot(2, 4, 7)
plot(f, 10*log10(pxx_sin));
xlabel('Frequency (Hz)');
ylabel('dB');
title('PSD of sinusoidal-like distribution')

%%
subplot(2, 4, 4)
histogram(x_bin, Nhist);
title('binomial distribution')

subplot(2, 4, 8)
plot(f, 10*log10(pxx_bin));
xlabel('Frequency (Hz)');
ylabel('dB');
title('PSD of binomial distribution')

The Problem of "Sinusoids Running Around Loops"

The representative of Fourier transform \(\frac{1}{j\omega+j\omega_0}\) back in the time domain \(e^{-j\omega_0 t}\) is infinite extent in time

Running around a loop, chasing one's tail — these are thought pictures that only work in a discretized, time-sequenced conceptual framework that has a beginning and an end

Fix in your mind that oscillations are a type of resonance

Dawson, Joel L. A Guide to Feedback Theory. Cambridge: Cambridge University Press, 2021.

RMS for non-sinusoidal periodic function

Nyquist rate & Nyquist frequency

• Nyquist rate

  The Nyquist rate is the minimum sample rate required to accurately measure a signal's highest frequency. It's equal to twice the highest frequency of the signal

• Nyquist frequency

  The Nyquist frequency is the highest frequency that can be represented without aliasing in a discrete signal. It's equal to half the sampling frequency

Oversampling Ratio (OSR) is defined as the ratio of the Nyquist frequency \(f_s/2\) to the signal bandwidth \(B\) given by \(\text{OSR}=f_s/2B\)

Summation & Integration

both are NOT stable

sinc function

where \(W\) is sampling frequency in Hz

sinc function is square integrable but not absolutely integrable

Zero-order hold (ZOH)

\[ h_{ZOH}(t) = \text{rect}(\frac{t}{T} - \frac{1}{2}) = \left\{ \begin{array}{cl} 1 & : \ 0 \leq t \lt T \\ 0 & : \ \text{otherwise} \end{array} \right. \] The effective frequency response is the continuous Fourier transform of the impulse response \[ H_{ZOH}(f) = \mathcal{F}\{h_{ZOH}(t)\} = T\frac{1-e^{j2\pi fT}}{j2\pi fT}=Te^{-j\pi fT}\text{sinc}(fT) \] where \(\text{sinc}(x)\) is the normalized sinc function \(\frac{\sin(\pi x)}{\pi x}\)

The Laplace transform transfer function of the ZOH is found by substituting \(s=j2\pi f\) \[ H_{ZOH}(s) = \mathcal{L}\{h_{ZOH}(t)\}=\frac{1-e^{-sT}}{s} \]

frequency convention

• radian frequency \(\omega_0\) in rad/s
• cyclic frequency \(f_0\) in Hz

Energy signals vs Power signal

Topic 5 Energy & Power Signals, Correlation & Spectral Density [https://www.robots.ox.ac.uk/~dwm/Courses/2TF_2021/N5.pdf]

modulation & demodulation

Hossein Hashemi, RF Circuits, [https://youtu.be/0f3yZMvD2Jg?si=2c1Q4y6WJq8Jj8oN]

phase delay & group delay

• Phase delay directly measures the device or system time delay of individual sinusoidal frequency components in the steady-state conditions.
• In the ideal case the envelope delay is equal to the phase delay
• envelope delay is a more sensitive measure of aberrations than phase delay

phase delay

If the phase delay peaks (exceeds the low-frequency value) you can expect to see high-frequency components late in the step response. This causes ringing.

group delay

steady-state at this frequency is a polarity flip; a 180 degrees phase shift; which is a transfer function of H(s)=-1. \[ H(s) = e^{j\pi} \] That is \(\phi(\omega) = \pi\) \[ \tau_p = \frac{\pi}{\omega} \] and \[ \tau_g = \frac{\partial \pi}{\partial \omega}=0 \]

Hollister, Allen L. Wideband Amplifier Design. Raleigh, NC: SciTech Pub., 2007.

Pupalaikis, Peter. (2006). Group Delay and its Impact on Serial Data Transmission and Testing. [https://cdn.teledynelecroy.com/files/whitepapers/group_delay-designcon2006.pdf]

[Pupalaikis et al., “Eye Patterns in Scopes”, DesignCon, Santa Clara CA, 2005https://cdn.teledynelecroy.com/files/whitepapers/eye_patterns_in_scopes-designcon_2005.pdf]

Starič, P. & Margan, E.. (2006). Wideband Amplifiers. 10.1007/978-0-387-28341-8.

Alan V. Oppenheim, Alan S. Willsky, and S. Hamid Nawab. 1996. Signals & systems (2nd ed.). Prentice-Hall, Inc., USA.

Phase delay vs group delay: Common misconceptions. [https://audiosciencereview.com/forum/index.php?threads/phase-delay-vs-group-delay-common-misconceptions.39591/]

Group Delay vs . Phase Delay

The effectiveness of the group delay analysis on evaluating a wideband circuit is questionable

differentiating operation:

• group delay provides a good insight on the delay variation at a vicinity of a certain frequency
• group delay makes a constant term be disappeared and distorts the weight of each polynomial term

CC Chen. Why Group Delay Optimization? [https://youtu.be/Lv7yO_LkKng?si=yg-vyUPyredA_dER]

W. Bae, B. Nikolić and D. -K. Jeong, "Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3543-3547, Dec. 2017, [https://sci-hub.se/10.1109/TVLSI.2017.2747157]

Feedback Rearrange

The closed loop transfer function of \(Y/X\) and \(Y_1/X_1\) are almost same, except sign

\[\begin{align} \frac{Y}{X} &= +\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \\ \frac{Y_1}{X_1} &= -\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \end{align}\]

define \(-Y_1=Y_n\), then \[ \frac{Y_n}{X_1} = \frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \]

Saurabh Saxena, IIT Madras. CICC2022 Clocking for Serial Links - Frequency and Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery

Convolution of probability distributions

The probability distribution of the sum of two or more independent random variables is the convolution of their individual distributions.

Thermal noise

Thermal noise in an ideal resistor is approximately white, meaning that its power spectral density is nearly constant throughout the frequency spectrum.

When limited to a finite bandwidth and viewed in the time domain, thermal noise has a nearly Gaussian amplitude distribution

Barkhausen criteria

Barkhausen criteria are necessary but not sufficient conditions for sustainable oscillations

it simply "latches up" rather than oscillates

NRZ Bandwidth

Maxim Integrated,NRZ Bandwidth - HF Cutoff vs. SNR [https://pdfserv.maximintegrated.com/en/an/AN870.pdf]

\(0.35/T_r\)

\(0.5/T_r\)

TODO 📅

System Type

Control of Steady-State Error to Polynomial Inputs: System Type

control systems are assigned a type number according to the maximum degree of the input polynominal for which the steady-state error is a finite constant. i.e.

• Type 0: Finite error to a step (position error)
• Type 1: Finite error to a ramp (velocity error)
• Type 2: Finite error to a parabola (acceleration error)

The open-loop transfer function can be expressed as \[ T(s) = \frac{K_n(s)}{s^n} \]

where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),

The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform is \[ R(s) = \frac{1}{s^{k+1}} \]

Then the equation for the error is simply \[ E(s) = \frac{1}{1+T(s)}R(s) \]

Application of the Final Value Theorem to the error formula gives the result

\[\begin{align} \lim _{t\to \infty} e(t) &= e_{ss} = \lim _{s\to 0} sE(s) \\ &= \lim _{s\to 0} s\frac{1}{1+\frac{K_n(s)}{s^n}}\frac{1}{s^{k+1}} \\ &= \lim _{s\to 0} \frac{s^n}{s^n + K_n}\frac{1}{s^k} \end{align}\]

• if \(n > k\), \(e=0\)
• if \(n < k\), \(e\to \infty\)
• if \(n=k\)
  • \(e_{ss} = \frac{1}{1+K_n}\) if \(n=k=0\)
  • \(e_{ss} = \frac{1}{K_n}\) if \(n=k \neq 0\)​

where we define \(K_n(0) = K_n\)

sinusoidal steady-state and frequency response

Due to KCL and \(u(t)=e^{j\omega t}\) and \(y(t)=H(j\omega)e^{j\omega t}\), we have ODE:

\[\begin{align} \frac{u(t) - y(t)}{R} = C \frac{dy(t)}{dt} \\ e^{j\omega t} - H(j\omega) e^{j\omega t} = H(j\omega)\cdot j\omega e^{j\omega t} \\ \end{align}\]

\(H(j\omega)\) is obtained as below \[ H(j\omega) = \frac{1}{1+j\omega} \]

Different Variants of the PSD Definition

In the practice of engineering, it has become customary to use slightly different variants of the PSD definition, depending on the particular application or research field.

• Two-Sided PSD, \(S_x(f)\)

  this is a synonym of the PSD defined as the Fourier Transform of the autocorrelation.

• One-Sided PSD, \(S'_x(f)\)

  this is a variant derived from the two-sided PSD by considering only the positive frequency semi-axis.

  To conserve the total power, the value of the one-sided PSD is twice that of the two-sided PSD \[ S'_x(f) = \left\{ \begin{array}{cl} 0 & : \ f \geq 0 \\ S_x(f) & : \ f = 0 \\ 2S_x(f) & : \ f \gt 0 \end{array} \right. \]

Note that the one-sided PSD definition makes sense only if the two-sided is an even function of \(f\)

If \(S'_x(f)\) is even symmetrical around a positive frequency \(f_0\), then two additional definitions can be adopted:

• Single-Sideband PSD, \(S_{SSB,x}(f)\)

  This is obtained from \(S'_x(f)\) by moving the origin of the frequency axis to \(f_0\) \[ S_{SSB,x}(f) =S'_x(f+f_0) \] This concept is particularly useful for describing phase or amplitude modulation schemes in wireless communications, where \(f_0\) is the carrier frequency.

  Note that there is no difference in the values of the one-sided versus the SSB PSD; it is just a pure translation on the frequency axis.

• Double-Sideband PSD, \(S_{DSB,x}(f)\)

  this is a variant of the SSB PSD obtained by considering only the positive frequency semi-axis.

  As in the case of the one-sided PSD, to conserve total power, the value of the DSB PSD is twice that of the SSB \[ S_{DSB,x}(f) = \left\{ \begin{array}{cl} 0 & : \ f \geq 0 \\ S_{SSB,x}(f) & : \ f = 0 \\ 2S_{SSB,x}(f) & : \ f \gt 0 \end{array} \right. \]

Note that the DSB definition makes sense only if the SSB PSD is even symmetrical around zero

Poles and Zeros of transfer function

poles

\[ H(s) = \frac{1}{1+s/\omega_0} \]

magnitude and phase at \(\omega_0\) and \(-\omega_0\) \[\begin{align} H(j\omega_0) &= \frac{1}{1+j} = \frac{1}{\sqrt{2}}e^{-j\pi/4} \\ H(-j\omega_0) &= \frac{1}{1-j} = \frac{1}{\sqrt{2}}e^{j\pi/4} \end{align}\]

system response \(y(t)\) of input \(\cos(\omega_0 t)\), note \(\cos(\omega_0t) = \frac{1}{2}(e^{j\omega_0 t} + e^{-j\omega_0 t})\) \[\begin{align} y(t) &= H(j\omega_0)\cdot \frac{1}{2}e^{j\omega_0 t} + H(-j\omega_0)\cdot \frac{1}{2}e^{-j\omega_0 t} \\ &= \frac{1}{\sqrt{2}}\cos(\omega_0t-\pi/4) \end{align}\]

\(\cos(\omega_0 t)\), with frequency same with pole DON'T have infinite response

That is, pole indicate decrease trending

zeros

similar with poles, \(\cos(\omega_0 t)\), with frequency same with zero DON'T have zero response

\[ H(s) = 1+s/\omega_0 \]

magnitude and phase at \(\omega_0\) and \(-\omega_0\) \[\begin{align} H(j\omega_0) &= 1+j = \sqrt{2}e^{j\pi/4} \\ H(-j\omega_0) &= 1-j = \sqrt{2}e^{-j\pi/4} \end{align}\]

system response \(y(t)\) of input \(\cos(\omega_0 t)\), note \(\cos(\omega_0t) = \frac{1}{2}(e^{j\omega_0 t} + e^{-j\omega_0 t})\) \[\begin{align} y(t) &= H(j\omega_0)\cdot \frac{1}{2}e^{j\omega_0 t} + H(-j\omega_0)\cdot \frac{1}{2}e^{-j\omega_0 t} \\ &= \sqrt{2}\cos(\omega_0t+\pi/4) \end{align}\]

baud rate

symbol rate, modulation rate or baud rate is the number of symbol changes per unit of time.

• Bit rate refers to the number of bits transmitted between two devices per unit of time
• The baud or symbol rate refers to the number of symbols that can be sent in the same amount of time

reference

Stephen P. Boyd. EE102 Lecture 10 Sinusoidal steady-state and frequency response [https://web.stanford.edu/~boyd/ee102/freq.pdf]

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 2018. Feedback Control of Dynamic Systems (8th Edition) (8th. ed.). Pearson.

Inter-Symbol Interference (or Leaky Bits) [http://blog.teledynelecroy.com/2018/06/inter-symbol-interference-or-leaky-bits.html]

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization. URL:[https://www.controlpaths.com/articles/an001_designing_iir_biquad_filter_bilinear/]

Frequency warping using the bilinear transform. URL:[https://www.controlpaths.com/2022/05/09/frequency-warping-using-the-bilinear-transform/]

Digital control loops. Theoretical approach. URL:[https://www.controlpaths.com/2022/02/28/digital-control-loops-theoretical-approach/]

Simulation of DSP algorithms in Verilog. URL:[https://www.controlpaths.com/2023/05/20/simulation-of-dsp-algorithms-in-verilog/]

Implementing a digital biquad filter in Verilog. URL:[https://www.controlpaths.com/2021/04/19/implementing-a-digital-biquad-filter-in-verilog/]

Implementing a FIR filter using folding. URL:[https://www.controlpaths.com/2021/05/17/implementing-a-fir-filter-using-folding/]

Oppenheim, Alan V. and Cram. “Discrete-time signal processing : Alan V. Oppenheim, 3rd edition.” (2011).

Extras: PID Compensator with Bilinear Approximation URL:[https://ctms.engin.umich.edu/CTMS/index.php?aux=Extras_PIDbilin]

noise power at filter output

Chembian Thambidurai, "Comparison Of Noise Power At Lowpass Filter Output" [link]

—, "On Noise Power At The Bandpass Filter Output" [link]

—, "Integrated Power of Thermal and Flicker Noise" [link]

TODO 📅

Sampling Noise

Chembian Thambidurai, "Noise, Sampling and Zeta Functions" [link]

A random signal \(v_n(t)\) is sampled using an ideal impulse sampler

TODO 📅

1/f Noise - Fourier Transform

Steve Smith. An Interesting Fourier Transform - 1/f Noise [https://www.dsprelated.com/showarticle/40.php]

TODO 📅

Pulsed Noise Signals

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

Above, the output of the multiplier be \(y(t)\) is passed through a ideal brick wall low pass filter with a bandwidth of \(f_0/2\)

When a random signal is multiplied by a pulse function, the resulting signal becomes a cyclo-stationary random process.

As rule of thumb, the spectrum of such a pulsed noise signal

• thermal noise is multiplied by \(D\)

• flicker noise is multiplied by \(D^2\),

where \(D\) is the duty cycle of the pulse signal

banlimited input

wideband white noise input

flicker noise input

with \(S_x(f)=\frac{K_f}{f}\)

Assuming \(\Delta f \ll f_0\)

ADC SNR & clock jitter

cyclostationary random process

\[\begin{align} \text{SNR}_\text{ADC}[\text{dB}] &= -20\cdot \log \sqrt{\left(10^{-\frac{\text{SNR}_\text{Quantization Noise}}{20}}\right)^2 + \left(10^{-\frac{\text{SNR}_\text{Jitter}}{20}}\right)^2} \\ &= -10\cdot \log \left(\left(10^{-\frac{\text{SNR}_\text{Quantization Noise}}{20}}\right)^2 + \left(10^{-\frac{\text{SNR}_\text{Jitter}}{20}}\right)^2\right) \\ &= -10\cdot \log \left(\left(10^{-\frac{10\log(\frac{3\times2^{2N}}{2})}{20}}\right)^2 + \left(10^{-\frac{-20\log{(2\pi f_\text{in}\sigma_\text{jitter})}}{20}}\right)^2\right) \\ &= -10\cdot \log \left( \frac{2}{3\times 2^{2N}} + (2\pi f_\text{in}\sigma_\text{jitter})^2 \right) \end{align}\]

Ayça Akkaya, "High-Speed ADC Design and Optimization for Wireline Links" [https://infoscience.epfl.ch/server/api/core/bitstreams/96216029-c2ff-48e5-a675-609c1e26289c/content]

CC Chen, Why Absolute Jitter Matters for ADCs & DACs? [https://youtu.be/jBgDDFFDq30?si=XFyTEfApN86Ef-RG]

Thomas Neu, TIPL 4704. Jitter vs SNR for ADCs [https://www.ti.com/content/dam/videos/external-videos/en-us/2/3816841626001/5529003238001.mp4/subassets/TIPL-4704-Jitter-vs-SNR.pdf]

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import numpy as np
import matplotlib.pyplot as plt

N = 12  # ADC bit
fin = 100e6 # the frequency of the sinusoidal input signal
jrms = np.linspace(0, 10, 1000)*1e-12 #ps

# ADC (SNR) with Quantization Noise & Jitter degradation
SNR_ADC = -10 * np.log10(10**(-np.log10(3*2**(2*N)/2)) + (2*np.pi*fin*jrms)**2)
ENOB = (SNR_ADC - 1.76) / 6.02

plt.plot(jrms*1e12, ENOB, label='100 MHZ input')
plt.plot([0, 10], [12, 12], '--', label='12-bit limit')
plt.plot([0, 10], [6, 6], '--', label='6-bit limit')

plt.xscale('linear')
plt.xlim([0, 10])
plt.ylim([5, 15])
plt.xlabel('RMS Jitter (ps)')
plt.ylabel('Effective Number of Bits (ENOB')
plt.grid(which='both')
plt.title('ENOB vs. RMS Clock Jitter (100 MHz)')
plt.legend()
plt.show()

Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data Converters. July, 2006 [pdf]

Chembian Thambidurai, "SNR of an ADC in the presence of clock jitter" [https://www.linkedin.com/posts/chembiyan-t-0b34b910_adcsnrjitter-activity-7171178121021304833-f2Wd/]

Unlike the quantization noise and the thermal noise, the impact of the clock jitter on the ADC performance depends on the input signal properties like its PSD

The error between the ideal sampled signal and the sampling with clock jitter can be treated as noise and it results in the degradation of the SNR of the ADC

For sinusoid input:

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import numpy as np
import matplotlib.pyplot as plt

ENOB = 8
fin = np.logspace(8, 11, 60)

# quantization noise: SNR = 6.02*ENOB + 1.76 dB
Ps_PnQ = 10**((6.02*ENOB + 1.76)/10)
PnQ = 1/Ps_PnQ

# jitter noise: SNR = 6 - 20log10(2*pi*fin*Jrms) dB @ref. Chembiyan T
Jrms_list = [25e-15, 50e-15, 100e-15, 250e-15, 500e-15, 1000e-15]
for Jrms in Jrms_list:
    # Ps_PnJ_lcl = 10**((6-20*np.log10(2*np.pi*fin*Jrms))/10)     # ref. Chembiyan T
    Ps_PnJ_lcl = 10**((0 - 20 * np.log10(2 * np.pi * fin * Jrms)) / 10)  # ref. Nicola Da Dalt
    PnJ_lcl = 1/Ps_PnJ_lcl
    SNR_lcl = 10*np.log10(1/(PnQ+PnJ_lcl))
    plt.plot(fin, SNR_lcl, label=r'$\sigma_{jitter}$'+'='+str(int(Jrms*1e15))+'fs')

plt.xscale('log')
plt.ylim([0, 55])
plt.xlabel(r'$f_{in}$ [Hz]')
plt.ylabel(r'SNR [dB]')
plt.grid(which='both')
# plt.title(r'ref. Chembiyan T')
plt.title(r'ref. Nicola Da Dalt')
plt.legend()
plt.show()

K. Tyagi and B. Razavi, "Performance Bounds of ADC-Based Receivers Due to Clock Jitter," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 5, pp. 1749-1753, May 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/KT_TCAS_2023.pdf]

N. Da Dalt, M. Harteneck, C. Sandner and A. Wiesbauer, "On the jitter requirements of the sampling clock for analog-to-digital converters," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002 [https://sci-hub.se/10.1109/TCSI.2002.802353]

M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of high-speed sampling systems," in IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, Feb. 1990 [https://sci-hub.se/10.1109/4.50307]

Ayça Akkaya, "High-Speed ADC Design and Optimization for Wireline Links" [https://infoscience.epfl.ch/server/api/core/bitstreams/96216029-c2ff-48e5-a675-609c1e26289c/content]

待学芯. ADC量化结果反推采样时钟抖动（Jitter） [https://mp.weixin.qq.com/s/55xfVQMe_N8zUGpI8ZvmsQ]

—. 关于时钟抖动(Jitter)与ADC的一些讨论 [https://mp.weixin.qq.com/s/GW1keHhfq7zrd036lyG0CQ]

DAC SNR & clock jitter

ampling Jitter Effects for ADC/DAC

• In both DAC or ADC cases, doubling the timing jitter doubles the noise level
• Also, doubling the frequency or amplitude doubles the jitter induced noise - SNR is not improved

Boris Murmann ISSCC 2022 SC1: Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications [pdf]

S. Kim, K. -Y. Lee and M. Lee, "Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2832-2841, Sept. 2018 [https://sci-hub.se/10.1109/TCSI.2018.2821198]

Martin Clara. High-Performance D/A-Converters - Application to Digital Transceivers, 2013 [pdf]

Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data Converters. July, 2006 [pdf]

Sampled Thermal Noise

The aliasing of the noise, or noise folding, plays an important role in switched-capacitor as it does in all switched-capacitor filters

Assume for the moment that the switch is always closed (that there is no hold phase), the single-sided noise density would be

\(v_s[n]\) is the sampled version of \(v_{RC}(t)\), i.e. \(v_s[n]= v_{RC}(nT_C)\) \[ S_s(e^{j\omega}) = \frac{1}{T_C} \sum_{k=-\infty}^{\infty}S_{RC}(j(\frac{\omega}{T_C}-\frac{2\pi k}{T_C})) \cdot d\omega \] where \(\omega \in [-\pi, \pi]\), furthermore \(\frac{d\omega}{T_C}= d\Omega\) \[ S_s(j\Omega) = \sum_{k=-\infty}^{\infty}S_{RC}(j(\Omega-k\Omega_s)) \cdot d\Omega \]

The noise in \(S_{RC}\) is a stationary process and so is uncorrelated over \(f\) allowing the \(N\) rectangles to be combined by simply summing their noise powers

where \(m\) is the duty cycle

Kundert, Ken. (2006). Simulating Switched-Capacitor Filters with SpectreRF [https://designers-guide.org/analysis/sc-filters.pdf]

Pavan, Schreier and Temes, "Understanding Delta-Sigma Data Converters, Second Edition" ISBN 978-1-119-25827-8

Tania Khanna, ESE568 Fall 2019, Mixed Signal Circuit Design and Modeling URL: https://www.seas.upenn.edu/~ese568/fall2019/

Matt Pharr, Wenzel Jakob, and Greg Humphreys. 2016. Physically Based Rendering: From Theory to Implementation (3rd. ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.

R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. Wiley-Interscience, 1986

Trevor Caldwell, Lecture 9 Noise in Switched-Capacitor Circuits [http://individual.utoronto.ca/trevorcaldwell/course/NoiseSC.pdf]

Christian-Charles Enz. High precision CMOS micropower amplifiers [pdf]

Below analysis focusing on sampled noise

Boris Murmann. Noise Analysis in Switched-Capacitor Circuits, ISSCC 2011 / tutorials [slides, transcript]

—. EE315A VLSI Signal Conditioning Circuits [pdf]

—. EE315B VLSI Data Conversion Circuits, Autumn 2013 [pdf]

• Calculate autocorrelation function of noise at the output of the RC filter
• Calculate the spectrum by taking the discrete time Fourier transform of the autocorrelation function

Bernhard E. Boser . Advanced Analog Integrated Circuits Switched Capacitor Gain Stages [https://people.eecs.berkeley.edu/~boser/courses/240B/lectures/M05%20SC%20Gain%20Stages.pdf]

Cyclostationary Noise (Modulated Noise)

[https://ece-research.unm.edu/bsanthan/ece541/cyclo.pdf]

Chembian Thambidurai, "Power Spectral Density of Pulsed Noise Signals" [link]

White Noise Modulation

Noisy Resistor & Clocked Switch

\[ v_t (t) = v_i(t)\cdot m_t(t) \]

where \(v_i(t)\) is input white noise, whose autocorrelation is \(A\delta(\tau)\), and \(m_t(t)\) is periodically operating switch, then autocorrelation of \(v_t(t)\) \[\begin{align} R_t (t_1, t_2) &= E[v_t(t_1)\cdot v_t(t_2)] \\ &= R_i(t_1, t_2)\cdot m_t(t_1)m_t(t_2) \end{align}\]

Then \[\begin{align} R_t(t, t-\tau) &= R_i(\tau)\cdot m_t(t)m_t(t-\tau) \\ & = A\delta(\tau) \cdot m_t(t)m_t(t-\tau) \\ & = A\delta(\tau) \cdot m_t(t) \end{align}\] Because \(m_t(t)=m_t(t+T)\), \(R_t(t, t-\tau)\) is is periodic in the variable \(t\) with period \(T\)

The time-averaged ACF is denoted as \(\tilde{R_t}(\tau)\)

\[ \tilde{R}_{t}(\tau) = m\cdot A\delta(\tau) \] That is, \[ S_t(f) = m\cdot S_{A}(f) \]

Colored Noise Modulation

\[ \tilde{R_t}(\tau) = R_i(\tau)\cdot m_{tac}(\tau) \]

where \(m_t(t)m_t(t-\tau)\) averaged on \(t\) is denoted as \(m_{tac}(\tau)\) or \(\overline{m_t(t)m_t(t-\tau)}\)

The DC value of \(m_{tac}(\tau)\) can be calculated as below

1. for \(m\le 0.5\), the DC value of \(m_{tac}(\tau)\) \[ \frac{m\cdot mT}{T} = m^2 \]

2. for \(m\gt 0.5\), the DC value of \(m_{tac}(\tau)\) \[ \frac{(m+2m-1)(1-m)T + (2m-1)\{mT -(1-m)T\}}{T} = m^2 \]

Therefore, time-average power spectral density and total power are scaled by \(m^2\) in fundamental frequency sideband

Switched-Capacitor Track signal

track signal pnoise (sc)

zoom in first harmonic by linear step of pnoise

decreasing the rising/falling time of clock, the harmonics still retain

equivalent circuit for pnoise (eq)

1. thermal noise of R is modulated at first
2. then filtered by ideal filter

sc vs eq

• sc: harmonic distortion
• eq: no harmonic distortion

Non-Stationary Processes (Comparator)

T. Sepke, P. Holloway, C. G. Sodini and H. -S. Lee, "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009 [https://dspace.mit.edu/bitstream/handle/1721.1/61660/Speke-2009-Noise%20Analysis%20for%20Comparator-Based%20Circuits.pdf]

Sepke, Todd. "Comparator design and analysis for comparator-based switched-capacitor circuits." (2006). [https://dspace.mit.edu/handle/1721.1/38925]

Wide-Sense-Stationary Noise

Much like sinusoidal-steady-state signal analysis, steady-state noise analysis methods assume an input \(x(t)\) of infinite duration, which is a Wide-Sense Stationary (WSS) random process

Frequency-domain Analysis

Time-domain Analysis

The output \(y(t)\) of a linear time-invariant (LTI) system \(h(t)\) \[\begin{align} R_{yy}(\tau) &= R_{xx}(\tau)*[h(\tau)*h(-\tau)] \\ &= S_{xx}(0)\delta(\tau) * [h(\tau)*h(-\tau)] \\ &= S_{xx}(0)[h(\tau)*h(-\tau)] \\ &= S_{xx}(0) \int_\alpha h(\alpha)h(\alpha-\tau)d\alpha \end{align}\]

with WSS white noise input \(x(t)\), \(R_{xx}(\tau)=S_{xx}(0)\delta(\tau)\), therefore

Non-stationary Noise

Assuming the noise applied duration is much less than the time constant, the output voltage does not reach steady-state and WSS noise analysis does not apply

In order to determine the response of an LTI system to a step noise input, the problem is more conveniently solved in the time-domain

input signal: step ramp input

noise current: step

Time-domain Analysis

The step noise input \(x(t) = \nu(t)u(t)\) \[ R_{xx}(t_1,t_2) = E[x(t_1)x(t_2)] = R_{\nu\nu}(t_1, t_2)u(t_1)u(t_2)=R_{\nu\nu}(t_1, t_2) \]

\[ R_{xy}(t_1, t_2) = E[x(t_1)y(t_2)] = E[x(t_1)(x(t_2)*h(t_2))] = E(x(t_1)x(t_2))*h(t_2) = R_{xx}(t_1,t_2)*h(t_2) \]

\[ R_{yy}(t_1,t_2) = E[y(t_1)y(t_2)] = E[(x(t_1)*h(t_1))y(t_2)] = E[x(t_1)y(t_2)]*h(t_1)=R_{xy}(t_1,t_2)*h(t_1) \]

the absolute value of each time index is important for a non-stationary signal, and only the time difference was important for WSS signals

\[\begin{align} R_{yy}(t_1,t_2) &= h(t_1)*R_{\nu\nu}(t_1, t_2)*h(t_2) \\ &= h(t_1)*S_{xx}(0)\delta(t_2-t_1)*h(t_2) \\ &=S_{xx}(0) h(t_1)*(\delta(t_2-t_1)*h(t_2)) \\ &= S_{xx}(0)h(t_1)*h(t_2-t_1) \\ &= S_{xx}(0)\int_\tau h(\tau)h(t_2-t_1+\tau))d\tau \end{align}\]

That is \[ \sigma^2_y (t)= R_{yy}(t_1,t_2)|_{t_1=t_2=t}=S_{xx}(0)\int_{-\infty}^t |h(\tau)|^2d\tau \]

\(t\), the upper limit of integration is just intuitive, which lacks strict derivation

Because stable systems have impulse responses that decay to zero as time goes to infinity, the output noise variance approaches the WSS result as time approaches infinity

Frequency-domain Analysis

Because the definition of the PSD assumes that the variance of the noise process is independent of time, the PSD of a non-stationary process is not very meaningful

Richard Schreier. ECE1371 Advanced Analog Circuits Lecture 8 - COMPARATOR & FLASH ADC DESIGN [http://individual.utoronto.ca/schreier/lectures/2015/8-6.pdf]

\[ R_{yy}(0) = \frac{1}{2\pi}\int_{-\infty}^{\infty}|H(\omega)|^2S_{xx}(\omega)d\omega = S \cdot \frac{1}{2\pi}\int_{-\infty}^{\infty}|H(\omega)|^2d\omega \overset{\text{Parseval's Relation}}{=} S\cdot \int_{-\infty}^{\infty}|h(t)|^2dt \]

Input Referred Noise

Noise Voltage to Timing Jitter Conversion & noise gain

with a step ramp input \(v_X(t) = Mtu(t)\)

The noise gain is \[ |A_N(t_i)| = A_0 (1-e^{t_i/\tau_o})u(t) \] where \(t_i\) is crossing time of ideal threshold comparator

\[\begin{align} \overline{v_n^2} &= \frac{\overline{v_{on}^2}}{|A_N|^2} \\ &= \frac{G_n}{G_m}\frac{kT}{C}\frac{1}{A_0}\frac{1+e^{-t_i/\tau_o}}{1-e^{-t_i/\tau_o}} \\ &=4kT\frac{G_n}{G_m^2}\frac{1}{4R_oC} \coth(\frac{t_i}{2\tau_o}) \\ &= 4kTR_n\frac{1}{4\tau_o} \coth(\frac{t_i}{2\tau_o}) \end{align}\]

where \(R_n = \frac{G_n}{G_m^2}\), the equivalent thermal noise resistance

reference

David Herres, The difference between signal under-sampling, aliasing, and folding URL: https://www.testandmeasurementtips.com/the-difference-between-signal-under-sampling-aliasing-and-folding-faq/

Pharr, Matt; Humphreys, Greg. (28 June 2010). Physically Based Rendering: From Theory to Implementation. Morgan Kaufmann. ISBN 978-0-12-375079-2. Chapter 7 (Sampling and reconstruction)

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition

活塞环(Piston Ring)

马力 vs 扭矩

扭矩 = 力 x 力臂 (T=FL)

悬挂 (vehicle suspension)

变速箱 (transmission)

变速箱实现转速和扭矩的转换：低档扭矩大，转速慢； 高档扭矩小，转速慢

发动机小齿轮和变速箱大齿轮啮合处的力相同（力的作用是相互的），但是力臂不同，于是实现了扭矩转换

阿克曼转向几何 (Ackerman steering geometry)

缸内直喷 (direct injection)

• 歧管喷油
• 缸内直喷
  • 省油
  • 动力更强
  • 喷油时间自由度大

This cascode compensation topology is popularly known as ahuja compensation

The cause of the positive zero is the feedforward current through \(C_m\).

To abolish this zero, we have to cut the feedforward path and create a unidirectional feedback through \(C_m\).

1. Adding a resistor(nulling resistor) is one way to mitigate the effect of the feedforward current.

2. Another approach uses a current buffer cascode to pass the small-signal feedback current but cut the feedforward current

People name this approach after the author Ahuja

The benefits of Ahuja compensation over Miller compensation are severa

• better PSRR

• higher unity-gain bandwidth using smaller compensation capacitor

• ability to cope better with heavy capacitive and resistive loads

Miller's approximation

Right-Half-Plane Zero

\[ \left[(v_i - v_o)sC_c - g_m v_i\right]R_o = v_o \] Then \[ \frac{v_o}{v_i} = -g_mR_o\frac{1-s\frac{C_c}{g_m}}{1+sR_oC_c} \] right-half-plane Zero \(\omega _z = \frac{g_m}{C_c}\)

Equivalent cap

The amplifier gain magnitude \(A_v = g_m R_o\) \[ I_\text{c,in} = (v_i - v_o)sC_c \] Then \[\begin{align} I_\text{c,in} &= (v_i + A_v v_i)sC_c \\ & = v_i s (1+A_v)C_c \end{align}\]

we get \(C_\text{in,eq}= (1+A_v)C_c\simeq A_vC_c\)

Similarly \[\begin{align} I_\text{c,out} &= (v_o - v_i)sC_c \\ & = v_o s (1+\frac{1}{A_v})C_c \end{align}\]

we get \(C_\text{out,eq}= (1+\frac{1}{A_v})C_c\simeq C_c\)

cascode compensation

Of course, , if the capacitance at the gate of \(M_1\) is taken into account, pole splitting is less pronounced.

including \(r_\text{o2}\)

\[ \frac{V_{out}}{I_{in}} \approx \frac{-g_{m1}R_SR_L(g_{m2}+C_Cs)}{\frac{R_S+r_\text{o2}}{r_\text{o2}}R_LC_LC_Cs^2+g_{m1}g_{m2}R_LR_SC_Cs+g_{m2}} \] The poles as

\[\begin{align} \omega_{p1} &\approx \frac{1}{g_{m1}R_LR_SC_c} \\ \omega_{p2} &\approx \frac{g_{m2}R_Sg_{m1}}{C_L}\frac{r_\text{o2}}{R_S+r_\text{o2}} \end{align}\]

and zero is not affected, which is \(\omega_z =\frac{g_{m2}}{C_C}\)

the above model simulation result is shown below

the zero is located between two poles

take into the capacitance at the gate of \(M_1\) and all other second-order effect

intuitive analysis of zero

miller compensation

• zero in the right half plane \[ g_\text{m1}V_P = sC_c V_P \]

cascode compensation

• zero in the left half plane \[ g_\text{m2}V_X = - sC_c V_X \]

How to Mitigate Impact of Zero

dominant pole \[ \omega_\text{p,d} = \frac {1} {R_\text{eq}g_\text{m9}R_{L}C_{c}} \] first nondominant pole \[ \omega_\text{p,nd} = \frac {g_\text{m4}R_\text{eq}g_\text{m9}} {C_L} \] zero \[ \omega_\text{z} = (g_\text{m4}R_\text{eq})(\frac {g_\text{m9}} {C_c}) \] a much greater magnitude than \(g_\text{m9}/C_C\)

Lectures

EE 240B: Advanced Analog Circuit Design, Prof. Bernhard E. Boser [OTA II, Multi-Stage]

Papers

B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers," in IEEE Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983, doi: 10.1109/JSSC.1983.1052012.

D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range," in IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984, doi: 10.1109/JSSC.1984.1052246.

Abo, Andrew & Gray, Paul. (1999). A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter.

Book's chapters

Design of analog CMOS integrated circuits, Behzad Razavi

• 10.5 Compensation of Two-Stage Op Amps
• 10.7 Other Compensation Techniques

Analog Design Essentials, Willy M.C. Sansen

• chapter #5 Stability of operational amplifiers - Compensation of positive zero

Analysis and Design of Analog Integrated Circuits 5th Edition, Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer

• 9.4.3 Two-Stage MOS Amplifier Compensation

CMOS Analog Circuit Design 3rd Edition, Phillip E. Allen, Douglas R. Holberg

• 6.2.2 Miller Compensation of the Two-Stage Op Amp

Ahuja variations

reference

B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers," IEEE 1. Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983. [https://sci-hub.se/10.1109/JSSC.1983.1052012]

U. Dasgupta, "Issues in "Ahuja" frequency compensation technique", IEEE International Symposium on Radio-Frequency Integration Technology, 2009. [https://sci-hub.se/10.1109/RFIT.2009.5383679]

R. 1. Reay and G. T. A. Kovacs, "An unconditionally stable two-stage CMOS amplifier," IEEE 1. Solid-State Circuits, vol. 30, no. 5, pp. 591- 594, May 1995.

A. Garimella and P. M. Furth, "Frequency compensation techniques for op-amps and LDOs: A tutorial overview," 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp. 1-4, doi: 10.1109/MWSCAS.2011.6026315.

H. Aminzadeh, R. Lotfi and S. Rahimian, "Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers," 2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 264-267, doi: 10.1109/ICECS.2006.379776.

H. Aminzadeh and K. Mafinezhad, "On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers," Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), Bangalore, India, 2008, pp. 283-288, doi: 10.1145/1393921.1393995.

Stabilizing a 2-Stage Amplifier URL:https://a2d2ic.wordpress.com/2016/11/10/stabilizing-a-2-stage-amplifier/