KNOW-HOW

charge pumps are capacitive DC-DC converters. The two most common switched capacitor voltage converters are the voltage inverter and the voltage doubler circuit

voltage doubler

output buffer capacitor

To achieve a stable DC output voltage

Step-Wise Ramp-Up

\[ V_{in} C_p + V_{out,n-1}C_o = (V_{out,n}-V_{in})C_p + V_{out,n}C_o \]

We derive a recursive equation that describes the output voltage \(V_{out,n}\) after the \(n\)th clock cycle \[ V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o} \]

Voltage Ripple & Droop

\[\begin{align} (V_t - V_h)(C_p + C_o) &= \frac{I_{load}}{2f_{sw}} \\ (V_h - V_b)C_o &= \frac{I_{load}}{2f_{sw}} \end{align}\]

we obtain \[ V_t - V_b = \frac{I_{load}}{f_{sw}C_o}\left(1 - \frac{C_p}{2(C_p + C_o)}\right) \] That is, peak-to-peak ripple \[ \Delta V_{out,p2p} \approx \frac{I_{load}}{f_{sw}C_o} \space\space\space\space \text{if}\space\space C_o \gg C_p \]

Then, with aforementioned Step-Wise Ramp-Up equation, \(V_t = \frac{2V_{in}C_p + V_bC_o}{C_p + C_o}\) \[\begin{align} V_b &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p}{2C_o}\right) \\ V_t &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 - \frac{C_p}{2(C_p+C_o)}\right) \end{align}\]

Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right) \approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p} \] which results in a simple expression for the output voltage droop

\[ \Delta V_{out} = \frac{I_{load}}{f_{sw}C_p} \]

The charge pump can be modeled as a voltage source with a source resistance \(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage drop across \(R_\text{out}\) due to the load current:

\[ R_{out} = \frac{\Delta V_{out}}{I_{load}} = \frac{1}{f_{sw}C_p} \]

multiphase CP

\[ (V_t - V_b) (C_p + C_o) = I_{load}\Delta t \]

Therefore peak-to-peak ripple \[ \Delta V_{out,p2p} = \frac{I_{load}\Delta t}{C_p+C_o} = \frac{I_{load}\Delta t}{C_{tot}} \]

where \(C_{tot} = C_p+C_o\)

with \[ \left\{ \begin{array}{cl} V_b &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} \\ V_t &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} + \frac{I_{load}\Delta t}{C_p+C_o} \end{array} \right. \]

Then \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}\Delta t}{C_p}\cdot \frac{C_p+2C_o}{2C_p+2C_o} \approx 2V_{in} - \frac{I_{load}\Delta t}{C_p} \] That is output voltage droop \[ \Delta V_{out} = \frac{I_{load}\Delta t}{C_p} \]

reference

Bernhard Wicht, "Design of Power Management Integrated Circuits". 2024 Wiley-IEEE Press

Breussegem, T. v., & Steyaert, M. (2013). CMOS integrated capacitive DC-DC converters. Springer

Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023).

Anton Bakker, Tim Piessens., ISSCC2014 T9: Charge Pump and Capacitive DC-DC Converter Design

Wicht, B., ISSCC2020 T2: Analog Building Blocks of DC-DC Converters [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T2Visuals.pdf]

Hoi Lee, ISSCC2018 T8: Fundamentals of Switched-Mode Power Converter Design [slides,transcript]

G. Palumbo and D. Pappalardo, "Charge Pump Circuits: An Overview on Design Strategies and Topologies," in IEEE Circuits and Systems Magazine, vol. 10, no. 1, pp. 31-45, First Quarter 2010 [pdf]

alternative view of sampling, assuming DC value is \(A\)

• \(x_c(t)\) and \(x_s(t)\)

  \(\overline{x_c} = A\); \(\overline{x_s}=\frac{A}{T}\): therefore \(X_s(j0) = \frac{1}{T}X_c(j0)\)

• \(x[n]\) and \(x_d[n]\)

  \(\overline{x} = A\); \(\overline{x_d}=\frac{A}{2}\): therefore \(X_d(e^{j0}) = \frac{1}{2}X(e^{j0})\)

expander

• \(x[n]\) and \(x_e[n]\)

  \(\overline{x} = A\); \(\overline{x_e}=A\): therefore \(X_e(e^{j0}) = X(e^{j0})\)

  Fourier transform of the output of the expander is a frequency-scaled version of the Fourier transform of the input

Subsampling or Downsampling

• Eqs. (4.72)

  the superposition of an infinite set of amplitude-scaled copies of \(X_c(j\Omega)\), frequency scaled through \(\omega = \Omega T_d\) and shifted by integer multiples of \(2\pi\)

• Eq. (4.77)

  the superposition of \(M\) amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by \(M\) and shifted by integer multiples of \(2\pi\)

downsampled by a factor of \(M = 2\)

Upsampling or Zero Insertion

Rouphael, Tony. (2009). RF and Digital Signal Processing for Software-Defined Radio. [pdf]

Assuming \(X(e^{j\omega_1}) = U_f(e^{j\omega_1})\) with \(\omega_1 = \Omega T_1\), upsampled by ratio \(L\), then obtain

\[ Y(e^{j\omega_2})=X(e^{j\omega_2 L}) = U_f(e^{j\omega_2 L}) \]

by EQ. (4.85), i.e. substitute \(\omega_1\) with \(\omega_2 L\), where with \(\omega_2 = \Omega T_2\) and \(T_2 L = T_1\)

Provided that \(\xi = e^{j\omega_1}\) and \(z = e^{j\omega_2}\), we have \(U_f(\xi)\) upsampled to \(U_f(z^L)\)

Interpolation filter

Pavan, Schreier and Temes, "Understanding Delta-Sigma Data Converters, Second Edition"

Markus Nentwig. Polyphase filter / Farrows interpolation [https://www.dsprelated.com/showarticle/22.php]

sampling identities

downsampling identity

upsampling identity

Polyphase Decomposition

Polyphase decomposition is a powerful technique used in digital signal processing to efficiently implement multirate systems.

where \(e_k[n]=h[nM+k]\)

Polyphase Implementation of Decimation Filters & Interpolation Filters

	Decimation system	Interpolation system
sampling identity

LPTV Implementation

TODO 📅

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a zero-order hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

Dr. Deepa Kundur, Multirate Digital Signal Processing: Part I [pdf, https://www.comm.utoronto.ca/dkundur/course/discrete-time-systems/]

ZOH interpolator

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a Zero-Order Hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

\[ F_1(z) = X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \]

Split the \(1:LM\) hold process into a \(1 : L\) hold followed by a \(1 : M\) hold \[ Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}} \] then \[\begin{align} F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\ &=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \end{align}\]

That is \(F_1(z)=F_2(z)\), i.e. they are equivalent

Random Signals & Multirate Systems

Balu Santhanam, Probability Theory & Stochastic Process 2020: Random Signals & Multirate Systems [https://ece-research.unm.edu/bsanthan/ece541/rand.pdf]

Decimation by Summing

proportional path

The loop gain of a proportional path is unchanged

In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is \[ LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}} \]

In (b), Accumulate-And-Dump (AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \] Hence \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot \frac{1}{1-\eta^{-1}} \end{align}\]

After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align} \phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}} \end{align}\] i.e., \[ LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \]

When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx 1\)

Therefore \[ LG_b(z) \approx \frac{1}{1-z^{-1}} \]

In the end \[ LG_a(z) \approx LG_b(z) \]

Assume PD output is constant

integral path

integral path gain reduced by \(L\)

In (a), \(\phi_o(z)=\frac{1}{(1-z^{-1})^2}\), i.e. \[ LG_a(z) = \frac{1}{(1-z^{-1})^2} \]

In (b), after Accumulate-And-Dump (AAD), \(\phi(\eta)\) is \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \]

After frequency integrator and phase integrator \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \cdot \frac{1}{(1-\eta^{-1})^2} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \cdot \frac{1}{(1-\eta^{-1})^2} \end{align}\] Then \(\phi_f(z)\) is shown as below \[\begin{align} \phi_f(z) &= \phi_o(z^L)\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{(1-z^{-L})^2}\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} \end{align}\]

That is, \[ LG_b(z) = \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} = \frac{1}{L}\cdot LG_a(z) \]

Assume PD output is constant

\[ \lim_{n\to +\infty} \frac{\Delta P_1}{\Delta P_0} = \lim_{n\to +\infty}\frac{n+2L}{nL+\alpha L+\beta L^2} = \frac{1}{L} \]

Decimation by Voting

In above screenshot

1. \(K_D\) is just relative value
2. frug shall not be scaled by decimator factor

proved as below

DC gain \(K_B\) of summing (boxcar filter) is decimation factor \(M\) , voting gain \(K_V\) is about \(0.54K_b=0.54M\)

1. downsampling \(\frac{1}{M}\) and ZOH \(\frac{1-z^{-M}}{1-z^{-1}}\) can be canceled out at low frequency
2. decimation gain: accumulator \(\frac{1-z^{-M}}{1-z^{-1}}\) replaced with linearizing gain \(K_B\) and majority voting replaced with \(K_V\)

proportional path: \[\begin{align} LG_{ph} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{1-z^{-M}} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{1-z^{-M}} \end{align}\]

integral path: \[\begin{align} LG_{fr} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{(1-z^{-M})^2}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{(1-z^{-M})^2} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{(1-z^{-M})^2} \end{align}\]

J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery" [slides,transcript]

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

J. Sonntag and J. Stonick, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]

J. Liang, A. Sheikholeslami, "On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits" [https://tspace.library.utoronto.ca/bitstream/1807/91138/3/Liang_Joshua_201706_PhD_thesis.pdf]

J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]

J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]

M. M. Khanghah, K. D. Sadeghipour, D. Kelly, C. Antony, P. Ossieur and P. D. Townsend, "A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers [https://cora.ucc.ie/bitstreams/7ae5bfaa-8dd9-45a7-8276-99676b7b6078/download]

[CDR CIRCUIT-BLOCKS: DESIGN AND VERIFICATION USING VERILOG - 2.6. DECIMATOR]

Michael H. Perrott, Tutorial on Digital Phase-Locked Loops, CICC 2009, San Jose, CA, Sept. 13, 2009 [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

Liu, Tao, Tiejun Li, Fangxu Lv, Bin Liang, Xuqiang Zheng, Heming Wang, Miaomiao Wu, Dechao Lu, and Feng Zhao. 2021. "Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits" Electronics 10 [https://www.mdpi.com/2079-9292/10/16/1888/pdf?version=1628492599]

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1. [https://assets-eu.researchsquare.com/files/rs-1817774/v1_covered.pdf?c=1664188179]

Chen, Junkun, Youzhi Gu, Xinjie Feng, Runze Chi, Jiangfeng Wu, and Yongzhen Chen. 2024. "Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model" Electronics [https://mdpi-res.com/electronics/electronics-13-04218/article_deploy/electronics-13-04218-v2.pdf?version=1730106095]

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9910561]

TODO 📅

Tristate: \(\alpha=1\)

XOR: \(\alpha=1\)

\(\frac{1}{T}\) in Divider

Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]

\(\frac{1}{T}\) & \(T\) come from CT-DT & DT-CT

H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10630516]

Sonntag JSSC 2006

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clear;
close all;
clc;


Tb = 200e-12;
Ts = Tb*8;			% the decimation factor was 8
z = tf('z', Ts);

Kdpc = 1/2^9;
Kv = 8*0.54;
Kpd = 10.6;
phug = 2^-3;
frug = 2^-12;
Nel = 18;

options = bodeoptions;
options.FreqUnits = 'MHz';
options.XLim = [1e-2, 1e1];
options.YLim = [-10, 5];

L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-11;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-10;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

legend('frug=2^{-12}','frug=2^{-11}', 'frug=2^{-10}', 'FontSize',10)
grid on;
title('phase transfer function', 'FontSize', 12)
xlabel('frequency', 'FontSize',10)
ylabel('frequency response', 'FontSize',10)

Full View

Kpd, Kb, Kv

• Kpd formula: 12.467; Kpd_bb_0 12.465
• Kpd_Kb: 49.860; Kpd_Kv 27.265
• Kb: 4.00; Kv 2.19

That is

1. gain of BoxCar is the decimation factor
2. Voting across 4 inputs had a 54% reduced gain relative to boxcar filter

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import numpy as np
from scipy.stats import norm
import itertools
from tqdm import tqdm
import matplotlib.pyplot as plt

sigmai = 0.032  #UI, input jitter
Ptrans = 0.5    # Transition density
deci_factor = 4

phase_error = np.linspace(-0.1, 0.1, 201)     #UI, phase offset
pd_late = norm.cdf(phase_error/sigmai)
pd_early = 1.0 - pd_late
pd_avg = pd_late*1.0 - 1.0*pd_early

Kpd_bb = (pd_avg[1:] - pd_avg[:-1])/(phase_error[1:] - phase_error[:-1])*Ptrans
Kpd_bb_0 = np.max(Kpd_bb)

## by formula
Kpd_calc = 1.0/(sigmai*np.sqrt(2*np.pi))

print(f'Kpd formula: {Kpd_calc:.3f}; Kpd_bb_0 {Kpd_bb_0:.3f}')  # Kpd formula: 12.467; Kpd_bb_0 12.465

plt.figure()
plt.plot(phase_error, pd_avg, color='r', linewidth=3)
plt.title('!! PD average output vs timing offset(UI)')
plt.grid()
plt.show()


prob = np.zeros((phase_error.shape[0],3))
prob[:,0] = pd_early*Ptrans     # -1
prob[:,1] = 1.0 - Ptrans        # 0
prob[:,2] = pd_late*Ptrans      # 1

pd_out = np.array([-1.0,0.0,1.0])
idxs = list([[0,1,2] for _ in range(deci_factor)])
boxcar_avg = []
voting_avg = []
for i in tqdm(range(phase_error.shape[0])):
    prob_i = prob[i,:]
    boxcar_tmp = 0.0
    voting_tmp = 0.0
    for idxs_tmp in itertools.product(*idxs):
        pd_list = pd_out[[idxs_tmp]]
        prob_list = prob_i[[idxs_tmp]]
        pd_sum = np.sum(pd_list)
        pd_vote = 1.0 if pd_sum > 0.0 else -1.0 if pd_sum <0.0 else 0.0
        prob_prod = np.prod(prob_list)
        boxcar_tmp += pd_sum*prob_prod
        voting_tmp += pd_vote*prob_prod
    boxcar_avg.append(boxcar_tmp)
    voting_avg.append(voting_tmp)

boxcar_avg = np.array(boxcar_avg)
voting_avg = np.array(voting_avg)

plt.figure()
plt.plot(phase_error,boxcar_avg, label='FIR BoxCar', color='r', linewidth=3)
plt.plot(phase_error,voting_avg, label='Voting', color='b', linewidth=3, linestyle='--')
plt.legend()
plt.title('!!PD+BoxCar / !!PD+Voting vs timing offset(UI)')
plt.grid()
plt.show()


Kpd_Kb = (boxcar_avg[1:] - boxcar_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_Kv = (voting_avg[1:] - voting_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_kb_0 = np.max(Kpd_Kb)
Kpd_kv_0 = np.max(Kpd_Kv)
print(f'Kpd_Kb: {Kpd_kb_0:.3f}; Kpd_Kv {Kpd_kv_0:.3f}')     # Kpd_Kb: 49.860; Kpd_Kv 27.265

plt.figure()
plt.plot(phase_error[:-1], Kpd_Kb, color='r', linewidth=3)
plt.plot(phase_error[:-1], Kpd_Kv, color='b', linewidth=3, linestyle='--')
plt.legend(['Kpd_Kb', 'Kpd_Kv'])
plt.title('Kpd*Kb / Kpd*Kv vs timing offset(UI)')
plt.grid()
plt.show()

Kb = Kpd_kb_0 / Kpd_bb_0
Kv = Kpd_kv_0 / Kpd_bb_0
print(f'Kb: {Kb:.2f}; Kv {Kv:.2f}')     # Kb: 4.00; Kv 2.19

with deci_factor = 8

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Kpd formula: 12.467; Kpd_bb_0 12.465
Kpd_Kb: 99.719; Kpd_Kv 39.155
Kb: 8.00; Kv 3.14

with deci_factor = 16

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Kpd formula: 12.467; Kpd_bb_0 12.465
Kpd_Kb: 199.439; Kpd_Kv 55.784
Kb: 16.00; Kv 4.48

reference

Alan V Oppenheim, Ronald W. Schafer. 2010. Discrete-Time Signal Processing, 3rd edition

R. E. Crochiere and L. R. Rabiner, "Multirate Digital Signal Processing", Prentice Hall, 1983.

John G. Proakis and Dimitris G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th edition, 2007.

D. Sundararajan. 2024. Digital Signal Processing: An Introduction 2nd Edition

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Qasim Chaudhari. Sample Rate Conversion [https://wirelesspi.com/sample-rate-conversion/]

Push-Pull

TODO 📅

Rinaldo Castello, "LINEARIZATION TECHNIQUES FOR PUSH-PULL AMPLIFIERS" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/AMPLIFIERS_Stanf_Tor_2016_Last.pdf]

Rail-to-Rail Op amp

[https://mixsignal.wordpress.com/wp-content/uploads/2013/03/689-604rail2rail.pdf]

[https://toshiba.semicon-storage.com/ap-en/semiconductor/knowledge/faq/linear_opamp/what-does-rail-to-rail-mean.html]

TODO 📅

self-biased active loading

Vishal Saxena "CMOS Comparator Design Extra Slides" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Comparator%20Slides.pdf]

W. Liu, P. Huang and Y. Chiu, "A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010 [https://sci-hub.se/10.1109/ISSCC.2010.5433830]

Slewing in Folded-Cascode Op Amps

In practice, we choose \(I_P \simeq I_{SS}\)

Avoid zero current in cascodes

• left circuit

  \(I_b \gt I_a\)

• right circuit

  \(I_b \gt 2I_a\)

Huijsing, J. H. (2017). Operational Amplifiers: Theory and Design. (3 ed.) Springer

[https://bbs.eetop.cn/forum.php?mod=redirect&goto=findpost&ptid=995502&pid=11548528]

Response Speed in Analog Circuits

Hyun-Sik Kim, KAIST, A-SSCC 2024 Circuit Insights: FT3 Accelerating Response Speed in Analog Circuits [link]

Bandwidth limitation

slew rate limitation

Assuming linear response \[ V_o(t) = 1 - e^{-\omega_T t} \]

\[ \frac{\mathrm{d}V_o}{\mathrm{d}t} = \omega_Te^{-\omega_T t} = \frac{g_m}{C_L}e^{-\omega_T t} = \frac{g_m}{I_B}\cdot \frac{I_B}{C_L}\cdot e^{-\omega_T t} \gt \frac{I_B}{C_L} \]

where \(\frac{g_m}{I_B} e^{-\omega_T t} \gt 1\) at initial response

Therefore, initial response speed is dominated by SR, rather than \(G_m\) (or bandwidth)

MOS parasitic Rd&Rs, Cd&Cs

Decrease the parasitic R&C

priority: \(R_s \gt R_d\), \(C_s \gt C_d\)

source follower

A. Sheikholeslami, "Voltage Follower, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457

—, ESSCIRC2023 Circuit Insights [https://youtu.be/2xFIZM5_FPw]

—, CICC2025 Circuit Insights: From Simple to Super Source Follower [https://youtu.be/CWfMKltPIQ8]

Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits (5th. ed.). Wiley Publishing. [pdf]

Super-source follower (SSF)

Flipped Voltage Follower (FVF)

T&H buffer in ADC

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_flipped-voltage-follower-fvf-basics-activity-7118482840803020800-qwyX?utm_source=share&utm_medium=member_desktop]

Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.

Double Differential pair

\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end

assume input and reference common voltage are same

Pros of (b)

• larger input range i.e., \(\gt \pm \sqrt{2}V_\text{ov}\) of (a), it works even one differential is off due to lower voltage
• larger \(g_m\) (smaller input difference of pair)

Cons of (b)

• sensitive to the difference of common voltage between \(V_\text{ip}\), \(V_\text{im}\) and \(V_\text{rp}\), \(V_\text{rm}\)

common-mode voltage difference

copy aforementioned formula here for convenience \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

at sample phase \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}= V_\text{cmr}\)

• \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\)
• \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

at compare start

• \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{cmr}+\Delta\), \(V_\text{rp}= V_\text{cmr}-\Delta\)

• \(I_\text{ip}\lt I_\text{ip0}\), \(I_\text{rp} \gt I_\text{rp0}\)

• \(I_\text{im}\gt I_\text{im0}\), \(I_\text{rm} \lt I_\text{rm0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to increase \(V_\text{ip}\) and decrease \(V_\text{im}\).

at the compare finish

\[\begin{align} V_\text{ip}= V_\text{cmi} + \Delta \\ V_\text{im}= V_\text{cmi} - \Delta \end{align}\]

and \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\), \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

If \(V_\text{cmr} - V_\text{cmi} = \sqrt{2}V_{OV} + \delta\), and \(\delta \gt 0\). one transistor carries the entire tail current

• \(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\), all the time

At the end, \(V_\text{im} = V_\text{cmi} - (\Delta - \delta)\), the error is \(\delta\)

In closing, \(V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV}\) for normal work

Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to limited impedance of current source and input pair offset

In the end \[ V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS} \]

Under the condition, every transistor of pairs are on in equilibrium

pair mismatch

\[\begin{align} I_{SE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \\ I_{DE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \end{align}\]

The input equivalient offset voltage \[\begin{align} V_{os,SE} &= \frac{I_{SE}}{2g_m} = \frac{\sigma_{vth,0} + \sigma_{vth,1}}{2} \\ V_{os,DE} &= \frac{I_{DE}}{g_m} = \sigma_{vth,0} + \sigma_{vth,1} \end{align}\]

Then \[\begin{align} \sigma_{vos,SE} &= \sqrt{\frac{2\sigma_{vth}^2}{4}} = \frac{\sigma_{vth}}{\sqrt{2}} \\ \sigma_{vos,DE} &= \sqrt{2\sigma_{vth}^2} = \sqrt{2}\sigma_{vth} \end{align}\]

We obtain \[ \sigma_{vos,DE} = 2\sigma_{vos,SE} \]

Input Differential pair

Todd Brooks, Broadcom "Input Programmable Gain Amplifier (PGA) Design for ADC Signal Conditioning" [https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/OSU%20Classroom%20Presentaton%20042511.ppt]

DM Distortion

CM Distortion

Resistive Degeneration

Resistive degeneration in differential pairs serves as one major technique for linear amplifier

The linear region for CMOS differential pair would be extended by \(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[\begin{align} V_{in}^+ -V_{in}^- &= V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} \\ &= \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \end{align}\]

Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf

Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]

Biasing Tradeoffs in Resistive-Degenerated Diff Pair

w/ Current–Mirror Load

S. Pavan, "Revisiting the CMOS Differential Pair With a Current–Mirror Load [CAS Education]," in IEEE Circuits and Systems Magazine, vol. 25, no. 2, pp. 74-78, Secondquarter 2025 [pdf]

TODO 📅

The DDSM performs integer arithmetic (equivalently, fixed-point with the binary point at the LSB) to realize a fractional value.

linearized model

Noise Cancellation Network

\[\begin{align} v[n] = \{0,1,2,...,M-1\} &\space\Rightarrow\space y[n] = 0 \space\Rightarrow\space e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \\ v[n] = \{M,M+1,M2,...,2M-1\} &\space\Rightarrow\space y[n] = 1 \space\Rightarrow\space e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \end{align}\]

\((1 − z^{−1})^3\)

For the three stages of the MASH 1-1-1 DDSM

1st order DDSM (digital accumulator)

assuming \(n_0=2\)

yield \(M=2^{n_0}=4\)

2nd order DDSM

In \(z\)-domain \[ \left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y \right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y \] That is \[ Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2 \] In time domain \[\begin{align} y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\ &= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2] \end{align}\]

LSB Dither

?? integer valued impulse responses

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [pdf]

stability of DSM

accumulator wordlength

Z. Ye and M. P. Kennedy, "Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 112-116, Feb. 2009 [https://sci-hub.se/10.1109/TCSII.2008.2010188]

—, "Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 4, pp. 714-726, April 2009 [https://sci-hub.se/10.1109/TCSI.2008.2003383]

Truncation DAC

accumulator is implicit quantizer

with \(\frac{y}{2^{m_2}} + q= v\), where \(v = \lfloor\frac{y}{2^{m_2}}\rfloor\)

\[ \left\{ \begin{array}{cl} Y + 2^{m_2} Q &= 2^{m_2}V \\ U - z^{-1}2^{m_2}Q &= Y \end{array} \right. \]

The STF & NTF is shown as below \[ V = \frac{1}{2^{m_2}}U + (1-z^{-1})Q \]

To avoid accumulator overflow, stable input range is only of a fraction of the full scale ( \(2^{m_1+m_2}-1\)) \[ u \leq 2^{m_1+m_2} - 2^{m_2} \]

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m1 = 2  # MSBs
m2 = 4  # LSBs

ymax = 2**(m1 + m2)
umax = 2**(m1 + m2) - 2**m2     # int(m1*'1'+m2*'0', 2)
# format(48, '06b')
# Out[4]: '110000'

u = 48
assert u <= umax

ylist = [0]; vlist = [0]
elist = []; outlist = []

Niter = 2**10
for _ in range(Niter):
    ecur = vlist[-1] - ylist[-1]
    elist.append(ecur)
    ycur = (u - ecur)
    assert ycur < ymax, print(ycur)
    ylist.append(ycur)
    ycur_bin = format(ycur, f'0{m1+m2}b')
    vcur = int(ycur_bin[:-m2]+'0'*m2, 2)
    vlist.append(vcur)
    outlist.append(int(ycur_bin[:-m2], 2))

print(vlist); print(ylist)
print(sum(vlist)/len(vlist)); print(sum(outlist)/len(outlist)*2**m2)

To avoid overflow

\[ \log_2(2^k + 2^{N-m}) \leq N \]

Thus \[ N \ge k - \log_2(1 - \frac{1}{2^m}) = k+m -\log_2(2^m-1) \]

suppose \(m\in [1,+\infty)\) \[ k < k - \log_2(1 - \frac{1}{2^m}) \leq k + 1 \] \(N = k +1\) is sufficient for any \(k\)

In the above Temes's sides, \(N = m_1+m_2\) and \(m=m_1\), we have \[ 2^k \leq 2^{m_1+m_2}\cdot (1-\frac{1}{2^{m_1}}) = 2^{m_1+m_2} - 2^{m_2} \]

Generally speaking, \(N \propto k\) and \(N \propto \frac{1}{m}\), especially \(N_{min} = k+1\) if single-bit quantizer \(m=1\)

DSM Order & Output Range

7.4.1 Delta-Sigma Modulator [https://iic-jku.github.io/radio-frequency-integrated-circuits/rfic.html#sec-pll-delta-sigma]

Google AI Mode [https://share.google/aimode/FTiU7YPjm3tnqEk7t]

Fractional-N PLL

Accumulated Quantization Error (AQE)

\[ (N+\alpha)T_{PLL} - \tau[n-1] +\tau[n] = (N+y[n])T_{PLL} \]

i.e. \[ \tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL} \]

where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV}, desired}\)

Y. Zhang et al., "A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602-614, March 2020, [pdf]

X. Wang and M. P. Kennedy, "Unified Analysis of Digital Δ-Σ Modulators (DDSMs) for Fractional-N Frequency Synthesis—Introducing the PASS Family of DDSMs Featuring Independent Shaping of the Probability Density and Spectral Envelope," in IEEE Transactions on Circuits and Systems I: Regular Papers [link]

X. Wang and M. P. Kennedy, "Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs," 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Valencia, Spain, 2023 [link]

\(\Delta\Sigma\) Noise in PLL

\[\begin{align} S_\phi(f) &= \frac{1}{12F_{ref}}|1-z^{-1}|^{2L}\cdot \left|\frac{2\pi z_{-1}}{1-z^{-1}}\right|^2\cdot \frac{1}{T_{ref}^2} T_{ref}^2 \\ &= \frac{1}{12F_{ref}} |1-z^{-1}|^{2L-2} 4\pi^2 \end{align}\]

with \(|1-z^{-1}| = |2\sin\frac{\pi f}{F_{ref}}|\)

\[ S_\phi(f) = \frac{1}{12F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)}\cdot 4\pi^2 = \frac{\pi^2}{3F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)} \]

Frequency & Time-Domian Model for Q-noise

metroidman, fractional N量化噪声对系统相位噪声的影响 两种分析方法 LTI频域法和时域采样DFT法 [link]

LTI Frequency domain model & analysis

fcw: Frequency Control Word

note

\(z=e^{j2\pi f \color{red}T_\text{ref}}\) — model's time tick is reference clock period

\(\frac{\Phi}{N}(z)\) — relationship between \(\Phi\) and \(N\)

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% --- System Parameters ---
fref = 40e6;
fcw = 360.123;
kvco = 2 * pi * 300e6;
 
% Components
icp = 60e-6; C0 = 40e-12;
R1 = 14000; C1 = 360e-12;
R2 = 1000; C2 = 20e-12;

% --- Frequency Vector ---
f = logspace(2, 9, 1000); 
s = 1i * 2 * pi * f;

% --- Loop Filter Transfer Function ---
num_lf = s .* R1 .* C1 + 1;
den_lf = (s.^3 .* R1 .* R2 .* C0 .* C1 .* C2 + ...
          s.^2 .* (R1.*C1.*C0 + R1.*C1.*C2 + R2.*C2.*C0 + R2.*C2.*C1) + ...
          s .* (C0 + C1 + C2));
loopfilter = num_lf ./ den_lf;

% --- Loop Gain and Noise Transfer Function ---
loopgain = (icp / (2*pi)) .* loopfilter .* (kvco ./ s) .* (1 / fcw);
hfra = (loopgain ./ (1 + loopgain)) .* 2*pi./(exp(s./fref) - 1) .* (1 - exp(-s./fref)).^3;

% --- Spectral Density calculation ---
sfra = 10 * log10((1 / (12 * fref)) .* abs(hfra).^2);

% --- Plot ---
semilogx(f, sfra, LineWidth=2);
ylim([-250, -100]); yticks(-250:10:-100); 
grid on; xlabel('Frequency (Hz)'); ylabel('dB');
title('Quantization Noise Effects', FontSize=14);

Time domain model & DFT analysis

Round in In[24] is redundant and likely unnecessary for the logic to function

\(\phi\) and phi is frequency (cycles per second) instead of angular frequency (radians per second)

classic PLL module transient response

initial state is Reset

classic PLL module in Matlab & Simulink

Kai Wang, Is there a way to improve the code speed? [https://www.mathworks.com/matlabcentral/answers/2039821-is-there-a-way-to-improve-the-code-speed]

classic PLL module in Julia

Julia version (Claude Opus 4.7) [https://gist.github.com/raytroop/53f210b2cca18ec77295dc91dbe35818]

classic PLL module in Mathematica

Impulse Train Modulator (ITM)

M. H. Perrott, M. D. Trott and C. G. Sodini, "A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis," in IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002 [https://www.cppsim.com/Publications/JNL/perrott_jssc02.pdf]

\(\Delta\Sigma\) DAC

LPF (RC Filter)

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

Sigma-delta digital-to-analog converters (SD DAC’s) are often used for discrete-time signals with sample rate much higher than their bandwidth

• Because of the high sample rate relative to signal bandwidth, a very simple DAC reconstruction filter (Analog lowpass filter) suffices, often just a one-pole RC lowpass

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R= 4.7e3;                 % ohms resistor value
C= .01e-6;                % F capacitor value
fs= 1e6;                  % Hz DAC sample rate
% input signal
x= [zeros(1,20) .9*ones(1,200) .1*ones(1,200)];
% find output y of SD DAC and output y_filt of RC filter
[y,y_filt]= sd_dacRC(x,R,C,fs);

t = linspace(0,length(x)-1, length(x))*1/fs*1e3;
subplot(3,1,1)
plot(t, x, '.'); title('x'); grid on
subplot(3,1,2)
plot(t, y, '.'); title('y'); grid on
subplot(3,1,3)
plot(t, y_filt); title('y_{filt}'); xlabel('t(ms)'); grid on

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% https://www.dsprelated.com/showarticle/1642.php
% Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter

% function [y,y_filt] = sd_dacRC(x,R,C,fs)  2/5/24 Neil Robertson
% 1-bit sigma-delta DAC with RC filter
% Model does not include a zero-order hold.
%
% x = input signal vector, 0 <= x < 1
% R = series resistor value, Ohms.  Normally R > 1000 for 3.3 V logic.
% C = shunt capacitor value, Farads
% fs = sample frequency, Hz
% y = DAC output signal vector, y(n) = 0 or 1
% y_filt = RC filter output signal vector
%
function [y,y_filt] = sd_dacRC(x,R,C,fs)
N= length(x);
x= fix(x*2^16)/2^16;        % quantize x to 16 bits
%I 1-bit Sigma-delta DAC
s= [x(1) zeros(1,N-1)];
for n= 2:N
    u= x(n) + s(n-1);
    s(n)= mod(u,1);        % sum
    y(n)= fix(u);          % carry
end

%II One-pole RC filter model
% Matched z-Transform https://ocw.mit.edu/courses/2-161-signal-processing-continuous-and-discrete-fall-2008/cc00ac6d468dc9dcf2238fc1d1a194d4_lecture_19.pdf
Ts= 1/fs;
Wc= 1/(R*C);               % rad -3 dB frequency
fc= Wc/(2*pi);             % Hz -3 dB frequency
a1= -exp(-Wc*Ts);
b0= 1 + a1;                % numerator coefficient
a= [1 a1];                 % denominator coeffs
y_filt= filter(b0,a,y);    % filter the DAC's output signal y

ZOH (Zero-Order Hold Models)

Neil Robertson, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

The last D2C is in human vision, which connect discrete time \(y(m)\) with line, implicitly

Sinc Corrector

Neil Robertson, Design a DAC sinx/x Corrector [https://www.dsprelated.com/showarticle/1191.php]

Dan Boschen. how to make CIC compensation filter [https://dsp.stackexchange.com/a/31596/59253]

—. Core Building Blocks for Software Defined Radio (SDR): DDC, DUC, NCO) [https://lnkd.in/p/e2MtC9QK]

Equalizing Techniques Flatten DAC Frequency Response [https://www.analog.com/en/resources/technical-articles/equalizing-techniques-flatten-dac-frequency-response.html]

aka. Inverse Sinc Compensation

TODO 📅

OSR & NS

maximum output signal 22kHz

\[SNR = 16\times 6.02 + 1.76 = 98.08\]

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OSR = 5.65e6/(2*22e3);
Nin = 16;
Nout = 1;

SNR_in = 6.02*Nin + 1.76;

SNR_ds = 6.02*Nout + 1.76 - 10*log10(pi^4/5) + 50*log10(OSR);

QN_in = 1/10^(SNR_in/10);
QN_ds = 1/10^(SNR_ds/10);

SNR_out = 10*log10(1/(QN_in + QN_ds));

Y. Liu, J. Gao and X. Yang, "24-bit low-power low-cost digital audio sigma-delta DAC," in Tsinghua Science and Technology, vol. 16, no. 1, pp. 74-82, Feb. 2011 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6077939]

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snr_if = 144;
snr_ds = 135;
snr_ana = 95;

n_if = 1/10^(snr_if/10);
n_ds = 1/10^(snr_ds/10);
n_ana = 1/10^(snr_ana/10);

snr_tot = 10*log10(1/(n_if + n_ds + n_ana))

% 
% snr_tot =
% 
%    94.9995

MASH 1-1-1 Model

J. W. M. Rogers, F. F. Dai, M. S. Cavin and D. G. Rahn, "A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC," in IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 678-689, March 2005 [https://sci-hub.se/10.1109/JSSC.2005.843604]

(a) a fractional accumulator, and (b) a triple-loop \(\Delta\Sigma\) accumulator for \(N(z) = 100 + 1/32\)

\(n=5\)

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import numpy as np
import matplotlib.pyplot as plt
import scipy.fft as fft
import scipy.signal.windows as windows

def acc_nbit(din, nbit=5, ncycles=2**10):
    mod = 2**nbit
    acc = 0
    eq = 0
    colist = []
    eqlist = []
    for i in range(ncycles):
        acc = din[i] + eq
        eq = acc % mod
        #print(acc, eq)
        co_tmp = int(acc >= mod)
        colist.append(co_tmp)
        eqlist.append(eq)
    return colist, eqlist

Ncyl = 2**16
cin1 = [1]*Ncyl

c1,eq1 = acc_nbit(cin1, ncycles=Ncyl)
cin2 = [0,*eq1[:-1]]
#cin2 = eq1

c2,eq2 = acc_nbit(cin2, ncycles=Ncyl)
cin3 = [0,*eq2[:-1]]
#cin3 =  eq2

c3,eq3 = acc_nbit(cin3, ncycles=Ncyl)

ctot = []

for i in range(2, Ncyl):
    # C1(z) + (1 − z^−1)C2(z) + (1 − z^−1)^2 C3(z)
    ctot_cur = c1[i] + c2[i]-c2[i-1] + c3[i]-2*c3[i-1] + c3[i-2]
    ctot.append(ctot_cur)

print(sum(c1)/len(c1))      # 0.03125
print(sum(ctot)/len(ctot))  # 0.03128147221289712

plt.figure(figsize=(20,8))
plt.subplot(1,2,1)
plt.plot(c1[:200], 'o-', label='c1')
plt.legend(loc='upper left'); plt.grid(True)
plt.subplot(1,2,2)
plt.plot(ctot[:200], 'o-', label='ctot')
plt.legend(loc='upper left'); plt.grid(True)


Ntot = int(2**np.floor(np.log2(len(ctot))))
c1_4fft = np.array(c1[:Ntot])
ctot_4fft = np.array(ctot[:Ntot])
whann = windows.hann(Ntot)
Y_c1 = abs(fft.rfft(c1_4fft*whann))/sum(whann)
Y_ctot = abs(fft.rfft(ctot_4fft*whann))/sum(whann)

print(Y_c1[0])      # 0.031250000002717625
print(Y_ctot[0])    # 0.031249999999526525

plt.figure(figsize=(20,8))
plt.subplot(2, 1, 1)
_, stemlines, _ = plt.stem(Y_c1, markerfmt=" ", label='c1')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')
plt.subplot(2, 1, 2)
_, stemlines, _ = plt.stem(Y_ctot, markerfmt=" ", label='ctot')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')

plt.show()

Harald Pretl, Radio-Frequency Integrated Circuits. 7.4 Fractional-N PLL [note] [MASH Modulator (3rd Order) code]

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# Stage 1: 1st order modulator with input signal
self.integrator1 += input_value
y1 = 1 if self.integrator1 >= 1.0 else 0
e1 = self.integrator1 - y1  # Quantization error
self.integrator1 = e1  # Store error for next iteration

# Stage 2: 1st order modulator fed with quantization error from stage 1
self.integrator2 += e1
y2 = 1 if self.integrator2 >= 1.0 else 0
e2 = self.integrator2 - y2
self.integrator2 = e2

# Stage 3: 1st order modulator fed with quantization error from stage 2
self.integrator3 += e2
y3 = 1 if self.integrator3 >= 1.0 else 0
e3 = self.integrator3 - y3
self.integrator3 = e3

# Digital noise cancellation logic for MASH 1-1-1
# Output = Y1 + (1-z^-1)*Y2 + (1-z^-1)^2*Y3
# Expanding (1-z^-1)^2 = 1 - 2*z^-1 + z^-2:
# Output = Y1 + Y2 - Y2[z^-1] + Y3 - 2*Y3[z^-1] + Y3[z^-2]

combined = y1 + (y2 - self.y2_prev) + (y3 - 2*self.y3_prev + self.y3_prev2)

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for i in range(length):
    dither = rng.uniform(-dither_amplitude, dither_amplitude) if dither_amplitude > 0 else 0.0
    combined, y1, y2, y3 = self.step(input_value + dither)
    combined_output[i] = combined
    y1_output[i] = y1
    y2_output[i] = y2
    y3_output[i] = y3

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# Plot 2: Frequency spectrum (with dither)
ax2 = plt.subplot(1, 2, 2)
N = len(mash_combined_with_dither)
fft_freq = np.fft.fftfreq(N)
pos_freq = fft_freq >= 0
fft_no = np.fft.fft(mash_combined_with_dither)
psd_no = 20 * np.log10(np.abs(fft_no) / N + 1e-12)

metroidman, 用Simulink Excel Mathematica三种不同工具从零搭建3阶ΣΔ调制器并进行时域和频率分析 [link]

Simulink

Excel

Mathematica

The code fcwit = Table[fcwi[i], {i, 9999}]; is the command that actually runs the simulation for a set duration.

Here is the breakdown of what is happening:

• Table[..., {i, 9999}]: This creates a list by repeating an operation 9,999 times. It acts like a for loop in other programming languages.
• fcwi[i]: This calls the function you defined earlier. For every value of i from 1 to 9,999, it calculates the instantaneous integer division ratio produced by the MASH modulator.
• fcwit = ...: It stores all 9,999 results into a single long list (an array) named fcwit.
• ; (Semicolon): This is important—it suppresses the output. Without it, Mathematica would print all 9,999 numbers on your screen, which would be a huge mess!

reference

Michael Peter Kennedy. scv-cas 2014: Digital Delta-Sigma Modulators [pdf,recording]

—, Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators [pdf]

Kaveh Hosseini and Peter Kennedy. 2006 Hardware Efficient Maximum Sequence Length Digital MASH Delta Sigma Modulator [pdf]

Jason Sachs. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

Neil Robertson, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Rick Lyons. How Discrete Signal Interpolation Improves D/A Conversion [https://www.dsprelated.com/showarticle/167.php]

Dan Boschen. sigma delta modulator for DAC [https://dsp.stackexchange.com/a/88357/59253]

Woogeun Rhee. ISCAS 2019 Mini Tutorials: Single-Bit Delta-Sigma Modulation Techniques for Robust Wireless Systems [https://youtu.be/OEyTM4-_OyA]

—, 2001 Phd Thesis: Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers [https://www.ime.tsinghua.edu.cn/Thesis_rhee.pdf]

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2017/05/2007-TCASI-S.-Pamarti-Statistics-of-the-Quantization-Noise-in-1-Bit-Dithered-Single-Quantizer-Digital-Delta-Sigma-Modulators.pdf]

—. "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]

—. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8]

Ian Galton. Delta-Sigma Fractional-N Phase-Locked Loops [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2022/10/fnpll_ieee_tutorial_2003_corrected.pdf]

—. ISSCC 2010 SC3: Fractional-N PLLs [https://www.nishanchettri.com/isscc-slides/2010%20ISSCC/Short%20Course/SC3.pdf]

—. “Delta-Sigma Fractional-N Phase-Locked Loops.” (2003).

Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T6Visuals.pdf]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

John Rogers, Calvin Plett, and Foster Dai. 2006. Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library). Artech House, Inc., USA. [pdf]

K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital Delta-Sigma Modulators (Analog Circuits and Signal Processing). New York, NY, USA: Springer, 2011.

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007.

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Delta-Sigma Modulators
│
├─ Analog ΔΣ Modulators
│  │
│  ├─ Discrete-Time Analog ΔΣ Modulator, DT ΔΣM
│  │  ├─ Switched-capacitor / switched-current loop filter
│  │  ├─ Input is sampled before or inside loop filter
│  │  └─ Very common in ΔΣ ADCs
│  │
│  └─ Continuous-Time Analog ΔΣ Modulator, CT ΔΣM
│     ├─ Continuous-time RC / gm-C / active-RC loop filter
│     ├─ Feedback DAC is continuous-time
│     ├─ Quantizer is usually clocked → synchronous CT ΔΣM
│     └─ Quantizer/comparator may be event-driven → asynchronous CT ΔΣM
│
└─ Digital ΔΣ Modulators, DDSM
   │
   ├─ Single-quantizer DDSM
   │  ├─ Output-feedback form
   │  └─ Error-feedback form, EFM
   │
   └─ MASH DDSM
      └─ Multi-stage noise-shaping modulator

"Quantizers" and "truncators", "integrators" and "accumulators" are used in delta-sigma ADCs and DACs, respectively

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

Oversampling

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

Nyquist sampling theorem @signal: no aliasing, signal remain the same

noise folding @noise: same total noise power spread over a wider frequency

[https://dsp.stackexchange.com/a/40261/59253]

Noise Shaping

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[h1, w1] = freqz([1 -1], 1);
[h2, w2] = freqz([1 -2 1], 1);

plot(w1/2/pi, abs(h1), LineWidth=3)
hold on
plot(w2/2/pi, abs(h2), LineWidth=3)
grid on
legend('MOD1', 'MOD2')
xlabel('fs')
ylabel('mag')
title('NTF of MOD1 & MOD2')

SQNR improvement

In general, for an \(l\)th order modulator with \(\text{NTF}(z) = (1 − z^{−1})^l\), the SQNR increases by \((6l + 3)\) dB for every doubling of the OSR, which provides \(l+0.5\) extra bits resolution

without the delta-sigma loop

\(10\log (2) \approx 3\)dB

first order delta-sigma modulator

\(30\log (2) \approx 9\)dB

second order delta-sigma modulator

\(50\log (2) \approx 15\)dB

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OSR= linspace(1,16,16);

SQNR_ovonly_delta = 10*log10(OSR);
SQNR_1st_delta = -10*log10(pi^2/3) + 30*log10(OSR);
SQNR_2st_delta = -10*log10(pi^4/5) + 50*log10(OSR);

plot(OSR, SQNR_ovonly_delta,'ro-', LineWidth=4);
hold on
plot(OSR, SQNR_1st_delta,'bo-', LineWidth=4);
plot(OSR, SQNR_2st_delta,'mo-', LineWidth=4);
grid on; grid minor;
xlim([1 16]); ylim([-20 50]);
xlabel('OSR', FontSize=16); ylabel('\DeltaSQNR (dB)', FontSize=16);
legend('Oversampling Only', '1st \Delta\Sigma', '2nd \Delta\Sigma', fontsize=16)

TI. ADC12EU050 Continuous-Time Sigma-Delta ADCs [https://www.ti.com/lit/an/snaa098/snaa098.pdf]

where \(N\) is the number of bits in the output, \(M\) is known as the over-sampling ratio, \(L\) is loop orders

Quantizer Bits & ENOB

without the delta-sigma loop

High-Order \(\Delta\Sigma\) Modulators

The greater the number of quantizer levels, the smaller quantization error

Performance Metrics

• signal-to-noise ratio (SNR)
• dynamic range (DR)
• signal-to-(noise + distortion) ratio (SNDR)

DR by "SNR Max" Definition (\(\Delta\Sigma\) Specific)

Quantizer overload

M. Neitola, "Lee's Rule Extended," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 4, pp. 382-386, April 2017

Maximum Stable Amplitude (MSA)

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% Schreier Delta-Sigma Toolbox required
OSR   = 64;
order = 3;
nlev  = 2;
H_inf = 1.5;

ntf = synthesizeNTF(order, OSR, 1, H_inf);

N    = 2^14;
fB   = floor(N/(2*OSR));            % last in-band bin index (0-based)
fin  = round(fB/3);                 % in-band test tone
amps = -80:2:0;
snr  = zeros(size(amps));

w    = ds_hann(N);
nb = 1;                              % Hann: 2*nb+1 = 3 signal bins

for k = 1:length(amps)
    A    = 10^(amps(k)/20);
    u    = A*sin(2*pi*fin/N*(0:N-1));
    v    = simulateDSM(u, ntf, nlev);
    spec = fft(v .* w) / (sum(w)/2);

    inband = spec(1:fB+1);          % <-- KEY: only in-band bins
    snr(k) = calculateSNR(inband, fin, nb);
end

plot(amps, snr,'-o'); grid on;
xlabel('Input amplitude (dBFS)');
ylabel('SNR (dB)');
title(sprintf('Order=%d, OSR=%d, %d-lev, ||NTF||_\\infty=%.1f',...
              order, OSR, nlev, H_inf));

\(\Delta \Sigma\) vs. \(\Delta\) modulation

• \(\Delta \Sigma\) modulators, and other noise-shaping modulators, change the spectrum of the noise but leave the signal unchanged

• \(\Delta\) modulators and other signal-predicting modulators shape the spectrum of the modulated signal but leave the quantization noise unchanged at the receiver

output vs. error-feedback

The error-feedback architecture is problematic for analog implementation, since it is sensitive to variations of its parameters (subtractor realization)

ADC

DAC

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

output-feedback

[https://www.linkedin.com/posts/danboschen_signalprocessing-dsp-pythonforengineers-activity-7345777588746788866-SprG?utm_source=share&utm_medium=member_desktop&rcm=ACoAAD-cuiIBDJ62eh9q3qTSSdslYXr-XMd8TGw]

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// https://github.com/hamsternz/second_order_sigma_delta_DAC

`timescale 1ns / 1ps
module second_order_dac(
  input wire i_clk,
  input wire i_res,
  input wire i_ce,
  input wire [15:0] i_func, 
  output wire o_DAC
);

  reg this_bit;
 
  reg [19:0] DAC_acc_1st;
  reg [19:0] DAC_acc_2nd;
  reg [19:0] i_func_extended;
   
  assign o_DAC = this_bit;

  always @(*)
     i_func_extended = {i_func[15],i_func[15],i_func[15],i_func[15],i_func};
    
  always @(posedge i_clk or negedge i_res)
    begin
      if (i_res==0)
        begin
          DAC_acc_1st<=16'd0;
          DAC_acc_2nd<=16'd0;
          this_bit = 1'b0;
        end
      else if(i_ce == 1'b1) 
        begin
          if(this_bit == 1'b1)
            begin
              DAC_acc_1st = DAC_acc_1st + i_func_extended - (2**15);
              DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st     - (2**15);
            end
          else
            begin
              DAC_acc_1st = DAC_acc_1st + i_func_extended + (2**15);
              DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st + (2**15);
            end
          // When the high bit is set (a negative value) we need to output a 0 and when it is clear we need to output a 1.
          this_bit = ~DAC_acc_2nd[19];
        end
    end
endmodule

Time and Frequency Domain

\(M \gt N\)

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/Intro_to_Delta_Sigma_Data_Converters.pdf]

Chun-Hsien Su ( 蘇純賢). Fundamentals of Sigma-Delta Data Converters,July, 2006 [pdf]

ADC

hackaday. Tearing Into Delta Sigma ADC’s [https://hackaday.com/2016/07/07/tearing-into-delta-sigma-adcs-part-1/]

DAC

an interpolation filter effectively up-samples its low-rate input and lowpass-filters the resulting high-rate data to produce a high-rate output devoid of images

P.E. Allen -CMOS Analog Circuit Design: Lecture 39 – Oversampling ADCs – Part I (6/26/14) [https://aicdesign.org/wp-content/uploads/2018/08/lecture39-140626.pdf]

P.E. Allen -CMOS Analog Circuit Design: Lecture 40 – Oversampling ADCs – Part II (7/17/15) [https://aicdesign.org/wp-content/uploads/2018/08/lecture40-150717.pdf]

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/Intro_to_Delta_Sigma_Data_Converters.pdf]

No delay-free loops

Any such physically feasible device will take a finite time to operate – in other words, the quantized output will only be available a small time after the quantizer has "looked" at the input - insert a one-sample delay

there cannot be a "delay free loop" is a common idea in sequential digital state machine design

Both integrator and quantizer are delay free

NTF realizability criterion: No delay-free loops in the modulator

linear settling & GBW of amplifier

TODO 📅

Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.

MOD1 & MOD2

MOD1: first-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD2: second-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD1

\[ V(z) = U(z) +(1-z^{-1})E(z) \]

• A binary DAC (and hence a binary modulator) is inherently linear
• With a CT loop filter, MOD1 has inherent anti-alising

\[\begin{align} v[1] &= u - (0) + e[1] \\ v[2] &= 2u - (v[1]) + e[2] \\ v[3] &= 3u - (v[1]+v[2]) + e[3] \\ v[4] &= 4u - (v[1]+v[2]+v[3]) + e[4] \end{align}\]

That is \[ v[n] = nu - \sum_{k=1}^{n-1}v[k] + e[n] \] Therefore, we have \(v[n-1] = (n-1)u - \sum_{k=1}^{n-2}v[k] + e[n-1]\), then \[\begin{align} v[n] &= nu - \sum_{k=1}^{n-1}v[k] + e[n] \\ &= u + \left((n-1)u - \sum_{k=1}^{n-2}v[k]\right) - v[n-1] + e[n] \\ &= u + v[n-1] - e[n-1] -v[n-1] + e[n] \\ &= u + e[n] - e[n-1] \end{align}\]

Dout, the low frequency component of ADC out is same with Vin

MOD2

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/2nd_Higher_Order.pdf]

MOD1 with DC Excitation

TODO 📅

Mismatch Shaping

Data-Weighted Averaging (DWA)

\[\begin{align} \sum_{i=0}^{n}v[i] + e_\text{DAC}[n] &= y[n] \\ \sum_{i=0}^{n-1}v[i] + e_\text{DAC}[n-1] &= y[n-1] \end{align}\]

and we have \(w[n] = y[n] - y[n-1]\), then \[ w[n] = v[n] + e_\text{DAC}[n] - e_\text{DAC}[n-1] \] i.e. \[ W = V + (1-z^{-1})e_\text{DAC} \]

Element Rotation:

[http://individual.utoronto.ca/schreier/lectures/12-2.pdf], [http://individual.utoronto.ca/trevorcaldwell/course/Mismatch.pdf]

integrator leakage

When the integrator includes leakage (\(\alpha\))

\[ x[n-1] + \alpha y[n-1] = y[n] \]

then, \[ \frac{Y}{X} = \frac{z^{_1}}{1-\alpha z^{-1}} \]

Schreier Delta-Sigma Toolbox

Richard Schreier (2026). Delta Sigma Toolbox [https://www.mathworks.com/matlabcentral/fileexchange/19-delta-sigma-toolbox]

TODO 📅

synthesizeNTF

simulateDSM

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function [v,xn,xmax,y] = simulateDSM(u,arg2,nlev,x0)
%[v,xn,xmax,y] = simulateDSM(u,ABCD,nlev=2,x0=0)
% or
%[v,xn,xmax,y] = simulateDSM(u,ntf,nlev=2,x0=0)
%
%Compute the output of a general delta-sigma modulator with input u,
%a structure described by ABCD, an initial state x0 (default zero) and 
%a quantizer with a number of levels specified by nlev.
%Multiple quantizers are implied by making nlev an array,
%and multiple inputs are implied by the number of rows in u.
%
%Alternatively, the modulator may be described by an NTF.
%The NTF is zpk object. (The STF is assumed to be 1.)
%The structure that is simulated is the block-diagional structure used by
%zp2ss.m.

calculateSNR

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function snr = calculateSNR(hwfft,f,nsig)

signalBins = [f-nsig+1:f+nsig+1];
s = norm(hwfft(signalBins));

noiseBins = 1:length(hwfft);
noiseBins(signalBins) = [];
n = norm(hwfft(noiseBins));

snr = dbv(s/n);

end

reference

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016). Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

Norsworthy, Steven R., Richard Schreier, Gábor C. Temes and Ieee Circuits. “Delta-sigma data converters : theory, design, and simulation.” (1997).

Horowitz, P., & Hill, W. (2015). The art of electronics (3rd ed.). Cambridge University Press.

John Rogers, Calvin Plett, and Foster Dai. 2006. Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library). Artech House, Inc., USA.

Razavi B. Analysis and Design of Data Converters. Cambridge University Press; 2025.

R. Schreier, ISSCC2006 tutorial: Understanding Delta-Sigma Data Converters

Shanthi Pavan, ISSCC2013 T5: Simulation Techniques in Data Converter Design [https://www.nishanchettri.com/isscc-slides/2013%20ISSCC/TUTORIALS/ISSCC2013Visuals-T5.pdf]

Bruce A. Wooley , 2012, "The Evolution of Oversampling Analog-to-Digital Converters" [https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf]

Venkatesh Srinivasan, ISSCC 2019 T5: Noise Shaping in Data Converters

B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016. [http://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf]

P. M. Aziz, H. V. Sorensen and J. vn der Spiegel, "An overview of sigma-delta converters," in IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 61-84, Jan. 1996 [https://sci-hub.st/10.1109/79.482138]

Richard E. Schreier, ECE 1371 Advanced Analog Circuits - 2015 [http://individual.utoronto.ca/schreier/ece1371-2015.html]

Gabor C. Temes. ECE 627-Oversampled Delta-Sigma Data Converters [https://classes.engr.oregonstate.edu/eecs/spring2017/ece627/lecturenotes.html]

Joshua Reiss. Understanding sigma delta modulation: the solved and unsolved issues

[https://www.eecs.qmul.ac.uk/~josh/documents/2008/Reiss-JAES-UnderstandingSigmaDeltaModulation-SolvedandUnsolvedIssues.pdf]

V. Medina, P. Rombouts and L. Hernandez-Corporales, "A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation [Feature]," in IEEE Circuits and Systems Magazine, vol. 24, no. 2, pp. 80-97, Secondquarter 2024

Carsten Wulff , Oversampling and Sigma-Delta ADCs [https://analogicus.com/aic2026/oversampling_and_sigma-delta_adcs]

PDM Microphones and Sigma-Delta A/D Conversion [https://tomverbeure.github.io/2020/10/04/PDM-Microphones-and-Sigma-Delta-Conversion.html]

Noise Analysis

sampling (amplification) phase

Noise Simulation

PSS + Pnoise Method

Comparator Output SNR during sampling region and decision region go up

Comparator Output SNR during regeneration region is constant, where noise is critical

Transient Noise Method

Noise Fmax sets the bandwidth of the random noise sources that are injected at each time point in the transient analysis

We can identify the RMS noise value easily by looking at 15.9% or 84.1% of CDF (\(1\sigma\)), the input-referred noise in the RMS is 0.9mV

Thus, if \(V_S\) is chosen so as to reduce the probability of zeros to 16%, then \(V_S = 1\sigma\), which is also the total root-mean square (rms) noise referred to the input.

Comparison of two methods

here, fundamental frequency = fclk; integrated noise (0 ~ 0.5fclk)

E. Gillen, G. Panchanan, B. Lawton and D. O'Hare, "Comparison of transient and PNOISE simulation techniques for the design of a dynamic comparator," 2022 33rd Irish Signals and Systems Conference (ISSC), Cork, Ireland, 2022, pp. 1-5

Chenguang Yang, "Comparator Design for High Speed ADC" [https://lup.lub.lu.se/luur/download?func=downloadFile&recordOId=9164380&fileOId=9164388]

J. Conrad, J. Kauffman, S. Wilhelmstatter, R. Asthana, V. Belagiannis and M. Ortmanns, "Confidence Estimation and Boosting for Dynamic-Comparator Transient-Noise Analysis," 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada, 2024, pp. 1-5

There are some ambiguity in formula in ADC Verification Rapid Adoption Kit (RAK)(Product Version: IC 6.1.8, SPECTRE 18.1 March, 2019)

• Transient Noise Analysis: \(\sqrt{2}\sigma\), why ratio \(\sqrt{2}\) ???
• PSS+Pnoise: why two fundamental tones fclk/2 ???

Common-Mode (Vcmi) Variation Effects

Zhaokai Liu. Time-interleaved SAR ADC Design Using Berkeley Analog Generator [https://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-109.pdf]

offset simulation

T. Caldwell. ECE 1371S Advanced Analog Circuits [http://individual.utoronto.ca/trevorcaldwell/course/comparators.pdf]

Eric Chang. EECS240-s18 Discussion 9

Graupner, Achim & Sobe, Udo. (2007). Offset-Simulation of Comparators. [https://designers-guide.org/analysis/comparator.pdf]

1 2 3 4

Comment on "Offset-Simulation of Comparators" If the input referred offset follows a normal distribution than it is sufficient to apply a single offset voltage to calculate the offset voltage. See details in Razavi, B., The StrongARM Latch [A Circuit for All Seasons], IEEE Solid-State Circuits Magazine, Volume:7, Issue: 2, Spring 2015

Omran, Hesham. (2019). Fast and accurate technique for comparator offset voltage simulation. Microelectronics Journal. 89. 10.1016/j.mejo.2019.05.004.

Matthews, Thomas W. and Perry L. Heedley. “A simulation method for accurately determining DC and dynamic offsets in comparators.” 48th Midwest Symposium on Circuits and Systems, 2005. (2005): 1815-1818 Vol. 2. [https://athena.ecs.csus.edu/~pheedley/MSDL/MSDL_DOTB_cmp_test_bench_MWSCAS05.pdf]

Hysteresis

P. Bruschi: Notes on Mixed Signal Design http://www2.ing.unipi.it/~a008309/mat_stud/MIXED/archive/2019/Optional_notes/Chap_3_4_Comparators.pdf

TODO 📅

Kickback Noise

Kickback noise trades with the dimensions of the input transistors and hence with the offset voltage

• affects the comparator's own decision
• corrupts the input voltage while it is sensed by other circuits

Tetsuya Iizuka,VLSI2021_Workshop3 "Nyquist A/D Converter Design in Four Days"

Figueiredo, Pedro & Vital, João. (2006). Kickback noise reduction techniques for CMOS latched comparators. Circuits and Systems II: Express Briefs, IEEE Transactions on. 53. 541 - 545. 10.1109/TCSII.2006.875308. [https://sci-hub.se/10.1109/TCSII.2006.875308]

P. M. Figueiredo and J. C. Vital, "Low kickback noise techniques for CMOS latched comparators," 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, BC, Canada, 2004, pp. I-537 [https://sci-hub.se/10.1109/ISCAS.2004.1328250]

Lei, Ka Meng & Mak, Pui-In & Martins, R.P.. (2013). Systematic analysis and cancellation of kickback noise in a dynamic latched comparator. Analog Integrated Circuits and Signal Processing. 77. 277-284. 10.1007/s10470-013-0156-1. [https://rto.um.edu.mo/wp-content/uploads/docs/ruimartins_cv/publications/journalpapers/57.pdf]

O. M. Ívarsson, "Comparator Kickback Reduction Techniques for High-Speed ADCs," Dissertation, 2024. [https://liu.diva-portal.org/smash/get/diva2:1872476/FULLTEXT01.pdf]

Current mirrors are used between stages to reduce charge kick back from the logic level swing of the latch onto the small comparator input capacitors

Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006 [pdf, slides]

K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/," in IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 1887-1895, Dec. 1997 [https://sci-hub.st/10.1109/4.643647]

CMOS Latch

TODO 📅

\[ V_{o,fb}^+ - V_{o,fb}^- = \frac{g_m}{sC_L}(V_o^+ - V_o^-) = A(s)\cdot(V_o^+ - V_o^-) \]

We have \[ A(s)\cdot (V_{i} + V_o) = V_o \]

that is \[ V_o = \frac{A(s)}{1-A(s)}V_{i} = \frac{1}{s - g_m/C_L}\cdot \frac{g_mV_i}{C_L} \]

therefore \[ V_o(t) = \frac{g_mV_i}{C_L}\cdot\exp\left({\frac{g_m}{C_L}t}\right) = V_o(t=0)\cdot\exp\left({\frac{g_m}{C_L}t}\right) \]

Asad Abidi, ISSCC 2023: Circuit Insights "The CMOS Latch" [https://youtu.be/sVe3VUTNb4Q]

Metastability

TODO 📅

If the comparator can not generate a well-defined logical output in half of the clock period, we say the circuit is "metastable"

Math Background

Relating \(\Phi\) and erf

Error Function (Erf) of the standard Normal distribution \[ \text{Erf}(x) = \frac{2}{\sqrt{\pi}}\int_0^x e^{-t^2} \mathrm{d}t. \] Cumulative Distribution Function (CDF) of the standard Normal distribution \[ \Phi(x) = \frac{1}{\sqrt{2\pi}}\int_{-\infty}^x e^{-z^2/2} \mathrm{d}z. \]

\[\begin{align} \Phi(x) &= \frac{\text{Erf}(x/\sqrt{2})+1}{2}. \\ \Phi(x\sqrt{2}) &= \frac{\text{Erf}(x) + 1}{2} \end{align}\]

Considering the mean and standard deviation \[ \Phi(x,\mu,\sigma)=\frac{1}{2}\left( 1+\text{Erf} \left( \frac{x-\mu}{\sigma\sqrt{2}} \right)\right) \]

John D. Cook. Relating Φ and erf [https://www.johndcook.com/erf_and_normal_cdf.pdf]

reference

Xu, H. (2018). Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs. UCLA. ProQuest ID: Xu_ucla_0031D_17380. Merritt ID: ark:/13030/m5f52m8x. Retrieved from [https://escholarship.org/uc/item/88h8b5t3]

A. Abidi and H. Xu, "Understanding the Regenerative Comparator Circuit," Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-8. [https://picture.iczhiku.com/resource/ieee/WHiYwoUjPHwZPXmv.pdf]

T. Sepke, P. Holloway, C. G. Sodini and H. -S. Lee, "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009 [https://dspace.mit.edu/bitstream/handle/1721.1/61660/Speke-2009-Noise%20Analysis%20for%20Comparator-Based%20Circuits.pdf]

Sepke, Todd. "Comparator design and analysis for comparator-based switched-capacitor circuits." (2006). [https://dspace.mit.edu/handle/1721.1/38925]

P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008 [https://picture.iczhiku.com/resource/eetop/SYirpPPPaAQzsNXn.pdf]

J. Kim, B. S. Leibowitz, J. Ren and C. J. Madden, "Simulation and Analysis of Random Decision Errors in Clocked Comparators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1844-1857, Aug. 2009, doi: 10.1109/TCSI.2009.2028449. URL:https://people.engr.tamu.edu/spalermo/ecen689/simulation_analysis_clocked_comparators_kim_tcas1_2009.pdf

J. Kim, B. S. Leibowitz and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 386-391, doi: 10.1109/ICCAD.2008.4681602. [https://websrv.cecs.uci.edu/~papers/iccad08/PDFs/Papers/05C.2.pdf]

Jaeha Kim, Lecture 12. Aperture and Noise Analysis of Clocked Comparators URL:https://ocw.snu.ac.kr/sites/default/files/NOTE/7038.pdf

Sam Palermo. ECEN720: High-Speed Links Circuits and Systems Spring 2023 Lecture 6: RX Circuits [https://people.engr.tamu.edu/spalermo/ecen689/lecture6_ee720_rx_circuits.pdf]

Y. Luo, A. Jain, J. Wagner and M. Ortmanns, "Input Referred Comparator Noise in SAR ADCs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 718-722, May 2019. [https://sci-hub.se/10.1109/TCSII.2019.2909429]

X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April 2020 [https://sci-hub.se/10.1109/JSSC.2019.2960485]

Chen, Long & Sanyal, Arindam & Ma, Ji & Xiyuan, Tang & Sun, Nan. (2016). Comparator Common-Mode Variation Effects Analysis and its Application in SAR ADCs. 10.1109/ISCAS.2016.7538972. [https://labs.engineering.asu.edu/mixedsignals/wp-content/uploads/sites/58/2017/08/ISCAS_comp_long_2016.pdf]

V. Stojanovic, and V. G. Oklobdzija, "Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536–548, April 1999. [https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Clocking/Vlada-Latches-JoSSC-Apr-1999.pdf]

C. Mangelsdorf, "Metastability: Deeply misunderstood [Shop Talk: What You Didn’t Learn in School]," in IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 8-15, Spring 2024

Rabuske, Taimur & Fernandes, Jorge. (2014). Noise-aware simulation-based sizing and optimization of clocked comparators. Analog Integr. Circuits Signal Process.. 81. 723-728. 10.1007/s10470-014-0428-4. [https://sci-hub.se/10.1007/s10470-014-0428-4]

Rabuske, Taimur & Fernandes, Jorge. (2016). Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications. 10.1007/978-3-319-39624-8.

Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, "A low-noise self-calibrating dynamic comparator for high-speed ADCs," 2008 IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, 2008 [slides, paper]

Art Schaldenbrand, Senior Product Manager, Keeping Things Quiet: A New Methodology for Dynamic Comparator Noise Analysis URL:https://www.cadence.com/content/dam/cadence-www/global/en_US/videos/tools/custom-_ic_analog_rf_design/NoiseAnalyisposting201612Chalk%20Talk.pdf

B. Razavi, "The Design of a Comparator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 12, Issue. 4, pp. 8-14, Fall 2020. [https://www.seas.ucla.edu/brweb/papers/Journals/BR_SSCM_4_2020.pdf]

—, "The StrongARM Latch [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Issue. 2, pp. 12-17, Spring 2015. [https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine4.pdf]

B. Murmann. ISSCC 2011 Tutorial: Noise Analysis in Switched Capacitor Circuits [slides, transcription]

—, "Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques," IEEE Solid-State Circuits Magazine, vol. 4, no. 2, pp. 46-54, June 2012 [https://sci-hub.se/10.1109/MSSC.2012.2192190]

X. Huang. Thermal noise analysis of switched-capacitor amplifier [theory, simulation]

CHUNG-CHUN (CC) CHEN. Why A Dedicated Noise Analysis for A Strong-arm Latch / Comparator? [https://youtu.be/S5GnvFxuxUA]

—. Why Transient Noise (Trannoise) Analysis for A Strong-arm Latch / Comparator? [https://youtu.be/gpQggSM9_PE]

—. Why A Periodic Steady-State (PSS), Periodic Noise (Pnoise), and Hand Calculation for A Sampler? [https://youtu.be/lGqCfg5R-rY]

Tony Chan Carusone,. 28 Comparator Specs and Characterization [https://youtu.be/mRfWM1bpr3k]

Prof. Seung-Tak Ryu (KAIST) "Advanced ADC Design Techniques" Online Course (2022) : Dynamic Latch [https://youtu.be/zE1ZdG_XzWk]

IC宇宙成长记. 动态比较器噪声仿真 [link]

Raised Cosine

Equations for the Raised Cosine and Square-Root Raised Cosine Shapes [https://engineering.purdue.edu/~ee538/SquareRootRaisedCosine.pdf]

Pulse Shaping Filter [https://wirelesspi.com/pulse-shaping-filter/]

Why Root Raised Cosine (RRC) Used at both transmitter and receiver ?

Toeplitz matrix

Robert M. Gray, Toeplitz and Circulant Matrices: A review [https://ee.stanford.edu/~gray/toeplitz.pdf]

toeplitz Toeplitz matrix, [https://www.mathworks.com/help/matlab/ref/toeplitz.html]

ZFS

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h = [0.01 -0.02 0.05 -0.1 0.2 1 0.15 -0.15 0.05 -0.02 0.005];
[val, idx] = max(h);

htc = h(idx-2:idx+2)';

H1 = [1 0.2 -0.1 0.05 -0.02;
    0.15 1 0.2 -0.1 0.05;
    -0.15 0.15 1 0.2 -0.1;
    0.05 -0.15 0.15 1 0.2;
    -0.02 0.05 -0.15 0.15 1];

c = [1 0.15 -0.15 0.05 -0.02];
r = fliplr([-0.02 0.05 -0.1 0.2 1]);
T = toeplitz(c, r);

isequal(H1, T) % logical 1

inv(T)
% 
% ans =
% 
%     1.0774   -0.2682    0.1932   -0.1314    0.0806
%    -0.2266    1.1272   -0.2983    0.2034   -0.1314
%     0.2326   -0.2737    1.1517   -0.2983    0.1932
%    -0.1405    0.2516   -0.2737    1.1272   -0.2682
%     0.0888   -0.1405    0.2326   -0.2266    1.0774

MMSE

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h=[0.004, 0.0010, 0.0023, 0.0052, 0.0812, 0.3437, 0.1775, 0.0917, 0.0526,...
    0.0360, 0.0224, 0.0162, 0.0152, 0.0097, 0.0090, 0.0067];

k = length(h);
n = 3;
l = 1;
m2 = 5;
m1 = 1;

H = zeros([k+n+l-2, n+l-1]);
H(1:end-2,1) = h;
H(2:end-1,2) = h;
H(3:end,3) = h;

c = zeros(length(h)+2, 1);
c(1:end-2) = h;
r = zeros(3, 1);
r(1) = h(1);

T = toeplitz(c, r);

isequal(H, T) % logical 1

transpose(toeplitz(c,r)) is same with toeplitz(r,c)

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isequal(transpose(toeplitz(c, r)), toeplitz(r, c)) % logical 1

V. Stojanovic, "Channel-Limited High-Speed Links: Modeling, Analysis and Design," PhD. Thesis, Stanford University, Sep. 2004. [pdf]

Bandpass Modulation

Pulse Amplitude Modulation (PAM)

David A. Johns, ECE1392H - Integrated Circuits for Digital Communications - Fall 2001 [System Overview]

\(S_m\) Google AI mode [https://share.google/aimode/BzYr2logpVTVs83LQ]

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snr_mpam = @(m,simga) 10*log10((4^m-1)/simga^2/3);

sigma = 0.1547;

SNR_m2 = snr_mpam(2, sigma);  % 23.1999
SNR_m3 = snr_mpam(3, sigma);  % 29.4324

Lecture 3, Tuesday January 13th 2026 - Modulation Types (PAM/QAM) [https://cioffi-group.stanford.edu/ee379a/Lectures/L3.pdf]

Carrier & Symbol Synchronization

\(\Delta\tau \lt \pm \frac{1}{100} T\) don't ensure \(\Delta \phi \ll 2\pi\) due to \(T \gg \frac{1}{f_c}\)

Carrier Synchronization

[https://ndl.ethernet.edu.et/bitstream/123456789/87843/14/LECT_13%2614.Synchronization.pdf]

Symbol Synchronization

[https://www.ieee802.org/3/dm/public/1125/cordaro_3dm_01_1125.pdf]

Mathuranathan, Symbol Timing Recovery for QPSK (digital modulations) [https://www.gaussianwaves.com/2013/11/symbol-timing-recovery-for-qpsk-digital-modulations/]

Qasim Chaudhari. Early-Late Bit Synchronizer in Digital Communication [https://wirelesspi.com/early-late-bit-synchronizer-in-digital-communication/]

Igor Freire. Symbol Timing Synchronization: A Tutorial [blog, code]

But the problem here is: "How does the receiver know the ideal sampling instants?". The solution is "someone has to supply those ideal sampling instants". A symbol time recovery circuit is used for this purpose.

Early/Late Symbol Recovery algorithm

• non-decision-directed timing estimator exploits the symmetry properties of the signal

1. If the Early Sample = Late Sample : The peak occurs at the on-time sampling instant \(T\). No adjustment in the timing is needed.
2. If |Early Sample| > |Late Sample| : Late timing, the sampling time is offset so that the next symbol is sampled \(T-\delta/2\) seconds after the current sampling time.
3. If |Early Sample| < |Late Sample| : Early timing, the sampling time is offset so that the next symbol is sampled \(T+\delta/2\) seconds after the current sampling time.

David Johns. ECE1392H - Integrated Circuits for Digital Communications - Fall 2001: [Timing Recovery]

Dither in Quantized Zero Crossing Detection (QZCD) (so-called 'Bang Bang' Phase Detector)

Mueller and Muller Timing Synchronization

K. Mueller and M. Muller, "Timing Recovery in Digital Synchronous Data Receivers," in IEEE Transactions on Communications, vol. 24, no. 5, pp. 516-531, May 1976 [pdf]

Qasim Chaudhari. Mueller and Muller Timing Synchronization Algorithm [https://wirelesspi.com/mueller-and-muller-timing-synchronization-algorithm/]

Eduardo Fuentetaja. "Analysis of the M&M Clock Recovery Algorithm" [https://edfuentetaja.github.io/sdr/m_m_analysis/]

C.-P. Tzeng, D. Hodges and D. Messerschmitt, "Timing Recovery in Digital Subscriber Loops Using Baud-Rate Sampling," in IEEE Journal on Selected Areas in Communications, vol. 4, no. 8, pp. 1302-1311, November 1986 [pdf]

H. Meyr, M. Moeneclaey, and S. A. Fechtel. "Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing." Wiley [pdf]

T. Musah and A. Namachivayam, "Robust Timing Error Detection for Multilevel Baud-Rate CDR," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 10, pp. 3927-3939, Oct. 2022 [https://sci-hub.jp/10.1109/TCSI.2022.3191740]

Fulvio Spagna, CICC2018 Clock and Data Recovery Systems [pdf]

TODO 📅

Intersymbol Interference (ISI)

L.W. Couch, Digital and Analog Communication Systems, 8th Edition, Pearson, 2013. [pdf]

Nyquist discovered three different methods for pulse shaping that could be used to eliminate ISI

• Nyquist's First Method (Zero ISI): physically unrealizable (i.e., the impulse response would be noncausal and of infinite duration), inaccurate sync will cause ISI

  

• Nyquist's second method: allows some ISI to be introduced in a controlled way

• Nyquist's third method: area under the \(h_e(t)\) pulse within the desired symbol interval, \(T_s\), is not zero, but the areas under \(h_e(t)\) in adjacent symbol intervals are zero

Nyquist Criterion & Pulses

David A. Johns, ECE1392H - Integrated Circuits for Digital Communications - Fall 2001 [System Overview]

Matched-Filter (MF)

David A. Johns, ECE1392H - Integrated Circuits for Digital Communications - Fall 2001 [System Overview]

Noise Enhancement in Linear Equalizers

John M. Cioffi, Lecture 13, Thursday February 19th 2026 - Intersymbol Interference, MMSE, and SNR [https://cioffi-group.stanford.edu/ee379a/Lectures/L13.pdf]

—, Lecture 14, Tuesday February 24th 2026 - Linear Equalizers [https://cioffi-group.stanford.edu/ee379a/Lectures/L14.pdf]

Shannon–Hartley theorem

David A. Johns, ECE1392H - Integrated Circuits for Digital Communications - Fall 2001 [Introduction]

LMS & its Quantized-Error Algorithms

Bruno Lima, Adaptive filtering in Python Implementations based on Adaptive Filtering: Algorithms and Practical Implementation (Paulo S. R. Diniz). [https://github.com/BruninLima/PydaptiveFiltering]

\[\begin{align} x_k &= [x[k], x[k-1], \ldots, x[k-M]]^T \in \mathbb{C}^{M+1}\\ y[k] &= w^H[k] x_k, \qquad e[k] = d[k] - y[k], \end{align}\]

LMS algorithm

\[ w[k+1] = w[k] + \mu\, e^*[k] \, x_k. \]

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if w_init is not None:
    self.w: np.ndarray = np.asarray(w_init, dtype=self._dtype)
else:
    self.w = np.zeros(self.filter_order + 1, dtype=self._dtype)

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x: np.ndarray = np.asarray(input_signal, dtype=complex).ravel()
d: np.ndarray = np.asarray(desired_signal, dtype=complex).ravel()

n_samples: int = int(x.size)
m: int = int(self.filter_order)

outputs: np.ndarray = np.zeros(n_samples, dtype=complex)
errors: np.ndarray = np.zeros(n_samples, dtype=complex)

x_padded: np.ndarray = np.zeros(n_samples + m, dtype=complex)
x_padded[m:] = x

for k in range(n_samples):
    x_k: np.ndarray = x_padded[k : k + m + 1][::-1]

    y_k: complex = complex(np.vdot(self.w, x_k)) 
    outputs[k] = y_k

    e_k: complex = d[k] - y_k
    errors[k] = e_k

    self.w = self.w + self.step_size * np.conj(e_k) * x_k

Sign-Data Algorithm \[ w[k+1] = w[k] + 2\mu\, e^*[k] \, \operatorname{sign}(x_k) \]

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for k in range(n_samples):
    x_k = x_padded[k : k + m + 1][::-1]

    y_k = complex(np.vdot(self.w, x_k))
    outputs[k] = y_k

    e_k = d[k] - y_k
    errors[k] = e_k

    sign_xk = np.sign(x_k)

    self.w = self.w + (2.0 * self.step_size) * np.conj(e_k) * sign_xk

sign–sign algorithm

reference

Proakis, John G., and Masoud Salehi. Digital Communications. 5th ed. McGraw-Hill, 2008. [pdf]

Sklar, Bernard. Digital communications: fundamentals and applications. Pearson, 2021.

Ling, F. (2017). Synchronization in Digital Communication Systems. Cambridge: Cambridge University Press.

Barry, John R., Edward A. Lee, and David G. Messerschmitt. Digital communication. Springer, 2003.

Qasim Chaudhari, Wireless Communications From the Ground Up – An SDR Perspective

John M. Cioffi, [Chapter 3 - Equalization], [Chapter 6 - Fundamentals of Synchronization]

Sen M. Kuo. Real-Time Digital Signal Processing: Fundamentals, Implementations and Applications, 3rd Edition. John Wiley & Sons 2013

Stankovic, Ljubisa. (2015). Digital Signal Processing with Selected Topics.

Paulo S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, 5th edition [pdf], [matlab], [python]

B. Farhang-Boroujeny (2013), Adaptive Filters: Theory and Applications (2nd ed.). John Wiley & Sons, Inc.

Simon O. Haykin (2014), "Adaptive Filter Theory" Prentice-Hall, Inc. 5rd edition

A. Chan Carusone and D. A. Johns, "Analog Filter Adaptation Using a Dithered Linear Search Algorithm," IEEE Int. Symp. Circuits and Syst., May 2002. [PDF], [Slides]

—, Ph. D. Thesis, "Digital Algorithms for Analog Adaptive Filters", Feb. 2002. [http://www.eecg.utoronto.ca/~tcc/thesis.pdf]

—, "Analog Adaptive Filters," tutorial at the IEEE Int. Symp. Circuits and Syst., Bangkok, Thailand, May 2003. [http://www.eecg.utoronto.ca/~tcc/iscas03_tutorial.pdf]

—, 2022 Optimization Tools for Future Wireline Transceivers [https://www.ieeetoronto.ca/wp-content/uploads/2022/12/UofT-Future-of-Wireline-Workshop-2022.pdf]

David Johns, "Integrated Circuits for Digital Communications" [https://www.eecg.toronto.edu/~johns/nobots/courses/ece1392/slides.pdf]

Chris Li, mmse_dfe [https://github.com/ChrisZonghaoLi/mmse_dfe]

ScottXjw, equalizer-code-FFE-DFE-VolterraFFEandDFE [https://github.com/ScottXjw/equalizer-code-FFE-DFE-VolterraFFEandDFE]

Qasim Chaudhari. Maximum Likelihood Estimation of Clock Offset [https://wirelesspi.com/maximum-likelihood-estimation-of-clock-offset/]

—. Channel Estimation in Wireless Communication. [https://wirelesspi.com/channel-estimation-in-wireless-communication/]

—. Phase Locked Loop (PLL) in a Software Defined Radio (SDR) [https://wirelesspi.com/phase-locked-loop-pll-in-a-software-defined-radio-sdr/]

—. Phase Locked Loop (PLL) for Symbol Timing Recovery [https://wirelesspi.com/phase-locked-loop-pll-for-symbol-timing-recovery/]

—. How Decision Feedback Equalizers (DFE) Work [https://wirelesspi.com/how-decision-feedback-equalizers-dfe-work/]

—. Maximum Likelihood Sequence Estimation (MLSE Equalizer) [https://wirelesspi.com/maximum-likelihood-sequence-estimation-mlse-equalizer/]

—. Gardner Timing Error Detector: A Non-Data-Aided Version of Zero-Crossing Timing Error Detectors [https://wirelesspi.com/gardner-timing-error-detector-a-non-data-aided-version-of-zero-crossing-timing-error-detectors/]

—. Digital Filter and Square Timing Recovery [https://wirelesspi.com/digital-filter-and-square-timing-recovery/]

—. What is a Symbol Timing Offset and How It Distorts the Rx Signal [https://wirelesspi.com/what-is-a-symbol-timing-offset-and-how-it-distorts-the-rx-signal/]

—. How Excess Bandwidth Governs Timing Recovery in Digital Communication Systems [https://wirelesspi.com/how-excess-bandwidth-governs-timing-recovery-in-digital-communication-systems/]

—. How Automatic Gain Control (AGC) Works [https://wirelesspi.com/how-automatic-gain-control-agc-works/]

discrete-time frequency: \(\hat{\omega}=\omega T_s\), units are radians per sample

Below diagram show the windowing effect and sampling

For general window function, we know \(W(e^{j\hat{\omega}})=\frac{1}{T_s}W_c(j\frac{\hat\omega}{T_s})\),

\[ \frac{W_c(j\frac{\hat{\omega}}{T_s})X_c(j\frac{\hat{\omega}}{T_s})}{T_s}\cdot \frac{1}{2\pi} = \frac{T_sW(e^{j\hat{\omega}})X_c(j\frac{\hat\omega}{T_s})}{T_s}\cdot \frac{1}{2\pi}=W(e^{j\hat{\omega}})X_c(j\frac{\hat\omega}{T_s})\cdot \frac{1}{2\pi} \overset{\hat{\omega}=0}{\Longrightarrow} \sum_{n=-N_w}^{+N_w}w[n] \cdot X_c(j\omega)\cdot \frac{1}{2\pi} \]

e.g. \(\frac{W_c(j\omega|\omega=0)}{T_s} = N\) for Rectangular Window, shown in above figure

warmup

Continuous Time Fourier Series (CTFS)

\[\begin{align} a_k &= \frac{1}{T}\int_T x(t)e^{-jk(2\pi/T)) t}dt \\ x(t) &= \sum_{k=-\infty}^{+\infty}a_ke^{jk(2\pi/T) t} \end{align}\]

Continuous-Time Fourier transform (CTFT)

\[\begin{align} X(j\omega) &=\int_{-\infty}^{+\infty}x(t)e^{-j\omega t}dt \\ x(t)&= \frac{1}{2\pi}\int_{-\infty}^{+\infty}X(j\omega)e^{j\omega t}d\omega \end{align}\]

[https://www.rose-hulman.edu/class/ee/yoder/ece380/Handouts/Fourier%20Transform%20Tables%20w.pdf]

Discrete-Time Fourier Transform (DTFT)

\[\begin{align} X(e^{j\hat{\omega}}) &=\sum_{n=-\infty}^{+\infty}x[n]e^{-j\hat{\omega} n} \\ x[n] &= \frac{1}{2\pi}\int_{2\pi}X(e^{j\hat{\omega}})e^{j\hat{\omega} n}d\hat{\omega} \end{align}\]

DTFT is defined for infinitely long signals as well as finite-length signal

DTFT is continuous in the frequency domain

We could verify that is the correct inverse DTFT relation by substituting the definition of the DTFT and rearranging terms

Discrete-Time Fourier Series (DTFS)

TODO 📅

Discrete Fourier Series (DFS)

TODO 📅

Discrete Fourier Transform (DFT)

Two steps are needed to change the DTFT sum into a computable form:

1. the continuous frequency variable \(\hat{\omega}\) must be sampled
2. the limits on the DTFT sum must be finite

\[\begin{align} X[k] &= \sum_{n=0}^{N-1}x[n]e^{-j(2\pi/N)kn}\space\space\space k=0,1,...,N-1 \\ x[n] &= \frac{1}{N}\sum_{k=0}^{N-1}X[k]e^{j(2\pi/N)kn} \space\space\space n=0,1,...,N-1 \end{align}\]

Part of the proof is given by the following step:

DFT \(X[k]\) is a sampled version of the DTFT \(X(e^{j\hat{\omega}})\), where \(\hat{\omega_k} = \frac{2\pi k}{N}\)

impulse train

CTFT:

using time-sampling property

DTFT:

Given \(x[n]=\sum_{k=-\infty}^{\infty}\delta(n-k)\)

\[\begin{align} X(e^{j\hat{\omega}}) &= X_s(j\frac{\hat{\omega}}{T}) \\ &= \frac{2\pi}{T}\sum_{k=-\infty}^{\infty}\delta(\frac{\hat{\omega}}{T}-\frac{2\pi k}{T}) \\ &= \frac{2\pi}{T}\sum_{k=-\infty}^{\infty}T\delta(\hat{\omega}-2\pi k) \\ &= 2\pi\sum_{k=-\infty}^{\infty}\delta(\hat{\omega}-2\pi k) \end{align}\]

[http://courses.ece.ubc.ca/359/notes/notes_part1_set4.pdf]

Fourier series of impulse train

Dirac delta (impulse) function

[https://bingweb.binghamton.edu/~suzuki/Math-Physics/LN-7_Dirac_delta_function.pdf]

Topic 3 The \(\delta\)-function & convolution. Impulse response & Transfer function [https://www.robots.ox.ac.uk/~dwm/Courses/2TF_2011/2TF-N3.pdf]

impulse scaling

\[ \delta(\alpha t)= \frac{1}{\alpha}\delta( t) \]

where \(\alpha\) is scaling ratio

Multiplication

aka Modulation or Windowing Theorem

CTFT: \[ x_1(t)x_2(t)\overset{FT}{\longrightarrow}\frac{1}{2\pi}X_1(\omega)*X_2(\omega) \]

DTFT:

Duality

Conjugate Symmetry

Parseval's Relation

CTFT:

DTFT:

DFT:

[https://cioffi-group.stanford.edu/doc/book/chap3.pdf]

Eigenfunctions & frequency response

Complex exponentials are eigenfunctions of LTI systems, that is,

continuous time: \(e^{j\omega t}\to H(j\omega)e^{j\omega t}\)

discrete time: \(e^{j\hat{\omega}n} \to H(e^{j\hat{\omega}})e^{j\hat{\omega}n}\)

where \(H(j\omega)\), \(H(e^{j\hat{\omega}})\) is frequency response of continuous-time systems and discrete-time systems, which is the function of \(\omega\) and \(\hat{\omega}\) \[\begin{align} H(j\omega) &= \int_{-\infty}^{+\infty}h(t)e^{-j\omega t}dt \\ \\ H(e^{j\hat{\omega}}) &= \sum_{n=-\infty}^{+\infty}h[n]e^{-j\hat{\omega} n} \end{align}\]

The frequency response of discrete-time LTI systems is always a periodic function of the frequency variable \(\hat{\omega}\) with period \(2\pi\)

Sampling Theorem

time-sampling theorem: applies to bandlimited signals

spectral sampling theorem: applies to timelimited signals

Aliasing

Given below sequence \[ X[n] =A e^{j\omega T_s n} \]

1. \(kf_s + \Delta f\)

​ \[\begin{align} x[n] &= Ae^{j\left( kf_s+\Delta f \right)2\pi T_sn} + Ae^{j\left( -kf_s-\Delta f \right)2\pi T_sn} \\ &= Ae^{j\Delta f\cdot 2\pi T_sn} + Ae^{-j\Delta f\cdot 2\pi T_sn} \end{align}\]

2. \(kf_s - \Delta f\)

​ \[\begin{align} x[n] &= Ae^{j\left( kf_s-\Delta f \right)2\pi T_sn} + Ae^{j\left( -kf_s+\Delta f \right)2\pi T_sn} \\ &= Ae^{-j\Delta f\cdot 2\pi T_sn} + Ae^{j\Delta f\cdot 2\pi T_sn} \end{align}\]

complex signal

\[\begin{align} A e^{j(\omega_s + \Delta \omega) T_s n} &= A e^{j(k\omega_s + \Delta \omega) T_s n} \\ A e^{j(\omega_s - \Delta \omega) T_s n} &= A e^{j(k\omega_s - \Delta \omega) T_s n} \end{align}\]

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from itertools import product

def samplealiasing(fsig, fs=1):
    fdisp = None
    N = 0

    while True:
        for signN, signFsig in product([-1, 1], [-1, 1]):
            fdisp_n = signN*N*fs + signFsig*fsig
            if fdisp_n >= 0 and fdisp_n < fs/2:
                fdisp = fdisp_n
                print(f"{fsig:.4f} is indistinguishable from {fdisp:.4f}, which is {'+' if signN>0 else '-'}{N} {'+' if signFsig>0 else '-'} {fsig:.4f}")
                return fdisp
        N += 1
        if N > 100:
            break
    return None

for i in range(1,6):
    samplealiasing(0.3125*i)

# 0.3125 is indistinguishable from 0.3125, which is -0 + 0.3125
# 0.6250 is indistinguishable from 0.3750, which is +1 - 0.6250
# 0.9375 is indistinguishable from 0.0625, which is +1 - 0.9375
# 1.2500 is indistinguishable from 0.2500, which is -1 + 1.2500
# 1.5625 is indistinguishable from 0.4375, which is +2 - 1.5625

another method inspired by [https://github.com/bmurmann/MEAD2026/blob/main/tb_boot_bottom_4.ipynb]

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# inspired by https://github.com/bmurmann/MEAD2026/blob/main/tb_boot_bottom_4.ipynb

def samplealiasing(fsig, fs=1):
    fdisp = None
    fsig_wrap = fsig % fs
    if fsig_wrap > fs/2:
        fdisp = fs - fsig_wrap
    else:
        fdisp = fsig_wrap
    print(f"{fsig:.4f} is indistinguishable from {fdisp:.4f}")
    
    return fdisp

for i in range(1,6):
    samplealiasing(0.3125*i)


# 0.3125 is indistinguishable from 0.3125
# 0.6250 is indistinguishable from 0.3750
# 0.9375 is indistinguishable from 0.0625
# 1.2500 is indistinguishable from 0.2500
# 1.5625 is indistinguishable from 0.4375

CTFS & CTFT

Fourier transform of a periodic signal with Fourier series coefficients \(\{a_k\}\) can be interpreted as a train of impulses occurring at the harmonically related frequencies and for which the area of the impulse at the \(k\)th harmonic frequency \(k\omega_0\) is \(2\pi\) times the \(k\)th Fourier series coefficient \(a_k\)

inverse CTFT & inverse DTFT

inverse CTFT shall integral from \(-\infty\) to \(+\infty\) to obtain \(\delta(t)\) in time domain, e.g., \(x_s(t)\) impulse train

Half Wave Symmetry

ECEN 2633 Chapter 16: Fourier Series [http://www.jazapka.people.ysu.edu/ECEN%202633%20Chapter%2016.pdf]

[Google AI Mode]

Poisson summation formula

metroidman, fractional N量化噪声对系统相位噪声的影响 两种分析方法 LTI频域法和时域采样DFT法 [link]

• symmetric "samples ↔︎ samples" version
• periodization version

Let's prove the symmetric "samples ↔︎ samples" formula

spectral sampling

spectral sampling by \(\omega_0\), and \(\frac{2\pi}{\omega_0} \gt \tau\) \[ X_{n\omega_0}(\omega) = \sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega - n\omega_0) \] Periodic repetition of \(x(t)\) is \[ x_{n\omega_0}(t) = \frac{1}{\omega_0}\sum_{n=-\infty}^{\infty}x(t -n\frac{2\pi}{\omega_0})=\frac{T_0}{2\pi}\sum_{n=-\infty}^{\infty}x(t -nT_0) \]

Then, if \(x_{T_0} (t)\), a periodic signal formed by repeating \(x(t)\) every \(T_0\) seconds (\(T_0 \gt \tau\)​), its CTFT is \[ X_{T_0}(\omega) = \frac{2\pi}{T_0} \cdot X_{n\omega_0}(\omega) = \frac{2\pi}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)\delta(\omega - n\omega_0) \] Then \(x_{T_0} (t)\) can be expressed with inverse CTFT as \[\begin{align} x_{T_0} (t) &= \frac{1}{2\pi}\int_{-\infty}^{\infty}X_{T_0}(\omega)e^{j\omega t}d\omega \\ &= \frac{1}{T_0}\sum_{n=-\infty}^{\infty}X(n\omega_0)e^{jn\omega_0 t} =\sum_{n=-\infty}^{\infty}\frac{1}{T_0}X(n\omega_0)e^{jn\omega_0 t} \end{align}\]

i.e. the coefficients of the Fourier series for \(x_{T_0} (t)\) is \(D_n =\frac{1}{T_0}X(n\omega_0)\)

alternative method by direct Fourier series

Why DFT ?

We can use DFT to compute DTFT samples and CTFT samples

\[ \overline{x}(t) = \sum_{n=0}^{N_0-1}x(nT)\delta(t-nT) \] applying the Fourier transform yieds \[ \overline{X}(\omega) = \sum_{n=0}^{N_0-1}x[n]e^{-jn\omega T} \] But \(\overline{X}(\omega)\), the Fourier transform of \(\overline{x}(t)\) is \(X(\omega)/T\), assuming negligible aliasing. Hence, \[ X(\omega) = T\overline{X}(\omega) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn\omega T} \] and \[ X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\omega_0 T} \] with \(\hat{\omega}_0 = \omega_0 T\) \[ X(k\omega_0) = T\sum_{n=0}^{N_0-1}x[n]e^{-jn k\hat{\omega}_0} \] i.e. the relationship between CTFT and DFT is \(X(k\omega_0) = T\cdot X[k]\), DFT is a tool for computing the samples of CTFT

C/D

Sampling with a periodic impulse train, followed by conversion to a discrete-time sequence

The periodic impulse train is \[ s(t) = \sum_{n=-\infty}^{\infty}\delta(t-nT) \] \(x_s(t)\) can be expressed as \[ x_s(t) = \sum_{n=-\infty}^{\infty}x_c(nT)\delta(t-nT) \] i.e., the size (area) of the impulse at sample time \(nT\) is equal to the value of the continuous-time signal at that time.

\(x_s(t)\)​ is, in a sense, a continuous-time signal (specifically, an impulse train)

samples of \(x_c(t)\) are represented by finite numbers in \(x[n]\) rather than as the areas of impulses, as with \(x_s(t)\)

Frequency-Domain Representation of Sampling

The relationship between the Fourier transforms of the input and the output of the impulse train modulator \[ X_s(j\omega) = \frac{1}{T}\sum_{k=-\infty}^{\infty}X_c(j(\omega -k\omega_s)) \] where \(\omega_s\) is the sampling frequency in radians/s

\(X(e^{j\hat{\omega}})\), the discrete-time Fourier transform (DTFT) of the sequence \(x[n]\), in terms of \(X_s(j\omega)\) and \(X_c(j\omega)\)

\[ X(e^{j\omega T}) = \frac{1}{T}\sum_{k=-\infty}^{\infty}X_c(j(\omega-k\omega_s)) \] or equivalently, \[ X(e^{j\hat{\omega}}) = \frac{1}{T}\sum_{k=-\infty}^{\infty}X_c(j(\frac{\hat{\omega}}{T}-\frac{2\pi k}{T})) \]

\(X(e^{j\hat{\omega}})\) is a frequency-scaled version of \(X_s(j\omega)\) with the frequency scaling specified by \(\hat{\omega} =\omega T\)

Ref. 9.5 DTFT connection with the CTFT

Here, \(\Omega = \omega T\)

The factor \(\frac{1}{T}\) in \(X(e^{j\hat{\omega}})\) is misleading, actually \(x[n]\) is not scaled by \(\frac{1}{T}\) once taking \(\hat{\omega}\) variable of integration into account \[\begin{align} x_r[n] &= \frac{1}{2\pi} \int_{2\pi}X(e^{j\hat{\omega}})e^{j\hat{\omega} n}d\hat{\omega} \\ &= \frac{1}{2\pi}\int_{2\pi}\frac{1}{T}\sum_{k=-\infty}^{+\infty}X_c \left[ j\left(\frac{\hat{\omega}}{T} - \frac{2\pi k}{T}\right)\right] e^{j\hat{\omega} n}d\hat{\omega} \\ &\approx \frac{1}{2\pi}\frac{1}{T}\int_{2\pi}X_c (\frac{\hat{\omega}}{T} ) e^{j\hat{\omega} n} d\hat{\omega} \\ &=\frac{1}{2\pi} \frac{1}{T}\int_{2\pi} \left[ \int_{\infty}X_c(\Phi)\delta (\Phi - \frac{\hat{\omega}}{T} )d\Phi \right] e^{j\hat{\omega} n} d\hat{\omega} \\ &=\frac{1}{2\pi} \frac{1}{T} \int_{\infty}X_c(\Phi)d\Phi \int_{2\pi}\delta (\Phi - \frac{\hat{\omega}}{T} )e^{j\hat{\omega} n} d\hat{\omega} \\ &=\frac{1}{2\pi} \frac{1}{T} \int_{\infty}X_c(\Phi)d\Phi \int_{2\pi}T\cdot \delta (\Phi T - \hat{\omega} )e^{j\hat{\omega} n} d\hat{\omega} \\ &=\frac{1}{2\pi} \int_{\infty}X_c(\Phi) e^{j\Phi T n}d\Phi \end{align}\]

That is \[\begin{align} x_r[n] &= \frac{1}{2\pi}\int_{2\pi} \frac{1}{T}X_c (\frac{\hat{\omega}}{T} ) e^{j\hat{\omega} n} d\hat{\omega} \\ &= \frac{1}{2\pi} \int_{\infty}X_c(\omega) e^{j\omega T n}d\omega \tag{31} \end{align}\]

assuming Nyquist–Shannon sampling theorem is met

\[\begin{align} x_r[n] &= \frac{1}{2\pi} \int_{\infty}X_c(\omega) e^{j\omega T n}d\omega \\ &= \frac{1}{2\pi} \int_{\infty}X_c(\omega) e^{j\omega t_n}d\omega \\ &= x_c(t_n) \end{align}\]

where \(t_n = T n\), then \(x_r[n] = x_c(nT)\)

Assuming \(x_c(t) = \cos(\omega_0 t)\), \(x_s(t)= \sum_{n=-\infty}^{\infty}x_c(nT)\delta(t-nT)\) and \(x[n]=x_c(nT)\), that is \[\begin{align} x_c(t) & = \cos(\omega_0 t) \\ x_s(t) &= \sum_{n=-\infty}^{\infty}\cos(\omega_0 nT)\delta(t-nT) \\ x[n] &= \cos(\omega_0 nT) \end{align}\]

• \(X_c(j\omega)\), the Fourier Transform of \(x_c(t)\) \[ X_c(j\omega) = \pi[\delta(\omega - \omega_0) + \delta(\omega + \omega_0)] \]

• \(X(e^{j\hat{\omega}})\), the the discrete-time Fourier transform (DTFT) of the sequence \(x[n]\) \[ X(e^{j\hat{\omega}}) =\sum_{k=-\infty}^{+\infty}\pi[\delta(\hat{\omega} - \hat{\omega}_0-2\pi k) + \delta(\hat{\omega} + \hat{\omega}_0-2\pi k)] \]

• \(X_s(j\omega)\), the Fourier Transform of \(x_s(t)\) \[ X_s(j\omega)= \frac{1}{T}\sum_{k=-\infty}^{+\infty}\pi[\delta(\omega - \omega_0-k\omega_s) + \delta(\omega + \omega_0-k\omega_s)] \]

Express \(X(e^{j\hat{\omega}})\) in terms of \(X_s(j\omega)\) and \(X_c(j\omega)\) \[ X(e^{j\hat{\omega}}) = \frac{1}{T}\sum_{k=-\infty}^{+\infty}\pi[\delta(\frac{\hat{\omega}}{T} - \omega_0-k\omega_s) + \delta(\frac{\hat{\omega}}{T} + \omega_0-k\omega_s)] \] Inverse \(X(e^{j\hat{\omega}})\) \[\begin{align} x_r[n] &= \frac{1}{2\pi} \int_{2\pi}X(e^{j\hat{\omega}}) e^{j\hat{\omega} n} d\hat{\omega} \\ &= \frac{1}{2\pi}\int_{2\pi} \pi[\delta(\frac{\hat{\omega}}{T} - \omega_0) + \delta(\frac{\hat{\omega}}{T} + \omega_0)]e^{j\hat{\omega} n} d\frac{\hat{\omega}}{T} \\ &= \frac{1}{2\pi}\int_{2\pi} \pi[\delta(\frac{\hat{\omega}}{T} - \omega_0)e^{j\hat{\omega}_0 n} + \delta(\frac{\hat{\omega}}{T} + \omega_0)e^{-j\hat{\omega}_0 n}] d\frac{\hat{\omega}}{T} \\ &= \frac{1}{2}[ e^{j\hat{\omega}_0 n}\int_{2\pi} [\delta(\frac{\hat{\omega}}{T} - \omega_0)d\frac{\hat{\omega}}{T} + e^{-j\hat{\omega}_0 n}\int_{2\pi} [\delta(\frac{\hat{\omega}}{T} + \omega_0)d\frac{\hat{\omega}}{T}] \\ &= \frac{1}{2}[ e^{j\hat{\omega}_0 n} + e^{-j\hat{\omega}_0 n} ] \\ &= \cos(\hat{\omega}_0 n) \end{align}\]

or follow EQ.(31)

\[\begin{align} x_r[n] &= \frac{1}{2\pi} \int_{\infty}X_c(\omega) e^{j\omega T n}d\omega \\ &= \frac{1}{2\pi} \int_{\infty} \pi[\delta(\omega - \omega_0) + \delta(\omega + \omega_0)]e^{j\omega T n}d\omega \\ &= \frac{1}{2}(e^{j\omega_0 T n}+e^{-j\omega_0 T n}) \\ &= \cos(\hat{\omega}_0 n) \end{align}\]

where \(\hat{\omega}_0 = \omega_0 T\)

impulse train sampling & impulse sequence

if \(x_c(t) = e^{j\Omega_0t}\), thus \(X_c (j\Omega) = A\delta(\Omega - \Omega_0)\)

Then \[ X_s (j\Omega) = \frac{A}{T_s}\sum_k \delta(\Omega -\Omega_0 - k\Omega_s) \]

DTFT of \(x[n]\) \[\begin{align} X(e^{j\omega}) &= \frac{1}{T_s} \sum_k X_c\left[j(\frac{\omega}{T_s}-\frac{2\pi k}{T_s})\right] \\ &= \frac{A}{T_s} \sum_k \delta(\frac{\omega}{T_s} -\Omega_0- \frac{2\pi k}{T_s}) \\ &= A \sum_k \delta(\omega -\omega_0 - 2\pi k) \end{align}\]

yield \[ x[n] = A e^{j\omega_0 n} = A e^{j\Omega_0 nT_s} \]

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import numpy as np
x = np.linspace(0,1,10000)
y = np.cos(2*np.pi*1*x)
rms = np.sqrt(np.power(y, 2).sum()/x.size)
print(rms)
print(1/2**0.5)

# 0.7071421356417675
# 0.7071067811865475

Example 4.1 impulse scaling \(\delta(\omega/T)=T\delta(\omega)\)

\[ \int \delta(\frac{\omega}{T})d\omega = \int T \delta(\omega)d\omega = \int T\delta(\frac{\omega}{T})d\frac{\omega}{T} = T \]

D/C

Zero Padding

Balu Santhanam. ECE-539: Digital Signal Processing: Zero padding and Resolution [http://ece-research.unm.edu/bsanthan/ece539/zero_pad.pdf]

David Castro PiñolDavid Castro Piñol. 𝗭𝗲𝗿𝗼 𝗣𝗮𝗱𝗱𝗶𝗻𝗴 𝗗𝗼𝗲𝘀𝗻’𝘁 𝗜𝗺𝗽𝗿𝗼𝘃𝗲 𝗦𝗽𝗲𝗰𝘁𝗿𝗮𝗹 𝗥𝗲𝘀𝗼𝗹𝘂𝘁𝗶𝗼𝗻 [link]

Zero padding improves frequency grid resolution, not spectral resolution

A smoother spectrum is not more information — it is better interpolation of the same information.

To truly improve spectral resolution, you must observe the signal longer (increase N).

Gotcha

A remarkable fact of linear systems is that the complex exponentials are eigenfunctions of a linear system, as the system output to these inputs equals the input multiplied by a constant factor.

• Both amplitude and phase may change
• but the frequency does not change

For an input \(x(t)\), we can determine the output through the use of the convolution integral, so that with \(x(t) = e^{st}\) \[\begin{align} y(t) &= \int_{-\infty}^{+\infty}h(\tau)x(t-\tau)d\tau \\ &= \int_{-\infty}^{+\infty} h(\tau) e^{s(t-\tau)}d\tau \\ &= e^{st}\int_{-\infty}^{+\infty} h(\tau) e^{-s\tau}d\tau \\ &= e^{st}H(s) \end{align}\]

Take the input signal to be a complex exponential of the form \(x(t)=Ae^{j\phi}e^{j\omega t}\)

\[\begin{align} y(t) &= h(t)*x(t) \\ &= H(j\omega)Ae^{j\phi}e^{j\omega t} \end{align}\]

The frequency response at \(-\omega\) is the complex conjugate of the frequency response at \(+\omega\), given \(h(t)\) is real

\[\begin{align} H^*(t) &= \left(\int_{-\infty}^{+\infty}h(t)e^{-j\omega t}dt\right)^* \\ &= \int_{-\infty}^{+\infty}h^*(t)e^{+j\omega t}dt \\ &= \int_{-\infty}^{+\infty}h(t)e^{-j(-\omega t)}dt \\ &= H(-j\omega) \end{align}\]

The real cosine signal is actually composed of two complex exponential signals: one with positive frequency and the other with negative \[ cos(\omega t + \phi) = \frac{e^{j(\omega t + \phi)} + e^{-j(\omega t + \phi)}}{2} \]

The sinusoidal response is the sum of the complex-exponential response at the positive frequency \(\omega\) and the response at the corresponding negative frequency \(-\omega\) because of LTI systems's superposition property

• input: \[\begin{align} x(t) &= A cos(\omega t + \phi) \\ &= \frac{1}{2}Ae^{\phi}e^{\omega t} + \frac{1}{2}Ae^{-\phi}e^{-\omega t} \end{align}\]

• output with \(H(j\omega)=Ge^{j\theta}\): \[\begin{align} y(t) &= H(j\omega)\frac{1}{2}Ae^{\phi}e^{\omega t} + H(-j\omega)\frac{1}{2}Ae^{-\phi}e^{-\omega t} \\ &= Ge^{j\theta}\frac{1}{2}Ae^{\phi}e^{\omega t} + Ge^{-j\theta}\frac{1}{2}Ae^{-\phi}e^{-\omega t} \\ &= GAcos(\omega t + \phi + \theta) \end{align}\]

Its phase shift is \(\theta\) and gain is \(G\), which is same with \(H(j\omega)\).

reference

Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing, 3rd edition [pdf]

B.P. Lathi, Roger Green. Linear Systems and Signals (The Oxford Series in Electrical and Computer Engineering) 3rd Edition [pdf]

Alan V. Oppenheim, Alan S. Willsky, and S. Hamid Nawab. 1996. Signals & systems (2nd ed.) [pdf]

James H. McClellan, Ronald Schafer, and Mark Yoder. 2015. DSP First (2nd. ed.). Prentice Hall Press, USA

Reference Ripple

C-H Chan (U. of Macau) "Extreme SAR ADCs - Exploring New Frontiers" Online Course (2024) : Reference Buffer in SAR ADC [https://youtu.be/vj98B7AaC9E]

C. Li, C. -H. Chan, Y. Zhu and R. P. Martins, "Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 82-93, Jan. 2019 [https://ime.um.edu.mo/wp-content/uploads/magazines/961546494e705f6fd16b9f785a121030.pdf]

J. Zhong, Y. Zhu, S. -W. Sin, S. -P. U and R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 9, pp. 2196-2206, Sept. 2015 [https://sci-hub.st/10.1109/TCSI.2015.2452331]

C. -H. Chan et al., "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2576-2588, Oct. 2017 [https://ime.um.edu.mo/wp-content/uploads/magazines/407e580ac0218605bcf9b9bbd0ea1109.pdf]

TODO 📅

Sampling Front-End (SFE) Pulse Response

sweep the setup time between ideal pulse input and clock, sample the output of SFE at falling edge

sample-by-sample

3rd harmonic

bit-by-bit

The amplitude of the reference ripple is code-dependent as it is correlated with switching energy in each bit cycling

Redundancy

decision level

final digital output for an \(N\)-bit \(M\)-step ADC can be calculated \[ D_{out} = s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0] -1)\cdot s(1) \]

track the decision level

For \(N\)-bit binary weighted algorithm,\(N=M\) and \(s(i)=2^{i-1}\), where \(i\in \{N, N-1,...,2,1 \}\)

\[\begin{align} D_{out} &= s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0] -1) \\ &= 2^{N-1} + \sum_{i=1}^{N-1}2^i\cdot b[i] - \sum_{i=0}^{N-2}2^{i} + (b[0] -1) \\ &= \sum_{i=0}^{N-1} b[i] \cdot 2^i \end{align}\]

alternative method for d2a & CDAC equivalent weight

\[\begin{align} D_{out} &= \sum_{i=1}^{M-1}(2b_i -1)w_{i-1} + (b_0-1)w_0 \\ &= \sum_{i=1}^{M-1}b_i\cdot 2w_{i-1} + b_0\cdot w_0 -\sum_{i=1}^{M-1}w_{i-1} -w_0 \\ &= \left[\sum_{i=1}^{M-1}b_i\cdot 2w_{i-1} + b_0\cdot w_0\right] - \frac{1}{2}\left[\sum_{i=1}^{M-1}2w_{i-1} +w_0 + w_0\right] \\ &= \sum_{i=0}^{M-1}b_i\cdot W_i - \frac{1}{2}\left[\sum_{i=0}^{M-1}W_i + W_0\right] \end{align}\]

where \(W_i = 2w_{i-1}\) for \(i\in [M-1,1]\) and \(W_0 = w_0\)

Error Tolerance Window

\[ \varepsilon_t(n) = \sum_{i=1}^{n-2} s(i) - s(n-1) \]

where \(n\in [1, N]\), and \(N\)-bit SAR

For the \(n\)th output bit, once a decision is made, the next decision level will either move up or down by the step size of \(s(n − 1)\)

If this decision is erroneous, then the sum of the follow-on step sizes, \(s(n − 2)\), \(s(n − 3)\), ..., \(s(1)\), must be large enough and exceed the value of the current step size to counteract this mistake

The exceeded amount is the tolerance window for that decision level

sub-binary search

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import numpy as np
import matplotlib.pyplot as plt


def sar(xi, ss):
    M = ss.size
    th = ss[0]
    oob = []
    for i in range(M):
        ocur = 1 if xi >= th else 0
        oob.append(ocur)
        if i + 1 < M:
            th += (2 * ocur - 1) * ss[i + 1]
        else:
            break

    binstr = ''.join([str(s) for s in oob])
    decval = int(binstr, 2)
    return binstr, decval


def sar_plot(ss, Npts=10000):
    ss = np.asarray(ss)
    ssum = np.sum(ss)
    xilist = np.linspace(0, ssum + 1, Npts)
    outlist = []
    for i in range(Npts):
        _, decval = sar(xilist[i], ss)
        outlist.append(decval)
    outmax = np.max(outlist)
    plt.figure(figsize=(16,8))
    plt.plot(xilist, outlist, '-', linewidth=4)
    plt.xticks(range(0, ssum + 2))
    plt.yticks(range(0, outmax + 2, 2))
    plt.title('search step: {}'.format(ss), fontsize=20)
    plt.xlabel('analog out', fontsize=20); plt.ylabel('digital out', fontsize=20)

    plt.grid(True)

ss = [8, 4, 2, 1]
sar_plot(ss)

ss = [8, 2, 2, 2, 1]
sar_plot(ss)

plt.show()

ENOB vs. fixed radix

When the ADC is designed with a fixed radix, \(\alpha\) and the required number of conversion steps, \(M\)

the sum of all the step sizes \(s_{tot}\) \[ s_{tot} = \sum_{k=0}^{M-1} s_0 \alpha^k = s_0\frac{\alpha^M-1}{\alpha-1} \]

where \(s(i)\) is step size and \(i \in [0, 1, 2, M-1]\)

The effective number of bits, \(N\), can be calculated \[ N \leq \log 2\left(\frac{s_{tot} + s_0}{s_0}\right) = \frac{\alpha^M+\alpha-2}{\alpha-1} \]

Speed Benefit

TODO 📅

MSB with noise simualtion

SAR ADC Noise Analysis

kT/C Noise in sampling

DAC Noise in conversion

T. Miki et al., "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015 [https://sci-hub.jp/10.1109/JSSC.2015.2417803]

Comparator Noise in conversion

noise analysis for dynamic integrator

noise analysis for latch phase

P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008

CDAC

The charge redistribution capacitor network is used to sample the input signal and serves as a digital-to-analog converter (DAC) for creating and subtracting reference voltages

sampling charge \[ Q = V_{in} C_{tot} \] conversion charge \[ Q = -C_{tot}V_c + V_{ref}C_\Delta \] That is \[ V_c = \frac{C_\Delta}{C_{tot}}V_{ref} - V_{in} \]

CDAC is actually working as a capacitive divider during conversion phase, the charge of internal node retain (charge conservation law)

assuming \(\Delta V_i\) is applied to series capacitor \(C_1\) and \(C_2\)

\[ (\Delta V_i - \Delta V_x) C_1 = \Delta V_x \cdot C_2 \] Then \[ \Delta V_x = \frac{C_1}{C_1+C_2}\Delta V_i \]

\(V_x= V_{x,0} + \Delta V_x\)

CDAC settling accuracy

\[\begin{align} V_x(s) &= \frac{C_1+C_2}{RC_1C_2}\cdot \frac{1}{s+\frac{C_1+C_2}{RC_1C_2}}\cdot V_i(s) \\ &= \frac{1}{\tau}\cdot \frac{1}{s+\frac{1}{\tau}}\cdot \frac{1}{s}\\ &= \frac{1}{\tau}\cdot \tau(\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}})=\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}} \end{align}\]

inverse Laplace Transform is \(V_x(t) = 1 - e^{-t/\tau}\)

\[\begin{align} V_y(s) &= V_x\frac{C_1}{C_1+C_2} \\ &= \frac{C_1}{C_1+C_2} \left(\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}}\right)\\ \end{align}\]

inverse Laplace Transform is \(V_y(t) = \frac{C_1}{C_1+C_2}\left(1 - e^{-t/\tau}\right)\)

\(V_x(t)\) and \(V_y(t)\) prove that the settling time is same

\(\tau = R\frac{C_1C_2}{C_1+C_2}\), which means usually worst for MSB capacitor (largest)

both \(\tau\) and \(\Delta V\) are the maximum

A popular way to improve the settling behavior, again, is to employ unit-element DACs that statistically reduce the switching activities, which, unfortunately, exhibits unnecessary complications to the power, area and speed tradeoffs of the design

CDAC Energy Consumption

\[ E_{Vref} = \int P(t)dt = \int V_{ref} I(t) dt = V_{ref}\int I(t)dt = V_{ref}\cdot \Delta Q \]

Given \(V_{c,0}=\frac{1}{2}V_{ref}-V_{in}\) and \(V_{c,1}=\frac{3}{4}V_{ref}-V_{in}\) \[\begin{align} Q_{b0,0} &= \left(V_{ref} - V_{c,0} \right)\cdot 2C = \left(\frac{1}{2}V_{ref}+V_{in} \right)\cdot 2C \\ Q_{b1,0} &= (0 - V_{c,0})\cdot C = \left(-\frac{1}{2}V_{ref}+V_{in} \right)\cdot C \\ Q_{b0,1} &= \left(V_{ref} - V_{c,1} \right)\cdot 2C = \left(\frac{1}{4}V_{ref}+V_{in} \right)\cdot 2C \\ Q_{b1,1} &= \left(V_{ref} - V_{c,1} \right)\cdot C = \left(\frac{1}{4}V_{ref}+V_{in} \right)\cdot C \end{align}\]

Therefore \[ E_{Vref} = V_{ref}\cdot (Q_{b0,1}+Q_{b1,1} - Q_{b0,0}-Q_{b1,0}) = \frac{1}{4}C V_{ref}^2 \]

CDAC total energy change \[\begin{align} \Delta E_{tot} &= \frac{1}{2}\cdot 2C \cdot (U_{2c,1}^2 - U_{2c,0}^2) + \frac{1}{2}\cdot C \cdot (U_{c,1}^2 - U_{c,0}^2) + \frac{1}{2}\cdot C \cdot (U_{c1,1}^2 - U_{c1,0}^2) \\ &= \left(-\frac{3}{16}V_{ref}^2 - \frac{1}{2}V_{ref}V_{in} - \frac{3}{32}V_{ref}^2+\frac{3}{4}V_{ref}V_{vin} + \frac{5}{32}V_{ref}^2-\frac{1}{4}V_{ref}V_{in}\right)C \\ &= -\frac{1}{8}CV_{ref}^2 \end{align}\]

alternative method

\[ \Delta E_{tot} = \frac{1}{2}\cdot\frac{3}{4}C\cdot V_{ref}^2 - \frac{1}{2}\cdot C\cdot V_{ref}^2 = -\frac{1}{8}CV_{ref}^2 \]

The total energy decreases by \(-\frac{1}{8}CV_{ref}^2\), though \(V_{ref}\) provides \(\frac{1}{4}C V_{ref}^2\)

The charge redistribution change the CDAC energy

\[ E_{c,0} = \frac{1}{2}CV^2 \] After charge redistribution \[ E_{c,1} = \frac{1}{2}\cdot 2C\cdot \left(\frac{1}{2}V\right)^2 = \frac{1}{4}CV^2 \]

That make sense, charge redistribution consume energy

CDAC structure

CDAC with constant common-mode voltage

Comparator

Comparator input cap effect

\[ -V_{in}\cdot 2^N C = V_c (2^N C + C_p) \] Then \(V_c = -\frac{2^N C}{2^N C + C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude by the factor

During conversion \[\begin{align} V_c &= -\frac{2^N C}{2^N C + C_p}V_{in} +V_{ref}\sum_{n=0}^{N-1} \frac{b_n\cdot2^n C}{2^N C + C_p} \\ &= \frac{2^N C}{2^N C + C_p}\left(-V_{in} + V_{ref}\sum_{n=0}^{N-1}\frac{b_n }{2^{N-n}} \right) \end{align}\]

That is, it does not change the sign

Comparator offset effect

Synchronous SAR ADC

It also divides a full conversion into several comparison stages in a way similar to the pipeline ADC, except the algorithm is executed sequentially rather than in parallel as in the pipeline case.

However, the sequential operation of the SA algorithm has traditionally been a limitation in achieving high-speed operation

• a clock running at least \((N + 1) \cdot F_s\) is required for an \(N\)-bit converter with conversion rate of \(F_s\)
• every clock cycle has to tolerate the worst case comparison time
• every clock cycle requires margin for the clock jitter

The power and speed limitations of a synchronous SA design comes largely from the high-speed internal clock

Split Arrary CDAC

Split capacitor, double-array cap

attenuation capacitance \(C_a\)

\[\begin{align} \Delta V_{dac} &= \frac{1}{2}b_3+\frac{1}{4}b_2+\frac{1}{4}\left(\frac{1}{2}b_1+\frac{1}{4}b_0 \right) \\ &= \frac{1}{2}b_3+\frac{1}{4}b_2 + \frac{1}{8}b_1+\frac{1}{16}b_0 \end{align}\]

Asynchronous SAR ADC

The comparator itself trigger the next bit-conversion cycle as soon as the present bit decision has been taken

The maximum resolving time reduction between synchronous and asynchronous case is two fold