KNOW-HOW

PAM-4 Pattern Generation

Keysight Technologies PAM-4 Design Challenges and the Implications on Test [pdf]

PRQS (Pseudo Random Quaternary Sequence)

Ilya Lyubomirsky, Finisar. PRQS Test Patterns for PAM4 [https://www.ieee802.org/3/bs/public/15_09/lyubomirsky_3bs_01_0915.pdf]

TODO 📅

Unipolar & Bipolar Non-Return-to-Zero (NRZ)

Mathuranathan, Line code – demonstration in Matlab and Python [link]

• For unipolar NRZ line coded signal, the average value of the signal is not zero and hence they have a significant DC component

  The DC impulses in the PSD do not carry any information and it also causes the transmission wires to heat up. This is a wastage of communication resource

• The bipolar NRZ signal is devoid of a significant impulse at the zero frequency (DC component is very close to zero)

  Furthermore, it has more power than the unipolar line code (note: PSD curve for bipolar NRZ is slightly higher compared to that of unipolar NRZ). Therefore, bipolar NRZ signals provide better signal-to-noise ratio (SNR) at the receiver.

Both Unipolar and Bipolar NRZ signal lacks embedded clock information, which posses synchronization problems at the receiver when the binary information has long runs of 0s and 1s

Baseline Wander

David A. Johns, ECE1392H - Integrated Circuits for Digital Communications - Fall 2001 [Equalization]

Pete Anslow, Ciena. Baseline wander with FEC [https://www.ieee802.org/3/bs/public/17_05/anslow_3bs_03_0517.pdf]

Vladimir Dmitriev-Zdorov. Baseline Wander, its Time Domain and Statistical Analysis [https://ibis.org/summits/feb19/dmitriev-zdorov.pdf]

Pavel Zivny, Tektronix. Baseline Wander: Systematic Approach to Rapid Simulation and Measurement [pdf]

Update on Performance Studies of 100 Gigabit Ethernet Enabled by Advanced Modulation Formats [https://www.ieee802.org/3/bm/public/sep12/wei_01_0912_optx.pdf]

Bandwidth of Digital Waveforms

NRZ Bandwidth

Maxim Integrated,NRZ Bandwidth - HF Cutoff vs. SNR [https://pdfserv.maximintegrated.com/en/an/AN870.pdf]

\(0.35/T_r\)

32 to 56 Gbps Serial Link Analysis and Optimization Methods for Pathological Channels [https://docs.keysight.com/eesofapps/files/678068240/678068273/1/1629077956000/tutorial-32-to-56-gbps-serial-link-analysis-optimization-methods-pathological-channels.pdf]

Rise Time Sine Wave \[\begin{align} \sin 2\pi f t_{20} &= -1+2\times 0.2 = -0.6 \\ \sin 2\pi f t_{80} &= -1+2\times 0.8 = 0.6 \end{align}\] \[ f = \frac{\arcsin(0.6) - \arcsin(-0.6)}{2\pi (t_{80} - t_{20})} = \frac{0.2}{T_r} \]

Step Response RC Tank

\[\begin{align} 0.8 &= 1- e^{-\frac{t_{80}}{\tau_{RC}}} \to t_{80} = -\ln0.2 \cdot \tau_{RC} \\ 0.2 &= 1- e^{-\frac{t_{80}}{\tau_{RC}}} \to t_{20} = -\ln0.8 \cdot \tau_{RC} \end{align}\]

Then rise time of 20% to 80% is \[ T_{r} = \tau_{RC}\cdot \ln\frac{0.8}{0.2} = 1.3863 \cdot \tau_{RC} \] we have \[ f_{3dB} = \frac{1}{2\pi}\frac{1}{\tau_{RC}} = \frac{1}{2\pi}\frac{ 1.3863}{T_r} = \frac{0.22}{T_r} \]

Measurements Bandwidth

Minh Quach. 4/30/2004 Signal Integrity Consideration and Analysis -Frequency & Time Domain Measurements/Analysis [https://ewh.ieee.org/r5/denver/sscs/Presentations/2004_04_Quach.pdf]

CMI & DMI

Ahmed Sada Staff Silicon Validation Engineer, Synopsys. Don't Be Intimidated: Manual Calibration for Stressed Eye Testing

Patrick Kennedy, Impact of Noise Coupler on 128 GT/s Rx Calibration and DUT Testing

Anritsu White paper: PCIe® 6.0: Testing for a New Generation [link]

Chung-Chun Chen (CC) 陳俊中, Why PCIe Adds a 2.1 GHz Interference Tone? [https://youtu.be/8qN2-QVUJRs]

sinusoidal differential mode interference (DMI), and common mode interference (CMI)

Mike Dudek Marvell, Differential-mode to Common-mode and Common-mode to Differential-mode reflection specifications [https://www.ieee802.org/3/dj/public/25_07/dudek_3dj_01_2507.pdf]

Ali Ghiasi Ghiasi Quantum LLC, Differential, Conversion, and Common Mode Return Losses [https://www.ieee802.org/3/ck/public/20_07/ghiasi_3ck_03a_0720.pdf]

TODO 📅

Single-Ended & Differential Signaling

[https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/handouts/markChapt.pdf]

[https://www.allaboutcircuits.com/technical-articles/the-why-and-how-of-differential-signaling/]

Since we have (ideally) no return current, the ground reference becomes less important. The ground potential can even be different at the sender and receiver or moving around within a certain acceptable range. However, you need to be careful because DC-coupled differential signaling (such as USB, RS-485, CAN) generally requires a shared ground potential to ensure that the signals stay within the interface's maximum and minimum allowable common-mode voltage.

Low-Latency PCIe

TODO 📅

AC-coupling vs DC-coupling

TODO 📅

PAM4

Eye-Diagram and Bit-Error-Ratio (BER)

Noman Hai, Synopsys. CICC 2025 Circuit Insights: Basics of Wireline Transmitter Circuits [https://youtu.be/oofViBGlrjM]

JTOL btw DSP-based vs Analog PAM4 RX

CC Chen, Why Analog PAM4 Receiver? [https://youtu.be/J2ojSMYiuBs]

DSP-Based SerDes

Tony Chan Carusone, Alphawave Semi. VLSI2025 SC2: Connectivity Technologies to Accelerate AI

Jitter Performance Limitations

Aliasing of baud-rate sampling

The most significant impairments are considered to be the sensitivity to sampling phase, and the effect of aliasing out of band signal and noise into the baseband

Tao Gui (Huawei), etc.. IEEE 802.3dj May Interim meeting San Antonio, Texas May 15, 2013: "Feasibility Study on Baud-Rate Sampling and Equalization (BRSE) for 800G-LR1" [https://www.ieee802.org/3/dj/public/23_05/gui_3dj_01a_2305.pdf]

D. S. Millar, D. Lavery, R. Maher, B. C. Thomsen, P. Bayvel and S. J. Savory, "A baud-rate sampled coherent transceiver with digital pulse shaping and interpolation,"in OFC 2013 [https://www.merl.com/publications/docs/TR2013-010.pdf]

Tahmoureszadeh, Tina. Master's Theses (2009 - ): Analog Front-end Design for 2x Blind ADC-based Receivers [http://hdl.handle.net/1807/29988]

Shafik, Ayman Osama Amin Mohamed. "Equalization Architectures for High Speed ADC-Based Serial I/O Receivers." PhD diss., 2016. [https://core.ac.uk/download/79652690.pdf]

ISI & DDJ filtering

Modulation and SNR

Data and noise mutually uncorrelated

\[ x_{RX,n}[p] = d[p]h_{RX}[0] +\sum \text{ISI} + n[p] \]

"ISI cancellation" based equalization is conceptually more straightforward but suffers from SNR penalty or error propagation

Jitter Amplification by Passive Channels

Enhancing Resolution with a \(\Delta \Sigma\) Modulator

Sub-Resolution Time Averaging

\(\Delta \Sigma\) modulator effectively dithers the LSB bit between zero and one, such that you can get the effective resolution of a much higher resolution DAC in the number of bits

Decimation

how they affect sampling phase

DLF's input bit-width can be reduced by decimating BBPD's output. Decimation is typically performed by realizing either majority voting (MV) or boxcar filtering.

Note that deserialization is inherent to both MV and boxcar filtering

• Decimation is commonly employed to alleviate the high-speed requirement. However, decimation increases loop-latency which causes excessive dither jitter.
• Decimation is basically, widen the data and slowing it down
• Decimating by \(L\) means frequency register only added once every \(L\) UI, thus integral path gain reduced by \(L\) in linear model
• proportional path gain is unchanged

CDR Linear Model

condition:

Linear model of the CDR is used in a frequency lock condition and is approaching to achieve phase lock

Using this model, the power spectral density (PSD) of jitter in the recovered clock \(S_{out}(f)\) is \[ S_{out}(f)=|H_T(f)|^2S_{in}(f)+|H_G(f)|^2S_{VCO}(f) \] Here, we assume \(\varphi_{in}\) and \(\varphi_{VCO}\) are uncorrelated as they come from independent sources.

Jitter Transfer Function (JTF)

\[ H_T(s) = \frac{\varphi_{out}(s)}{\varphi_{in}(s)}|_{\varphi_{vco}=0}=\frac{K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}}{s^2+K_{PD}K_{VCO}R_s+\frac{K_{PD}K_{VCO}}{C}} \]

Using below notation \[\begin{align} \omega_n^2=\frac{K_{PD}K_{VCO}}{C} \\ \xi=\frac{K_{PD}K_{VCO}}{2\omega_n^2} \end{align}\]

We can rewrite transfer function as follows \[ H_T(s)=\frac{2\xi\omega_n s+\omega_n^2}{s^2+2\xi \omega_n s+\omega_n^2} \]

The jitter transfer represents a low-pass filter whose magnitude is around 1 (0 dB) for low jitter frequencies and drops at 20 dB/decade for frequencies above \(\omega_n\)

• the recovered clock track the low-frequency jitter of the input data
• the recovered clock DONT track the high-frequency jitter of the input data

The recovered clock does not suffer from high-frequency jitter even though the input signal may contain high-frequency jitter, which will limit the CDR tolerance to high-frequency jitter.

Jitter Peaking in Jitter Transfer Function

The peak, slightly larger than 1 (0dB) implies that jitter will be amplified at some frequencies in the CDR, producing a jitter amplitude in the recovered clock, and thus also in the recovered data, that is slightly larger than the jitter amplitude in the input data.

This is certainly undesirable, especially in applications such as repeaters.

Jitter Generation

If the input data to the CDR is clean with no jitter, i.e., \(\varphi_{in}=0\), the jitter of the recovered clock comes directly from the VCO jitter. The transfer function that relates the VCO jitter to the recovered clock jitter is known as jitter generation. \[ H_G(s)=\frac{\varphi_{out}}{\varphi_{VCO}}|_{\varphi_{in}=0}=\frac{s^2}{s^2+2\xi \omega_n s+\omega_n^2} \] Jitter generation is high-pass filter with two zeros, at zero frequency, and two poles identical to those of the jitter transfer function

Jitter Tolerance (JTOL)

To quantify jitter tolerance, we often apply a sinusoidal jitter of a fixed frequency to the CDR input data and observe the BER of the CDR

The jitter tolerance curve DONT capture a CDR's true tolerance to random jitter. Because we are applying "sinusoidal" jitter, which is deterministic signal.

We can deal only with the jitter's amplitude and frequency instead of the PSD of the jitter thanks to deterministic sinusoidal jitter signal. \[ JTOL(f) = \left | \varphi_{in}(f) \right |_{\text{pp-max}} \quad \text{for a fixed BER} \] Where the subscript \(\text{pp-max}\) indicates the maximum peak-to-peak amplitude. We can further expand this equation as follows \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right| \cdot |\varphi_e(f)|_\text{pp-max} \]

Relative jitter, \(\varphi_e\) must be less than 1UIpp for error-free operation

In an ideal CDR, the maximum peak-to-peak amplitude of \(|\varphi_e(f)|\) is 1UI, i.e.,\(|\varphi_e(f)|_\text{pp-max}=1UI\)

Accordingly, jitter tolerance can be expressed in terms of the number of UIs as \[ JTOL(f)=\left| \frac{\varphi_{in}(f)}{\varphi_{e}(f)} \right|\quad \text{[UI]} \] Given the linear CDR model, we can write \[ JTOL(f)=\left| 1+\frac{K_{PD}K_{VCO}H_{LF}(f)}{j2\pi f} \right|\quad \text{[UI]} \] Expand \(H_{LF}(f)\) for the CDR, we can write \[ JTOL(f)=\left| 1-2\xi j \left(\frac{f_n}{f}\right) - \left(\frac{f_n}{f}\right)^2 \right|\quad \text{[UI]} \] At frequencies far below and above the natural frequency, the jitter tolerance can be approximated by the following \[ JTOL(f) = \left\{ \begin{array}{cl} \left(\frac{f_n}{f}\right)^2 & : \ f\ll f_n \\ 1 & : \ f\gg f_n \end{array} \right. \]

the jitter tolerance at very high jitter frequencies is limited to 1UIpp

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clc;
clear all;

f_fn = logspace(-1, 2, 60);
for xi = [2, 1, 0.5, 0.2]
    jtol = abs(1- 1i*2*xi.*(1./f_fn)- (1./f_fn).^2);
    loglog(f_fn, jtol,LineWidth=2)
    disp(["min(JTpp)=", min(jtol),"@\xi=",xi])
    hold on
end    
grid on;
xlabel("f/f_n")
ylabel('JT_{pp}')
legend('\xi=2', '\xi=1', '\xi=0.5', '\xi=0.2')

CC Chen, Circuit Images: Why JTOL in a CDR? [https://youtu.be/kZExm9wy0G8]

—. Why Pseudo-JTOL in a CDR Design or Verification? [https://youtu.be/DZyzLhk59aY]

OJTF

Concepts of JTF and OJTF

Simplified Block Diagram of a Clock-Recovery PLL

Jitter Transfer Function (JTF)

• Input Signal Versus Recovered Clock
• JTF, by jitter frequency, compares how much input signal jitter is transferred to the output of a clock-recovery's PLL (recovered clock)
  • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter that is faithfully transferred (closed-loop gain) to the clock recovery PLL's output signal. JTF in this situation is approximately 1.
  • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in decreasing jitter (open-loop gain) on the clock recovery PLL's output, because the jitter is filtered out and no longer reaches the PLL's VCO

Observed Jitter Transfer Function

• Input Signal Versus Sampled Signal
• OJTF compares how much input signal jitter is transferred to the output of a receiver's decision making circuit as effected by a clock recovery's PLL. As the recovered clock is the reference for detecting the input signal
  • Input signal jitter that is within the clock recovery PLL's loop bandwidth results in jitter on the recovered clock which reduces the amount of jitter that can be detected. The input signal and clock signal are closer in phase
  • Input signal jitter that is outside the clock recovery PLL's loop bandwidth results in reduced jitter on the recovered clock which increases the amount of jitter that can be detected. The input signal and clock signal are more out of phase. Jitter that is on both the input and clock signals can not detected or is reduced

JTF and OJTF for 1st Order PLLs

The observed jitter is a complement to the PLL jitter transfer response OJTF=1-JTF (Phase matters!)

OTJF gives the amount of jitter which is tracked and therefore not observed at the output of the CDR as a function of the jitter rate applied to the input.

Jitter Measurement

\[ J_{\text{measured}} = JTF_{\text{DUT}} \cdot OJTF_{\text{instrument}} \]

The combination of the OJTF of a jitter measurement device and the JTF of the clock generator under test gives the measured jitter as a function of frequency.

For example, a clock generator with a type 1, 1st order PLL measured with a jitter measurement device employing a golden PLL is \[ J_{\text{measured}} = \frac{\omega_1}{s+\omega_1}\frac{s}{s+\omega_2} \]

Accurate measurement of the clock JTF requires that the OJTF cutoff of the jitter measurement be significantly below that of the clock JTF and that the measurement is compensated for the instrument's OJTF.

The overall response is a band pass filter because the clock JTF is low pass and the jitter measurement device OJTF is high pass.

The compensation for the instrument OJTF is performed by measuring the jitter of the reference clock at each jitter rate being tested and comparing the reference jitter with the jitter measured at the output of the DUT.

The lower the cutoff frequency of the jitter measurement device the better the accuracy of the measurement will be.

The cutoff frequency is limited by several factors including the phase noise of the DUT and measurement time.

Digital Sampling Oscilloscope

How to analyze jitter:

• TIE (Time Interval Error) track
• histogram
• FFT

TIE track provides a direct view of how the phase of the clock evolves over time.

histogram provides valuable information about the long term variations in the timing.

FFT allows jitter at specific rates to be measured down to the femto-second range.

Maintaining the record length at a minimum of \(1/10\) of the inverse of the PLL loop bandwidth minimizes the response error

reference

Dalt, Nicola Da and Ali Sheikholeslami. “Understanding Jitter and Phase Noise: A Circuits and Systems Perspective.” (2018).

neuhelium, 抖动、眼图和高速数字链路分析基础 URL: http://www.neuhelium.com/ueditor/net/upload/file/20200826/DSOS254A/03.pdf

Keysight JTF & OJTF Concepts, https://rfmw.em.keysight.com/DigitalPhotonics/flexdca/FlexPLL-UG/Content/Topics/Quick-Start/jtf-pll-theory.htm?TocPath=Quick%20Start%7C_____4

Complementary Transmitter and Receiver Jitter Test Methodlogy, URL: https://www.ieee802.org/3/bm/public/mar14/ghiasi_01_0314_optx.pdf

SerDesDesign.com CDR_BangBang_Model URL: https://www.serdesdesign.com/home/web_documents/models/CDR_BangBang_Model.pdf

M. Schnecker, Jitter Transfer Measurement in Clock Circuits, LeCroy Corporation, DesignCon 2009. URL: http://cdn.teledynelecroy.com/files/whitepapers/designcon2009_lecroy_jitter_transfer_measurement_in_clock_circuits.pdf

Link Budgets

VCO model

TODO 📅

respone to vctrl focus on phase

[https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va]

ADC Spec

TODO 📅

ENOB - Not sufficient & not accurate enough

• Based on SNDR
• Assume unbounded Gaussian distribution

quantization noise is ~ bounded uniform distribution

Using unbounded Gaussian -> pessimistic BER prediction

AFE Nonlinearity

"total harmonic distortion" (THD) in AFE

Relative to NRZ-based systems, PAM4 transceivers require more stringent circuit linearity, equalizers which can implement multi-level inter-symbol interference (ISI) cancellation, and improved sensitivity

Because if it compresses, it turns out you have to use a much more complicated feedback filter. As long as it behaves linearly, the feedback filter itself can remain a linear FIR

Linearity can actually be a critical constraint in these signal paths, and you really want to stay as linear as you can all the way up until the point where you've canceled all of the ISI

A. Roshan-Zamir, O. Elhadidy, H. -W. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sept. 2017 [https://people.engr.tamu.edu/spalermo/ecen689/2017_reconfigurable_16_32Gbps_NRZ_PAM4_SERDES_roshanzamir_jssc.pdf]

Hongtao Zhang, designcon2016. "PAM4 Signaling for 56G Serial Link Applications − A Tutorial"[https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf]

Elad Alon, ISSCC 2014, "T6: Analog Front-End Design for Gb/s Wireline Receivers"

Impulse Response or Pulse Response

TX FFE

TX FFE suffers from the peak power constraint, which in effect attenuates the average power of the outgoing signal - the low-frequency signal content has been attenuated down to the high-frequency level

[https://www.signalintegrityjournal.com/articles/1228-feedforward-equalizer-location-study-for-high-speed-serial-systems]

S. Palermo, "CMOS Nanoelectronics Analog and RF VLSI Circuits," Chapter 9: High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems, McGraw-Hill, 2011.

Eye-Opening Monitor (EOM)

An architecture that evaluates the received signal quality

data slicers, phase slicers, error slicers, scope slicers

Analui, Behnam & Rylyakov, Alexander & Rylov, Sergey & Meghelli, Mounir & Hajimiri, Ali. (2006). A 10-Gb/s two-dimensional eye-opening monitor in 0.13-??m standard CMOS. Solid-State Circuits, IEEE Journal of. 40. 2689 - 2699, [https://chic.caltech.edu/wp-content/uploads/2013/05/B-Analui_JSSC_10-Gbs_05.pdf]

reference

G. Balamurugan, A. Balankutty and C. -M. Hsu, "56G/112G Link Foundations Standards, Link Budgets & Models," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-95 [https://youtu.be/OABG3u2H2J4] [https://picture.iczhiku.com/resource/ieee/SHKhwYfGotkIymBx.pdf]

Paul Muller Yusuf Leblebici École Polytechnique Fédérale de Lausanne (EPFL). Pattern generator model for jitter-tolerance simulation; VHDL-AMS models

Anritsu Company, "Measuring Channel Operating Margin," 2016. [https://dl.cdn-anritsu.com/en-us/test-measurement/files/Technical-Notes/White-Paper/11410-00989A.pdf]

Kiran Gunnam, Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part I: Modeling," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 97-109, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10608184]

H. Shakiba, D. Tonietto and A. Sheikholeslami, "High-Speed Wireline Links-Part II: Optimization and Performance Assessment," in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 110-121, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874]

G. Souliotis, A. Tsimpos and S. Vlassis, "Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization," in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 203-217, 2023 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10184121]

loop dynamic

Hanumolu, Pavan Kumar. 2006. Design Techniques for Clocking High Performance Signaling Systems. : Oregon State University. https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1v53k219r]

Hae-Chang Lee, "An Estimation Approach To Clock And Data Recovery" [https://www-vlsi.stanford.edu/people/alum/pdf/0611_HaechangLee_Phase_Estimation.pdf]

R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” in Phase-Locking in High-Performance Systems, B. Razavi, Ed. New Jersey: IEEE Press, 2003, pp. 34-45. [http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf]

J. Kim, Design of CMOS Adaptive-Supply Serial Links, Ph.D. Thesis, Stanford University, December 2002. [https://www-vlsi.stanford.edu/people/alum/pdf/0212_Kim_______Design_Of_CMOS_AdaptiveSu.pdf]

P. K. Hanumolu, M. G. Kim, G. -y. Wei and U. -k. Moon, "A 1.6Gbps Digital Clock and Data Recovery Circuit," IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, USA, 2006, pp. 603-606 [https://sci-hub.se/10.1109/CICC.2006.320829]

Da Dalt N. A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers. 2005;52(1):21–31. [https://sci-hub.se/10.1109/TCSI.2004.840089]

Jang S, Kim S, Chu SH, Jeong GS, Kim Y, Jeong DK. An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phase frequency detection. IEEE Transactions on Circuits and Systems II: Express Briefs. 2015;62(9):836–840. [https://sci-hub.se/10.1109/TCSII.2015.2435691]

CDR Loop Latency

Denoting the CDR loop latency by \(\Delta T\) , we note that the loop transmission is multiplied by \(exp(-s\Delta T)\simeq 1-s\Delta T\).The resulting right-half-plane zero, \(f_z\) degrades the phase margin and must remain about one decade beyond the BW \[ f_z\simeq \frac{1}{2\pi \Delta T} \]

This assumption is true in practice since the bandwidth of the CDR (few mega Hertz) is much smaller than the data rate (multi giga bits/second).

Fernando , Marvell Italy."Considerations for CDR Bandwidth Proposal" [https://www.ieee802.org/3/bs/public/16_03/debernardinis_3bs_01_0316.pdf]

Loop Bandwidth

The closed-loop −3-dB bandwidth is sometimes called the “loop bandwidth”

Continuous-Time Approximation Limitations

A rule of thumb often used to ensure slow changes in the loop is to select the loop bandwidth approximately equal to one-tenth of the input frequency.

Gardner, F.M. (1980). Charge-Pump Phase-Lock Loops. IEEE Trans. Commun., 28, 1849-1858.

Homayoun, Aliakbar and Behzad Razavi. “On the Stability of Charge-Pump Phase-Locked Loops.” IEEE Transactions on Circuits and Systems I: Regular Papers 63 (2016): 741-750.

N. Kuznetsov, A. Matveev, M. Yuldashev and R. Yuldashev, "Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4049-4061, Oct. 2021

Deog-Kyoon Jeong, Topics in IC Design - 2.1 Introduction to Phase-Locked Loop [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%202%20-%20Charge-Pump%20PLL%2C%20Freuqency%20Synthesizers%2C%20and%20SSCG.pdf]

Limit Cycle Oscillation

limit cycles imply self-sustained oscillators due nonlinear nature

Ouzounov, S., Hegt, H., Van Roermund, A. (2007). SUB-HARMONIC LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSION. In: Van Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. [https://sci-hub.se/10.1007/1-4020-5186-7_6]

Digital CDR Category

• DCO part is analogous so that it cannot be perfectly modeled
• Digital-to-phase converter is well-defined phase output, thus, very good to model real situation

Z-domain modeling

The difference equation is \[ \phi[n] = \phi[n-1] + K_{DCO}V_C[n]\cdot T\cdot2\pi \] z-transform is \[ \frac{\Phi(z)}{V_C(z)}=\frac{2\pi K_{DCO}T}{1-z^{-1}} \]

where \(K_{DCO}\) : \(\Delta f\) (Hz/bit)

\(\Delta \Sigma\)-dithering in DCO

Quantization noise

Here, \(\alpha_T\) is data transition density

BBPD quantization noise

DAC quantization noise

M. -J. Park and J. Kim, "Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, June 2013 [https://sci-hub.st/10.1109/TCSI.2012.2220502]

reference

J. Stonick. ISSCC 2011 "DPLL-Based Clock and Data Recovery"

P. Hanumolu. ISSCC 2015 "Clock and Data Recovery Architectures and Circuits"

Amir Amirkhany. ISSCC 2019 "Basics of Clock and Data Recovery Circuits"

Fulvio Spagna. INTEL, CICC2018, "Clock and Data Recovery Systems"

M. Perrott. 6.976 High Speed Communication Circuits and Systems (lecture 21). Spring 2003. Massachusetts Institute of Technology: MIT OpenCourseWare, [lec21.pdf]

Akihide Sai. ISSCC 2023, T5 "All Digital Plls From Fundamental Concepts To Future Trends"

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

—, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

Fernando De Bernardinis, eSilicon. "Introduction to DSP Based Serial Links" [https://www.corsi.univr.it/documenti/OccorrenzaIns/matdid/matdid835215.pdf]

Yohan Frans, CICC2019 ES3-3- "ADC-based Wireline Transceivers" [pdf]

H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10630516]

Marinaci, Stefano. "Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate" [https://cds.cern.ch/record/2870334/files/CERN-THESIS-2023-147.pdf]

P. Palestri et al., "Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1392-1401, July 2021 [https://sci-hub.se/10.1109/TVLSI.2021.3068450]

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol. 41, Dec. 2006, pp. 2930-2944 [https://cppsim.com/Publications/JNL/perrott_jssc06.pdf]

M.H. Perrott. CICC 2009 "Tutorial on Digital Phase-Locked Loops" [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

—, Short Course On Phase-Locked Loops and Their Applications Day 4, PM Lecture "Examples of Leveraging Digital Techniques in PLLs" [https://www.cppsim.com/PLL_Lectures/day4_pm.pdf]

—, Short Course On Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA "Digital Frequency Synthesizers" [https://www.cppsim.com/PLL_Lectures/digital_pll.pdf]

Gain Kim, "Equalization, Architecture, and Circuit Design for High-Speed Serial Link Receiver" [pdf]

Deog-Kyoon Jeong Topics in IC(Wireline Transceiver Design) - 3.1. Introduction to All Digital PLL [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%203%20-%20ADPLL.pdf]

—, Topics in IC(Wireline Transceiver Design) - 6.1 Introduction to Clock and Data Recovery [https://ocw.snu.ac.kr/sites/default/files/NOTE/Lec%206%20-%20Clock%20and%20Data%20Recovery.pdf]

High-speed Serial Interface Lect. 16 – Clock and Data Recovery 3 [http://tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect16_CDR-3.pdf]

Shiva Kiran. Phd thesis 2018. Modeling and Design of Architectures for High-Speed ADC-Based Serial Links [https://hdl.handle.net/1969.1/192031]

—, et al., "Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 3, pp. 536-548, March 2019 [https://sci-hub.se/10.1109/TCPMT.2018.2853080]

K. Zheng, "System-Driven Circuit Design for ADC-Based Wireline Data Links", Ph.D. Dissertation, Stanford University, 2018 [https://purl.stanford.edu/hw458fp0168]

S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S. Hoyos and S. Palermo, "Statistical modeling of metastability in ADC-based serial I/O receivers," 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems [pdf]

John M. Cioffi. "Decoding Methods" [https://cioffi-group.stanford.edu/doc/book/chap7.pdf]

—. "Equalization" [https://cioffi-group.stanford.edu/doc/book/chap3.pdf]

Iain. What is Trellis Coding? [https://youtu.be/rnjy4_gXLAg]

—. Decoding Convolutional Codes: The Viterbi Algorithm Explained [https://youtu.be/IJE94FhyygM]

Noman Hai, Synopsys, Canada CASS Talks 2025 - May 2, 2025: High-speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes [https://www.youtube.com/live/wHNOlxHFTzY]

T. Chan Carusone, T. O. Dickson, S. Palermo, S. Shekhar and M. Mansuri, "Modern Wireline Transceivers," in IEEE Journal of Solid-State Circuits [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11311714]y

Poddar, Ajay & Rohde, Ulrich & Apte, Anisha. (2013). How Low Can They Go?: Oscillator Phase Noise Model, Theoretical, Experimental Validation, and Phase Noise Measurements. Microwave Magazine, IEEE. [http://time.kinali.ch/rohde/noise/how_low_can_they_go-2013-poddar_rohde_apte.pdf]

F. L. Traversa, M. Bonnin and F. Bonani, "The Complex World of Oscillator Noise: Modern Approaches to Oscillator (Phase and Amplitude) Noise Analysis," in IEEE Microwave Magazine, vol. 22, no. 7, pp. 24-32, July 2021 [https://sci-hub.ru/10.1109/MMM.2021.3069535]

Phase Noise Definition

Eq. (3.25) is widely adopted by industry and academia

using the narrow angle assumption, the two definitions above are equivalent

If the narrow angle condition is not satisfied, however, the two definitions differ

Sam Palermo, ECEN620: Network Theory Broadband Circuit Design Fall 2025, Lecture 7: Voltage-Controlled Oscillators[https://people.engr.tamu.edu/spalermo/ecen620/lecture07_ee620_vcos.pdf]

Phase Noise Profile

Power Spectral Density of Brownian Motion despite non-stationary [https://dsp.stackexchange.com/a/75043/59253]

white noise — \(1/f^2\) Phase Noise Profile

Sudhakar Pamarti. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8]

flicker noise — \(1/f^3\) Phase Noise Profile \[ S_{\phi n} = \frac{K}{f}\left(\frac{K_{VCO}}{2\pi f}\right)^2 \propto \frac{1}{f^3} \]

[https://dsp.stackexchange.com/a/75152/59253]

Free-running Oscillator

Note that \(f_{min}\) is related to the observation time. The longer we observe the device under test, the smaller \(f_{min}\) must be

Ali Sheikholeslami ISSCC 2008 T5: Basics of Chip-to-Chip and Backplane Signaling

B. Casper and F. O'Mahony, "Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links-A Tutorial," in IEEE Transactions on Circuits and Systems I. [https://people.engr.tamu.edu/spalermo/ecen689/clocking_analysis_hs_links_casper_tcas1_2009.pdf]

Leeson's model — LTI

M.H. Perrott, Short Course On Phase-Locked Loops and Their Applications Day 2, AM Lecture Basic Building Blocks Voltage-Controlled Oscillators [https://www.cppsim.com/PLL_Lectures/day2_am.pdf]

—, 6.976 High Speed Communication Circuits and Systems Lecture 12 Noise in Voltage Controlled Oscillators [https://ocw.mit.edu/courses/6-976-high-speed-communication-circuits-and-systems-spring-2003/ceb3d539691d5393a29af71ae98afb62_lec12.pdf]

Leeson's model is outcome of linearized VCO noise analysis

Assuming voltage noise tone \((\omega_0+\omega_m)\) and \((\omega_0-\omega_m)\) are independent and symmetric

Leeson's limitations

1/f noise Upconversion & Thermal noise Upconversion

Hajimiri's ISF— LTV in Time Domain

A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," in IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998 [paper], [slides]

—, RFIC 2024 Technical Lecture: Noise in Oscillators from Understanding to Design

Thomas H. Lee. Linearity, Time-Variation, Phase Modulation and Oscillator Phase Noise [https://class.ece.iastate.edu/djchen/ee507/PhaseNoiseTutorialLee.pdf]

Aditya Varma Muppala, [https://adityamuppala.github.io/assets/Notes_YouTube/Oscillators_ISF_model.pdf]

The peak magnitude of the ISF, \[ \Gamma_{\max}=\max_\theta |\Gamma(\theta)|, \] can be greater than 1, equal to 1, or less than 1.

A value \(\Gamma>1\) therefore does not mean "more than 100%." It simply means that the oscillator has relatively high phase sensitivity at that particular phase.

\(\psi(t)\) is literally the instantaneous frequency deviation. Check the dimensions: \(i(t)/q_{max}\) has units of A/C = 1/s, and \(\Gamma\) is dimensionless, so \(\psi(t) = \Gamma(\omega_0 t)\,i(t)/q_{max}\) is in rad/s. The diagram is saying \(d\phi/dt = \psi(t)\), i.e. \(\phi(t) = \int_{-\infty}^{t}\psi(\tau)d\tau\). An ideal integrator has transfer function \(1/j\Delta\omega\), so in power spectra: \[ S_\phi(\Delta\omega) = \frac{S_\psi(\Delta\omega)}{\Delta\omega^2} \] That single block is the origin of every \(1/\Delta\omega^2\) factor in phase noise theory — including the \((\omega_0/2Q\Delta\omega)^2\) term in Leeson's equation

Pure sinusoidal voltage

White-noise Folding

Suppose a low frequency sinusoidal perturbation current \(i(t) = I_m \cos[(m\omega_0 +\Delta \omega)t]\),

\[\begin{align} \phi(t) &= \frac{1}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t I_m\cos((m\omega_0 +\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t I_m\cos((m\omega_0 +\Delta \omega)\tau)\cos(n\omega_0\tau)d\tau\right] \\ &= \frac{I_m}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t \cos((m\omega_0 +\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t \frac{\cos((m\omega_0 + \Delta \omega+ n\omega_0)\tau)+ \cos((m\omega_0+\Delta \omega - n\omega_0)\tau)}{2}d\tau\right] \end{align}\]

If \(m=0\) \[ \phi(t) \approx \frac{I_0C_0}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \] If \(m\neq 0\) and \(m=n\) \[ \phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \]

When performing the phase noise computation integral, there will be a negligible contribution from all terms, other than \(n=m\)

apply equation (18) derived from sinusoidal to white noise

Corrections to "A General Theory of Phase Noise in Electrical Oscillators"

A. Hajimiri and T. H. Lee, "Corrections to "A General Theory of Phase Noise in Electrical Oscillators"," in IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp. 928-928, June 1998 [https://sci-hub.se/10.1109/4.678662]

L. Lu, Z. Tang, P. Andreani, A. Mazzanti and A. Hajimiri, "Comments on “Comments on “A General Theory of Phase Noise in Electrical Oscillators””," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2170-2170, Sept. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005028]

Noise power around the frequency \(\color{blue}n\omega_0 + \Delta\omega\) causes two equal sidebands at \(\omega_0 \pm \Delta\omega\). However, the noise power at \(\color{blue}n\omega_0 - \Delta\omega\) has a similar effect as mentioned in the paper. Therefore, twice the power of noise at \(n\omega_0 + \Delta\omega\) should be taken into account

Given \(i(t) = I_m \cos[(m\omega_0 - \Delta \omega)t]\) and \(m \ge 1\)

\[\begin{align} \phi(t) &= \frac{1}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t I_m\cos((m\omega_0 -\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t I_m\cos((m\omega_0 -\Delta \omega)\tau)\cos(n\omega_0\tau)d\tau\right] \\ &= \frac{I_m}{q_\text{max}}\left[\frac{C_0}{2}\int_{-\infty}^t \cos((m\omega_0 -\Delta \omega)\tau)d\tau + \sum_{n=1}^\infty C_n\int_{-\infty}^t \frac{\cos((m\omega_0 - \Delta \omega+ n\omega_0)\tau)+ \cos((m\omega_0-\Delta \omega - n\omega_0)\tau)}{2}d\tau\right] \end{align}\]

If \(m\ge 1\) and \(m=n\) \[ \phi(t) \approx \frac{I_mC_m}{2q_\text{max}\Delta \omega}\sin(\Delta\omega t) \] That is

\[\begin{align} \mathcal{L}\{\Delta \omega\} &= 10\log\left(\frac{I_0^2C_0^2}{16q_\text{max}^2\Delta \omega^2} + 2\frac{I_m^2C_m^2}{16q_\text{max}^2\Delta \omega^2}\right) = 10\log\left(\frac{\overline{i_n^2/\Delta f}\cdot \frac{C_0^2}{2} }{4q_\text{max}^2\Delta \omega^2} + \frac{\overline{i_n^2/\Delta f}\cdot\sum_{m=1}^\infty C_m^2 }{4q_\text{max}^2\Delta \omega^2}\right) \\ &= 10\log \frac{\overline{i_n^2/\Delta f}(C_0^2/2+\sum_{m=1}^\infty C_m^2)}{4q_\text{max}^2\Delta \omega^2} = 10\log \frac{\overline{i_n^2/\Delta f}\cdot \Gamma_\text{rms}^2}{2q_\text{max}^2\Delta \omega^2} \end{align}\]

[pdf]

1/f-noise Upconversion

Suppose \(c_0\neq 0\), corresponding phase noise in response to injected noise \(i_n(t)\) is equal to:

\[ \phi_{n,c_0} = \int_{-\infty}^t c_0 i_n(\tau) d\tau \qquad \boxed{S_{\phi n,c_0}(f) = \frac{c_0^2}{\omega^2}S_i(f)= \frac{\mathcal{\Gamma}_\text{dc}^2}{\omega^2}S_i(f)} \]

alternative derivation

Michael Perrott August 12, 2008, Short Course On Phase-Locked Loops and Their Applications Day 2, AM Lecture Basic Building Blocks Voltage-Controlled Oscillators [https://www.cppsim.com/PLL_Lectures/day2_am.pdf]

White Noise Input

1/f Noise in Input Current

Current Noise Modulation

another alternative derivation

\[ S_{\phi,USB} = \frac{S_n^{''}}{q_\text{max}^2\Delta\omega^2}\left(a_0^2+\sum_{k\neq0}a_k^2\right)=\frac{S_n^{''}}{q_\text{max}^2\Delta\omega^2}\left(\frac{c_0^2}{4}+\sum_{k=1}^\infty \frac{c_k^2}{2}\right)=\frac{S_n^{'}}{4q_\text{max}^2\Delta\omega^2}\left(\frac{c_0^2}{2}+\sum_{k=1}^\infty c_k^2\right) \] where \(S_n^{''}\) is two sided PSD, \(S_n^{}\) is one sided PSD

Diff. Pair Noise with ISF

only half of this current is differentially injected in the tank at the zero-crossing

Given \(\Gamma_{MOS}\) shown as above slide \[ F_{rms,MOS}^2 = \frac{1/4\cdot T_\text{w}}{T_0/2} = \frac{T_\text{w}}{2T_0} \]

P. Andreani, X. Wang, "On the Phase-Noise and Phase-Error Performances of Multiphase LC CMOS VCOs," IEEE Journal of Solid-State Circuits, vol. 39, pp. 1883-1893, Nov. 2004. [https://backend.orbit.dtu.dk/ws/files/4109919/Wang.pdf]

P. Andreani, X. Wang, L. Vandi, A. Frad, "A study of phase noise in Colpitts and LC-tank CMOS oscillators," IEEE Journal of Solid-State Circuits, vol. 40, pp. 1107-1118, May 2005. [https://backend.orbit.dtu.dk/ws/files/3976825/Andreani.pdf]

A. Bevilacqua, P. Andreani, "An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 5, pp. 938-945, May 2012 [https://sci-hub.jp/10.1109/TCSI.2012.2190564]

For Class-B with an Ideal Current Source

• noise factor is \(\boxed{1+\gamma_n}\)
• \(-g_m\) transistors (M1,2) do not contribute to \(1/f\) noise upconversion

Note the contrast with thermal noise: white noise is uncorrelated between the two crossings, so the two kicks don't cancel — their variances add. That's why the same commutation mechanism gives you the full \(\gamma_n\) term in \(F = 1+\gamma_n\) for the \(1/f^2\) region, yet contributes nothing in \(1/f^3\)

Tail-Current Noise Conversion with the ISF

A. Hajimiri and T. H. Lee, "Design issues in CMOS differential LC oscillators," in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999. [paper]

T. H. Lee, Linearity, Time-Variation, Phase Modulation and Oscillator Phase Noise. [slides]

K. Gunnam and M. VahidFar, eds., Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 1st ed. River Publishers, 2017.

The differential pair commutates twice per oscillation cycle. After half a cycle, the two sides exchange roles, but the common tail node returns to the same state. Therefore, both the tail voltage and the tail-current ISF have half-period symmetry: \[ v_\text{tail}\left(t+\frac{T_0}{2}\right)=v_\text{tail}(t), \qquad \Gamma_\text{tail}(\theta+\pi)=\Gamma_\text{tail}(\theta). \] It follows that the tail ISF can have a DC component but only even harmonics of \(\omega_0\): \[ \Gamma_\text{tail}(\theta) =\sum_{k=-\infty}^{\infty}c_{2k}e^{j2k\theta} \approx c_0+c_2e^{j2\theta}+c_{-2}e^{-j2\theta}, \] where the approximation retains the DC and dominant second-harmonic terms.

Tail-current noise first produces an instantaneous frequency perturbation, which is then integrated into phase: \[ \dot{\phi}_\text{tail}(t) =\frac{\Gamma_\text{tail}(\omega_0t)i_\text{n,tail}(t)}{q_\text{max}}, \qquad \boxed{\phi_\text{tail}(t) =\frac{1}{q_\text{max}}\int_{-\infty}^{t} \Gamma_\text{tail}(\omega_0\tau)i_\text{n,tail}(\tau)\,d\tau.} \]

Multiplication by the periodic ISF acts as a mixer. For stationary tail-current noise, using a two-sided PSD convention, the phase-noise PSD at an offset \(\Omega\ll\omega_0\) is \[ S_{\phi,\text{tail}}(\Omega) =\frac{1}{q_\text{max}^2\Omega^2} \sum_{k=-\infty}^{\infty}|c_{2k}|^2 S_{i,\text{tail}}(\Omega-2k\omega_0). \] Thus, \(c_0\) converts low-frequency noise directly to close-in phase noise, while \(c_{\pm2}\) downconvert noise near \(2\omega_0\pm\Omega\) to the same offset \(\Omega\). Noise near \(\omega_0\) makes no first-order contribution because the odd Fourier coefficients vanish.

In the DC-plus-second-harmonic approximation, only low-frequency noise and noise near \(2\omega_0\) create close-in phase noise.

More generally, a nonsinusoidal tail ISF can also fold noise near \(4\omega_0,6\omega_0,\ldots\); low-frequency conversion vanishes when the DC coefficient \(c_0\) is zero.

Closed-Form Formula for the ISF

If the state variables are node voltages, write \(\Delta \vec X = \sum_i \Delta v_i\,\hat e_i\) (with \(\Delta v_i = \Delta q_i/C_i\)) and the dot product distributes: \[ \Delta\phi = \frac{2\pi}{T}\frac{\big(\sum_i \Delta v_i \hat e_i\big)\cdot \dot{\vec X}}{\lVert\dot{\vec X}\rVert^{2}} \;=\frac{2\pi}{T}\; \sum_i\,\frac{\Delta v_i\, \dot v_i}{\lVert\dot{\vec X}\rVert^{2}} \;=\; \sum_i \Delta\phi_i, \] For second-order system, one can use the normalized waveform and its derivative as the state variables \[ \Gamma_{1}(x)=\frac{f'(x)}{f^{2}(x)+f'^{2}(x)} \qquad \Gamma_{2}(x)=\frac{f''(x)}{f'^{2}(x)+f''^{2}(x)} \] In the case of an ideal sinusoidal oscillator \(f=\cos(x)\) \[ \Gamma_{1}(x)=-\sin(x) \qquad \Gamma_{2}(x)=-\cos(x) \] A finite charge impulse into the node cannot make the inductor current jump (\(v\) stays bounded, so \(i_L=\frac{1}{L}\int v\,dt\) is continuous) — current component of the perturbation is exactly zero. That's physics of the input, not an approximation: \(\Delta\vec X = (\Delta v,\,0)\) exactly, so \(\Gamma_2\) gets multiplied by zero

Total phase noise sums over physical sources, each weighted by its own ISF

• If every noise source in the circuit injects current into nodes — transistor channel noise, resistor noise, the usual on-chip situation — then the \(\Gamma_1\) family is the whole story with no approximation
• \(\Gamma_2\) enters only when a source physically acts as a series voltage on the inductor (flux injection), such as the coil's series resistance

quietly assumes the normal component contributes zero phase shift, i.e., that surfaces of equal phase (isochrons) cross the limit cycle orthogonally

Real oscillators violate this to varying degrees (amplitude-to-phase conversion), which is why the paper ranks direct impulse-injection simulation as the most accurate

The dot product and norm in (31)–(33) mean different things in different coordinates, so the same physical oscillator run through (33) in two different coordinate systems yields two different ISFs — and only one coordinate choice yields the paper's intended answer

Consider the ideal parallel LC network — pure sinusoid wave

Suppose a current pulse with area \(q\) suddenly changes the charge across the capacitor, its voltage changes by \(\Delta v_c=\Delta q/C\)

Decompose the horizontal kick \(\Delta\vec r=(\Delta x,0)\) and \(\Delta x=\Delta v_C/A_0\), with tangential direction \(\hat t=(-\sin\theta,\cos\theta)\) and radial direction \(\hat r=(\cos\theta,\sin\theta)\) \[ \Delta \phi = \arctan\left(\frac{\Delta\vec r\cdot \hat t}{1 + \Delta\vec r\cdot \hat r}\right) = \arctan\left(\frac{-\Delta x \sin \theta}{1 + \Delta x \cos \theta}\right)\approx -\frac{\Delta v_C}{A_0} \sin(\omega_0 \tau) \]

Therefore, the ISF of an ideal parallel LC resonator can be expressed as \(\boxed{\Gamma(\omega \tau)=-\sin(\omega_0 \tau)}\), which is independent of peak voltage value \(A_0\)

C. Calculation of ISF Based on the First Derivative

additive voltage error

A fixed \(\Delta V\) at a crossing shifts the crossing time by \(\Delta t = \Delta V/\dot v\), so \(\Delta\phi = \omega_0\Delta V/\dot v\). Express this against the normalized injection \(\Delta\phi = \Gamma\cdot\Delta V/V_{\max}\) and solve: \[ \Gamma_{\text{crossing}} = \frac{\omega_0 V_{\max}}{\dot v} = \frac{1}{f'} \] Now take eq. (37) at the mid-transition, where \(f'' = 0\) (inflection point): \[ \Gamma = \frac{f'}{f'^2 + f''^2}\;\Big|_{f''=0} = \frac{f'}{f'^2} = \frac{1}{f'} \]

\[ \boxed{ \text{steeper transition} \quad\Longrightarrow\quad \text{smaller ISF peak} } \] with \(\Gamma = \sin x\), at crossing \(\sin x =1\), which is derivative of edge \[ \Delta \phi = \Gamma \frac{\Delta q}{q_\text{max}} = \sin x\cdot \frac{\Delta q}{C\cdot A}= \sin x\cdot \frac{\Delta q}{C\cdot A\sin x} \]

Effective ISF

cyclostationary noise sources

Cyclostationary noise can be viewed as stationary noise, \(i_{n0}(t)\), multiplied by a periodic envelope, \(\alpha(\omega_0 t)\).

Effective ISF — ISF multiplied with Noise Modulating Function (NMF)

For Colpitts Oscillator, \(\Gamma_\text{eff}(x)\) is different from \(\Gamma(x)\), however \(\Gamma_\text{eff}(x)\) and \(\Gamma(x)\) are almost identical for ring oscillator

thermal noise with NMF

source-specific ISF + its NMF

flicker noise with effective non-normalized ISF

Y. Hu, T. Siriburanon and R. B. Staszewski, "A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path," in IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1977-1987, July 2018 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8345650]

—, "Oscillator Flicker Phase Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [paper] [slides]

—, "Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019 [https://sci-hub.jp/10.1109/TCSII.2019.2896483]

With the paper’s implicit \(1\text{-Hz}\) noise bandwidth, Eq. (3) \[ v_{1/f}(t) = \sqrt{2}\,V_{1/f,\mathrm{rms}} \cos(\Delta\omega t+\gamma) \] represents one narrowband sinusoidal noise component.

Here: \[ V_{1/f,\mathrm{rms}} = \sqrt{S_{v,1/f}(\Delta f)\cdot 1\,\mathrm{Hz}} \] is the RMS voltage amplitude of that component. Therefore, strictly within Eq. (3), \[ [V_{1/f,\mathrm{rms}}]=\mathrm V. \] Because the bandwidth is implicitly \(1\,\mathrm{Hz}\), its numerical value equals the amplitude spectral density expressed in \(\mathrm{V}/\sqrt{\mathrm{Hz}}\): \[ V_{1/f,\mathrm{rms}}[\mathrm V] \overset{B=1\,\mathrm{Hz}}{=} \sqrt{S_{v,1/f}} \left[\frac{\mathrm V}{\sqrt{\mathrm{Hz}}}\right] \sqrt{1\,\mathrm{Hz}}. \] Also, more precisely:

• \(\Delta\omega t+\gamma\) is the phase of the sinusoidal component.
• \(\cos(\Delta\omega t+\gamma)\) is the dimensionless sinusoidal waveform.
• \(\gamma\) is the random initial phase.
• \(\sqrt{2}V_{1/f,\mathrm{rms}}\) is the peak amplitude.

Indeed, \[ \operatorname{rms} \left\{ \sqrt{2}V_{1/f,\mathrm{rms}} \cos(\Delta\omega t+\gamma) \right\} = V_{1/f,\mathrm{rms}}. \] Therefore, the same interpretation applies to Eq. (4): \[ i_{1/f,\mathrm{cyclo}}(t) = \sqrt{2}I_{1/f,\mathrm{rms}}(t) \cos(\Delta\omega t+\gamma). \] Under the implicit \(1\text{-Hz}\) bandwidth, \[ [I_{1/f,\mathrm{rms}}(t)]=\mathrm A, \] From Eq. (4), \[ i_{1/f,\mathrm{cyclo}}(t) = \sqrt{2}\,I_{1/f,\mathrm{rms}}(t) \cos(\Delta\omega t+\gamma). \] Substitute this into the phase perturbation integral: \[ \begin{aligned} \phi(t) &= \int_{-\infty}^{t} h_{\mathrm{DS}}(\tau) i_{1/f,\mathrm{cyclo}}(\tau)\,d\tau \\ &= \sqrt{2} \int_{-\infty}^{t} h_{\mathrm{DS}}(\tau) I_{1/f,\mathrm{rms}}(\tau) \cos(\Delta\omega\tau+\gamma)\,d\tau. \end{aligned} \] Define the periodically varying effective ISF as \[ \color{blue}\boxed{h_{\mathrm{eff}}(t) \equiv h_{\mathrm{DS}}(t)I_{1/f,\mathrm{rms}}(t)} \] Therefore, \[ \phi(t) = \sqrt{2} \int_{-\infty}^{t} h_{\mathrm{eff}}(\tau) \cos(\Delta\omega\tau+\gamma)\,d\tau. \] Since \(h_{\mathrm{eff}}(t)\) is periodic with period \(T=2\pi/\omega_0\), write \[ h_{\mathrm{eff}}(t) = h_{\mathrm{eff,dc}} + \sum_{k=1}^{\infty} H_k\cos(k\omega_0t+\psi_k), \] where \[ h_{\mathrm{eff,dc}} = \frac{1}{T} \int_0^T h_{\mathrm{eff}}(t)\,dt = \frac{1}{T} \int_0^T h_{\mathrm{DS}}(t) I_{1/f,\mathrm{rms}}(t)\,dt. \] This is Eq. (7).

Substitution gives \[ \begin{aligned} \phi(t) ={}& \sqrt{2}h_{\mathrm{eff,dc}} \int^t\cos(\Delta\omega\tau+\gamma)\,d\tau \\ &+ \sqrt{2}\sum_{k=1}^{\infty}H_k \int^t \cos(k\omega_0\tau+\psi_k) \cos(\Delta\omega\tau+\gamma)\,d\tau. \end{aligned} \] The first term is \[ \sqrt{2}h_{\mathrm{eff,dc}} \int^t\cos(\Delta\omega\tau+\gamma)\,d\tau = \frac{\sqrt{2}h_{\mathrm{eff,dc}}}{\Delta\omega} \sin(\Delta\omega t+\gamma). \] For the harmonic terms, use \[ \cos A\cos B = \frac{1}{2}\left[\cos(A+B)+\cos(A-B)\right]. \] Thus, the exact harmonic contribution is \[ \begin{aligned} \phi_k(t) = \frac{\sqrt{2}H_k}{2} \Bigg[ & \frac{ \sin\!\left[(k\omega_0+\Delta\omega)t+\psi_k+\gamma\right] }{ k\omega_0+\Delta\omega } \\ +& \frac{ \sin\!\left[(k\omega_0-\Delta\omega)t+\psi_k-\gamma\right] }{ k\omega_0-\Delta\omega } \Bigg]. \end{aligned} \] These terms lie near \(k\omega_0\pm\Delta\omega\), whereas the DC term produces a slowly varying phase component directly at \(\Delta\omega\).

Because \[ \Delta\omega\ll\omega_0, \] the slow component is also much larger after integration: \[ \frac{1}{\Delta\omega} \gg \frac{1}{k\omega_0\pm\Delta\omega}. \] Therefore, keeping only the dominant low-frequency phase term, \[ \color{blue}\boxed{ \phi(t) \approx \frac{\sqrt{2}h_{\mathrm{eff,dc}}}{\Delta\omega} \sin(\Delta\omega t+\gamma) } \] The essential mechanism is \[ \underbrace{h_{\mathrm{DS}}(t)}_{\text{periodic ISF}} \, \underbrace{I_{1/f,\mathrm{rms}}(t)}_{\text{periodic noise amplitude}} \longrightarrow \underbrace{h_{\mathrm{eff,dc}}}_{\text{nonzero average}}, \]

M. Shahmohammadi, M. Babaie and R. B. Staszewski, "A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2610-2624, Nov. 2016 [https://pure.tudelft.nl/ws/portalfiles/portal/30880387/07571191.pdf]

Murphy's Model — LTV in Frequency Domain

C. Samori, A. L. Lacaita, F. Villa and F. Zappa, "Spectrum folding and phase noise in LC tuned oscillators," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 7, pp. 781-790, July 1998 [https://sci-hub.ru/10.1109/82.700925]

D. Murphy, J. J. Rael and A. A. Abidi, "Phase Noise in LC Oscillators: A Phasor-Based Analysis of a General Result and of Loaded Q ," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 6, pp. 1187-1203, June 2010 [https://sci-hub.ru/10.1109/TCSI.2009.2030110]

The differential pair plays two distinct roles. Toward its own noise it acts as a sampling gate — each transistor contributes only within the short conduction windows at the zero crossings — and the resulting injection is almost purely phase-modulating.

Toward the tail noise it acts as a single-balanced mixer, commutating the upstream current with a square wave and folding it as a single sideband that splits equally into AM and PM

Diff. Pair Noise

For diff. pair noise, the diff. pair is its own noise gate

half of the noise current of each generator reaches the tank, while the remaining half circulates within the transistor

A reference pulse train centered at \(t=0\) would have plain positive coefficients (\(\tfrac{T_w}{T_0}\), with \(\operatorname{sinc} \approx 1\)). \[ c_n = \frac{1}{2}\cdot \frac{T_w}{T_0/2}\operatorname{sinc}\left(\frac{nT_w}{T_0/2}\right)=\frac{T_w}{T_0}\operatorname{sinc}\left(\frac{2nT_w}{T_0}\right) \] The real injection sits at \(t=T_0/4\), and since the pulse-train period is \(P=T_0/2\), that offset is exactly \(P/2\) — a half-period shift. Every coefficient therefore picks up \((-1)^m\) — \(e^{j2m\omega_0\cdot T_0/4}=e^{jm\pi}\) \[ c_{2m} = \underbrace{(-1)^m}_{\text{position}}\, \underbrace{\frac{T_w}{T_0}}_{\text{area / period}}\, \underbrace{\operatorname{sinc}\!\left(\frac{2mT_w}{T_0}\right)}_{\to\,1 \text{ as } T_w \ll T_0} \]

Consequently, excess noise arises solely from the components at \(\omega_0\pm \omega_m\), since all other spectral components lie outside the tank bandwidth and are therefore suppressed by the resonator's frequency-selective filtering

With Cyclostationary Noise (Modulated Noise) [https://raytroop.github.io/2024/04/27/noise/#cyclostationary-noise-modulated-noise]

For one MOS, Two-Sided PSD is \[ S_O = S_I \cdot \mathcal{D}\cdot \mathcal{h}^2 = 2kT\gamma g_m\cdot \frac{2T_W}{T_0}\cdot\frac{1}{4} = \frac{T_W}{2T_0}\cdot 2kT\gamma g_m \] yield One-Sided PSD of one MOS \[ S_O' = \textcolor{blue}{\frac{T_W}{2T_0}}\cdot 4kT\gamma g_m \]

The single-tone analysis establishes that the differential-pair current is injected as almost pure phase noise, while summing the white-noise power over all harmonics of the gating function (\(\overline{H^2}=T_W/2T_0\)) sets its magnitude; together these yield the differential-pair contribution to the oscillator phase noise.

phase noise is independent of the transconductance of the transistors

Tail Noise

For the tail noise, the diff. pair is a mixer

\[ V_{AM} = \tfrac{1}{2}\big(C_+ + \overline{C}_-\big) = \tfrac{1}{2}\Big(\tfrac{c_1^* i}{2} + \tfrac{c_3^* i}{2}\Big)\qquad V_{PM} = \tfrac{1}{2}\big(C_+ - \overline{C}_-\big) = \tfrac{1}{2}\Big(\tfrac{c_1^* i}{2} - \tfrac{c_3^* i}{2}\Big) \] \(V_{AM}\approx V_{PM}\) for a square wave \(|c_1|=3|c_3|\) — modulated tail noise is divided into AM and phase noise almost equally \[ S_{I,PN} = S_{nI,T} \cdot \mathcal{D}\cdot \mathcal{h}^2 \cdot \frac{1}{2} = S_{nI,T} \cdot 1 \cdot \frac{1}{4}\cdot \frac{1}{2} = \boxed{\frac{1}{8}\cdot S_{nI,T}} \] The commutation folds tail noise as a (near) single sideband, which is equivalent to equal AM and PM — and only the PM half counts toward phase noise

Noise around \(\boxed{2\omega_0 \pm\omega_m}\) dominate phase noise due to \(|c_1|, |c_3| \gg |c_{2m+1}| \space\space\space\space \forall m>1\)

E. Hegazi, H. Sjoland and A. Abidi, "A filtering technique to lower oscillator phase noise," 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), San Francisco, CA, USA, 2001 [paper, slides]

Peter Kinget, ISSCC 2010 short course, Transistor-Level Design of Critical PLL Circuits

In the first-order, noise around DC (flicker) is upconverted as a pair of correlated, symmetric sidebands around the carrier — which is pure AM

J. J. Rael and A. A. Abidi, "Physical processes of phase noise in differential LC oscillators," IEEE Custom Integrated Circuits Conference (CICC), 2000 [https://people.engr.tamu.edu/spalermo/ecen620/physical_processes_pn_diff_lc_osc_rael_cicc_2000.pdf]

practical outcome once second-order conversion effects are included

• flicker near DC → AM/bias modulation → converted to FM → 1/f³ PN (the purple arrow in its spectrum)
• while thermal noise at 2f_osc → direct PN → 1/f² PN (the blue arrow)

Demir's Model — NLTV

A. Demir, A. Mehrotra and J. Roychowdhury, "Phase noise in oscillators: a unifying theory and numerical methods for characterization," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674, May 2000 [https://sci-hub.jp/10.1109/81.847872]

A. Demir and A. Sangiovanni-Vincentelli, Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems, vol. 425. Boston, MA, USA: Kluwer Academic Publishers, 1998

A. Mehrotra and A. Sangiovanni-Vincentelli, Noise Analysis of Radio Frequency Circuits, 1st ed. New York, NY, USA: Springer, 2004

Demir's theory is essentially Floquet theory applied to the limit cycle of an autonomous oscillator, and the PPV is one specific Floquet vector

PPV (Perturbation Projection Vector)

A. Demir and J. Roychowdhury, "A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 188-197, Feb. 2003 [https://sci-hub.se/10.1109/TCAD.2002.806599]

Helene Thibieroz, Customer Support CIC. Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately [https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=3056e59ea76165373f90152f915a829d25dabebc]

Aditya Varma Muppala. Perturbation Projection Vector (PPV) Theory | Oscillators 11 | MMIC 16 [youtu.be, notes]

S. Levantino and P. Maffezzoni, "Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 10, pp. 1499-1507, Oct. 2012 [https://sci-hub.se/10.1109/TCAD.2012.2194493]

Limit Cycles

[https://adityamuppala.github.io/assets/Notes_YouTube/MMIC_Limit_Cycles.pdf]

Nonlinear Dynamics

Lorentzian spectrum

We typically use the two spectra, \(S_{\phi n}(f)\) and \(S_{out}(f)\), interchangeably, but we must resolve these inconsistencies. voltage spectrum is called Lorentzian spectrum

The periodic signal \(x(t)\) can be expanded in Fourier series as:

Assume that the signal is subject to excess phase noise, which is modeled by adding a time-dependent noise component \(\alpha(t)\). The noisy signal can be written \(x(t+\alpha(t))\), the added excess phase \(\phi(t)= \frac{\alpha(t)}{\omega_0}\)

The autocorrelation of the noisy signal is by definition:

The autocorrelation averaged over time results in:

By taking the Fourier transform of the autocorrelation, the spectrum of the signal \(x(t + \alpha(t))\)​ can be expressed as

It is also interesting to note how the integral in Equation 9.80 around each harmonic is equal to the power of the harmonic itself \(|X_n|^2\)

The integral \(S_x(f)\) around harmonic is \[\begin{align} P_{x,n} &= \int_{f=-\infty}^{\infty} |X_n|^2\frac{\omega_0^2n^2c}{\frac{1}{4}\omega_0^4n^4c^2+(\omega +n\omega_0)^2}df = |X_n|^2\int_{\Delta f=-\infty}^{\infty}\frac{2\beta}{\beta^2+(2\pi\cdot\Delta f)^2}d\Delta f \\ &= |X_n|^2\frac{1}{\pi}\arctan(\frac{2\pi \Delta f}{\beta})|_{-\infty}^{\infty} = |X_n|^2 \end{align}\]

The phase noise does not affect the total power in the signal, it only affects its distribution

• Without phase noise, \(S_v(f)\) is a series of impulse functions at the harmonics of \(f_o\).
• With phase noise, the impulse functions spread, becoming fatter and shorter but retaining the same total power

[https://community.cadence.com/cadence_technology_forums/f/rf-design/51484/comparing-transient-noise-pnoise-and-pnoise-with-lorentian-approximation-of-a-ring-oscillator/1382911]

Razavi's PN

Additive Noise to PN

\(n_I(t)\) and \(n_Q(t)\) have the same PSD and are uncorrelated

Tail Thermal Noise

low-frequency content:

around \(\omega_0\):

no phase noise is produced

around \(2\omega_0\):

\(\frac{2}{\pi}[n_I(t)\cos2\omega_0 t - n_Q(t)\sin2\omega_0 t]\cdot \color{red}\cos\omega_0 t\) produce most phase noise

\(\frac{2}{\textcolor{green}{3}\pi}[n_I(t)\cos2\omega_0 t - n_Q(t)\sin2\omega_0 t]\cdot \color{red}\cos3\omega_0 t\) produce phase noise, but can be negligible — \(10\log(1+\frac{1}{3^2})\approx +0.46\, \text{dB}\)

Tail Flicker Noise

Abidi & Hooman's PN

A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC Oscillator," in IEEE Open Journal of the Solid-State Circuits Society, vol. 5, pp. 45-59, 2025 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10818782]

A. Mirzaei and A. A. Abidi, "The Spectrum of a Noisy Free-Running Oscillator Explained by Random Frequency Pulling," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 3, pp. 642-653, March 2010 [https://sci-hub.jp/10.1109/TCSI.2009.2024970]

J. J. Rael and A. A. Abidi, "Physical processes of phase noise in differential LC oscillators," IEEE Custom Integrated Circuits Conference (CICC), 2000 [https://people.engr.tamu.edu/spalermo/ecen620/physical_processes_pn_diff_lc_osc_rael_cicc_2000.pdf]

\[ V_{PM}\cos \omega_m t \overset{\text{power}}{\longrightarrow} \frac{S_{Vpm}}{2} = \frac{1}{2}(2kTR + 2kTR) \] quadrature noise → geometric tilt \(\phi,\, \Phi\) (bounded) → frequency shift \(f \propto \theta\) → accumulated phase \(\phi = \int f\,dt,\, \Theta\). Me

Noise Passing through a Nonlinearity

Bank's General Result

J. Bank, "A harmonic-oscillator design methodology based on describing functions," Ph.D. dissertation, Dept. Signals Syst., Sch. Elect. Eng., Chalmers Univ. Techn., Chalmers, Sweden, 2006. [https://publications.lib.chalmers.se/records/fulltext/17376.pdf]

A. Mazzanti and A. Bevilacqua, "On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 9, pp. 2334-2341, Sept. 2015 [https://sci-hub.jp/10.1109/TCSI.2015.2451915]

For the oscillation condition \(\overline{g_m}R_p=1\), the total noise-current power spectral density (PSD) is \[ \overline{i_n^2} = \overline{i_R^2} + \overline{i_{gnr}^2} = \frac{4kT}{R_p} + 4kT\gamma\overline{g_m} = \frac{4kT}{R_p}\left(1+\gamma\overline{g_m}R_p\right) = \frac{4kT}{R_p}(1+\gamma). \]

More generally, if \(K\overline{g_m}R_p=1\), then \(\overline{g_m}R_p=1/K\), and the PSD becomes \[ \overline{i_n^2} = \frac{4kT}{R_p}\left(1+\frac{\gamma}{K}\right). \]

Two-Port Oscillators

flicker noise upconversion

Y. Hu, T. Siriburanon and R. B. Staszewski, "Oscillator Flicker Phase Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [paper] [slides]

—, "Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019 [https://sci-hub.jp/10.1109/TCSII.2019.2896483]

E. G. Ioannidis, C. G. Theodorou, T. A. Karatsori, S. Haendler, C. A. Dimitriadis and G. Ghibaudo, "Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology," in IEEE Transactions on Electron Devices, vol. 62, no. 5, pp. 1574-1579, May 2015 [https://sci-hub.jp/10.1109/TED.2015.2411678]

Two different mechanisms: \[ \boxed{\text{tail-transistor }1/f\text{ noise}} \qquad\text{vs.}\qquad \boxed{\text{cross-coupled-pair }1/f\text{ noise}} \] They are not upconverted through exactly the same physical path

Tail-current-source flicker noise

J. J. Rael and A. A. Abidi, "Physical processes of phase noise in differential LC oscillators," Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), Orlando, FL, USA, 2000 [https://people.engr.tamu.edu/spalermo/ecen620/physical_processes_pn_diff_lc_osc_rael_cicc_2000.pdf]

A. Bevilacqua and P. Andreani, "An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 5, pp. 938-945, May 2012 [https://sci-hub.jp/10.1109/TCSI.2012.2190564]

\[ v_{n,\mathrm{tail}}^{1/f} \rightarrow \Delta I_T \rightarrow \text{AM and harmonic-content modulation} \rightarrow \Delta\omega_0 \rightarrow \phi(t). \]

They explicitly associate tail-current flicker noise with the sensitivity of oscillation frequency to tail current, \[ K_{I_T\rightarrow\omega} = \frac{\partial\omega_{\mathrm{osc}}}{\partial I_T}. \] Thus, \[ S_{\phi}(\Delta f) \approx \frac{ \left| \partial\omega_{\mathrm{osc}}/\partial I_T \right|^2 S_{I_T}(\Delta f)} {(2\pi\Delta f)^2}. \] For \(S_{I_T}\propto1/\Delta f\), this produces \(S_\phi\propto1/\Delta f^3\).

Cross-coupled-pair flicker noise

Y. Hu, T. Siriburanon and R. B. Staszewski, "A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path," in IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1977-1987, July 2018 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8345650]

F. Pepe, A. Bonfanti, S. Levantino, C. Samori and A. L. Lacaita, "Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators," in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 6, pp. 2382-2394, June 2013 [https://sci-hub.jp/10.1109/TMTT.2013.2259257]

P. Andreani and A. Fard, "More on the 1/f2 Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2703-2712, Dec. 2006 [https://backend.orbit.dtu.dk/ws/files/3913656/Andreani.pdf]

Its central model is \[ i_{n,1/f}(t) = \alpha(t)n_{1/f}(t), \] where \(\alpha(t)\) represents the cyclostationary modulation of MOS flicker noise. The relevant phase-conversion function is then \[ \Gamma_{\mathrm{eff}}(t) = \Gamma(t)\alpha(t). \] The low-frequency noise produces first-order phase accumulation when \[ \Gamma_{\mathrm{eff,DC}} = \frac{1}{T_0} \int_0^{T_0} \Gamma_{\mathrm{eff}}(t)\,dt \neq 0. \]

Tail Capacitance Effect

Flicker noise of the tail transistor \[ M_{\mathrm{tail}}\text{ flicker} \rightarrow \Delta I_T \rightarrow \Delta A,\Delta H_n \rightarrow \Delta\omega_0. \]

Tail capacitance affecting pair flicker \[ C_T \rightarrow \text{asymmetric }i_{D1}(t) \rightarrow \Gamma_{\mathrm{eff,DC}}\neq0 \rightarrow M_{1,2}\text{ flicker upconversion}. \]

The tail capacitor is not itself a flicker-noise generator. It modifies the periodic operating point and breaks the cancellation of the cross-coupled pair’s flicker-noise-induced phase perturbations

Chembiyan's Phase Perturbation

Chembiyan T, "Brownian Motion And The Oscillator Phase Noise" [link]

—, "Jitter and Phase Noise in Oscillators" [link]

—, "Jitter and Phase Noise in Phase Locked Loops" [link]

—, "PLLs and reference spurs" [link]

w/ stationary noise with Gaussian PDF

If keep \(\phi_{rms}\) in \(R_x(\tau)\), i.e. \[ R_x(\tau)=\frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0 \tau)e^{R_\phi(\tau)}\approx \frac{A^2}{2}e^{-\phi_{rms}^2}\cos(2\pi f_0 \tau)(1+R_\phi(\tau)) \] The PSD of the signal is \[ S_x(f) = \mathcal{F} \{ R_x(\tau) \} = \frac{P_c}{2}e^{-\phi_{rms}^2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right] + \frac{P_c}{2}e^{-\phi_{rms}^2}\left[\delta(f+f_0)+\delta(f-f_0)\right] \] ❗❗above Eq isn't consistent with stationary white noise process - the following section

w/ stationary white noise

Assuming that the delay line is noiseless

Expanding the cosine function we get \[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D))E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi f_0(t+\tau/2-T_D))E[\sin(\phi(t)+\phi(t-\tau))] \right\} \end{align}\]

where, both the process \(\phi(t)-\phi(t-\tau)\) and \(\phi(t)+\phi(t-\tau)\) are independent of time \(t\), i.e. \(E[\cos(\phi(t)+\phi(t-\tau))] = m_{\cos+}(\tau)\), \(E[\cos(\phi(t)-\phi(t-\tau))] = m_{\cos-}(\tau)\), \(E[\sin(\phi(t)+\phi(t-\tau))] = m_{\sin+}(\tau)\) and \(E[\sin(\phi(t)-\phi(t-\tau))] = m_{\sin-}(\tau)\)

we obtain \[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) - \sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D))m_{\cos+}(\tau) - \sin(4\pi f_0(t+\tau/2-T_D))m_{\sin+}(\tau) \right\} \end{align}\]

The second term in the above expression is periodic in \(t\) and to estimate its PSD, we compute the time-averaged autocorrelation function \[ R_y(\tau) = \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)m_{\cos-}(\tau) - \sin(2\pi f_0\tau)m_{\sin-}(\tau)\right\} \]

After nontrivial derivation

w/ Weiner process

The phase process \(\phi(t)\) is also gaussian but with an increasing variance which grows linearly with time \(t\)

\[\begin{align} R_y(t,\tau) &= \frac{A^2}{2}\left\{\cos(2\pi f_0\tau)E[\cos(\phi(t)-\phi(t-\tau))] - \sin(2\pi f_0\tau)E[\sin(\phi(t)-\phi(t-\tau))]\right\} \\ &+ \frac{A^2}{2}\left\{\cos(4\pi f_0(t+\tau/2-T_D)E[\cos(\phi(t)+\phi(t-\tau))] - \sin(4\pi f_0(t+\tau/2-T_D)E[\sin(\phi(t)+\phi(t-\tau))] \right\} \end{align}\]

The spectrum of \(y(t)\) is determined by the asymptotic behavior of \(R_y(t,\tau)\) as \(t\to \infty\)

❗❗ \(\lim_{t\to\infty}R_y(t,\tau)\) rather than time-averaged autocorrelation function of cyclostationary process, ref. Demir's paper

We define \(\zeta(t, \tau)=\phi(t)+\phi(t-\tau) = \phi(t)-\phi(t-\tau) + 2\phi(t-\tau)\), the expected value of \(\zeta(t,\tau)\) is 0, the variance is \(\sigma_{\zeta}^2=(k\sigma)^2(\tau + 4(t-\tau))=(k\sigma)^2(4t-3\tau)\) \[ E[\cos(\zeta(t,\tau))]=\frac{1}{\sqrt{2\pi \sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\cos(\zeta)d\zeta = e^{-\sigma_{\zeta}^2/2}=e^{-(k\sigma)^2(4t-\tau)} \] i.e., \(\lim _{t\to \infty} E[\cos(\zeta(t,\tau))] = \lim_{t\to \infty}e^{-(k\sigma)^2(4t-\tau)} = 0\)

For \(E[\sin(\zeta(t,\tau))]\), we have \[ E[\sin(\zeta(t,\tau))] = \frac{1}{\sqrt{2\pi \sigma_{\zeta}^2}}\int_{-\infty}^{\infty}e^{-\zeta^2/2\sigma_{\zeta}^2}\sin(\zeta)d\zeta \] i.e., \(E[\sin(\zeta(t,\tau))]\) is odd function, therefore \(E[\sin(\zeta(t,\tau))]=0\)

Finally, we obtain

ISF & PPV Extraction

PPV values from pss/pnoise simulation in spectreRF [https://community.cadence.com/cadence_technology_forums/f/rf-design/35062/ppv-values-from-pss-pnoise-simulation-in-spectrerf]

ISF Function Extraction in Cadence Virtuoso [https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/43969/isf-function-extraction-in-cadence-virtuoso]

ISF from Transient Analysis

David Dolt. ECEN 620 Network Theory - Broadband Circuit Design: "VCO ISF Simulation" [https://people.engr.tamu.edu/spalermo/ecen620/ISF_SIM.pdf]

an injected current impulse with charge \(\Delta q=\int i(t)\,dt\), produces the permanent phase shift \[ \Delta\phi = \Gamma(\omega_0\tau)\frac{\Delta q}{q_{\max}}. \] Therefore, \[ \Gamma(\omega_0\tau) = \Delta\phi \frac{q_{\max}}{\Delta q}. \]

\[ \boxed{ \text{Same injected charge} \quad\Longrightarrow\quad \Delta\phi\propto\frac{\Gamma}{q_{\max}} } \] So:

• To compare actual robustness against equal charge impulses, compare \(\Delta\phi/\Delta q\)
• To compare the formal dimensionless ISFs, multiply each simulated phase response by its own \(q_{\max}/\Delta q\)

Aditya Varma Muppala, ISF Simulation in Cadence Using Transient Analysis | Oscillators 07 | MMIC 12 [https://youtu.be/yiMn2rCtTXY]

\[ h_{\phi}(t,{\tau}) = \frac{\Gamma(\omega_0{\tau})}{q_{\max}} u(t-\tau) \]

Therefore, \[ \boxed{ \Gamma(\omega_0{\tau}) = \frac{\Delta t}{T_0} \cdot 2\pi \cdot \frac{q_{\max}}{\Delta q} } \]

1. \(\Delta q\) should be:
   • not too small \(\rightarrow\) numerical error
   • not too large \(\rightarrow\) nonlinearity
2. \(\Delta t\) should be measured after the amplitude settles down (steady-state solution).
3. The impulse should be injected after the oscillator stabilizes.
4. The simulation step size used to measure \(\Delta t\) should be small.
5. The transient-simulation error tolerance should be small.

Use cross function to find zero crossing when impulse is off. Set significant digits to 16 and note down the value. \[ T_{i=0} = 15.62239156\times10^{-9} = 15.622\times10^{-9} + 0.39156\times10^{-12} \]

• Subtract it from the cross output. ADE output truncates it, so break it up into different unit scales.
• Check that the output is approximately zero before running sweeps.

Oscillator Injection Linearity

time shift by sweeping current pulse delay

Aditya Varma Muppala, Noise Modulation Function (NMF) Simulation in Cadence | Oscillators 08 | MMIC 13 [https://youtu.be/CvcLG9cSreg] [code]

source-specific ISF

For example, if MOS drain thermal noise is represented as a current source between drain and source, then the perturbation used to obtain the source-specific ISF should also be injected between those same drain and source nodes

NMF \(\alpha_{NMF}(t)\) shall work with the corresponding source-specific ISF/PPV

\[ \boxed{I_n(t)=4kT\gamma \cdot \textcolor{red}{g_m(t)} = 4kT\gamma \cdot \textcolor{red}{\alpha_{NMF} (t)g_{m,0}}} \]

ISF from PSS + Positive Sidebands of PXF

Hu, Yizhe, "Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 1962-1966, Dec. 2019 [https://sci-hub.ru/10.1109/TCSII.2019.2896483]

—. (2019). A Simulation Technique of Impulse Sensitivity Function (ISF) Based on Periodic Transfer Function (PXF). 10.13140/RG.2.2.32151.60323. [link]

—, "Oscillator Flicker Phase Noise: A Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 538-544, Feb. 2021 [paper] [slides]

Aditya Varma Muppala, Fast Simulation of ISF and PPV using PSS and PXF in Cadence | Oscillators 12 | MMIC 19 [video note code]

• freqaxis=in

  PXF preserves the signed input-frequency axis. Therefore, both positive- and negative-frequency input sidebands can be used directly to extract the ISF

• freqaxis=absin (default)

  Positive sidebands can be used directly. For negative sidebands, the PXF result corresponds to the Hermitian-symmetric positive-frequency response and must first be complex-conjugated; equivalently, retain its magnitude and reverse its phase

time reference between tran simulation and pss/pxf is different, that's why circshift is used.

1
2
3

ISF_Tran2 = interp1(time_Tran,-ISF_Tran{:,2},t);

plot(t/1e-9,circshift(ISF_Tran2,633),'--','LineWidth',3)

Complex Derivation of PXF from ISF

credits to chatgpt

Using a complex exponential representation gives the same result as the cosine derivation in the slides, provided the Fourier coefficient conventions are handled consistently.

1. Test Current

Instead of

\[ i_t(t)=I_t\cos\!\left((k\omega_0+\Delta\omega)t+\gamma_k\right), \]

use the analytic signal

\[ \tilde{i}_t(t) = I_t e^{j[(k\omega_0+\Delta\omega)t+\gamma_k]}. \]

2. Complex Fourier Series of ISF

The slide defines the real ISF as

\[ h_{DS}(t) = \frac12 h_0\cos\theta_0 + \sum_{m=1}^{\infty} h_m\cos(m\omega_0t+\theta_{h,m}). \]

Expressing it as a complex Fourier series,

\[ h_{DS}(t) = \sum_{m=-\infty}^{\infty} H_m e^{jm\omega_0t}, \]

gives

\[ H_{\pm m} = \frac{h_m}{2} e^{\pm j\theta_{h,m}}. \]

Hence

\[ H_{-k} = \frac{h_k}{2} e^{-j\theta_{h,k}}. \]

3. Phase Perturbation

The phase perturbation is

\[ \phi(t) = \int h_{DS}(t)i_t(t)\,dt. \]

Substituting the Fourier series,

\[ \phi(t) = I_t \sum_m \frac{H_m} {j[(m+k)\omega_0+\Delta\omega]} e^{j[(m+k)\omega_0+\Delta\omega]t}. \]

Only the slowly varying term contributes significantly, so choose

\[ m=-k, \]

which yields

\[ \boxed{ \phi(t) = \frac{I_tH_{-k}} {j\Delta\omega} e^{j(\Delta\omega t+\gamma_k)}. } \]

4. Oscillator Voltage

Represent the oscillator voltage as

\[ V_{DS} = V_{H1} e^{j(\omega_0t+\phi(t))}. \]

Using the small-angle approximation,

The small-angle approximation remains valid even if the phase perturbation is complex, provided its magnitude is small \(|\theta| \ll 1\)

\[ e^{j\phi}\approx1+j\phi, \]

gives

\[ V_{DS} \approx V_{H1}e^{j\omega_0t} + \frac{V_{H1}I_tH_{-k}} {\Delta\omega} e^{j(\omega_0+\Delta\omega)t}. \]

Therefore,

\[ \boxed{ H_{\mathrm{PXF}} = \frac{V_{H1}}{\Delta\omega} H_{-k}. } \]

5. Relation to the Slide

The fundamental drain voltage is

\[ v_{DS}(t) = V_{h1}\cos(\omega_0t+\theta), \]

whose complex coefficient is

\[ \boxed{ V_{H1} = \frac{V_{h1}}{2} e^{j\theta}. } \]

Since

\[ H_{-k} = \frac{h_k}{2} e^{-j\theta_{h,k}}, \]

we obtain

\[ H_{\mathrm{PXF}} = \frac{V_{h1}}{2\Delta\omega} \cdot \frac{h_k}{2} e^{j(\theta-\theta_{h,k})} = \frac{V_{h1}h_k} {4\Delta\omega} e^{j(\theta-\theta_{h,k})}. \]

Thus

\[ \boxed{ |H_{\mathrm{PXF}}| = \frac{V_{h1}h_k} {4\Delta\omega} } \]

and

\[ \boxed{ \angle H_{\mathrm{PXF}} = \theta-\theta_{h,k}. } \]

These are exactly Eqs. (6) and (7) in the slide.

Conclusion

The complex-exponential derivation is algebraically simpler than the cosine derivation. The only subtlety is the Fourier-series convention:

• Positive-frequency coefficient of a cosine: \[ H_k=\frac{h_k}{2}e^{j\theta_{h,k}}. \]

• Fundamental voltage phasor: \[ V_{H1}=\frac{V_{h1}}{2}e^{j\theta}. \]

Accounting for these \(1/2\) factors yields the identical PXF expression derived in the slides.

PPV from PSS inbuilt solver

Aditya Varma Muppala, Fast Simulation of ISF and PPV using PSS and PXF in Cadence | Oscillators 12 | MMIC 19 [https://youtu.be/Lu6VEWEEdxo]

TODO 📅

References

Jun Yin. ISSCC 2025 T10: mm-Wave Oscillator Design

Pietro Andreani. ISSCC 2011 T1: Integrated LC oscillators

—. ISSCC 2017 F2: Integrated Harmonic Oscillators

—. SSCS Distinguished Lecture: RF Harmonic Oscillators Integrated in Silicon Technologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-Toronto.pdf]

—. ESSCIRC 2019 Tutorials: RF Harmonic Oscillators Integrated in Silicon Technologies [https://youtu.be/k1I9nP9eEHE]

—. "Harmonic Oscillators in CMOS—A Tutorial Overview," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021 [pdf]

C. Samori, ISSCC2016 T1 "Tutorial: Understanding Phase Noise in LC VCOs"

—, "Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits," in IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 81-91, Fall 2016 [https://sci-hub.ru/10.1109/MSSC.2016.2573979]

—, Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/DL-VCO-short.pdf]

A. Hajimiri, RFIC2024 "Noise in Oscillators from Understanding to Design"

Antonio Liscidini, ESSCIRC 2019 Tutorials: Phase Noise in Wireless Applications [https://youtu.be/nGmQ0JdoSE4]

Aditya Varma Muppala. Oscillators [https://youtube.com/playlist?list=PL9Trid0A4Da2fOmYTEjhAnUkGPxyiH7H6&si]

P.E. Allen - 2003. ECE 6440 - Frequency Synthesizers: Lecture 160 – Phase Noise - II [https://pallen.ece.gatech.edu/Academic/ECE_6440/Summer_2003/L160-PhNoII(2UP).pdf]

Jaeha Kim. Lecture 8. Special Topics: Design Trade -Offs in LC -Tuned Oscillators

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007.

Darabi H. Radio Frequency Integrated Circuits and Systems. 2nd ed. Cambridge University Press; 2020.

Hegazi, Emad, Asad Abidi, and Jacob Rael. The Designer's Guide to High-purity Oscillators. [New York]: Kluwer Academic Publishers, 2005. The Designer's Guide to High-Purity Oscillators

Bae, Woorham, and Deog-Kyoon Jeong. Analysis and Design of CMOS Clocking Circuits for Low Phase Noise. Institution of Engineering and Technology, 2020.

M. Babaie, M. Shahmohammadi, R. B. Staszewski, (2019) "RF CMOS Oscillators for Modern Wireless Applications" River Publishers [https://www.riverpublishers.com/pdf/ebook/RP_E9788793609488.pdf]

• proportional term (P) depends on the present error
• integral term (I) depends on past errors
• derivative term (D) depends on anticipated future errors

PID controller makes use of linear extrapolation of the measured output

PI controller does not make use of any prediction of the future state of the system

The prediction by linear extrapolation (D) can generate large undesired control signals because measurement noise is amplified, that's why D is not used widely

---

The Problem of "Sinusoids Running Around Loops"

The representative of Fourier transform \(\frac{1}{j\omega+j\omega_0}\) back in the time domain \(e^{-j\omega_0 t}\) is infinite extent in time

Running around a loop, chasing one's tail — these are thought pictures that only work in a discretized, time-sequenced conceptual framework that has a beginning and an end

Fix in your mind that oscillations are a type of resonance

System Type

Control of Steady-State Error to Polynomial Inputs: System Type

control systems are assigned a type number according to the maximum degree of the input polynominal for which the steady-state error is a finite constant. i.e.

• Type 0: Finite error to a step (position error)
• Type 1: Finite error to a ramp (velocity error)
• Type 2: Finite error to a parabola (acceleration error)

If we consider tracking the reference input alone and set \(W = V = 0\)

The open-loop transfer function can be expressed as \[ T(s) = \frac{K_n(s)}{s^n} \]

where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),

The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform is \[ R(s) = \frac{1}{s^{k+1}} \]

Then the equation for the error, \(R(s)-Y(s)\) is simply \[ E(s) = \frac{1}{1+T(s)}R(s) \]

Application of the Final Value Theorem to the error formula gives the result

\[\begin{align} \lim _{t\to \infty} e(t) &= e_{ss} = \lim _{s\to 0} sE(s) \\ &= \lim _{s\to 0} s\frac{1}{1+\frac{K_n(s)}{s^n}}\frac{1}{s^{k+1}} \\ &= \lim _{s\to 0} \frac{s^n}{s^n + K_n}\frac{1}{s^k} \end{align}\]

• if \(n > k\), \(e=0\)
• if \(n < k\), \(e\to \infty\)
• if \(n=k\)
  • \(e_{ss} = \frac{1}{1+K_n}\) if \(n=k=0\)
  • \(e_{ss} = \frac{1}{K_n}\) if \(n=k \neq 0\)​

where we define \(K_n(0) = K_n\)

rearrangement

The closed loop transfer function of \(Y/X\) and \(Y_1/X_1\) are almost same, except sign

\[\begin{align} \frac{Y}{X} &= +\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \\ \frac{Y_1}{X_1} &= -\frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \end{align}\]

define \(-Y_1=Y_n\), then \[ \frac{Y_n}{X_1} = \frac{H_1(s)H_2(s)}{1+H_1(s)H_2(s)} \]

Saurabh Saxena, IIT Madras. CICC2022 Clocking for Serial Links - Frequency and Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery

Effect of Feedback on Noise

Feedback does not improve the noise performance of circuits.

The input-referred noise voltage and current remain the same if the feedback network introduces no noise

derivative control

Introduction: PID Controller Design. [https://ctms.engin.umich.edu/CTMS/?example=Introduction&section=ControlPID]

Stability Criterion

Barkhausen criteria

Barkhausen criteria are necessary but not sufficient conditions for sustainable oscillations

it simply "latches up" rather than oscillates

Nyquist Stability Criterion

Michael H. Perrott, High Speed Communication Circuits and Systems, Lecture 15 Integer-N Frequency Synthesizers[https://www.cppsim.com/CommCircuitLectures/lec15.pdf]

Zoran Gajic. Nyquist Stability Criterion [https://eceweb1.rutgers.edu/~gajic/psfiles/nyquist.pdf]

TODO 📅

Root-Locus Techniques

closed-loop system

Mason's Gain Rule

Rick Lyons, Using Mason's Rule to Analyze DSP Networks [https://www.dsprelated.com/showarticle/76.php]

Mason's gain formula (MGF) is a method for finding the transfer function of a linear signal-flow graph (SFG).

TODO 📅

reference

Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. Feedback Control of Dynamic Systems, Global Edition (8th Edition). Pearson. [pdf]

Åström, K.J. & Murray, Richard. (2021). Feedback Systems: An Introduction for Scientists and Engineers Second Edition [pdf]

Dawson, Joel L. A Guide to Feedback Theory. Cambridge: Cambridge University Press, 2021. [pdf]

Yan Lu, ISSCC2021 T10: Fundamentals of Fully Integrated Voltage Regulators

Jens Anders (University of Stuttgart, DE). ESSERC2025 Circuits Insights: The Magic of Feedback in Analog Circuit Design [https://youtu.be/NyXuA6WZ8Hg]

charge pumps are capacitive DC-DC converters. The two most common switched capacitor voltage converters are the voltage inverter and the voltage doubler circuit

voltage doubler

output buffer capacitor

To achieve a stable DC output voltage

Step-Wise Ramp-Up

\[ V_{in} C_p + V_{out,n-1}C_o = (V_{out,n}-V_{in})C_p + V_{out,n}C_o \]

We derive a recursive equation that describes the output voltage \(V_{out,n}\) after the \(n\)th clock cycle \[ V_{out,n} = \frac{2V_{in}C_p + V_{out,n-1}C_o}{C_p + C_o} \]

Voltage Ripple & Droop

\[\begin{align} (V_t - V_h)(C_p + C_o) &= \frac{I_{load}}{2f_{sw}} \\ (V_h - V_b)C_o &= \frac{I_{load}}{2f_{sw}} \end{align}\]

we obtain \[ V_t - V_b = \frac{I_{load}}{f_{sw}C_o}\left(1 - \frac{C_p}{2(C_p + C_o)}\right) \] That is, peak-to-peak ripple \[ \Delta V_{out,p2p} \approx \frac{I_{load}}{f_{sw}C_o} \space\space\space\space \text{if}\space\space C_o \gg C_p \]

Then, with aforementioned Step-Wise Ramp-Up equation, \(V_t = \frac{2V_{in}C_p + V_bC_o}{C_p + C_o}\) \[\begin{align} V_b &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p}{2C_o}\right) \\ V_t &= 2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 - \frac{C_p}{2(C_p+C_o)}\right) \end{align}\]

Therefore, average output voltage \(\overline{V}_{out}\) in steady-state is \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}}{f_{sw}C_p}\left(1 + \frac{C_p^2}{4C_o(C_p+C_o)}\right) \approx 2V_{in} - \frac{I_{load}}{f_{sw}C_p} \] which results in a simple expression for the output voltage droop

\[ \Delta V_{out} = \frac{I_{load}}{f_{sw}C_p} \]

The charge pump can be modeled as a voltage source with a source resistance \(R_\text{out}\). Therefore, \(\Delta V_{out}\) can be seen as the voltage drop across \(R_\text{out}\) due to the load current:

\[ R_{out} = \frac{\Delta V_{out}}{I_{load}} = \frac{1}{f_{sw}C_p} \]

multiphase CP

\[ (V_t - V_b) (C_p + C_o) = I_{load}\Delta t \]

Therefore peak-to-peak ripple \[ \Delta V_{out,p2p} = \frac{I_{load}\Delta t}{C_p+C_o} = \frac{I_{load}\Delta t}{C_{tot}} \]

where \(C_{tot} = C_p+C_o\)

with \[ \left\{ \begin{array}{cl} V_b &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} \\ V_t &= 2V_{in} - \frac{I_{load}\Delta t}{C_p} + \frac{I_{load}\Delta t}{C_p+C_o} \end{array} \right. \]

Then \[ \overline{V}_{out} = \frac{V_t+V_b}{2}=2V_{in} - \frac{I_{load}\Delta t}{C_p}\cdot \frac{C_p+2C_o}{2C_p+2C_o} \approx 2V_{in} - \frac{I_{load}\Delta t}{C_p} \] That is output voltage droop \[ \Delta V_{out} = \frac{I_{load}\Delta t}{C_p} \]

reference

Bernhard Wicht, "Design of Power Management Integrated Circuits". 2024 Wiley-IEEE Press

Breussegem, T. v., & Steyaert, M. (2013). CMOS integrated capacitive DC-DC converters. Springer

Zhang, Milin, Zhihua Wang, Jan van der Spiegel and Franco Maloberti. "Advanced Tutorial on Analog Circuit Design." (2023).

Anton Bakker, Tim Piessens., ISSCC2014 T9: Charge Pump and Capacitive DC-DC Converter Design

Wicht, B., ISSCC2020 T2: Analog Building Blocks of DC-DC Converters [https://www.nishanchettri.com/isscc-slides/2020%20ISSCC/TUTORIALS/T2Visuals.pdf]

Hoi Lee, ISSCC2018 T8: Fundamentals of Switched-Mode Power Converter Design [slides,transcript]

G. Palumbo and D. Pappalardo, "Charge Pump Circuits: An Overview on Design Strategies and Topologies," in IEEE Circuits and Systems Magazine, vol. 10, no. 1, pp. 31-45, First Quarter 2010 [pdf]

alternative view of sampling, assuming DC value is \(A\)

• \(x_c(t)\) and \(x_s(t)\)

  \(\overline{x_c} = A\); \(\overline{x_s}=\frac{A}{T}\): therefore \(X_s(j0) = \frac{1}{T}X_c(j0)\)

• \(x[n]\) and \(x_d[n]\)

  \(\overline{x} = A\); \(\overline{x_d}=\frac{A}{2}\): therefore \(X_d(e^{j0}) = \frac{1}{2}X(e^{j0})\)

expander

• \(x[n]\) and \(x_e[n]\)

  \(\overline{x} = A\); \(\overline{x_e}=A\): therefore \(X_e(e^{j0}) = X(e^{j0})\)

  Fourier transform of the output of the expander is a frequency-scaled version of the Fourier transform of the input

Subsampling or Downsampling

• Eqs. (4.72)

  the superposition of an infinite set of amplitude-scaled copies of \(X_c(j\Omega)\), frequency scaled through \(\omega = \Omega T_d\) and shifted by integer multiples of \(2\pi\)

• Eq. (4.77)

  the superposition of \(M\) amplitude-scaled copies of the periodic Fourier transform \(X (e^{j\omega})\), frequency scaled by \(M\) and shifted by integer multiples of \(2\pi\)

downsampled by a factor of \(M = 2\)

Upsampling or Zero Insertion

Rouphael, Tony. (2009). RF and Digital Signal Processing for Software-Defined Radio. [pdf]

Assuming \(X(e^{j\omega_1}) = U_f(e^{j\omega_1})\) with \(\omega_1 = \Omega T_1\), upsampled by ratio \(L\), then obtain

\[ Y(e^{j\omega_2})=X(e^{j\omega_2 L}) = U_f(e^{j\omega_2 L}) \]

by EQ. (4.85), i.e. substitute \(\omega_1\) with \(\omega_2 L\), where with \(\omega_2 = \Omega T_2\) and \(T_2 L = T_1\)

Provided that \(\xi = e^{j\omega_1}\) and \(z = e^{j\omega_2}\), we have \(U_f(\xi)\) upsampled to \(U_f(z^L)\)

Interpolation filter

Pavan, Schreier and Temes, "Understanding Delta-Sigma Data Converters, Second Edition"

Markus Nentwig. Polyphase filter / Farrows interpolation [https://www.dsprelated.com/showarticle/22.php]

sampling identities

downsampling identity

upsampling identity

up/down-sampling cascading

In general,

\[ \boxed{\downarrow N\;\rightarrow\;\uparrow N \neq \text{identity}} \]

while

\[ \boxed{\uparrow N\;\rightarrow\;\downarrow N = \text{identity}} \]

a useful way to remember the asymmetry:

\[ \boxed{ \uparrow N\rightarrow\downarrow N: \quad \text{insert zeros, then remove those zeros} \Rightarrow x[n] } \]

but

\[ \boxed{ \downarrow N\rightarrow\uparrow N: \quad \text{remove real samples, then insert zeros} \Rightarrow \text{information lost}. } \]

If you put an ideal anti-aliasing filter before downsampling and an ideal interpolation filter after upsampling, then for a sufficiently bandlimited signal you can reconstruct the original signal. That case is where the apparent \(N\) or \(1/N\) gain factors become especially important.

For \(y[n]=x[Nn],\) the DTFT is

\[ \boxed{ Y(e^{j\omega}) = \frac{1}{N} \sum_{k=0}^{N-1} X\left(e^{j(\omega+2\pi k)/N}\right) } \]

so the \(1/N\) appears explicitly.

But this doesn't mean downsampling has a physical gain of \(1/N\). The \(N\) compressed/shifted spectral copies are summed

assuming the downsampler keeps the samples inserted at multiples of \(N\).

For example, let \(N=2\):

\[ x[n]=[a,b,c,d,e,f,\ldots] \]

Downsample by 2:

\[ x_d[n]=[a,c,e,\ldots] \]

Then upsample by 2:

\[ y[n]=[a,0,c,0,e,0,\ldots] \]

Clearly,

\[ \boxed{y[n]\neq x[n]} \]

The information in \(b,d,f,\ldots\) was destroyed by the downsampler. Upsampling cannot reconstruct it; it only inserts zeros.

In fact, the cascade is

\[ \boxed{ y[n]= \begin{cases} x[n], & n=0,\pm N,\pm2N,\ldots\\ 0, & \text{otherwise}. \end{cases}} \]

Time domain

The cascade multiplies \(x[n]\) by an impulse train:

\[ y[n]=x[n]\,c_N[n],\qquad c_N[n]=\sum_{r=-\infty}^{\infty}\delta[n-rN] \]

The useful trick is to write that comb as a sum of complex exponentials (a DFT identity):

\[ c_N[n]=\frac{1}{N}\sum_{k=0}^{N-1}e^{j2\pi kn/N}=\frac{1}{N}\sum_{k=0}^{N-1}W_N^{-kn},\qquad W_N\triangleq e^{-j2\pi/N} \]

So the cascade is a modulation by \(N\) carriers, which is exactly where the aliasing comes from.

\(z\) domain \[ Y(z)=\sum_n x[n]c_N[n]z^{-n}=\frac{1}{N}\sum_{k=0}^{N-1}\sum_n x[n]\big(zW_N^{k}\big)^{-n} \]

\[ \boxed{\;Y(z)=\frac{1}{N}\sum_{k=0}^{N-1}X\!\left(zW_N^{k}\right)=\frac{1}{N}\sum_{k=0}^{N-1}X\!\left(z\,e^{-j2\pi k/N}\right)\;} \]

You get the same thing by composing the two stages. Decimation by \(N\):

\[ V(z)=\frac{1}{N}\sum_{k=0}^{N-1}X\!\left(z^{1/N}W_N^{k}\right) \]

Expansion by \(N\) just substitutes \(z\to z^N\):

\[ Y(z)=V(z^N)=\frac{1}{N}\sum_{k=0}^{N-1}X\!\left(zW_N^{k}\right) \]

L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S. Levantino and C. Samori, "A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2775-2786, July 2021 [https://sci-hub.st/10.1109/TCSI.2021.3072344]

↑N followed immediately by \(\downarrow N\) is identity

Start with \(x[n]\)

Upsample:

\[ x_u[n]= \begin{cases} x[n/N],&n=N k\\ 0,&\text{otherwise}. \end{cases} \]

Then downsample:

\[ y[n]=x_u[Nn] \]

Therefore

\[ \boxed{y[n]=x[n]} \]

So

\[ \boxed{ x[n]\xrightarrow{\uparrow N}\xrightarrow{\downarrow N}x[n] } \]

has total gain 1, not \(1/N\).

The frequency-domain formula confirms this. After upsampling,

\[ X_u(e^{j\omega})=X(e^{jN\omega}) \]

Then downsampling gives

\[ \begin{aligned} Y(e^{j\omega}) &= \frac1N \sum_{k=0}^{N-1} X_u\left(e^{j(\omega+2\pi k)/N}\right)\\ &= \frac1N \sum_{k=0}^{N-1} X\left(e^{jN(\omega+2\pi k)/N}\right)\\ &= \frac1N \sum_{k=0}^{N-1} X(e^{j(\omega+2\pi k)}). \end{aligned} \]

Because the DTFT is \(2\pi\)-periodic,

\[ X(e^{j(\omega+2\pi k)})=X(e^{j\omega}) \]

so

\[ Y(e^{j\omega}) = \frac1N \underbrace{\sum_{k=0}^{N-1}X(e^{j\omega})}_{N\text{ identical terms}} = \boxed{X(e^{j\omega})} \]

So the apparent \(1/N\) is exactly canceled by the \(N\) spectral copies being summed.

Polyphase Decomposition

Polyphase decomposition is a powerful technique used in digital signal processing to efficiently implement multirate systems.

where \(e_k[n]=h[nM+k]\)

Polyphase Implementation of Decimation Filters & Interpolation Filters

	Decimation system	Interpolation system
sampling identity

LPTV Implementation

TODO 📅

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a zero-order hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

Dr. Deepa Kundur, Multirate Digital Signal Processing: Part I [pdf, https://www.comm.utoronto.ca/dkundur/course/discrete-time-systems/]

ZOH interpolator

The interpolation filter following an up-sampler generally is time varying and cannot be represented by a simple transfer function. The equivalent filter in a Zero-Order Hold is an exception, perhaps unique, that can be represented with a time-invariant transfer function

\[ F_1(z) = X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \]

Split the \(1:LM\) hold process into a \(1 : L\) hold followed by a \(1 : M\) hold \[ Y(\eta)=X(\eta^{L})\frac{1-\eta^{-L}}{1-\eta^{-1}} \] then \[\begin{align} F_2(z) &= Y(z^M)\cdot\frac{1-z^{-M}}{1-z^{-1}} \\ &=X(z^{LM})\frac{1-z^{-LM}}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &= X(z^{LM})\frac{1-z^{-LM}}{1-z^{-1}} \end{align}\]

That is \(F_1(z)=F_2(z)\), i.e. they are equivalent

Random Signals & Multirate Systems

Balu Santhanam, Probability Theory & Stochastic Process 2020: Random Signals & Multirate Systems [https://ece-research.unm.edu/bsanthan/ece541/rand.pdf]

Decimation by Summing

proportional path

The loop gain of a proportional path is unchanged

In (a), the loop gain is \(\frac{\phi_o(z)}{\phi_e(z)}\), which is \[ LG_a(z)=\frac{\phi_o(z)}{\phi_e(z)} = \frac{1}{1-z^{-1}} \]

In (b), Accumulate-And-Dump (AAD) is \(\frac{1-z^{-L}}{1-z^{-1}}\), then \(\phi_m(\eta)\) can be expressed as \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \] Hence \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \frac{1}{1-\eta^{-1}} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L}\cdot \frac{1}{1-\eta^{-1}} \end{align}\]

After zero-order hold process, we obtain \(\phi_f(z)\), which is \[\begin{align} \phi_f(z) &= \phi_o(z^L) \cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &=\frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{1-z^{-L}}\cdot \frac{1-z^{-L}}{1-z^{-1}} \end{align}\] i.e., \[ LG_b(z) = \frac{1}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \]

When bandwidth is much less than sampling rate (data rate), \(\frac{1}{L}\cdot \frac{1-z^{-L}}{1-z^{-1}} \approx 1\)

Therefore \[ LG_b(z) \approx \frac{1}{1-z^{-1}} \]

In the end \[ LG_a(z) \approx LG_b(z) \]

Assume PD output is constant

integral path

integral path gain reduced by \(L\)

In (a), \(\phi_o(z)=\frac{1}{(1-z^{-1})^2}\), i.e. \[ LG_a(z) = \frac{1}{(1-z^{-1})^2} \]

In (b), after Accumulate-And-Dump (AAD), \(\phi(\eta)\) is \[ \phi_m(\eta) = \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \]

After frequency integrator and phase integrator \[\begin{align} \phi_o(\eta) &= \phi_m(\eta) \cdot \frac{1}{(1-\eta^{-1})^2} \\ &= \frac{1-\eta^{-1}}{1-\eta^{-1/L}}\cdot \frac{1}{L} \cdot \frac{1}{(1-\eta^{-1})^2} \end{align}\] Then \(\phi_f(z)\) is shown as below \[\begin{align} \phi_f(z) &= \phi_o(z^L)\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1-z^{-L}}{1-z^{-1}}\cdot \frac{1}{L}\cdot \frac{1}{(1-z^{-L})^2}\cdot \frac{1-z^{-L}}{1-z^{-1}} \\ &= \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} \end{align}\]

That is, \[ LG_b(z) = \frac{1}{L} \cdot \frac{1}{(1-z^{-1})^2} = \frac{1}{L}\cdot LG_a(z) \]

Assume PD output is constant

\[ \lim_{n\to +\infty} \frac{\Delta P_1}{\Delta P_0} = \lim_{n\to +\infty}\frac{n+2L}{nL+\alpha L+\beta L^2} = \frac{1}{L} \]

Decimation by Voting

In above screenshot

1. \(K_D\) is just relative value
2. frug shall not be scaled by decimator factor

proved as below

DC gain \(K_B\) of summing (boxcar filter) is decimation factor \(M\) , voting gain \(K_V\) is about \(0.54K_b=0.54M\)

1. downsampling \(\frac{1}{M}\) and ZOH \(\frac{1-z^{-M}}{1-z^{-1}}\) can be canceled out at low frequency
2. decimation gain: accumulator \(\frac{1-z^{-M}}{1-z^{-1}}\) replaced with linearizing gain \(K_B\) and majority voting replaced with \(K_V\)

proportional path: \[\begin{align} LG_{ph} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{1-z^{-M}}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{1-z^{-M}} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{1-z^{-M}} \end{align}\]

integral path: \[\begin{align} LG_{fr} &= K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{M}\cdot \frac{1}{(1-z^{-M})^2}\cdot \frac{1-z^{-M}}{1-z^{-1}} \\ &\approx K_{BB}\cdot \frac{1-z^{-M}}{1-z^{-1}}\cdot \frac{1}{(1-z^{-M})^2} \\ &= K_{BB}\cdot K_D\cdot \frac{1}{(1-z^{-M})^2} \end{align}\]

Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12 [https://sci-hub.se/10.1109/TMTT.2020.3029188]

J. Liang, A. Sheikholeslami, "On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits" [https://tspace.library.utoronto.ca/bitstream/1807/91138/3/Liang_Joshua_201706_PhD_thesis.pdf]

J. Liang, A. Sheikholeslami. ISSCC2017. "A 28Gbps Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance" [slides,paper]

J. Liang, A. Sheikholeslami,, "Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs," in IEEE Journal of Solid-State Circuits [https://sci-hub.se/10.1109/JSSC.2018.2839038]

M. M. Khanghah, K. D. Sadeghipour, D. Kelly, C. Antony, P. Ossieur and P. D. Townsend, "A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers [https://cora.ucc.ie/bitstreams/7ae5bfaa-8dd9-45a7-8276-99676b7b6078/download]

[CDR CIRCUIT-BLOCKS: DESIGN AND VERIFICATION USING VERILOG - 2.6. DECIMATOR]

Michael H. Perrott, Tutorial on Digital Phase-Locked Loops, CICC 2009, San Jose, CA, Sept. 13, 2009 [https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf]

Liu, Tao, Tiejun Li, Fangxu Lv, Bin Liang, Xuqiang Zheng, Heming Wang, Miaomiao Wu, Dechao Lu, and Feng Zhao. 2021. "Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits" Electronics 10 [https://www.mdpi.com/2079-9292/10/16/1888/pdf?version=1628492599]

Gu, Youzhi & Feng, Xinjie & Chi, Runze & Chen, Yongzhen & Wu, Jiangfeng. (2022). Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model. 10.21203/rs.3.rs-1817774/v1. [https://assets-eu.researchsquare.com/files/rs-1817774/v1_covered.pdf?c=1664188179]

Chen, Junkun, Youzhi Gu, Xinjie Feng, Runze Chi, Jiangfeng Wu, and Yongzhen Chen. 2024. "Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model" Electronics [https://mdpi-res.com/electronics/electronics-13-04218/article_deploy/electronics-13-04218-v2.pdf?version=1730106095]

K. Yadav, P. -H. Hsieh and A. C. Carusone, "Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System," in IEEE Open Journal of Circuits and Systems [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9910561]

TODO 📅

Tristate: \(\alpha=1\)

XOR: \(\alpha=1\)

\(\frac{1}{T}\) in Divider

Michael H. Perrott, PLL Design Using the PLL Design Assistant Program. [https://designers-guide.org/forum/Attachments/pll_manual.pdf]

\(\frac{1}{T}\) & \(T\) come from CT-DT & DT-CT

H. Kang et al., "A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS," in IEEE Access, vol. 12, pp. 109900-109911, 2024 [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10630516]

Sonntag JSSC 2006

J. L. Sonntag and J. Stonick, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links," in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006 [https://sci-hub.se/10.1109/JSSC.2006.875292]

—, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.. [https://sci-hub.se/10.1109/CICC.2005.1568725]

J. Stonick. ISSCC 2011 tutorials, T5: "DPLL-Based Clock and Data Recovery"

Phase transfer function

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clear;
close all;
clc;


Tb = 200e-12;
Ts = Tb*8;			% the decimation factor was 8
z = tf('z', Ts);

Kdpc = 1/2^9;
Kv = 8*0.54;
Kpd = 10.6;
phug = 2^-3;
frug = 2^-12;
Nel = 18;

options = bodeoptions;
options.FreqUnits = 'MHz';
options.XLim = [1e-2, 1e1];
options.YLim = [-10, 5];

L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-11;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

hold on;
frug = 2^-10;
L = Kpd*Kv*Kdpc/(1-z^-1)*(phug + frug/(1-z^-1))*z^-Nel;
TF = L/(1+L);
bodemag(TF,options);

legend('frug=2^{-12}','frug=2^{-11}', 'frug=2^{-10}', 'FontSize',10)
grid on;
title('phase transfer function', 'FontSize', 12)
xlabel('frequency', 'FontSize',10)
ylabel('frequency response', 'FontSize',10)

Full View

Offsets in Phase Slicer

dead zone, p_n always 0 whether early or late!!!

TODO 📅

Kpd, Kb, Kv

• Kpd formula: 12.467; Kpd_bb_0 12.465
• Kpd_Kb: 49.860; Kpd_Kv 27.265
• Kb: 4.00; Kv 2.19

That is

1. gain of BoxCar is the decimation factor
2. Voting across 4 inputs had a 54% reduced gain relative to boxcar filter

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import numpy as np
from scipy.stats import norm
import itertools
from tqdm import tqdm
import matplotlib.pyplot as plt

sigmai = 0.032  #UI, input jitter
Ptrans = 0.5    # Transition density
deci_factor = 4

phase_error = np.linspace(-0.1, 0.1, 201)     #UI, phase offset
pd_late = norm.cdf(phase_error/sigmai)
pd_early = 1.0 - pd_late
pd_avg = pd_late*1.0 - 1.0*pd_early

Kpd_bb = (pd_avg[1:] - pd_avg[:-1])/(phase_error[1:] - phase_error[:-1])*Ptrans
Kpd_bb_0 = np.max(Kpd_bb)

## by formula
Kpd_calc = 1.0/(sigmai*np.sqrt(2*np.pi))

print(f'Kpd formula: {Kpd_calc:.3f}; Kpd_bb_0 {Kpd_bb_0:.3f}')  # Kpd formula: 12.467; Kpd_bb_0 12.465

plt.figure()
plt.plot(phase_error, pd_avg, color='r', linewidth=3)
plt.title('!! PD average output vs timing offset(UI)')
plt.grid()
plt.show()


prob = np.zeros((phase_error.shape[0],3))
prob[:,0] = pd_early*Ptrans     # -1
prob[:,1] = 1.0 - Ptrans        # 0
prob[:,2] = pd_late*Ptrans      # 1

pd_out = np.array([-1.0,0.0,1.0])
idxs = list([[0,1,2] for _ in range(deci_factor)])
boxcar_avg = []
voting_avg = []
for i in tqdm(range(phase_error.shape[0])):
    prob_i = prob[i,:]
    boxcar_tmp = 0.0
    voting_tmp = 0.0
    for idxs_tmp in itertools.product(*idxs):
        pd_list = pd_out[[idxs_tmp]]
        prob_list = prob_i[[idxs_tmp]]
        pd_sum = np.sum(pd_list)
        pd_vote = 1.0 if pd_sum > 0.0 else -1.0 if pd_sum <0.0 else 0.0
        prob_prod = np.prod(prob_list)
        boxcar_tmp += pd_sum*prob_prod
        voting_tmp += pd_vote*prob_prod
    boxcar_avg.append(boxcar_tmp)
    voting_avg.append(voting_tmp)

boxcar_avg = np.array(boxcar_avg)
voting_avg = np.array(voting_avg)

plt.figure()
plt.plot(phase_error,boxcar_avg, label='FIR BoxCar', color='r', linewidth=3)
plt.plot(phase_error,voting_avg, label='Voting', color='b', linewidth=3, linestyle='--')
plt.legend()
plt.title('!!PD+BoxCar / !!PD+Voting vs timing offset(UI)')
plt.grid()
plt.show()


Kpd_Kb = (boxcar_avg[1:] - boxcar_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_Kv = (voting_avg[1:] - voting_avg[:-1])/(phase_error[1:] - phase_error[:-1])
Kpd_kb_0 = np.max(Kpd_Kb)
Kpd_kv_0 = np.max(Kpd_Kv)
print(f'Kpd_Kb: {Kpd_kb_0:.3f}; Kpd_Kv {Kpd_kv_0:.3f}')     # Kpd_Kb: 49.860; Kpd_Kv 27.265

plt.figure()
plt.plot(phase_error[:-1], Kpd_Kb, color='r', linewidth=3)
plt.plot(phase_error[:-1], Kpd_Kv, color='b', linewidth=3, linestyle='--')
plt.legend(['Kpd_Kb', 'Kpd_Kv'])
plt.title('Kpd*Kb / Kpd*Kv vs timing offset(UI)')
plt.grid()
plt.show()

Kb = Kpd_kb_0 / Kpd_bb_0
Kv = Kpd_kv_0 / Kpd_bb_0
print(f'Kb: {Kb:.2f}; Kv {Kv:.2f}')     # Kb: 4.00; Kv 2.19

with deci_factor = 8

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Kpd formula: 12.467; Kpd_bb_0 12.465
Kpd_Kb: 99.719; Kpd_Kv 39.155
Kb: 8.00; Kv 3.14

with deci_factor = 16

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Kpd formula: 12.467; Kpd_bb_0 12.465
Kpd_Kb: 199.439; Kpd_Kv 55.784
Kb: 16.00; Kv 4.48

reference

Alan V Oppenheim, Ronald W. Schafer. 2010. Discrete-Time Signal Processing, 3rd edition

R. E. Crochiere and L. R. Rabiner, "Multirate Digital Signal Processing", Prentice Hall, 1983.

John G. Proakis and Dimitris G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th edition, 2007.

D. Sundararajan. 2024. Digital Signal Processing: An Introduction 2nd Edition

F. M. Gardner, "Phaselock Techniques", 3rd Edition, Wiley Interscience, Hoboken, NJ, 2005 [https://picture.iczhiku.com/resource/eetop/WyIgwGtkDSWGSxnm.pdf]

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Qasim Chaudhari. Sample Rate Conversion [https://wirelesspi.com/sample-rate-conversion/]

Push-Pull

TODO 📅

Rinaldo Castello, "LINEARIZATION TECHNIQUES FOR PUSH-PULL AMPLIFIERS" [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/AMPLIFIERS_Stanf_Tor_2016_Last.pdf]

Rail-to-Rail Op amp

[https://mixsignal.wordpress.com/wp-content/uploads/2013/03/689-604rail2rail.pdf]

[https://toshiba.semicon-storage.com/ap-en/semiconductor/knowledge/faq/linear_opamp/what-does-rail-to-rail-mean.html]

TODO 📅

self-biased active loading

Vishal Saxena "CMOS Comparator Design Extra Slides" [https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Comparator%20Slides.pdf]

W. Liu, P. Huang and Y. Chiu, "A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2010 [https://sci-hub.se/10.1109/ISSCC.2010.5433830]

Slewing in Folded-Cascode Op Amps

In practice, we choose \(I_P \simeq I_{SS}\)

Avoid zero current in cascodes

• left circuit

  \(I_b \gt I_a\)

• right circuit

  \(I_b \gt 2I_a\)

Huijsing, J. H. (2017). Operational Amplifiers: Theory and Design. (3 ed.) Springer

[https://bbs.eetop.cn/forum.php?mod=redirect&goto=findpost&ptid=995502&pid=11548528]

Response Speed in Analog Circuits

Hyun-Sik Kim, KAIST, A-SSCC 2024 Circuit Insights: FT3 Accelerating Response Speed in Analog Circuits [link]

Bandwidth limitation

slew rate limitation

Assuming linear response \[ V_o(t) = 1 - e^{-\omega_T t} \]

\[ \frac{\mathrm{d}V_o}{\mathrm{d}t} = \omega_Te^{-\omega_T t} = \frac{g_m}{C_L}e^{-\omega_T t} = \frac{g_m}{I_B}\cdot \frac{I_B}{C_L}\cdot e^{-\omega_T t} \gt \frac{I_B}{C_L} \]

where \(\frac{g_m}{I_B} e^{-\omega_T t} \gt 1\) at initial response

Therefore, initial response speed is dominated by SR, rather than \(G_m\) (or bandwidth)

MOS parasitic Rd&Rs, Cd&Cs

Decrease the parasitic R&C

priority: \(R_s \gt R_d\), \(C_s \gt C_d\)

source follower

A. Sheikholeslami, "Voltage Follower, Part 1 [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 14, no. 3, pp. 13-15, Summer 2022, doi: 10.1109/MSSC.2022.3182791

—, "Voltage Follower, Part II [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 1, pp. 17-19, winter 2023, doi: 10.1109/MSSC.2022.3218083

—, "Voltage Follower, Part III [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 2, pp. 14-26, Spring 2023, doi: 10.1109/MSSC.2023.3269457

—, "Voltage Follower, Part IV [Circuit Intuitions]," in IEEE Solid-State Circuits Magazine, vol. 15, no. 3, pp. 6-19, Summer 2023, doi: 10.1109/MSSC.2023.3287342

—, ESSCIRC2023 Circuit Insights [https://youtu.be/2xFIZM5_FPw]

—, CICC2025 Circuit Insights: From Simple to Super Source Follower [https://youtu.be/CWfMKltPIQ8]

Paul R. Gray. 2009. Analysis and Design of Analog Integrated Circuits (5th. ed.). Wiley Publishing.

Flipped Voltage Follower (FVF)

[https://www.linkedin.com/posts/chembiyan-t-0b34b910_flipped-voltage-follower-fvf-basics-activity-7118482840803020800-qwyX?utm_source=share&utm_medium=member_desktop]

Z. Guo et al., "A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 116-118, doi: 10.1109/ISSCC42614.2022.9731650.

moving the current source from the source to the drain is referred to as flipping, and hence the name FVF

T&H buffer in ADC

\[ \boxed{G_m = g_{m1} r_{o1}\cdot g_{m2} \qquad \qquad R_{out} = \frac{1}{g_{m1}r_{o1}\cdot g_{m2}}} \]

FVF exhibits a much-reduced output resistance (by a factor of gr mo) while maintaining the same voltage gain as that of an SVF (simple voltage follower)

Super-source follower (SSF)

class AB SSF (AB-SSF)

A major limitation shared by all three designs is an asymmetry in response to a sudden rise/fall of an input waveform

\[ SR^+_{SVF} \gt SR^-_{SVF} \qquad \qquad SR^+_{FVF} \lt SR^-_{FVF} \qquad \qquad SR^+_{SSF} \gt SR^-_{SSF} \]

Differential pair

Todd Brooks, Broadcom "Input Programmable Gain Amplifier (PGA) Design for ADC Signal Conditioning" [https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/OSU%20Classroom%20Presentaton%20042511.ppt]

virtual ground?

\[ \color{blue}V_P = V_{CM} - V_{TH} - \frac{1}{2} \sqrt{ -(2\Delta V)^2 + 4V_{ov,eq}^2 } \]

nonlinearity

Resistive Degeneration

Resistive degeneration in differential pairs serves as one major technique for linear amplifier

The linear region for CMOS differential pair would be extended by \(±I_{SS}R/2\) as all of \(I_{SS}/2\) flows through \(R\). \[ V_{in}^+ -V_{in}^- = V_{OV} + V_{TH}+\frac{I_{SS}}{2}R - V_{TH} = \sqrt{\frac{2I_{SS}}{\mu_nC_{OX}\frac{W}{L}}} + \frac{I_{SS}R}{2} \]

Jri Lee, "Communication Integrated Circuits." https://cc.ee.ntu.edu.tw/~jrilee/publications/Comm_IC.pdf

Figure 14.12, Design of Analog CMOS Integrated Circuits, Second Edition [https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf]

Biasing Tradeoffs in Resistive-Degenerated Diff Pair

w/ Current–Mirror Load

S. Pavan, "Revisiting the CMOS Differential Pair With a Current–Mirror Load [CAS Education]," in IEEE Circuits and Systems Magazine, vol. 25, no. 2, pp. 74-78, Secondquarter 2025 [pdf]

TODO 📅

Double Differential pair

\(V_\text{ip}\) and \(V_\text{im}\) are input, \(V_\text{rp}\) and \(V_\text{rm}\) are reference voltage \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

In differential comparison mode, the feedback loop ensure \(V_\text{ip} = V_\text{rp}\), \(V_\text{im} = V_\text{rm}\) in the end

assume input and reference common voltage are same

Pros of (b)

• larger input range i.e., \(\gt \pm \sqrt{2}V_\text{ov}\) of (a), it works even one differential is off due to lower voltage
• larger \(g_m\) (smaller input difference of pair)

Cons of (b)

• sensitive to the difference of common voltage between \(V_\text{ip}\), \(V_\text{im}\) and \(V_\text{rp}\), \(V_\text{rm}\)

common-mode voltage difference

copy aforementioned formula here for convenience \[ V_o = A_v(\overline{V_\text{ip} - V_\text{im}} - \overline{V_\text{rp} - V_\text{rm}}) \]

at sample phase \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{rm}= V_\text{cmr}\)

• \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\)
• \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

at compare start

• \(V_\text{ip}= V_\text{im}= V_\text{cmi}\) and \(V_\text{rp}= V_\text{cmr}+\Delta\), \(V_\text{rp}= V_\text{cmr}-\Delta\)

• \(I_\text{ip}\lt I_\text{ip0}\), \(I_\text{rp} \gt I_\text{rp0}\)

• \(I_\text{im}\gt I_\text{im0}\), \(I_\text{rm} \lt I_\text{rm0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} \lt 0\), we need to increase \(V_\text{ip}\) and decrease \(V_\text{im}\).

at the compare finish

\[\begin{align} V_\text{ip}= V_\text{cmi} + \Delta \\ V_\text{im}= V_\text{cmi} - \Delta \end{align}\]

and \(I_\text{ip0}= I_\text{im0} = I_\text{i0}\), \(I_\text{rp0}= I_\text{rm0} = I_\text{r0}\)

i.e. \(\overline{I_\text{ip} + I_\text{rm}} - \overline{I_\text{im} + I_\text{rp}} = 0\)

If \(V_\text{cmr} - V_\text{cmi} = \sqrt{2}V_{OV} + \delta\), and \(\delta \gt 0\). one transistor carries the entire tail current

• \(I_\text{ip} =0\) and \(I_\text{rp} = I_{SS}\), all the time

At the end, \(V_\text{im} = V_\text{cmi} - (\Delta - \delta)\), the error is \(\delta\)

In closing, \(V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV}\) for normal work

Furthermore, the difference between \(V_\text{cmr}\) and \(V_\text{cmi}\) should be minimized due to limited impedance of current source and input pair offset

In the end \[ V_\text{cmr} - V_\text{cmi} \lt \sqrt{2}V_{OV} - V_{OS} \]

Under the condition, every transistor of pairs are on in equilibrium

pair mismatch

\[\begin{align} I_{SE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \\ I_{DE} &= g_m(\sigma_{vth,0} + \sigma_{vth,1}) \end{align}\]

The input equivalient offset voltage \[\begin{align} V_{os,SE} &= \frac{I_{SE}}{2g_m} = \frac{\sigma_{vth,0} + \sigma_{vth,1}}{2} \\ V_{os,DE} &= \frac{I_{DE}}{g_m} = \sigma_{vth,0} + \sigma_{vth,1} \end{align}\]

Then \[\begin{align} \sigma_{vos,SE} &= \sqrt{\frac{2\sigma_{vth}^2}{4}} = \frac{\sigma_{vth}}{\sqrt{2}} \\ \sigma_{vos,DE} &= \sqrt{2\sigma_{vth}^2} = \sqrt{2}\sigma_{vth} \end{align}\]

We obtain \[ \sigma_{vos,DE} = 2\sigma_{vos,SE} \]

Gm/ID Approach in Transistor Sizing

Hesham Omran, The Analog Designer's Toolbox (ADT) | Invited Talk by IEEE Santa Clara Valley Section CAS Society [https://youtu.be/FT6kKC5OdE0]

Jespers, P. G. A., & Murmann, B. (2017). Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press.

Boris Murmann, February 26, 2016, Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables [https://www.ieeetoronto.ca/wp-content/uploads/2020/06/20160226toronto_sscs.pdf]

small gm/ID for High ro, or high Early voltage \(V_A\)

C/ID Approach in Transistor Sizing

Armin Tajalli, 27 August 2024, Algorithmic Analog Design C/ID: A Design Oriented FET Modeling and Design Approach [https://lcas.ece.utah.edu/wp-content/uploads/sites/91/2024/10/Introduction-to-CID-Algorithm-in-Circuit-Design.pdf]

—, CICC 2026 Circuit Insights, C over ID Approach in Transistor Sizing

TODO 📅

The DDSM performs integer arithmetic (equivalently, fixed-point with the binary point at the LSB) to realize a fractional value.

linearized model

Noise Cancellation Network

\[\begin{align} v[n] = \{0,1,2,...,M-1\} &\quad\Longrightarrow\quad y[n] = 0 \quad\Longrightarrow\quad e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \\ v[n] = \{M,M+1,M2,...,2M-1\} &\quad\Longrightarrow\quad y[n] = 1 \quad\Longrightarrow\quad e_q[n] = \{0, -\frac{1}{M},-\frac{2}{M},...,-\frac{M-1}{M}\} \end{align}\]

\((1 − z^{−1})^3\)

For the three stages of the MASH 1-1-1 DDSM

1st order DDSM (digital accumulator)

assuming \(n_0=2\)

yield \(M=2^{n_0}=4\)

2nd order DDSM

In \(z\)-domain \[ \left\{(A + D - Y)\frac{z^{-1}}{1-z^{-1}} - 2Y \right\}\frac{z^{-1}}{1-z^{-1}} + Q = Y \] That is \[ Y = A z^{-2} + Dz^{-2} + Q(1-z^{-1})^2 \] In time domain \[\begin{align} y[n] &= \alpha[n-2] + d[n-2] + q[n]-2q[n-1]+q[n-2] \\ &= \alpha + d[n-2] + q[n]-2q[n-1]+q[n-2] \end{align}\]

LSB Dither

?? integer valued impulse responses

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [pdf]

DSM stability

accumulator wordlength

Z. Ye and M. P. Kennedy, "Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 112-116, Feb. 2009 [https://sci-hub.se/10.1109/TCSII.2008.2010188]

—, "Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 4, pp. 714-726, April 2009 [https://sci-hub.se/10.1109/TCSI.2008.2003383]

Truncation DAC

accumulator is implicit quantizer

with \(\frac{y}{2^{m_2}} + q= v\), where \(v = \lfloor\frac{y}{2^{m_2}}\rfloor\)

\[ \left\{ \begin{array}{cl} Y + 2^{m_2} Q &= 2^{m_2}V \\ U - z^{-1}2^{m_2}Q &= Y \end{array} \right. \]

The STF & NTF is shown as below \[ V = \frac{1}{2^{m_2}}U + (1-z^{-1})Q \]

To avoid accumulator overflow, stable input range is only of a fraction of the full scale ( \(2^{m_1+m_2}-1\)) \[ u \leq 2^{m_1+m_2} - 2^{m_2} \]

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m1 = 2  # MSBs
m2 = 4  # LSBs

ymax = 2**(m1 + m2)
umax = 2**(m1 + m2) - 2**m2     # int(m1*'1'+m2*'0', 2)
# format(48, '06b')
# Out[4]: '110000'

u = 48
assert u <= umax

ylist = [0]; vlist = [0]
elist = []; outlist = []

Niter = 2**10
for _ in range(Niter):
    ecur = vlist[-1] - ylist[-1]
    elist.append(ecur)
    ycur = (u - ecur)
    assert ycur < ymax, print(ycur)
    ylist.append(ycur)
    ycur_bin = format(ycur, f'0{m1+m2}b')
    vcur = int(ycur_bin[:-m2]+'0'*m2, 2)
    vlist.append(vcur)
    outlist.append(int(ycur_bin[:-m2], 2))

print(vlist); print(ylist)
print(sum(vlist)/len(vlist)); print(sum(outlist)/len(outlist)*2**m2)

A conservative sufficient condition for avoiding accumulator overflow is

\[ \log_2(2^k + 2^{N-m}) \leq N \]

Thus \[ N \ge k - \log_2(1 - \frac{1}{2^m}) = k+m -\log_2(2^m-1) \]

For an integer quantizer width \(m\geq 1\), \[ k < k - \log_2(1 - \frac{1}{2^m}) \leq k + 1 \] The minimum integer \(N\) satisfying this bound is \[ N_{\min}=\left\lceil k-\log_2(1-2^{-m})\right\rceil=k+1. \]

In the above Temes's slides, \(N = m_1+m_2\) and \(m=m_1\), we have \[ 2^k \leq 2^{m_1+m_2}\cdot (1-\frac{1}{2^{m_1}}) = 2^{m_1+m_2} - 2^{m_2} \]

Thus, this bound requires one guard bit beyond the \(k\)-bit input width, independent of \(m\). For a single-bit quantizer (\(m=1\)), the guard bit is the adder carry-out.

DSM Order & Output Range

7.4.1 Delta-Sigma Modulator [https://iic-jku.github.io/radio-frequency-integrated-circuits/rfic.html#sec-pll-delta-sigma]

Fractional-N PLL

S. Pamarti, J. Welz and I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492-503, March 2007 [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2017/05/2007-TCASI-S.-Pamarti-Statistics-of-the-Quantization-Noise-in-1-Bit-Dithered-Single-Quantizer-Digital-Delta-Sigma-Modulators.pdf]

—. "LSB Dithering in MASH Delta–Sigma D/A Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779-790, April 2007 [https://sci-hub.se/10.1109/TCSI.2006.888780]

—. CICC 2020 ES2-2: Basics of Closed- and Open-Loop Fractional Frequency Synthesis [https://youtu.be/t1TY-D95CY8]

Ian Galton. Delta-Sigma Fractional-N Phase-Locked Loops [https://ispg.ucsd.edu/wordpress/wp-content/uploads/2022/10/fnpll_ieee_tutorial_2003_corrected.pdf]

—. ISSCC 2010 SC3: Fractional-N PLLs

—. “Delta-Sigma Fractional-N Phase-Locked Loops.” (2003)

Mike Shuo-Wei Chen, ISSCC 2020 T6: Digital Fractional-N Phase Locked Loop Design

Accumulated Quantization Error (AQE)

\[ (N+\alpha)T_{PLL} - \tau[n-1] +\tau[n] = (N+y[n])T_{PLL} \]

i.e. \[ \tau[n] = \tau[n-1] + (y[n] - \alpha)T_{PLL} \]

where \(\tau[n] = t_{v_{DIV}} - t_{v_{DIV}, desired}\)

Y. Zhang et al., "A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602-614, March 2020, [pdf]

X. Wang and M. P. Kennedy, "Unified Analysis of Digital Δ-Σ Modulators (DDSMs) for Fractional-N Frequency Synthesis—Introducing the PASS Family of DDSMs Featuring Independent Shaping of the Probability Density and Spectral Envelope," in IEEE Transactions on Circuits and Systems I: Regular Papers [link]

X. Wang and M. P. Kennedy, "Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs," 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Valencia, Spain, 2023 [link]

\(\Delta\Sigma\) Noise in PLL

\[\begin{align} S_\phi(f) &= \frac{1}{12F_{ref}}|1-z^{-1}|^{2L}\cdot \left|\frac{2\pi z_{-1}}{1-z^{-1}}\right|^2\cdot \frac{1}{T_{ref}^2} T_{ref}^2 \\ &= \frac{1}{12F_{ref}} |1-z^{-1}|^{2L-2} 4\pi^2 \end{align}\]

with \(|1-z^{-1}| = |2\sin\frac{\pi f}{F_{ref}}|\)

\[ S_\phi(f) = \frac{1}{12F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)}\cdot 4\pi^2 = \frac{\pi^2}{3F_{ref}} \cdot \left|2\sin\frac{\pi f}{F_{ref}}\right|^{2(L-1)} \]

Jri Lee,【【鳌中堂笔记·抢先体验版】 锁相环08】[bilibili link]

俞思辰, Analog and Digital PLL Phase Noise Model [https://bbs.eetop.cn/thread-996183-1-1.html]

Frequency & Time-Domian Model for Q-noise

metroidman, fractional N量化噪声对系统相位噪声的影响 两种分析方法 LTI频域法和时域采样DFT法 [link]

LTI Frequency domain model & analysis

fcw: Frequency Control Word

note

\(z=e^{j2\pi f \color{red}T_\text{ref}}\) — model's time tick is reference clock period

\(\frac{\Phi}{N}(z)\) — relationship between \(\Phi\) and \(N\)

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% --- System Parameters ---
fref = 40e6;
fcw = 360.123;
kvco = 2 * pi * 300e6;

% Components
icp = 60e-6; C0 = 40e-12;
R1 = 14000; C1 = 360e-12;
R2 = 1000; C2 = 20e-12;

% --- Frequency Vector ---
f = logspace(2, 9, 1000);
s = 1i * 2 * pi * f;

% --- Loop Filter Transfer Function ---
num_lf = s .* R1 .* C1 + 1;
den_lf = (s.^3 .* R1 .* R2 .* C0 .* C1 .* C2 + ...
          s.^2 .* (R1.*C1.*C0 + R1.*C1.*C2 + R2.*C2.*C0 + R2.*C2.*C1) + ...
          s .* (C0 + C1 + C2));
loopfilter = num_lf ./ den_lf;

% --- Loop Gain and Noise Transfer Function ---
loopgain = (icp / (2*pi)) .* loopfilter .* (kvco ./ s) .* (1 / fcw);
hfra = (loopgain ./ (1 + loopgain)) .* 2*pi./(exp(s./fref) - 1) .* (1 - exp(-s./fref)).^3;

% --- Spectral Density calculation ---
sfra = 10 * log10((1 / (12 * fref)) .* abs(hfra).^2);

% --- Plot ---
semilogx(f, sfra, LineWidth=2);
ylim([-250, -100]); yticks(-250:10:-100);
grid on; xlabel('Frequency (Hz)'); ylabel('dB');
title('Quantization Noise Effects', FontSize=14);

Time domain model & DFT analysis

Round in In[24] is redundant and likely unnecessary for the logic to function

\(\phi\) and phi is frequency (cycles per second) instead of angular frequency (radians per second)

\(\Delta\Sigma\) DAC

LPF (RC Filter)

Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter [https://www.dsprelated.com/showarticle/1642.php]

Sigma-delta digital-to-analog converters (SD DAC’s) are often used for discrete-time signals with sample rate much higher than their bandwidth

• Because of the high sample rate relative to signal bandwidth, a very simple DAC reconstruction filter (Analog lowpass filter) suffices, often just a one-pole RC lowpass

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R= 4.7e3;                 % ohms resistor value
C= .01e-6;                % F capacitor value
fs= 1e6;                  % Hz DAC sample rate
% input signal
x= [zeros(1,20) .9*ones(1,200) .1*ones(1,200)];
% find output y of SD DAC and output y_filt of RC filter
[y,y_filt]= sd_dacRC(x,R,C,fs);

t = linspace(0,length(x)-1, length(x))*1/fs*1e3;
subplot(3,1,1)
plot(t, x, '.'); title('x'); grid on
subplot(3,1,2)
plot(t, y, '.'); title('y'); grid on
subplot(3,1,3)
plot(t, y_filt); title('y_{filt}'); xlabel('t(ms)'); grid on

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% https://www.dsprelated.com/showarticle/1642.php
% Neil Robertson, Model a Sigma-Delta DAC Plus RC Filter

% function [y,y_filt] = sd_dacRC(x,R,C,fs)  2/5/24 Neil Robertson
% 1-bit sigma-delta DAC with RC filter
% Model does not include a zero-order hold.
%
% x = input signal vector, 0 <= x < 1
% R = series resistor value, Ohms.  Normally R > 1000 for 3.3 V logic.
% C = shunt capacitor value, Farads
% fs = sample frequency, Hz
% y = DAC output signal vector, y(n) = 0 or 1
% y_filt = RC filter output signal vector
%
function [y,y_filt] = sd_dacRC(x,R,C,fs)
N= length(x);
x= fix(x*2^16)/2^16;        % quantize x to 16 bits
%I 1-bit Sigma-delta DAC
s= [x(1) zeros(1,N-1)];
for n= 2:N
    u= x(n) + s(n-1);
    s(n)= mod(u,1);        % sum
    y(n)= fix(u);          % carry
end

%II One-pole RC filter model
% Matched z-Transform https://ocw.mit.edu/courses/2-161-signal-processing-continuous-and-discrete-fall-2008/cc00ac6d468dc9dcf2238fc1d1a194d4_lecture_19.pdf
Ts= 1/fs;
Wc= 1/(R*C);               % rad -3 dB frequency
fc= Wc/(2*pi);             % Hz -3 dB frequency
a1= -exp(-Wc*Ts);
b0= 1 + a1;                % numerator coefficient
a= [1 a1];                 % denominator coeffs
y_filt= filter(b0,a,y);    % filter the DAC's output signal y

ZOH (Zero-Order Hold Models)

Neil Robertson, DAC Zero-Order Hold Models [https://www.dsprelated.com/showarticle/1627.php]

The last D2C is in human vision, which connect discrete time \(y(m)\) with line, implicitly

Sinc Corrector

Neil Robertson, Design a DAC sinx/x Corrector [https://www.dsprelated.com/showarticle/1191.php]

Dan Boschen. how to make CIC compensation filter [https://dsp.stackexchange.com/a/31596/59253]

—. Core Building Blocks for Software Defined Radio (SDR): DDC, DUC, NCO) [https://lnkd.in/p/e2MtC9QK]

Equalizing Techniques Flatten DAC Frequency Response [https://www.analog.com/en/resources/technical-articles/equalizing-techniques-flatten-dac-frequency-response.html]

aka. Inverse Sinc Compensation

TODO 📅

OSR & NS

maximum output signal 22kHz

\[SNR = 16\times 6.02 + 1.76 = 98.08\]

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OSR = 5.65e6/(2*22e3);
Nin = 16;
Nout = 1;

SNR_in = 6.02*Nin + 1.76;

SNR_ds = 6.02*Nout + 1.76 - 10*log10(pi^4/5) + 50*log10(OSR);

QN_in = 1/10^(SNR_in/10);
QN_ds = 1/10^(SNR_ds/10);

SNR_out = 10*log10(1/(QN_in + QN_ds));

Y. Liu, J. Gao and X. Yang, "24-bit low-power low-cost digital audio sigma-delta DAC," in Tsinghua Science and Technology, vol. 16, no. 1, pp. 74-82, Feb. 2011 [https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6077939]

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snr_if = 144;
snr_ds = 135;
snr_ana = 95;

n_if = 1/10^(snr_if/10);
n_ds = 1/10^(snr_ds/10);
n_ana = 1/10^(snr_ana/10);

snr_tot = 10*log10(1/(n_if + n_ds + n_ana))

%
% snr_tot =
%
%    94.9995

MASH 1-1-1

J. W. M. Rogers, F. F. Dai, M. S. Cavin and D. G. Rahn, "A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC," in IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 678-689, March 2005 [https://sci-hub.se/10.1109/JSSC.2005.843604]

(a) a fractional accumulator, and (b) a triple-loop \(\Delta\Sigma\) accumulator for \(N(z) = 100 + 1/32\)

\(n=5\)

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import numpy as np
import matplotlib.pyplot as plt
import scipy.fft as fft
import scipy.signal.windows as windows

def acc_nbit(din, nbit=5, ncycles=2**10):
    mod = 2**nbit
    acc = 0
    eq = 0
    colist = []
    eqlist = []
    for i in range(ncycles):
        acc = din[i] + eq
        eq = acc % mod
        #print(acc, eq)
        co_tmp = int(acc >= mod)
        colist.append(co_tmp)
        eqlist.append(eq)
    return colist, eqlist

Ncyl = 2**16
cin1 = [1]*Ncyl

c1,eq1 = acc_nbit(cin1, ncycles=Ncyl)
cin2 = [0,*eq1[:-1]]
#cin2 = eq1

c2,eq2 = acc_nbit(cin2, ncycles=Ncyl)
cin3 = [0,*eq2[:-1]]
#cin3 =  eq2

c3,eq3 = acc_nbit(cin3, ncycles=Ncyl)

ctot = []

for i in range(2, Ncyl):
    # C1(z) + (1 − z^−1)C2(z) + (1 − z^−1)^2 C3(z)
    ctot_cur = c1[i] + c2[i]-c2[i-1] + c3[i]-2*c3[i-1] + c3[i-2]
    ctot.append(ctot_cur)

print(sum(c1)/len(c1))      # 0.03125
print(sum(ctot)/len(ctot))  # 0.03128147221289712

plt.figure(figsize=(20,8))
plt.subplot(1,2,1)
plt.plot(c1[:200], 'o-', label='c1')
plt.legend(loc='upper left'); plt.grid(True)
plt.subplot(1,2,2)
plt.plot(ctot[:200], 'o-', label='ctot')
plt.legend(loc='upper left'); plt.grid(True)


Ntot = int(2**np.floor(np.log2(len(ctot))))
c1_4fft = np.array(c1[:Ntot])
ctot_4fft = np.array(ctot[:Ntot])
whann = windows.hann(Ntot)
Y_c1 = abs(fft.rfft(c1_4fft*whann))/sum(whann)
Y_ctot = abs(fft.rfft(ctot_4fft*whann))/sum(whann)

print(Y_c1[0])      # 0.031250000002717625
print(Y_ctot[0])    # 0.031249999999526525

plt.figure(figsize=(20,8))
plt.subplot(2, 1, 1)
_, stemlines, _ = plt.stem(Y_c1, markerfmt=" ", label='c1')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')
plt.subplot(2, 1, 2)
_, stemlines, _ = plt.stem(Y_ctot, markerfmt=" ", label='ctot')
plt.setp(stemlines, 'linewidth', 4)
plt.ylim([0,0.04]); plt.grid(True); plt.legend(loc='upper left')

plt.show()

Harald Pretl, Radio-Frequency Integrated Circuits. 7.4 Fractional-N PLL [note] [MASH Modulator (3rd Order) code] [github link]

3rd order MASH (1-1-1) modulator that converts a constant input value (0-1) into a multi-bit sequence

for this unipolar 1-bit implementation, the valid instantaneous input is:

\[ \boxed{0 \le x \le 1} \] At each stage, the accumulator is quantized to 0 or 1, leaving the remainder: \[ e_i = \text{accumulator}_i-y_i,\qquad 0\le e_i<1 \]

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# Parameters
input_value = 0.125  # Constant input (0-1)
sequence_length = 2**15  # Length of sequence
display_samples = 100  # Number of samples to display in time plot
dither_seed = 0  # RNG seed for reproducible dithering (None for random)

# Dithering configurations to compare
dither_amplitude_no_dither = 0.0  # No dithering
dither_amplitude_with_dither = 0.000001  # With dithering


# Stage 1: 1st order modulator with input signal
self.integrator1 += input_value
y1 = 1 if self.integrator1 >= 1.0 else 0
e1 = self.integrator1 - y1  # Quantization error
self.integrator1 = e1  # Store error for next iteration

# Stage 2: 1st order modulator fed with quantization error from stage 1
self.integrator2 += e1
y2 = 1 if self.integrator2 >= 1.0 else 0
e2 = self.integrator2 - y2
self.integrator2 = e2

# Stage 3: 1st order modulator fed with quantization error from stage 2
self.integrator3 += e2
y3 = 1 if self.integrator3 >= 1.0 else 0
e3 = self.integrator3 - y3
self.integrator3 = e3

# Digital noise cancellation logic for MASH 1-1-1
# Output = Y1 + (1-z^-1)*Y2 + (1-z^-1)^2*Y3
# Expanding (1-z^-1)^2 = 1 - 2*z^-1 + z^-2:
# Output = Y1 + Y2 - Y2[z^-1] + Y3 - 2*Y3[z^-1] + Y3[z^-2]

combined = y1 + (y2 - self.y2_prev) + (y3 - 2*self.y3_prev + self.y3_prev2)

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for i in range(length):
    dither = rng.uniform(-dither_amplitude, dither_amplitude) if dither_amplitude > 0 else 0.0
    combined, y1, y2, y3 = self.step(input_value + dither)
    combined_output[i] = combined
    y1_output[i] = y1
    y2_output[i] = y2
    y3_output[i] = y3

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# Plot 2: Frequency spectrum (with dither)
ax2 = plt.subplot(1, 2, 2)
N = len(mash_combined_with_dither)
fft_freq = np.fft.fftfreq(N)
pos_freq = fft_freq >= 0
fft_no = np.fft.fft(mash_combined_with_dither)
psd_no = 20 * np.log10(np.abs(fft_no) / N + 1e-12)

metroidman, 用Simulink Excel Mathematica三种不同工具从零搭建3阶ΣΔ调制器并进行时域和频率分析 [link]

output-feedback MASH 1-1-1 DDSM

Simulink

for a fractional frequency-control word:

\[ \mathrm{FCW} = \underbrace{\lfloor\mathrm{FCW}\rfloor}_{\text{integer}} + \underbrace{x}_{\text{fractional}} \]

with the fractional part entering the MASH and the integer part added back at the output.

Each stage contains an accumulator

\[ H(z)=\frac{1}{1-z^{-1}} \]

followed by a quantizer (floor), and the quantizer output is fed back around the accumulator. That is why it is called output-feedback

For the three stages, using your labels, the quantization errors are approximately

\[\begin{align} q_1&=u_1-y_1\\ q_2&=u_2-y_2\\ q_3&=u_3-y_3 \end{align}\]

The important MASH feature is that the quantization error of one stage drives the next stage:

\[ q_1 \rightarrow \text{stage 2}, \qquad q_2 \rightarrow \text{stage 3} \]

At the top, the blocks labeled

\[ \frac{z-1}{z}=1-z^{-1} \]

form the digital noise-cancellation network. Ignoring sign-convention differences, the MASH output has the standard form

\[ \boxed{ y_{\mathrm{MASH}} = y_1 + (1-z^{-1})y_2 + (1-z^{-1})^2y_3 } \]

so that the first- and second-stage quantization errors cancel, leaving the third-stage error shaped by

\[ \boxed{ (1-z^{-1})^3} \]

with the usual additive quantizer-noise convention, your \(q_1,q_2,q_3\) are the negative of the quantization errors

Excel

The table is consistent with the labels in your Simulink diagram

Mathematica

The code fcwit = Table[fcwi[i], {i, 9999}]; is the command that actually runs the simulation for a set duration.

Here is the breakdown of what is happening:

• Table[..., {i, 9999}]: This creates a list by repeating an operation 9,999 times. It acts like a for loop in other programming languages.
• fcwi[i]: This calls the function you defined earlier. For every value of i from 1 to 9,999, it calculates the instantaneous integer division ratio produced by the MASH modulator.
• fcwit = ...: It stores all 9,999 results into a single long list (an array) named fcwit.
• ; (Semicolon): This is important—it suppresses the output. Without it, Mathematica would print all 9,999 numbers on your screen, which would be a huge mess!

For each first-order stage, \[ \begin{aligned} y_1 &=z^{-1}x+(1-z^{-1})q_1\\ y_2 &=-z^{-1}q_1+(1-z^{-1})q_2\\ y_3 &=-z^{-1}q_2+(1-z^{-1})q_3 \end{aligned} \] The error-cancellation network is \[ y=z^{-2}y_1 +z^{-1}(1-z^{-1})y_2 +(1-z^{-1})^2y_3 \] Substitute: \[ \begin{aligned} y ={}&z^{-2}\left[z^{-1}x+(1-z^{-1})q_1\right] \\ &+z^{-1}(1-z^{-1}) \left[-z^{-1}q_1+(1-z^{-1})q_2\right]\\ &+(1-z^{-1})^2 \left[-z^{-1}q_2+(1-z^{-1})q_3\right] \end{aligned} \] Now \(q_1\) cancels: \[ z^{-2}(1-z^{-1})q_1 -z^{-2}(1-z^{-1})q_1=0 \] And \(q_2\) cancels: \[ z^{-1}(1-z^{-1})^2q_2 -z^{-1}(1-z^{-1})^2q_2=0 \] What remains is \[ \boxed{ y=z^{-3}x+(1-z^{-1})^3\textcolor{red}{q_3} } \] Only the last stage's quantization error survives — that is the defining property of a MASH.

• Fig. 3.10 style (delaying integrators): delays are mandatory, \(H_1=z^{-2}\) minimum
• non-delaying accumulators style (STF = 1): no delays needed

So, in short: \[ \boxed{\text{The delays are necessary in Fig. 3.10, but not universally necessary for MASH 1-1-1}} \] They compensate for the one-cycle STF delay introduced by each \(\frac{z^{-1}}{1-z^{-1}}\) stage.

From Eq. (9.47), \[ N_{\text{frac}}[k] = C_1[k] +(1-z^{-1})C_2[k] +(1-z^{-1})^2 C_3[k] \] or \[ N_{\text{frac}}[k] = C_1[k] +\big(C_2[k]-C_2[k-1]\big) +\big(C_3[k]-2C_3[k-1]+C_3[k-2]\big) \] Since each carry is one bit, \[ C_i[k]\in\{0,1\} \] Therefore, \[ C_1\in[0,1],\qquad (1-z^{-1})C_2\in[-1,1] \] and \[ (1-z^{-1})^2C_3\in[-2,2] \] So the worst-case sum is \[ \boxed{-3\le N_{\text{frac}}\le 4} \] A 3-bit two's-complement number only represents \[ \boxed{-4,\ldots,+3} \] so it cannot represent \(+4\). Therefore that implementation uses 4 bits: \[ \boxed{\text{signed }[-3,+4]\Rightarrow 4\text{ bits}} \] whereas Fig. 3.14 uses \[ \boxed{\text{8 encoded levels}\Rightarrow 3\text{ bits}} \] So the distinction is: \[ \boxed{ \begin{array}{ll} 3\text{ bits} & \text{enough to encode the 8 possible levels with special coding},\\[2mm] 4\text{ bits} & \text{needed for straightforward signed two's-complement arithmetic.} \end{array}} \]

So there is no fundamental disagreement: \[ \boxed{ \begin{array}{c} \text{Fig. 9.21: signed arithmetic representation} \rightarrow 4\text{ bits}\\[2mm] \text{Fig. 3.14: encoded divider-selection word} \rightarrow 3\text{ bits} \end{array}} \]

The important fact is that a MASH 1-1-1 only needs to select 8 divider levels; therefore the final divider control can indeed be implemented with 3 physical bits.

MASH structures

MASH 1-1-1 DDSM — output feedback vs error feedback [https://github.com/raytroop/mash_of_ef_int]

Output-feedback (OF)

Error-feedback (EF), non-pipelined

Error-feedback (EF), pipelined

In a MASH 1-1-1, pipelined means registers are inserted between the three stages.

At clock \(n\):

• Non-pipelined: Stage 2 uses Stage 1’s newly computed residue from clock \(n\); Stage 3 similarly uses Stage 2’s new residue.
• Pipelined: Stage 2 uses Stage 1’s residue from clock \(n-1\), and Stage 3 uses Stage 2’s residue from clock \(n-1\)

This allows all stages to operate concurrently on different samples, shortening the hardware critical path. The tradeoff is two clocks of latency, although throughput remains one output per clock after startup

The noise-cancellation outputs must therefore be realigned:

\[ \boxed{y_1[n-2],\qquad y_2[n-1],\qquad y_3[n]} \]

Output-feedback (OF), Exact integer model

The models add the integer part, so the average of out is \(\text{ip} + k/M\), not \(k/M\) alone. Call mash_of_int(k, M, 0, …) with \(ip = 0\) and the average is exactly \(k/M\) \[ \boxed{\operatorname{mean}(\text{out}) \to \text{integer}+\frac{k}{M}} \]

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def mash_ef_int(k, M, integer, n_samples, r_init=(0, 0, 0)):
    r = list(r_init)
    ncl_y3_prev = ncl_s_prev = 0
    out, carries, residues = [], [], []
    for _ in range(n_samples):
        stage_in = k
        y = [0, 0, 0]
        for i in range(3):
            a = r[i] + stage_in
            y[i] = a // M
            r[i] = a - M * y[i]
            stage_in = r[i]
        s = y[1] + (y[2] - ncl_y3_prev)
        out.append(integer + y[0] + (s - ncl_s_prev))
        ncl_y3_prev, ncl_s_prev = y[2], s
        carries.append(tuple(y))
        residues.append(tuple(r))
    return out, carries, residues

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# ---------------------------------------------------------------------------
# Exact integer models: fractional input k/M, modulus M (hardware-style)
# ---------------------------------------------------------------------------
def mash_of_int(k, M, integer, n_samples, u_init=(0, 0, 0)):
    u, y_prev = list(u_init), [0, 0, 0]
    ncl_y3_prev = ncl_s_prev = 0
    out, carries, residues, e3 = [], [], [], []
    for _ in range(n_samples):
        stage_in = k
        y, q = [0, 0, 0], [0, 0, 0]
        for i in range(3):
            u[i] += stage_in - M * y_prev[i]
            y[i] = u[i] // M
            q[i] = u[i] - M * y[i]
            stage_in = q[i]
        s = y[1] + (y[2] - ncl_y3_prev)
        out.append(integer + y[0] + (s - ncl_s_prev))
        ncl_y3_prev, ncl_s_prev, y_prev = y[2], s, y
        carries.append(tuple(y))
        residues.append(tuple(q))
        e3.append(M * y[2] - u[2])     # E3 = y3 - u3, in units of 1/M
    return out, carries, residues, e3

Error-feedback (EF), Exact integer model

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def mash_ef_int(k, M, integer, n_samples, r_init=(0, 0, 0)):
    r = list(r_init)
    ncl_y3_prev = ncl_s_prev = 0
    out, carries, residues = [], [], []
    for _ in range(n_samples):
        stage_in = k
        y = [0, 0, 0]
        for i in range(3):
            a = r[i] + stage_in
            y[i] = a // M
            r[i] = a - M * y[i]
            stage_in = r[i]
        s = y[1] + (y[2] - ncl_y3_prev)
        out.append(integer + y[0] + (s - ncl_s_prev))
        ncl_y3_prev, ncl_s_prev = y[2], s
        carries.append(tuple(y))
        residues.append(tuple(r))
    return out, carries, residues

For both pairs, _int means the same feedback structure implemented with exact integer arithmetic, with internal signals scaled by a modulus \(M\)

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print("T5  Fixed-point, exhaustive: 8 bits (M = 256), every k, IC 0 and 1, 2M samples")
M, bad = 256, 0
for k in range(M):
    for ic in (0, 1):
        a = mash_of_int(k, M, 0, 2 * M, u_init=(ic, 0, 0))[:3]
        b = mash_ef_int(k, M, 0, 2 * M, r_init=(ic, 0, 0))
        # Python compares all these nested contents recursively, so a != b is a single True if any value differs.
        bad += a != b
print("    mismatching (k, IC) cases: %d of %d" % (bad, 2 * M))

reference

Michael Peter Kennedy. scv-cas 2014: Digital Delta-Sigma Modulators [pdf,recording]

—, Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators [pdf]

Kaveh Hosseini and Peter Kennedy. 2006 Hardware Efficient Maximum Sequence Length Digital MASH Delta Sigma Modulator [pdf]

Jason Sachs. Return of the Delta-Sigma Modulators, Part 1: Modulation [https://www.dsprelated.com/showarticle/1517/return-of-the-delta-sigma-modulators-part-1-modulation]

Neil Robertson, Modeling a Continuous-Time System with Matlab [https://www.dsprelated.com/showarticle/1055.php]

—, “A Simplified Matlab Function for Power Spectral Density”, DSPRelated.com, March, 2020, [https://www.dsprelated.com/showarticle/1333.php]

Rick Lyons. How Discrete Signal Interpolation Improves D/A Conversion [https://www.dsprelated.com/showarticle/167.php]

Dan Boschen. sigma delta modulator for DAC [https://dsp.stackexchange.com/a/88357/59253]

Woogeun Rhee. ISCAS 2019 Mini Tutorials: Single-Bit Delta-Sigma Modulation Techniques for Robust Wireless Systems [https://youtu.be/OEyTM4-_OyA]

—, 2001 Phd Thesis: Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers [https://www.ime.tsinghua.edu.cn/Thesis_rhee.pdf]

Pavan, Shanthi, Richard Schreier, and Gabor Temes. (2016) 2016. Understanding Delta-Sigma Data Converters. 2nd ed. Wiley.

John Rogers, Calvin Plett, and Foster Dai. 2006. Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library). Artech House, Inc., USA.

K. Hosseini and M. P. Kennedy, Minimizing Spurious Tones in Digital Delta-Sigma Modulators (Analog Circuits and Signal Processing). New York, NY, USA: Springer, 2011.

Rhee, W. (2020). Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems. The Institution of Engineering and Technology

Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori. Integrated frequency synthesizers for wireless systems. Cambridge University Press, 2007.

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Delta-Sigma Modulators
│
├─ Analog ΔΣ Modulators
│  │
│  ├─ Discrete-Time Analog ΔΣ Modulator, DT ΔΣM
│  │  ├─ Switched-capacitor / switched-current loop filter
│  │  ├─ Input is sampled before or inside loop filter
│  │  └─ Very common in ΔΣ ADCs
│  │
│  └─ Continuous-Time Analog ΔΣ Modulator, CT ΔΣM
│     ├─ Continuous-time RC / gm-C / active-RC loop filter
│     ├─ Feedback DAC is continuous-time
│     ├─ Quantizer is usually clocked → synchronous CT ΔΣM
│     └─ Quantizer/comparator may be event-driven → asynchronous CT ΔΣM
│
└─ Digital ΔΣ Modulators, DDSM
   │
   ├─ Single-quantizer DDSM
   │  ├─ Output-feedback form
   │  └─ Error-feedback form, EFM
   │
   └─ MASH DDSM
      └─ Multi-stage noise-shaping modulator

"Quantizers" and "truncators", "integrators" and "accumulators" are used in delta-sigma ADCs and DACs, respectively

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

Oversampling

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

Nyquist sampling theorem @signal: no aliasing, signal remain the same

noise folding @noise: same total noise power spread over a wider frequency

[https://dsp.stackexchange.com/a/40261/59253]

Noise Shaping

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[h1, w1] = freqz([1 -1], 1);
[h2, w2] = freqz([1 -2 1], 1);

plot(w1/2/pi, abs(h1), LineWidth=3)
hold on
plot(w2/2/pi, abs(h2), LineWidth=3)
grid on
legend('MOD1', 'MOD2')
xlabel('fs')
ylabel('mag')
title('NTF of MOD1 & MOD2')

SQNR improvement

In general, for an \(l\)th order modulator with \(\text{NTF}(z) = (1 − z^{−1})^l\), the SQNR increases by \((6l + 3)\) dB for every doubling of the OSR, which provides \(l+0.5\) extra bits resolution

without the delta-sigma loop

\(10\log (2) \approx 3\)dB

first order delta-sigma modulator

\(30\log (2) \approx 9\)dB

second order delta-sigma modulator

\(50\log (2) \approx 15\)dB

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OSR= linspace(1,16,16);

SQNR_ovonly_delta = 10*log10(OSR);
SQNR_1st_delta = -10*log10(pi^2/3) + 30*log10(OSR);
SQNR_2st_delta = -10*log10(pi^4/5) + 50*log10(OSR);

plot(OSR, SQNR_ovonly_delta,'ro-', LineWidth=4);
hold on
plot(OSR, SQNR_1st_delta,'bo-', LineWidth=4);
plot(OSR, SQNR_2st_delta,'mo-', LineWidth=4);
grid on; grid minor;
xlim([1 16]); ylim([-20 50]);
xlabel('OSR', FontSize=16); ylabel('\DeltaSQNR (dB)', FontSize=16);
legend('Oversampling Only', '1st \Delta\Sigma', '2nd \Delta\Sigma', fontsize=16)

TI. ADC12EU050 Continuous-Time Sigma-Delta ADCs [https://www.ti.com/lit/an/snaa098/snaa098.pdf]

where \(N\) is the number of bits in the output, \(M\) is known as the over-sampling ratio, \(L\) is loop orders

Quantizer Bits & ENOB

without the delta-sigma loop

High-Order \(\Delta\Sigma\) Modulators

The greater the number of quantizer levels, the smaller quantization error

Performance Metrics

• signal-to-noise ratio (SNR)
• dynamic range (DR)
• signal-to-(noise + distortion) ratio (SNDR)

DR by "SNR Max" Definition (\(\Delta\Sigma\) Specific)

Quantizer overload

M. Neitola, "Lee's Rule Extended," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 4, pp. 382-386, April 2017

Maximum Stable Amplitude (MSA)

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% Schreier Delta-Sigma Toolbox required
OSR   = 64;
order = 3;
nlev  = 2;
H_inf = 1.5;

ntf = synthesizeNTF(order, OSR, 1, H_inf);

N    = 2^14;
fB   = floor(N/(2*OSR));            % last in-band bin index (0-based)
fin  = round(fB/3);                 % in-band test tone
amps = -80:2:0;
snr  = zeros(size(amps));

w    = ds_hann(N);
nb = 1;                              % Hann: 2*nb+1 = 3 signal bins

for k = 1:length(amps)
    A    = 10^(amps(k)/20);
    u    = A*sin(2*pi*fin/N*(0:N-1));
    v    = simulateDSM(u, ntf, nlev);
    spec = fft(v .* w) / (sum(w)/2);

    inband = spec(1:fB+1);          % <-- KEY: only in-band bins
    snr(k) = calculateSNR(inband, fin, nb);
end

plot(amps, snr,'-o'); grid on;
xlabel('Input amplitude (dBFS)');
ylabel('SNR (dB)');
title(sprintf('Order=%d, OSR=%d, %d-lev, ||NTF||_\\infty=%.1f',...
              order, OSR, nlev, H_inf));

\(\Delta \Sigma\) vs. \(\Delta\) modulation

• \(\Delta \Sigma\) modulators, and other noise-shaping modulators, change the spectrum of the noise but leave the signal unchanged

• \(\Delta\) modulators and other signal-predicting modulators shape the spectrum of the modulated signal but leave the quantization noise unchanged at the receiver

output vs. error-feedback

The error-feedback architecture is problematic for analog implementation, since it is sensitive to variations of its parameters (subtractor realization)

ADC

DAC

P. Kiss, J. Arias and Dandan Li, "Stable high-order delta-sigma DACS," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, 2003 [https://www.ele.uva.es/~jesus/analog/tcasi2003.pdf]

output-feedback

[https://www.linkedin.com/posts/danboschen_signalprocessing-dsp-pythonforengineers-activity-7345777588746788866-SprG?utm_source=share&utm_medium=member_desktop&rcm=ACoAAD-cuiIBDJ62eh9q3qTSSdslYXr-XMd8TGw]

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// https://github.com/hamsternz/second_order_sigma_delta_DAC

`timescale 1ns / 1ps
module second_order_dac(
  input wire i_clk,
  input wire i_res,
  input wire i_ce,
  input wire [15:0] i_func, 
  output wire o_DAC
);

  reg this_bit;
 
  reg [19:0] DAC_acc_1st;
  reg [19:0] DAC_acc_2nd;
  reg [19:0] i_func_extended;
   
  assign o_DAC = this_bit;

  always @(*)
     i_func_extended = {i_func[15],i_func[15],i_func[15],i_func[15],i_func};
    
  always @(posedge i_clk or negedge i_res)
    begin
      if (i_res==0)
        begin
          DAC_acc_1st<=16'd0;
          DAC_acc_2nd<=16'd0;
          this_bit = 1'b0;
        end
      else if(i_ce == 1'b1) 
        begin
          if(this_bit == 1'b1)
            begin
              DAC_acc_1st = DAC_acc_1st + i_func_extended - (2**15);
              DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st     - (2**15);
            end
          else
            begin
              DAC_acc_1st = DAC_acc_1st + i_func_extended + (2**15);
              DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st + (2**15);
            end
          // When the high bit is set (a negative value) we need to output a 0 and when it is clear we need to output a 1.
          this_bit = ~DAC_acc_2nd[19];
        end
    end
endmodule

Time and Frequency Domain

\(M \gt N\)

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/Intro_to_Delta_Sigma_Data_Converters.pdf]

Chun-Hsien Su ( 蘇純賢). Fundamentals of Sigma-Delta Data Converters,July, 2006 [pdf]

ADC

hackaday. Tearing Into Delta Sigma ADC’s [https://hackaday.com/2016/07/07/tearing-into-delta-sigma-adcs-part-1/]

DAC

an interpolation filter effectively up-samples its low-rate input and lowpass-filters the resulting high-rate data to produce a high-rate output devoid of images

P.E. Allen -CMOS Analog Circuit Design: Lecture 39 – Oversampling ADCs – Part I (6/26/14) [https://aicdesign.org/wp-content/uploads/2018/08/lecture39-140626.pdf]

P.E. Allen -CMOS Analog Circuit Design: Lecture 40 – Oversampling ADCs – Part II (7/17/15) [https://aicdesign.org/wp-content/uploads/2018/08/lecture40-150717.pdf]

David Johns and Ken Martin. Oversampling Converters [https://www.eecg.toronto.edu/~johns/ece1371/slides/14_oversampling.pdf]

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/Intro_to_Delta_Sigma_Data_Converters.pdf]

No delay-free loops

Any such physically feasible device will take a finite time to operate – in other words, the quantized output will only be available a small time after the quantizer has "looked" at the input - insert a one-sample delay

there cannot be a "delay free loop" is a common idea in sequential digital state machine design

Both integrator and quantizer are delay free

NTF realizability criterion: No delay-free loops in the modulator

linear settling & GBW of amplifier

TODO 📅

Switched capacitor has been the common realization technique of discrete-time (DT) modulators, and in order to achieve a linear settling, the sampling frequency used in these converters needs to be significantly lower than the gain bandwidth product (GBW) of the amplifiers.

MOD1 & MOD2

MOD1: first-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD2: second-order noise-shaped converter (\(\Delta\Sigma\) modulator)

MOD1

\[ V(z) = U(z) +(1-z^{-1})E(z) \]

• A binary DAC (and hence a binary modulator) is inherently linear
• With a CT loop filter, MOD1 has inherent anti-alising

\[\begin{align} v[1] &= u - (0) + e[1] \\ v[2] &= 2u - (v[1]) + e[2] \\ v[3] &= 3u - (v[1]+v[2]) + e[3] \\ v[4] &= 4u - (v[1]+v[2]+v[3]) + e[4] \end{align}\]

That is \[ v[n] = nu - \sum_{k=1}^{n-1}v[k] + e[n] \] Therefore, we have \(v[n-1] = (n-1)u - \sum_{k=1}^{n-2}v[k] + e[n-1]\), then \[\begin{align} v[n] &= nu - \sum_{k=1}^{n-1}v[k] + e[n] \\ &= u + \left((n-1)u - \sum_{k=1}^{n-2}v[k]\right) - v[n-1] + e[n] \\ &= u + v[n-1] - e[n-1] -v[n-1] + e[n] \\ &= u + e[n] - e[n-1] \end{align}\]

Dout, the low frequency component of ADC out is same with Vin

MOD2

[https://web.engr.oregonstate.edu/~temes/ece627/Lecture_Notes/2nd_Higher_Order.pdf]

MOD1 with DC Excitation

TODO 📅