J. Zhong, Y. Zhu, S. -W. Sin, S. -P. U and R. P. Martins, "Thermal
and Reference Noise Analysis of Time-Interleaving SAR and
Partial-Interleaving Pipelined-SAR ADCs," in IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 62, no. 9, pp. 2196-2206,
Sept. 2015 [https://sci-hub.st/10.1109/TCSI.2015.2452331]
The amplitude of the reference ripple is code-dependent as it is
correlated with switching energy in each bit cycling
quantization error &
quantization noise
Notice \(e_q\in (0, \Delta)\) and
its average is \(\Delta/2\). To
calculate SNDR, DC component shall be excluded
Don't confuse resolution\(\Delta\) with Bounded Quantization
Noise\(-\Delta/2 \sim
\Delta/2\)
Redundancy
decision level
final digital output for an \(N\)-bit \(M\)-step ADC can be calculated \[
D_{out} = s(M) + \sum_{i=1}^{M-1}(2\cdot b[i] - 1)\times s(i) + (b[0]
-1)\cdot s(1)
\]
i
M
M-1
M-2
...
2
1
0
b[i]
b[M-1]
b[M-2]
...
b[2]
b[1]
b[0]
s[i]
s(M)
s(M-1)
s(M-2)
...
s(2)
s(1)
track the decision level
For \(N\)-bit binary weighted
algorithm,\(N=M\) and \(s(i)=2^{i-1}\), where \(i\in \{N, N-1,...,2,1 \}\)
For the \(n\)th output bit, once a
decision is made, the next decision level will either move up or down by
the step size of \(s(n − 1)\)
If this decision is erroneous, then the sum of the follow-on step
sizes, \(s(n − 2)\), \(s(n − 3)\), ..., \(s(1)\), must be large enough and exceed the
value of the current step size to counteract this mistake
The exceeded amount is the tolerance window for that decision
level
When the ADC is designed with a fixed radix, \(\alpha\) and the required number of
conversion steps, \(M\)
the sum of all the step sizes \(s_{tot}\)\[
s_{tot} = \sum_{k=0}^{M-1} s_0 \alpha^k = s_0\frac{\alpha^M-1}{\alpha-1}
\]
where \(s(i)\) is step size and
\(i \in [0, 1, 2, M-1]\)
The effective number of bits, \(N\),
can be calculated \[
N \leq \log 2\left(\frac{s_{tot} + s_0}{s_0}\right) =
\frac{\alpha^M+\alpha-2}{\alpha-1}
\]
Speed Benefit
TODO 📅
MSB with noise simualtion
CDAC
The charge redistribution capacitor network is used to
sample the input signal and serves as a digital-to-analog converter
(DAC) for creating and subtracting reference voltages
inverse Laplace Transform is \(V_y(t) =
\frac{C_1}{C_1+C_2}\left(1 - e^{-t/\tau}\right)\)
\(V_x(t)\) and \(V_y(t)\) prove that the settling time is
same
\(\tau = R\frac{C_1C_2}{C_1+C_2}\),
which means usually worst for MSB capacitor (largest)
both \(\tau\) and \(\Delta V\) are the maximum
A popular way to improve the settling behavior, again, is to employ
unit-element DACs that statistically reduce the switching activities,
which, unfortunately, exhibits unnecessary complications to the power,
area and speed tradeoffs of the design
That make sense, charge redistribution consume
energy
CDAC structure
CDAC with constant common-mode voltage
Comparator
Comparator input cap effect
\[
-V_{in}\cdot 2^N C = V_c (2^N C + C_p)
\] Then \(V_c = -\frac{2^N C}{2^N C +
C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude
by the factor
During conversion \[\begin{align}
V_c &= -\frac{2^N C}{2^N C + C_p}V_{in} +V_{ref}\sum_{n=0}^{N-1}
\frac{b_n\cdot2^n C}{2^N C + C_p} \\
&= \frac{2^N C}{2^N C + C_p}\left(-V_{in} +
V_{ref}\sum_{n=0}^{N-1}\frac{b_n }{2^{N-n}} \right)
\end{align}\]
That is, it does not change the sign
Comparator offset effect
Synchronous SAR ADC
It also divides a full conversion into several comparison stages in a
way similar to the pipeline ADC, except the algorithm is
executed sequentially rather than in parallel
as in the pipeline case.
However, the sequential operation of the SA algorithm has
traditionally been a limitation in achieving high-speed
operation
a clock running at least \((N + 1) \cdot
F_s\) is required for an \(N\)-bit converter with conversion rate of
\(F_s\)
every clock cycle has to tolerate the worst case comparison
time
every clock cycle requires margin for the clock jitter
The power and speed limitations of a synchronous SA design comes
largely from the high-speed internal clock
The comparator itself trigger the next bit-conversion cycle as soon
as the present bit decision has been taken
The maximum resolving time reduction between synchronous and
asynchronous case is two fold
comparator metastable state
when the input is sufficiently small. The time needed for
the comparator outputs to fully resolve may take arbitrarily
long
In this case, the ready signal generator should still set the
flag and the decision result is simply taken from the previous
value stored in the SR latch
both outputs (\(Q_p\) and \(Q_n\)) will drop together, NAND is
inverter actually
The transition point of this NAND gate is skewed to
eliminate metastability issues arising when the input differential
voltage level is small (comparator)
reference
Andrea Baschirotto, "T6: SAR ADCs" ISSCC2009
Pieter Harpe, ISSCC 2016 Tutorial: "Basics of SAR ADCs Circuits &
Architectures"
Mike Shuo-Wei Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW
Asynchronous ADC in 0.13-μm CMOS," in IEEE Journal of Solid-State
Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006 [pdf,
slides]
C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit
50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in
IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp.
731-740, April 2010 [https://sci-hub.se/10.1109/JSSC.2010.2042254]
L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From
Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State
Circuits Society, vol. 1, pp. 149-161, 2021 [pdf]
W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant
Successive-Approximation-Register Analog-to-Digital Converter With
Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46,
no. 11, pp. 2661-2672, Nov. 2011 [https://sci-hub.st/10.1109/JSSC.2011.2163556]
D. Pfaff et al., "7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss
Transceiver in 3nm FinFET CMOS," 2024 IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, USA, 2024 [https://iccircle.com/static/upload/img20240529101747.pdf]
—, "A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free
Transceiver in 3-nm FinFET CMOS (Invited)," 2025 IEEE Custom
Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp.
1-8, doi: 10.1109/CICC63670.2025.10983461.
E. Swindlehurst et al., "An 8-bit 10-GHz 21-mW Time-Interleaved SAR
ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch," IEEE
Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, 2021,
[https://sci-hub.se/10.1109/JSSC.2021.3057372]
SFDR & INL
Beware, this is of course only true under the same conditions at
which the INL was taken, i.e. typically low input signal
frequency
Track Time
Finite Acquisition Time - Consider a sinusoidal input
Boris Murmann, EE315B VLSI Data Conversion Circuits, Autumn 2013 [pdf]
Redundancy
Max tolerance of comparator offset is \(\pm
V_{FS}/4\)
\(b_j\) error is \(\pm 1\)
\(b_{j+1}\) error is \(\pm 2\) , wherein \(b_{j+1}\): \(0\to
2\) or \(1\to -1\)
i.e. complementary analog and digital errors cancel each other, \(V_o +\Delta V_{o}\) should be in
over-/under-range comparators (\(-V_{FS}/2 \sim 3V_{FS}/2\))
Krämer, M. et al. (2015) High-resolution SAR A/D converters with
loop-embedded input buffer. dissertation. Available at: [http://purl.stanford.edu/fc450zc8031].
A. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to
Digital Converter," IEEE J. Solid-State Circuits, pp. 599, May 1999 [https://sci-hub.se/10.1109/4.760369]
Dessouky and Kaiser, "Input switch configuration suitable for
rail-to-rail operation of switched opamp circuits," Electronics Letters,
Jan. 1999. [https://sci-hub.se/10.1049/EL:19990028]
N. Blachman, "The intermodulation and distortion due to quantization
of sinusoids," in IEEE Transactions on Acoustics, Speech, and Signal
Processing, vol. 33, no. 6, pp. 1417-1426, December 1985 [https://sci-hub.st/10.1109/TASSP.1985.1164729]
The quantization noise is an infinite sum of input signal
odd harmonics, where the amplitude of the harmonics is
determined by a sum of a Bessel function
"Quantization noise is white", because for a high
number of bits, it looks white in the FFT
ENOB & SQNR
The quantization noise power \(P_Q\)
for a uniform quantizer with step size \(\Delta\) is given by \[
P_Q = \frac{\Delta ^2}{12}
\] For a full-scale sinusoidal input signal with an amplitude
equal to \(V_{FS}/2\), the input signal
is given by \(x(t) =
\frac{V_{FS}}{2}\sin(\omega t)\)
Then input signal power \(P_s\) is
\[
P_s = \frac{V_{FS}^2}{8}
\] Therefore, the signal-to-quantization noise ratio
(SQNR) is given by \[
\text{SQNR} = \frac{P_s}{P_Q} =
\frac{V_{FS}^2/8}{\Delta^2/12}=\frac{V_{FS}^2/8}{V_{FS}^2/(12\times
2^{2N})} = \frac{3\times 2^{2N}}{2}
\] where \(N\) is the number of
quantization bits
When represented in dBs \[
\text{SQNR(dB)} = 10\log(\frac{P_s}{P_Q}) = 10\log(\frac{3\times
2^{2N}}{2})= 20N\log(2) + 10\log(\frac{3}{2})= 6.02N + 1.76
\]
DAC DNL
One difference between ADC and DAC is that DAC DNL can be less
than -1 LSB
Standard deviation of INL is maximum at mid-scale
(k=N/2)
Hold Mode Feedthrough
P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS," 2008 IEEE
International Solid-State Circuits Conference - Digest of Technical
Papers, San Francisco, CA, USA, 2008, pp. 544-634
B. Sedighi, A. T. Huynh and E. Skafidas, "A CMOS track-and-hold
circuit with beyond 30 GHz input bandwidth," 2012 19th IEEE
International Conference on Electronics, Circuits, and Systems (ICECS
2012), Seville, Spain, 2012, pp. 113-116
\[
y[n+N_R'] = \sin\left( 2\pi (n+N_R')\frac{M_C}{N_R} \right) =
\sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi N_R'\frac{M_C}{N_R}\right)
= \sin\left( 2\pi n \frac{M_C}{N_R} + 2\pi
N_R'\frac{kM_C'}{kN_R'} \right) = \sin\left( 2\pi n
\frac{M_C}{N_R}\right)
\]
So, the samples is repeated \(y[n] =
y[n+N_R']\)
\(N_R\) & \(M_C\)irreducible ratio
(mutually prime)
Periodic sampling points result in periodic
quantization errors
Periodic quantization errors result in harmonic
distortion
Choosing M/N non-prime repeats the signal quantization periodically
and fewer quantization steps are measured. The quantization repeats
periodically and creates a line spectrum that can obscure real frequency
lines (e.g. the red lines in the images below, created by
non-linearities of the ADC).
It divides the process into several comparison stages, the number of
which is proportional to the number of bits
Due to the pipeline structure of both analog and digital signal path,
inter-stage residue amplification is needed which
consumes considerable power and limits high speed operation
During \(\Phi_1\), all capacitor are
shorted, the net charge at \(V_x\) is
0
During \(\Phi_2\), the charge at
bottom plate of CDAC \[
Q_{DAC,btm} = \sum_{i=0}^{N-1}(b_i\cdot V_R - V_x)\cdot 2^{i}C_u =
C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x
\] the charge at the internal plate of integrator \[
Q_{intg} = V_x C_p + (V_x - V_o)2^NC_u
\] and we know \(-V_x A = V_o\)
and \(Q_{DAC,btm} = Q_{intg}\)\[
C_uV_R\sum_{i=0}^{N-1}b_i2^i - (2^N-1)C_uV_x = V_x C_p + (V_x -
V_o)2^NC_u
\] i.e. \[
C_uV_R\sum_{i=0}^{N-1}b_i2^i = (2^N-1)C_uV_x + V_x C_p + (V_x -
V_o)2^NC_u
\] therefore \[
-V_o = \frac{2^N
C_u}{\frac{(2^{N+1}-1)C_u+C_p}{A}+2^NC_u}\sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right)\approx
\sum_{i=0}^{N-1}b_i\left(2^i\frac{V_R}{2^N}\right)
\]
Midscale (MSB Transition) often is the largest DNL
error
\(C_4\) and \(C_1+C_2+C_3\) are independent (can't cancel
out) and their variance is two largest (\(16\sigma_u^2\), \(15\sigma_u^2\), ), the total standard
deviation is \(\sqrt{16\sigma_u^2+15\sigma_u^2}=\sqrt{31}\sigma_u\)
reference
Maloberti, F. Data Converters. Dordrecht, Netherlands:
Springer, 2007.
Ahmed M. A. Ali 2016, "High Speed Data Converters" [pdf]
Razavi B. Analysis and Design of Data Converters. Cambridge
University Press; 2025.
source follower alleviate gate leakage impact on reference
current
constant-gm
aka. Beta-multiplier reference
\(I_\text{out}\) is
PTAT in case temperature coefficient of \(R_s\) is less than that of \(\mu_n\)
Body effect of M2
Boris Murmann, Systematic Design of Analog Circuits Using
Pre-Computed Lookup Tables
S. Pavan, "Systematic Development of CMOS Fixed-Transconductance Bias
Circuits," in IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 69, no. 5, pp. 2394-2397, May 2022
S. Pavan, "A Fixed Transconductance Bias Circuit for CMOS Analog
Integrated Circuits", IEEE International Symposium on Circuits and
Systems, ISCAS 2004, Vancouver , May 2004
Why MOS in saturation ?
\(g_m\), \(g_\text{ds}\) at fixed \(V_\text{GS}\)
\(g_{ds}\) is constant in saturation
region
in triode region \[
g_{ds} = \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}-V_{DS})
\]
Interestingly, \(g_m\) in the
saturation region is equal to the inverse of \(R_\text{on}\) in the deep triode
region.
\(g_m\), \(g_\text{ds}\) at fixed \(I_d\), \(V_G\)
In triode region\[
I_D =
\frac{1}{2}\mu_nC_{ox}\frac{W}{L}[2(V_{GS}-V_{TH})V_{DS}-V_{DS}^2]
\] where \(I_D\) and \(V_G\) is fixed
Then \(V_S\) can be expressed with
\(V_D\), that is \[
V_S = V_{GT} - \sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}
\] where \(V_{GT}=V_G-V_{TH}\),
\(V_{dsat}\) is \(V_{DS}\) saturation voltage \[
g_m =
\mu_nC_{ox}\frac{W}{L}\left(V_D-V_{GT}+\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}\right)
\] Then \[
\frac{\partial g_m}{\partial V_D} \propto 1 -
\frac{V_{GT}-V_D}{\sqrt{(V_{GT}-V_D)^2+V_{dsat}^2}} \gt 0
\]
We get \(I_{\Delta_{V_{TH}}}\simeq
1.71\%\) and \(I_{\Delta_{WL}} \simeq
1.73\%\)
Biasing
current source and global variation Monte Carlo
iwl: biased by mirror
iwl_ideal: biased by vdc source, whose
value is typical corner
For local variation, constant voltage bias
(vb_const in schematic) help reduce variation from \(\sqrt{2}\Delta V_{th}\) to \(\Delta V_{th}\)
For global variation, all device have same
variation, mirror help reduce variation by sharing same \(V_{gs}\)
global variation + local variation (All MC)
local variation (Mismatch MC)
global variation (Process MC)
We had better bias mos gate with mirror rather than the vdc
source while simulating sub-block.
This is real situation due to current source are always biased by
mirror and vdc biasing don't give the right result in global
variation Monte Carlo simulation (542.8n is too pessimistic,
13.07p is right result)
For any given constant values of u and v, the
constant values of variables that solve the the feed back relationship
are called the operating points, or equilibrium
points.
Operating points can be either stable or
unstable.
An operating point is unstable if any or some small perturbation near
it causes divergence away from that operating point.
If the loop gain evaluated at an operating point is less than
one, that operating point is stable.
This is a sufficient condition
With \(m_{1\to 2} = 1\)\[
\text{Loop Gain} \simeq \frac{V_{BN}-V_{T2}}{V_{BN}-V_{T2} + V_R}
\tag{$LG_0$}
\] Assuming all MOS in strong inv operation, \(I\), \(V_{BN}\) and \(V_R\) is obtain \[\begin{align}
I &= \frac{2\beta _1 + 2\beta _2 - 4\sqrt{\beta _1 \beta
_2}}{R^2\beta _1 \beta _2} \\
V_{BN} &= V_{T2} + \frac{2}{R\beta _2}(1- \sqrt{\frac{\beta
_2}{\beta _1}}) \\
IR &= \frac{2}{R}\left( \frac{1}{\sqrt{\beta_2}}
- \frac{1}{\sqrt{\beta_1}} \right)
\end{align}\]
Substitute \(V_{BN}\) and \(V_R\) of \(LG_0\)\[\begin{align}
\text{Loop Gain} & \simeq
\frac{1-\sqrt{\frac{\beta_2}{\beta_1}}}{\frac{\beta_2}{\beta_1} -
3\sqrt{\frac{\beta_2}{\beta_1}}+2} \\
&= \frac{1}{2-\sqrt{\frac{\beta_2}{\beta_1}}} \tag{$LG_1$}
\end{align}\]
Alternative approach for
Loop Gain
using derivation of large signal
❗❗❗ R should not be on the other side
Self-Biasing Cascode
reference
B. Razavi, "The Design of a Low-Voltage Bandgap Reference [The Analog
Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3,
pp. 6-16, Summer 2021, doi: 10.1109/MSSC.2021.3088963
E. Alvarez-Fontecilla, P. S. Wilkins and S. C. Rose, "Understanding
High-Resolution Dynamic Element Matching DACs [Feature]," in IEEE
Circuits and Systems Magazine, vol. 23, no. 4, pp. 34-43,
Fourthquarter 2023
E. Alvarez-Fontecilla and P. S. Wilkins, "Linearity Through Democracy
[Feature]," in IEEE Circuits and Systems Magazine, vol. 25, no.
1, pp. 58-69, Firstquarter 2025
Autozeroing
offset is sampled and then subtracted from the
input
Measure the offset somehow and then subtract it from the input
signal
then \[
\Delta I_1 = \frac{1}{2}(V_{a1} - V_{b1})(g_{m,a1}+g_{m,b1})
\] That is, \(g_{m,a1}+g_{m,b1} = \mu
C_{OX}\frac{W}{L}(V_{a1}+V_{b1} - 2V_{TH})\)
To minimize the difference between \(\Delta
I_1\) and \(\Delta I_0\), the
drift of both differential and common mode between \(V_a\) and \(V_b\) shall be alleviated
Chopping
offset is modulated away from the signal band and
then filtered out
Modulate the offset away from DC and then filter it out
Good: Magically reduces offset, 1/f noise, drift
Bad: But creates switching spikes, chopper ripple
and other artifacts …
Chopping in the Frequency
Domain
Square-wave Modulation
definition of convolution \(y(t) =
x(t)*h(t)= \int_{-\infty}^{\infty} x(\tau)h(t-\tau)d\tau\)
The Fourier transform of \(s(t)=x(t)x(t)\), and we know \[\begin{align}
S(j2n\omega_0) &= \frac{1}{2\pi}\int X(j(2n\omega_0
-\omega))X(j\omega) d\omega\\
&= \frac{1}{2\pi}\int X(j(\omega-2n\omega_0))X(j\omega) d\omega
\end{align}\]
lower effective gain: DC level at the output of the
amplifiers is a bit less than what it should be
chopping artifacts at the even harmonics: frequency of
output is \(2f_{ch}\)
Below we justify \(A_\text{eff} =
A(1-4\tau/T_\text{ch})\)\[\begin{align}
V_o(t) &= A + (V_0-A)e^{-t/\tau} \\
V_o(T/2) &= -V_0
\end{align}\]
then \[
V_0 = -A\frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}}
\] Then DC level is \[
A_\text{eff} = \frac{1}{T/2}\int_0^{T/2} V_o(t)dt =
A\left(1-\frac{4\tau}{T}\cdot
\frac{1-e^{-T/2\tau}}{1+e^{-T/2\tau}}\right)\approx
A\left(1-\frac{4\tau}{T}\right)
\]
The spectrum of the narrowband FM signal is very similar to that of
an amplitude modulation (AM) signal but has the phase
reversal for the other sideband component
Assume the modulation frequency of PM and AM are
same, \(\omega_m\)
A. A. Abidi and D. Murphy, "How to Design a Differential CMOS LC
Oscillator," in IEEE Open Journal of the Solid-State Circuits
Society, vol. 5, pp. 45-59, 2025, doi: 10.1109/OJSSCS.2024 [pdf]
The three most widely adopted techniques are direct
spectrum, phase detector, and
two-channel cross-correlation.
While the direct spectrum technique measures phase noise with the
existence of the carrier signal, the other two remove the carrier
(demodulation) before phase noise is measured.
Though direct spectrum technique method may not be useful
for measuring very close-in phase noise to a drifting carrier,
it is convenient for qualitative quick evaluation on sources with
relatively high noise
\[
y(t) = A\cos(2\pi f_0t+\phi_n(t)) \approx A \cos(2\pi f_0 t) - A \phi_n
(t)\sin(2\pi f_0 t)
\]
\[
R_x(\tau) = \frac{A^2}{2}\cos(2\pi f_0\tau)
+ \frac{A^2}{2}R_\phi(\tau)\cos(2\pi f_0\tau)
\] The PSD of the signal x(t) is given by \[
S_x(f) = \mathcal{F}\{R_x(\tau)\} =
\frac{P_c}{2}\left[\delta(f+f_0)+\delta(f-f_0)\right]+\frac{P_c}{2}\left[S_\phi(f+f_0)+S_\phi(f-f_0)\right]
\] where \(P_c = A^2/2\) is the
carrier power of the signal
Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing,
3rd edition [pdf]
R. E. Ziemer and W. H. Tranter, Principles of Communications, 7th
ed., Wiley, 2013 [pdf]
John G. Proakis and Masoud Salehi, Fundamentals of communication
systems 2nd ed [pdf]
Rhee, W. and Yu, Z., 2024. Phase-Locked Loops: System
Perspectives and Circuit Design Aspects. John Wiley & Sons
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007
Phillips, Joel R. and Kenneth S. Kundert. "Noise in mixers,
oscillators, samplers, and logic: an introduction to cyclostationary
noise." Proceedings of the IEEE 2000 Custom Integrated Circuits
Conference. [pdf, slides]
ACMatch analysis linearizes the circuit about the DC operating point
and computes the variations of AC responses
due to statistical parameters defined in statistics blocks.
Only mismatch parameters are considered. The analysis skips the
process parameters.
//Curve parameters real gm; real A; real factor; real Vop; real vcp;
integer light_i; integer en; analog begin
@(initial_step) begin en = 0; A = 1; Vop = 1; factor = 10; end //Enable digitalization @(cross(V(EN)-vthreshold,1)) begin if(V(EN)>=vthreshold) en = 1; else en = 0; end case(light): 0: begin A = 0; Vop = 0; end 1: begin A = -1.2; Vop = 1.71; end 2: begin A = -0.8; Vop = 1.64; end 3: begin A = -0.4; Vop = 1.50; end 4: begin A = 0.1; Vop = 1.43; end 5: begin A = 0.7; Vop = 1.36; end 6: begin A = 1.1; Vop = 1.22; end default: begin A = -1.2; Vop = 1.71; end endcase
//gm = A + atan(factor*(Vop-V(Vsolar))); //Transconductance
alias bk hiSetBindKey when ( isCallable('schGetEnv') bk("Schematics" "Ctrl<Key>x" "schHiCreateInst(\"basic\" \"nonConn\" \"symbol\")") bk("Schematics" "Ctrl<Key>v" "schHiCreateInst(\"analogLib\" \"vdc\" \"symbol\")") bk("Schematics" "Ctrl<Key>g" "schHiCreateInst(\"analogLib\" \"gnd\" \"symbol\")") bk("Schematics" "Shift<Key>9" "geDeleteNetProbe()") bk("Schematics" "<Key>0" "geDeleteAllProbe(getCurrentWindow()t)") ) unalias bk
leBindKeys.il
layout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
alias bk hiSetBindKey when ( isCallable('leGetEnv) bk("Layout" "<Key>1" "leSetEntryLayer(\"M0PO\") leSetAllLayerVisible(nil) leSetEntryLayer(\"M0OD\") leSetEntryLayer(\"VIA0\") leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(\"M1\") hiRedraw()" ) ; M1-VIA1-M2 bk("Layout" "<Key>2" "leSetEntryLayer(\"M1\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA1\") leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(\"M2\") hiRedraw()" ) ; M2-VIA2-M3 bk("Layout" "<Key>3" "leSetEntryLayer(\"M2\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA2\") leSetEntryLayer(list(\"M3\" \"pin\")) leSetEntryLayer(\"M3\") hiRedraw()" ) ; M3-VIA3-M4 bk("Layout" "<Key>4" "leSetEntryLayer(\"M3\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA3\") leSetEntryLayer(list(\"M4\" \"pin\")) leSetEntryLayer(\"M4\") hiRedraw()" ) ; M4-VIA4-M5 ; select M4 layer, turn off other layer visibilty, select VIA4 M5_pin M5 and turn on them bk("Layout" "<Key>5" "leSetEntryLayer(\"M4\") leSetAllLayerVisible(nil) leSetEntryLayer(\"VIA4\") leSetEntryLayer(list(\"M5\" \"pin\")) leSetEntryLayer(\"M5\") hiRedraw()" ) ; all visiable bk("Layout" "<Key>0" "leSetAllLayerVisible(t) hiRedraw()" ) ) unalias bk
Design Variable in vpwlf
PWL File as Design Var? parameter in vpwlf cell
is convenient for sweep simulation or corner simulation, wherein there
are multiple pwl files .
The file path should be surrounded with
double-quotes to be protected from evaluation.
save option
Using Spectre Save Effectively RAK
none:
Does not save any data (currently does save one node chosen at
random)
selected:
Saves only signals specified with save statements. The default
setting.
lvlpub:
Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits.
lvl:
Saves all signals up to nestlvl deep in the subcircuit hierarchy.
This option is relevant for subcircuits.
allpub:
Saves only signals that are normally useful.
all:
Saves all signals.
Signals that are "normally useful" include the shared node voltages
and currents through voltage sources and iprobes, and exclude the
internal nodes on devices (the internal collector, base, emitter on a
BJT, the internal drain, source on a FET, and so on). It also excludes
currents through inductors, controlled sources, transmission lines,
transformers, etc.
If you use lvl or all instead of
lvlpub or allpub, you will also get
internal node voltages and currents through other components that happen
to compute current.
Thus, using *pub excludes internal nodes on devices
(the internal collector, base, emitter on a BJT, the internal drain and
source on a FET, etc). It also excludes the currents through inductors,
controlled sources, transmission lines, transformers, etc.
nestlvl
This variable is used to save groups of signals as results and when
signals are saved in subcircuits. The nestlvl parameter also specifies
how many levels deep into the subcircuit hierarchy you want to save
signals.
virtuoso "dlopen failed
to open 'libdl.so'"
1
$ sudo yum install glibc-devel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Last metadata expiration check: 0:01:02 ago on Sat 24 Sep 2022 12:13:54 AM CST. Dependencies resolved. ========================================================================================================================================= Package Architecture Version Repository Size ========================================================================================================================================= Installing: glibc-devel x86_64 2.28-189.5.el8_6 baseos 78 k Installing dependencies: glibc-headers x86_64 2.28-189.5.el8_6 baseos 482 k kernel-headers x86_64 4.18.0-372.26.1.el8_6 baseos 9.4 M libxcrypt-devel x86_64 4.1.1-6.el8 baseos 24 k
* DSPF files to use with Corner Definitions * This is an example file showing how to define different dspf files for different corners * using model files for individual components as the * building blocks. simulator lang=spectre library dspf_files_corners
section rcworst_25 dspf_include "DSPF_RC_WORSE25.spf" end section rcworst_25
section rcworst_125 dspf_include "DSPF_RC_WORSE125.spf" end section rcworst_125
endlibrary dspf_files_corners
Add the file created above ‘myDSPF_File.scs’ in
‘Add/Edit Model Files’ of Corners setup form
split pins in dspf_emir
dspf extract using starrc
multiple label and rectangle in vssa net
general dspf
SHORT_PINS: YES
other pin are short together
dspf for emir analysis
It seems that dspf_emir don't contain the
rectangle pin information.
only label is necessary
setup
spectre result
netlist type
dspf option
emir analysis
dspf
/
disable
✓
dspf_emir
/
disable
✗
dspf_emir
shortPins="yes"
disable
✓
dspf_emir
shortPins="no"
disable
✗
dspf_emir
/
enable
✓
dspf_emir
shortPins="yes"
enable
✓
dspf_emir
shortPins=”no”
enable
✓
shortPins="yes" is preferred default option for
dspf_emir, which has split pins
DSPF Syntax
::=*|P ?
describes pins in the net. Multiple pin descriptions can be listed in
one line.
::=( {}?)
represents the name of the pin. represents the type
of the pin. It can be any of the following: I (Input), O (Output),
B (Bidirectional), X (don’t care), S (Switch), and J (Jumper).
represents the capacitance value associated with the pin.
is optional. It represents the location of the pin. Multiple pin
locations are allowed
split pins
1 2 3 4 5
*|P (avss_1 O 0 207.7555 59.9170) *|P (avss_10 O 0 181.1610 151.1130) *|P (avss_11 O 0 186.6330 151.1130) *|P (avss_12 O 0 192.1050 151.1130) *|P (avss_13 O 0 197.5770 151.1130)
StarRC User Guide and Command Reference Version O-2018.06, June
2018
DSPF Options
Case Sensitivity
netlist format
default option
Spectre netlist
case sensitive
dspf format
case insensitive
For a dspf format, it will be treated as a spice
netlist format, which is by default case insensitive
Pay attention to VerilogIn block, which may contain upper
case / lower case net name, e.g NET1 and net1.
The extracted DSPF using extraction tool also contain NET1 and net1,
which shall not be shorted together.
Port Order
If you use .dspf_include, the following rules apply:
The subcircuit description is taken from the DSPF file even if the
same subcircuit description is available in the schematic netlist.
Depending on the port_order option, the port order of
the subcircuit definition is taken from the pre-layout schematic netlist
or from the DSPF file subcircuit definition, as shown below.
port_order=sch – (Default). The port order is taken
from schematic subcircuit definition. The same port number and names are
required. If the schematic subcircuit definition is not available, a
warning is issued in the log file, and DSPF port order is used.
port_order=spf – The port order is taken from the DSPF
subcircuit definition.
SPICE_SUBCKT_FILE of StarRC
The StarRC tool reads the files specified by the
SPICE_SUBCKT_FILE command to obtain port ordering
information. The files control the port ordering of the top
cell as well. The port order and the port list members read from the
.subckt for a skip cell are preserved in the output
netlist.
The file usually is the cdl netlist of extracted cell, this
way, port order is not problem
CDF termOrder
DSPF same order
DSPF
input.scs
different order
manual change DSPF's pin order shown as below
port_order=sch
dspf port is mapping to schematic by name, and the
simulation result is right
port_order=spf
dspf pin order is retained, and no mapping between
spectre netlist and dspf.
The simulation result is wrong
bus_delim="_ <>"
The way this works is that the first part of bus_delim is
the "schematic" delimiter (i.e. what's in the spectre netlist), and the
other part is the DSPF delimiter
Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit
Simulator - Analog/Custom Design - Cadence Blogs - Cadence Community https://shar.es/afO6e1
StarRC™ User Guide and Command Reference Version O-2018.06, June
2018
Virtual Connectivity
Normally, if the layout connectivity extractor finds disjoint,
unconnected geometries with the same net name text attached, the
extractor will view this as an open circuit.
Virtual connection results in the extraction of a single net from
two or more disjoint physical nets when the physical net segments share
the same name.
Virtual connectivity is triggered by the rule file VIRTUAL
CONNECT COLON and VIRTUAL CONNECT NAME
specification statements.
Virtual connectivity can also be specified through the Calibre
Interactive GUI.
Virtual connectivity is of primary interest in
LVS applications
connect all nets by name:
VIRTUAL CONNECT NAME "?"
VIRTUAL CONNECT COLON
Virtual Connect Colon is used to virtually connect
nets that share a common prefix before a colon, like
VDD:1, VDD:2, and so forth.
If you specify YES, then the connectivity extractor first
strips off all characters from the first colon to the end of
the label names.
Next, the extractor forms a virtual connection between any two labels
that have the same name and that originally contained a
colon.
Colons can appear anywhere in the name with the exception that a
colon at the beginning of a name is treated as a regular character (that
is, it has no special effect).
up to the first colon character encountered
The colon is discarded in the extracted net
name
VIRTUAL CONNECT NAME
Virtual Connect Name virtually connects nets that
share the same name
Each name is a net name and can be optionally enclosed in quotes.
The connectivity extractor forms a virtual connection between
any two labels having the same name such that
the label name appears in a Virtual Connect Name
specification statement in the rule file.
VIRTUAL CONNECT NAME ? == Connect all nets by name
Note that if Virtual Connect Colon YES is also
specified, then Virtual Connect Name operates on names
after all colon suffixes have been stripped off.
Calibre Interactive stores a list of your most recently opened
runsets in your home directory as .cgidrcdb or
.cgilvsdb for Calibre Interactive DRC or LVS,
respectively.
When invoked, the Calibre DRC and LVS windows automatically load the
runset used when the last session was closed.
Runsets are ASCII files that set up Calibre Interactive for a Calibre
run. They contain only information that differs from the default
configuration of Calibre Interactive. There is a one-to-one
correspondence between entry lines in the runset file and fields and
button items in the Calibre Interactive user interface. Here is as
example of a DRC runset:
The runset filename opened at startup (if no runset is specified on
the command line) can also be specified by setting the
MGC_CALIBRE_DRC_RUNSET_FILE environment variable for DRC,
and the MGC_CALIBRE_LVS_RUNSET_FILE environment variable
for LVS. If these environment variables are set, they take precedence
over all other runset opening behavior options.
On the transient options form, there's a field called "infotimes" -
specify the times at which you want it to output the dc operating point
data. You can then annotate the "transient operating points" from any of
these times after the simulation, or access them via the results
browser.
Or you could get the operating point data to be continuously saved
during the transient for selected devices - if so, create a file called
(say) "save.scs" (make sure it has a ".scs" suffix), and put: save
M1:oppoint or save M*:oppoint sigtype=dev in this file, and then
reference the file via Setup->Model Libraries or as a "definition
file" on Setup->Simulation Files. With this approach you can then
find the operating point data for the selected devices in the results
browser and plot it versus time (be cautious of saving too much though
because this can generate a lot of data if you're not careful)
<divider> represents the hierarchical pathname
divider. The default hierarchical character is forward slash
(/).
*|DELIMITER <delimiter>
<delimiter> represents the delimiter character
used to concatenate an instance name and pin name to form an instance
pin name.
It is also represents the delimiter character used to concatenate a
net name and subnode number to form a subnode name. The default
character is colon (:)
*|BUSBIT <left_busbit_char><right_busbit_char>
<left_busbit_char> and
<right_busbit_char> are used at the end of an
identifier of an array to select a single object of the array.
Objects which may be indexed include nets, primary pins, and
instance pins
*|NET <netName> <netCap>
<netName> represents the name of a net. It can be
a user-provided net name, the name of the driving pin, or the name of
the driving instance pin.
<netCap> represents the total
capacitance value in farads associated with the net. This may be
comprised of capacitances to ground and capacitances to nearby
wires.
*|P <pinName> <pinType> <pinCap> {<coord>}
<pinName> represents the name of the pin.
<pinType> represents the type of the pin. It can
be any of the following: I (Input), O (Output), B (Bidirectional), X
(don’t care), S (Switch), and J (Jumper).
<pinCap> represents the capacitance value
associated with the pin.
<coord> is optional. It represents the location
of the pin. Multiple pin locations are allowed.
*|S <subNodeName> {<coord>}
subnodes in the net
<subNodeName> represents the name of the subnode.
A subnode name is obtained by concatenating the net name and a subnode
number using the delimiter specified in the DELIMITER statement. The
default delimiter is colon (:).
<instPinName> represents the name of the instance
pin. An instance pin name is obtained by concatenating the
<instName> and the <pinName> with
a delimiting character which is specified by the DELIMITER
statement
<instName> represents the name of the
instance
*|DeviceFingerDelim "@"
MOS finger delimiter
For example, M8's finger is 4, then split into 4 Devices
in DSPF
MM8, MM8@2, MM8@3,
MM8@4
its drain terminal will be
MM8:d, MM8@2:d, MM8@3:d,
MM8@4:d
DSPF Syntax
DSPF has two sections:
a net section
The net section consists of a series of net description blocks. Each
net description block corresponds to a net in the physical design. A net
description block begins with a net statement followed by pins, instance
pins, subnodes, and parasitic resistor/capacitor
(R/C) components that characterize the
electrical behavior of the net.
an instance section
The instance section consists of a series of SPICE instance
statements. SPICE instance statements begin with an
X.
Each file consists of hierarchical cells and interconnects only.
The DSPF format is as generic and as much like SPICE as possible.
While native SPICE statements describe the R/C sections, some non-native
SPICE statements complete the net descriptions. These non-native SPICE
statements start with the notation "*|" to differentiate them from
native SPICE statements. For native SPICE statements, a continuation
line begins with the conventional "+" sign in the first column.
The native SPICE statements used by the DSPF format are listed
below:
.SUBCKT represents a subcircuit statement.
.ENDS represents the end of a subcircuit
statement.
R represents a resistor element.
C represents a capacitor element.
E represents a voltage-controlled voltage sources
element.
X represents an instance of a cell;
* represents a comment line unless it is
*| or *+.
.END is an optional statement that represents the end
of a simulation session
spectre netlist
hier_delimiter="."
Used to set hierarchical delimiter. Length of
hier_delimiter should not be longer than 1, except the
leader escape character
This option maps the bus delimiter between schematic netlist and
parasitic file (i.e. DSPF, SPEF, or DPF). The option defines the bus
delimiter in the schematic netlist, and optionally the bus delimiter in
the parasitic file. By default, the bus delimiter of the parasitic file
is taken from the parasitic file header (i.e. |BUSBIT [],
|BUS_BIT [], or *|BUS_DELIMITER []). If the bus delimiter is not
defined in the parasitic file header, you need to specify it by using
the spfbusdelim option in schematic netlist.
Exampel
spfbusdelim=<> - A<1> in the schematic netlist is mapped
to A_1 in the DSPF file, if the bus delimiter header in the DSPF file is
"_".
spfbusdelim=@ [] - A@1 in the schematic netlist is mapped to to A[1]
in the DSPF file (the bus delimiter in DSPF header will be
ignored).
How to Save Net voltage in
DSPF
!!! follow the name of net section in DSPF - prepend to top-level
devices in the schematic with X
Assume node n1...n4 are named as below in DSPF file (prefix
X)
n1
XXosc/zip:1
n2
XXosc/zip:2
n3
XXosc/zip:3
n4
XXosc/zip:4
To save these nodes, you can add follow code in Definition
Files
saveopt.scs
1 2 3 4
save Xwrapper.Xvco.XXosc\/zip\:1 save Xwrapper.Xvco.XXosc\/zip\:2 save Xwrapper.Xvco.XXosc\/zip\:3 save Xwrapper.Xvco.XXosc\/zip\:4
Escape character \ is used for hierarchical pathname
divider / and subnode :
By the way, . is hierarchical delimiter of
Spectre
Calibre always prepend one X to instance name of
schematic in generated DSPF file
The DSPF design is flatten, the DIVIDER character
indicate the hierarchy
1
save Xwrapper.Xvco.XXosc\/zip
The above save voltage, however I'm NOT sure which node it save.
To avoid this unsure problem, the MOS terminal may be better choice
to save.
But keep in mind
OD resistance is lumped in the FEOL model
M0OD and above layer resistances are extracted by RC tool
How to Save Current in DSPF
!!! follow the name of instance section of DSPF - prepend to
top-level devices in the schematic with XX
MOS in schematic: Xsupply.M4
MOS related information in DSPF (prefix XX in instance
section):
1 2 3 4 5 6 7 8 9
... // net section *|I XXsupply/MM4:d XXsupply/MM4 d B 0.0
<instName> in
*|I <instPinName> <instName> <pinName> <pinType><pinCap> {<coord>?}
which has prefix X corresponding to schematic is
NOT the instance name in DSPF. The instance name is in
instance section and has prefix XX
!!! Only work for MOS terminal current. Fail to apply to block
pin
Thinking about voltage
and current save
MOS device always prepend with M
To save net voltage, take account of the prefix
X of top-level device
To save MOS terminal, take account of the prefix
XX of top-level device
Post-layout netlists are created by layout extraction tools - Mentor
Calibre
Differences
Between DSPF and Schematic Names
MOS Terminal Mismatch ( ‘s’ vs ‘1’)
Schematic: number '1' ,'2', '3','4'
DSPF: 'd', 'g', 's','b'
.simrc file
If DSPF files show such differences, you can set options in the
.simrc file to update the save statement in the
netlist so that the device names match with those in the DSPF
file
Additionally, dspf_include reads all the DSPF lines
starting with * (|NET, |I, *|P,*|S), while
include considers all related lines as comments.
Only verified to DSPF output of Mentor Calibre
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
; ensure that the netlist is recreated each time nlReNetlistAll=t
The net name is x1/x1:DRN. During the simulation, the following
warning is reported:
Warning from spectre during initial setup.
1 2
WARNING (SPECTRE-8282): `xpi1.x1/x1' is not a device or subcircuit instance name. WARNING (SPECTRE-8287): Ignoring invalid item `xpi1.x1/x1:DRN' in save statement.
How can I save this net for plotting and measurements?
Solution
The colon (:) in the save statement specifies terminal
current. So, the save statement used above is for terminal
current and, hence, the warning messages are reported.
1
save xpi1.x1\/x1:DRN
You need to modify the save statement as below:
1
save xpi1.x1\/x1\:DRN
Now, run the simulation and the issue will be resolved.
DSPF r vs rcc
rcc
c
only c dspf give the lumped
capacitance
EMIR via Voltus-Fi
general terminology
DC related
Imax in T*'s DRC document is the maximum allowed
DC current, which depends on Length and Width
only
Iavg is the average value of the current, which is
the effective DC current. Therefore, Iavg
rules are identical to Imax
rules \[
I_{\text{avg}}=\frac{\int_0^\tau I(t)dt}{\tau}
\] Similarly, Iabsavg rules are
identical to Imax rules, too \[
I_{\text{AbsAvg}}=\frac{\int_0^\tau |I(t)|dt}{\tau}
\]
rms
Irms is the root-mean-square of the current through
a metal line, which depends w(in um), the drawn
width of the metal line and \(\Delta
T\), the temperature rise due to Joule heating. \[
I_{\text{rms}}=\left[\frac{\int_0^\tau I(t)^2dt}{\tau} \right]^{1/2}
\]
peak current
Ipeak in T*'s DRC document is the current at which a
metal line undergoes excessive Joule heating and can begin to melt.
Ipeak is corresponding to
EM Current Analysis: max in Voltus-Fi Analysis Setup \[
I_{\text{peak}}=\max(|I(t)|)
\] The limit for the peak current is \[
I_{\text{peak,limit}}=\frac{I_{\text{peak\_DC}}}{\sqrt{r
} }
\] where r is the duty ratio
The relationship between Ipeak and
Ipeak_DC is merged in DRC document so that there is
only Ipeak equation in document
\(I_{\text{peak,limit}}\) depends on
\(t_D\), r, width and length
\[
r=\frac{t_D}{\tau}
\]
where \(t_D\) is equivalent duration
\[
t_D =\frac{\int_0^\tau |I(t)|dt}{I_{\text{peak}}}
\] or \[
r=\frac{I_{\text{AbsAvg}}}{I_{\text{peak}}}
\]
where the drawn width is 1um, r is 0.1
\[
9.37*(1-0.004)/\sqrt0.1 = 29.512
\]
acpeak/pwc
It's same with max EM Current Analysis in
Voltus-Fi
dynamicACPeak
This option affect how duty ratio r is computed in max
and acpeak/pwc EM current Analysis
When the dynamicACPeak variable is set to
true or multiPeak\[
r=\frac{T_d}{T_{\text{total}}}
\]
where \(T_{\text{total}} = \text{EMIR time
window}\)
\(T_d\) = the time duration in
microsecond of the total "On Time" period based on IPWC
Pulse-Wise Constant EM current calculation (IPWC)
where Tau is \(T_d\) in above formula
!!! It seems that t*'s PDK don't support
dynamicACPeak=true
IR drop filter layers
EM techfile (qrcTechFile) may take diffusion contact
(n_odtap, p_odtap in DSPF file) into account during IR
drop analysis. And these segment often dominate IR drop, but we as IC
designer can NOT improve them. In general, the IR drop to M1 layer is
enough and feasible.
Regular
analysis statements in emir configuration
1 2
net name=[I0.vdd I0.vss] analysis=[vmax vavg] net name=[I0.*] analysis =[imax ivavg irms]
emirreport command
Creating reports for specific nets after simulation using
emirreport
Create a new config file as shown below:
1 2 3
** test.conf** net name=[I1.VDD I1.VSS] analysis=[iavg] net name=[I1.VBIAS] analysis=[imax]
Run emirreport on the command line using the
emirdatabase (emir*.bin) and test.conf
created above in
input.emir0_bin: The first EMIR Analysis which is DC or
Transient, which depends on Analyses order
input_tran.emir0_bin: EMIR Analysis in Transient
simulation
input_dcOp.emir0_bin: EMIR Analysis in DC
simulation
For example
Two results are generated input.emir0_bin and
input_dcOp.emir0_bin and their reports respectly
Fix Electromigration
Type
wider wire
downsize drivers
decrease fanout
RJ JMAX
✓
✓
JAVG
JABSAVG
JACPEAK
JACRMS
✓
✓
✓
Iavg
The average value of the current, which is the effective DC
current
Irms
Irms rule relates to the heat or Joule-heating of metal
lines
Ipeak
The main goal of the Ipeak limits is to ensure that no thermal
breakdown could occur on single overshoot events. If the signal may not
have a high current density but if it has a very large peak current
density, then, local melting will happen and cause failures
QA
Q. Why “length” column in EM results form doesn’t show extracted
length, it shows “NA”.
A. Voltus-Fi reports the “length” column only when length rules are
present in the emDataFile.
Seeing different port currents with and without emir simulations
for same dspf included in EMIR Direct method using dspf_include.
Split Pins (*|P) in DSPF are only shorted in the EMIR flow not in the
regular spectre flow. Islands patching is only performed in EMIR
only
Setting temperature for EM analysis
By Default, Voltus-FI and VPS pick up the current density limit for
temperature at which simulation has been performed.
By the way, Design Variables - temperature will
override the temperature in Setup toolbar which is gray in ADE
Explorer
AC Peak EM analysis - Voltus-Fi
The available options within the EM current analysis section in the
EMIR Analysis Setup form are:
max / avg / avgabs / rms.
In order to enable the AC Peak based information when
loading the EM results, both max and avg should be
selected when setting up the EMIR Analysis Setup.
With this configuration, the AC Peak option becomes available and can
be used.
How to print average, rms, and peak current of device
tap in Spectre/Voltus FI EMIR analysis
The following option enables you to save the average, rms, and peak
tap currents in the emir0bin file and report it in the
input.rpt_tapi file.
1
solver report_tapi=true
Add this option in emir.conf to enable the reporting
of tap current after the Spectre EMIR simulation. The input.rpt_tapi
file will be saved in the psf/raw directory.
Note: This feature is supported in SPECTRE20.1 ISR14
and later versions.
emir.conf file
emir.conf file is generated automaticaly after configure
EM/IR Analysis in ADE, which is in netlist
directory.
Setting default path for EM rules file in APS EMIR analysis
set the following environment variable in your terminal
1
setenv EMDATAFILE < path to EM rules file>
or set in .cdsinit
1
setShellEnvVar("EMDATAFILE=<path to EM rules file>")
Print node names and length associated with parasitic resistors
in EM report file
export CDS_MMSIM_VOLTUSFI_ROOT=$CDSHOME
Printing the parasitic resistor length in the EM report
1
emirutil reportLength=true
Printing nodes that are associated with the parasitic
resistor
1
emirutil reportNodeName=true
Once these are enabled, you will have the Length,
Node_1, and Node_2 columns printed in
the EM report file, as shown below:
Is it possible to run RMS IR Drop analysis using Voltus-Fi?
Typically, in a simulation, Power/Ground nets are always biased with
a constant DC source. Hence, at present, Voltus-Fi only
supports Average and Maximum (Peak) IR Drop
analysis.
For a net to have data for IR analysis(vmax/vavg), the net/node must
be connected to a DC vsource or a vsource which is constant
within the emir time window.
Can we change the time window of EM computation after the
simulation completed ?
It is not possible to modify the EM time window without re-running
the full simulation.
However you can specify several time window in the emir conf file for
instance for 2 time window [0 to 10n] and [10n 20n]
1
time window=[0 10n 10n 20n]
In that case it will create 2 emir_bin files and
then 2 different em report files according to the 2 different time
windows.
How to print segment_W values being used to compute EM limits
You can use the following option to print segment_W to
the report:
1
emirutil reportSegmentWidth=[true]
This would print a Segment_w column in the report
containing the segment width values used for computing the limit:
Pass/Fail %
Resistor
layer
Current
Width
PathLength
I limit
X1
Y1
X2
Y2
J/JMAX
Res
ViaArea
No of needed vias
width/#via
J limit
Segment_w
(mA)
(um)
(um)
(um)
(um)
(um)
(um)
(nm^2)
(um/#)
(A/um)
pass-100.0
Rj3292
Met1
9.02376e-12
0.1
42.72
1.10067
0.350
11.568
0.350
11.376
8.19843e-12
0.7382
NA
NA
0.0001
0.0110067
0.1
pathLength vs Length in EM report file
Length: parasitic resistor length, which is set by
emirutil reportLength=true
pathlength: Blech length is also known as "Short length" or "Path
length", and can be explained as : The longest and continuous
centerline path from edge to edge among the connected wire
shapes on the same metal layer.
For all resistors falling on this shape, same
pathLength is reported.
After the longest path in shape has been determined the tool applies
the same blech length to all the resistor falling on that shape.
This resistor length is NOT used in EM analysis
because EM rules consider Blech length of the resistor.
where W is the wire width and L is the Blech length.
By default the tool will sum all branches of a given
metal layer. In other words the path length that will be used
to look up the EM density limit is :
To enable EMIR in PSS, you have to enable DC and/or Tran simulation
simultaneously. Two or more binary results file should be generated and
select the file based file name or configure text file in
psf directory.
(given ICADVM 18.1 ISR11, Spectre 19.1 ISR6)
StarRC
NETLIST_CONNECT_OPENS
Connector resistors - non-physical
resistors (well or substrate layer, that is not extracted for
resistance)
A. B. Kahng, S. Nath and T. S. Rosing, "On potential design impacts
of electromigration awareness," 2013 18th Asia and South Pacific Design
Automation Conference (ASP-DAC), 2013, pp. 527-532, doi:
10.1109/ASPDAC.2013.6509650.
Kumar, Neeraj and Mohammad S. Hashmi. “Study, analysis and modeling
of electromigration in SRAMs.” (2014).
N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A practical
approach to static signal electromigration analysis," Proceedings 1998
Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998,
pp. 572-577, doi: 10.1109/DAC.1998.724536.
Blaauw, David & Oh, Chanhee & Zolotov, Vladimir &
Dasgupta, Aurobindo. (2003). Static electromigration analysis for
on-chip signal interconnects. Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on. 22. 39 - 48.
10.1109/TCAD.2002.805728.
J. -H. Seol, K. Choo, D. Blaauw, D. Sylvester and T. Jang, "Reference
Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur," in
IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp.
2993-3007, Oct. 2021 [https://sci-hub.se/10.1109/JSSC.2021.3089930]
K. J. Wang, A. Swaminathan and I. Galton, "Spurious Tone Suppression
Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL," in
IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp.
2787-2797, Dec. 2008 [https://sci-hub.se/10.1109/JSSC.2008.2005716]
Frequency Divider
Gunnman, Kiran, and Mohammad Vahidfar. Selected Topics in RF,
Analog and Mixed Signal Circuits and Systems. Aalborg: River
Publishers, 2017
Large values of N lowers the loop BW which is bad for jitter
MMD (Multimodulus Divider)
TODO 📅
Noise in dividers (jitter
generation)
S. Levantino, L. Romano, S. Pellerano, C. Samori and A. L. Lacaita,
"Phase noise in digital frequency dividers," in IEEE Journal of
Solid-State Circuits, vol. 39, no. 5, pp. 775-784, May 2004 [https://sci-hub.se/10.1109/JSSC.2004.826338]
Lacaita, Andrea Leonardo, Salvatore Levantino, and Carlo Samori.
Integrated frequency synthesizers for wireless systems.
Cambridge University Press, 2007.
W. F. Egan, "Modeling phase noise in frequency dividers," in IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol.
37, no. 4, pp. 307-315, July 1990 [https://sci-hub.se/10.1109/58.56498]
Multiplying the frequency of a signal by a factor of N using an
ideal frequency multiplier increases the phase noise of
the multiplied signal by \(20\log(N)\)
dB.
Similarly dividing a signal frequency by \(N\) reduces the phase noise of the output
signal by \(20\log(N)\) dB
The sideband offset from the carrier in the frequency
multiplied/divided signal is the same as for the original signal.
\(20\log (N)\)
Rule
If the carrier frequency of a clock is divided down by a factor of
\(N\) then we expect the phase noise to
decrease by \(20\log(N)\).The primary
assumption here is a noiseless conventional digital
divider.
The \(20\log(N)\) rule only applies
to phase noise and not integrated phase noise or phase
jitter. Phase jitter should generally measure about the
same.
What About Phase Jitter?
We integrate SSB phase noise L(f) [dBc/Hz] to
obtain rms phase jitter in seconds as follows for “brick wall”
integration from f1 to f2 offset frequencies in Hz and where f0 is the
carrier or clock frequency.
Note that the rms phase jitter in seconds is inversely proportional
to f0. When frequency is divided down, the phase noise, L(f),
goes down by a factor of 20log(N). However, since the frequency goes
down by N also, the phase jitter expressed in units of time is
constant.
Therefore, phase noise curves, related by 20log(N), with the same
phase noise shape over the jitter bandwidth, are expected to
yield the same phase jitter in seconds.
spurs are carrier or clock frequency spectral
imperfections measured in the frequency domain just like phase noise.
However, unlike phase noise they are discrete frequency
components.
Spurs are deterministic
Spur power is independent of bandwidth
Spurs contribute bounded peak jitter in the time domain
Sources of Spurs:
External (coupling from other noisy block) Supply, substrate, bond
wires, etc.
Internal (int-N/fractional-N operation)
Frac spur: Fractional divider (multi-modulus and
frequency accumulation)
the frequency resolution, is equal to the reference
frequency, meaning that only integer multiples of the reference
frequency can be synthesized
Stability requirements limit the loop bandwidth to about
one tenth of the reference frequency; therefore
decreasing the reference frequency increases the settling time as
the loop bandwidth also has to be decreased
a reduced loop bandwidth allows less suppression of the VCO’s
inherent phase noise
Another drawback of the integer-N PLL is the trade-off
between phase noise and settling time when the divider ratio
becomes large (The contributions to the output phase noise of
almost all PLL building blocks, except the VCO, are multiplied
by the division ratio)
if a small reference frequency is chosen, the reference spur
in the output phase noise is located at a smaller offset
frequency
Fractional-N
Dither Feedback Divider Ratio by a delta-sigma
modulator
Frequency Accumulation
Switched Capacitor Banks
Q: why \(R_b\) ?
A: TODO 📅
Hu, Yizhe. "Flicker noise upconversion and reduction mechanisms in
RF/millimeter-wave oscillators for 5G communications." PhD diss.,
2019.
S. D. Toso, A. Bevilacqua, A. Gerosa and A. Neviani, "A thorough
analysis of the tank quality factor in LC oscillators with switched
capacitor banks," Proceedings of 2010 IEEE International Symposium
on Circuits and Systems, Paris, France, 2010, pp. 1903-1906
False locking
TODO 📅
divider failure
even-stage ring oscillator ( multipath ring oscillators)
DLL: harmonic locking, stuck locking
clock edge impact
ck1 is div2 of ck0
edge of ck0 is affected differently by ck1
edge of ck1 is affected equally by ck0
Tri-gate Clock MUX vs
Pass-gate Clock MUX
TODO 📅
Why Type 2 PLL ?
Type: # of integrators within the loop
Order: # of poles in the closed-loop
transfer function
Type \(\leq\) Order
That is, to have a wide bandwidth, a high loop gain is required
More importantly, the type 1 PLL has the problem of a
static phase error for the change of an input
frequency
A step response test is an easy way to determine the
bandwidth.
Sum a small step into the control voltage of your oscillator
(VCO or NCO), and measure the 90% to 10% fall time of the
corrected response at the output of the loop filter as shown in this
block diagram
a first order loop \[
BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}
\] Where \(BW\) is the 3 dB
bandwidth in Hz and \(𝑡\) is the
10%/90% rise or fall time.
For second order loops with a typical damping factor of 0.7
this relationship is closer to: \[
BW = \frac{0.33}{t}\space\space\space\space \text{(second order system,
damping factor = 0.7)}
\]
Pulse Code Modulation (PCM) is a method for digitally representing
analog signals by sampling their amplitude at regular intervals and then
encoding these samples into binary numbers
Energy/bit (pJ/b)
1mW/Gbps = 1pJ/bit
Joules are a unit of work or energy.
Watts are a unit of power which is the rate at
which energy is generated or consumed.
modulation depth
The modulation index (or
modulation depth) of a modulation scheme
describes by how much the modulated variable of the carrier signal
varies around its unmodulated level
white noise doesn't mean it has a
Gaussian/normal distribution
The only criteria for a (discrete) signal to be
"white" is for each sample to be independently
taken from the same probability distribution
By understanding input signal's statistical nature, we can gather
more insights about certain requirements for our circuits than just from
frequency domain
The Nyquist rate is the minimum sample rate required
to accurately measure a signal's highest frequency. It's equal to
twice the highest frequency of the
signal
Nyquist frequency
The Nyquist frequency is the highest frequency that can be
represented without aliasing in a discrete signal. It's
equal to half the sampling frequency
Oversampling Ratio (OSR) is defined as the ratio of
the Nyquist frequency\(f_s/2\) to the signal bandwidth\(B\) given by \(\text{OSR}=f_s/2B\)
Summation & Integration
impulse response
Transform
ROC
Summation
\(u(t)\)
\(\frac{1}{s}\)
\(\mathfrak{Re}\{s\}\gt 0\)
Integration
\(u[n]\)
\(\frac{1}{1-z^{-1}}\)
\(|z| \gt 1\)
both are NOT stable
sinc function
where \(W\) is sampling frequency in
Hz
sinc function is square integrable but notabsolutely integrable
Zero-order hold (ZOH)
\[
h_{ZOH}(t) = \text{rect}(\frac{t}{T} - \frac{1}{2}) = \left\{
\begin{array}{cl}
1 & : \ 0 \leq t \lt T \\
0 & : \ \text{otherwise}
\end{array} \right.
\] The effective frequency response is the continuous Fourier
transform of the impulse response \[
H_{ZOH}(f) = \mathcal{F}\{h_{ZOH}(t)\} = T\frac{1-e^{j2\pi fT}}{j2\pi
fT}=Te^{-j\pi fT}\text{sinc}(fT)
\] where \(\text{sinc}(x)\) is
the normalized sinc function \(\frac{\sin(\pi
x)}{\pi x}\)
The Laplace transform transfer function of the ZOH is found by
substituting \(s=j2\pi f\)\[
H_{ZOH}(s) = \mathcal{L}\{h_{ZOH}(t)\}=\frac{1-e^{-sT}}{s}
\]
Phase delay directly measures the device or system time delay of
individual sinusoidal frequency components in the
steady-state conditions.
In the ideal case the envelope delay is equal to the phase
delay
envelope delay is a more sensitive measure of aberrations than phase
delay
phase delay
If the phase delay peaks (exceeds the low-frequency value) you can
expect to see high-frequency components late in the step response. This
causes ringing.
group delay
steady-state at this frequency is a polarity flip; a 180 degrees
phase shift; which is a transfer function of H(s)=-1. \[
H(s) = e^{j\pi}
\] That is \(\phi(\omega) =
\pi\)\[
\tau_p = \frac{\pi}{\omega}
\] and \[
\tau_g = \frac{\partial \pi}{\partial \omega}=0
\]
Hollister, Allen L. Wideband Amplifier Design. Raleigh, NC:
SciTech Pub., 2007.
W. Bae, B. Nikolić and D. -K. Jeong, "Use of Phase Delay Analysis for
Evaluating Wideband Circuits: An Alternative to Group Delay Analysis,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 25, no. 12, pp. 3543-3547, Dec. 2017, [https://sci-hub.se/10.1109/TVLSI.2017.2747157]
Convolution of
probability distributions
The probability distribution of the sum of two or more
independent random variables is the
convolution of their individual distributions.
Thermal noise
Thermal noise in an ideal resistor is approximately
white, meaning that its power spectral density is
nearly constant throughout the frequency spectrum.
When limited to a finite bandwidth and viewed in the time
domain, thermal noise has a nearly Gaussian amplitude
distribution
Barkhausen criteria
Barkhausen criteria are necessary but not sufficient
conditions for sustainable oscillations
it simply "latches up" rather than oscillates
System Type
Control of Steady-State Error to Polynomial Inputs: System Type
control systems are assigned a type number according
to the maximum degree of the input polynominal for which the
steady-state error is a finite constant. i.e.
Type 0: Finite error to a step (position error)
Type 1: Finite error to a ramp (velocity error)
Type 2: Finite error to a parabola (acceleration error)
The open-loop transfer function can be expressed as \[
T(s) = \frac{K_n(s)}{s^n}
\]
where we collect all the terms except the pole (\(s\)) at eh origin into \(K_n(s)\),
The polynomial inputs, \(r(t)=\frac{t^k}{k!} u(t)\), whose transform
is \[
R(s) = \frac{1}{s^{k+1}}
\]
Then the equation for the error is simply \[
E(s) = \frac{1}{1+T(s)}R(s)
\]
Application of the Final Value Theorem to the error formula
gives the result
\(H(j\omega)\) is obtained as below
\[
H(j\omega) = \frac{1}{1+j\omega}
\]
Different Variants of
the PSD Definition
In the practice of engineering, it has become customary to use
slightly different variants of the PSD definition, depending on the
particular application or research field.
Two-Sided PSD, \(S_x(f)\)
this is a synonym of the PSD defined as the Fourier Transform of the
autocorrelation.
One-Sided PSD, \(S'_x(f)\)
this is a variant derived from the two-sided PSD by
considering only the positive frequency semi-axis.
To conserve the total power, the value of the
one-sided PSD is twice that of the two-sided PSD \[
S'_x(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_x(f) & : \ f = 0 \\
2S_x(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the one-sided PSD definition makes sense only if the
two-sided is an even function of \(f\)
If \(S'_x(f)\) is even
symmetrical around a positive frequency \(f_0\), then two additional definitions can
be adopted:
Single-Sideband PSD, \(S_{SSB,x}(f)\)
This is obtained from \(S'_x(f)\) by moving the origin of the
frequency axis to \(f_0\)\[
S_{SSB,x}(f) =S'_x(f+f_0)
\] This concept is particularly useful for describing phase or
amplitude modulation schemes in wireless communications, where \(f_0\) is the carrier frequency.
Note that there is no difference in the values of the one-sided
versus the SSB PSD; it is just a pure translation on the frequency
axis.
Double-Sideband PSD, \(S_{DSB,x}(f)\)
this is a variant of the SSB PSD obtained by considering only the
positive frequency semi-axis.
As in the case of the one-sided PSD, to conserve total power, the
value of the DSB PSD is twice that of the SSB \[
S_{DSB,x}(f) = \left\{ \begin{array}{cl}
0 & : \ f \geq 0 \\
S_{SSB,x}(f) & : \ f = 0 \\
2S_{SSB,x}(f) & : \ f \gt 0
\end{array} \right.
\]
Note that the DSB definition makes sense only if the SSB PSD is even
symmetrical around zero
Poles and Zeros of
transfer function
poles
\[
H(s) = \frac{1}{1+s/\omega_0}
\]
magnitude and phase at \(\omega_0\)
and \(-\omega_0\)\[\begin{align}
H(j\omega_0) &= \frac{1}{1+j} = \frac{1}{\sqrt{2}}e^{-j\pi/4} \\
H(-j\omega_0) &= \frac{1}{1-j} = \frac{1}{\sqrt{2}}e^{j\pi/4}
\end{align}\]
Unlike the quantization noise and the thermal noise, the impact of
the clock jitter on the ADC performance depends on the input signal
properties like its PSD
The error between the ideal sampled signal and the
sampling with clock jitter can be treated as noise and it results
in the degradation of the SNR of the ADC
K. Tyagi and B. Razavi, "Performance Bounds of ADC-Based Receivers
Due to Clock Jitter," in IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 70, no. 5, pp. 1749-1753, May 2023 [https://www.seas.ucla.edu/brweb/papers/Journals/KT_TCAS_2023.pdf]
N. Da Dalt, M. Harteneck, C. Sandner and A. Wiesbauer, "On the jitter
requirements of the sampling clock for analog-to-digital converters," in
IEEE Transactions on Circuits and Systems I: Fundamental Theory and
Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002 [https://sci-hub.se/10.1109/TCSI.2002.802353]
M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of
high-speed sampling systems," in IEEE Journal of Solid-State Circuits,
vol. 25, no. 1, pp. 220-224, Feb. 1990 [https://sci-hub.se/10.1109/4.50307]
In both DAC or ADC cases, doubling the timing jitter doubles the
noise level
Also, doubling the frequency or amplitude doubles the jitter induced
noise - SNR is not improved
Boris Murmann ISSCC 2022 SC1: Introduction to ADCs/DACs: Metrics,
Topologies, Trade Space, and Applications [pdf]
S. Kim, K. -Y. Lee and M. Lee, "Modeling Random Clock Jitter Effect
of High-Speed Current-Steering NRZ and RZ DAC," in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp.
2832-2841, Sept. 2018 [https://sci-hub.se/10.1109/TCSI.2018.2821198]
Martin Clara. High-Performance D/A-Converters - Application to
Digital Transceivers, 2013 [pdf]
Chun-Hsien Su (蘇純賢). Design of Oversampled Sigma-Delta Data
Converters. July, 2006 [pdf]
Sampled Thermal Noise
The aliasing of the noise, or noise
folding, plays an important role in switched-capacitor as it
does in all switched-capacitor filters
Assume for the moment that the switch is always closed (that
there is no hold phase), the single-sided noise density would be
\(v_s[n]\) is the sampled version of
\(v_{RC}(t)\), i.e. \(v_s[n]= v_{RC}(nT_C)\)\[
S_s(e^{j\omega}) = \frac{1}{T_C}
\sum_{k=-\infty}^{\infty}S_{RC}(j(\frac{\omega}{T_C}-\frac{2\pi
k}{T_C})) \cdot d\omega
\] where \(\omega \in [-\pi,
\pi]\), furthermore \(\frac{d\omega}{T_C}= d\Omega\)\[
S_s(j\Omega) = \sum_{k=-\infty}^{\infty}S_{RC}(j(\Omega-k\Omega_s))
\cdot d\Omega
\]
The noise in \(S_{RC}\) is a
stationary process and so is uncorrelated over \(f\) allowing the \(N\) rectangles to be combined by simply
summing their noise powers
Matt Pharr, Wenzel Jakob, and Greg Humphreys. 2016. Physically Based
Rendering: From Theory to Implementation (3rd. ed.). Morgan Kaufmann
Publishers Inc., San Francisco, CA, USA.
R. Gregorian and G. C. Temes. Analog MOS Integrated Circuits for
Signal Processing. Wiley-Interscience, 1986
Chembian Thambidurai, "Power Spectral Density of Pulsed Noise
Signals" [link]
White Noise Modulation
Noisy Resistor & Clocked Switch
\[
v_t (t) = v_i(t)\cdot m_t(t)
\]
where \(v_i(t)\) is input
white noise, whose autocorrelation is \(A\delta(\tau)\), and \(m_t(t)\) is periodically operating switch,
then autocorrelation of \(v_t(t)\)\[\begin{align}
R_t (t_1, t_2) &= E[v_t(t_1)\cdot v_t(t_2)] \\
&= R_i(t_1, t_2)\cdot m_t(t_1)m_t(t_2)
\end{align}\]
Then \[\begin{align}
R_t(t, t-\tau) &= R_i(\tau)\cdot m_t(t)m_t(t-\tau) \\
& = A\delta(\tau) \cdot m_t(t)m_t(t-\tau) \\
& = A\delta(\tau) \cdot m_t(t)
\end{align}\] Because \(m_t(t)=m_t(t+T)\), \(R_t(t, t-\tau)\) is is periodic in the
variable \(t\) with period \(T\)
The time-averaged ACF is denoted as \(\tilde{R_t}(\tau)\)
\[
\tilde{R}_{t}(\tau) = m\cdot A\delta(\tau)
\] That is, \[
S_t(f) = m\cdot S_{A}(f)
\]
Much like sinusoidal-steady-state signal analysis,
steady-state noise analysis methods assume an input
\(x(t)\) of infinite
duration, which is a Wide-Sense Stationary (WSS) random
process
Frequency-domain Analysis
Time-domain Analysis
The output \(y(t)\) of a linear
time-invariant (LTI) system \(h(t)\)\[\begin{align}
R_{yy}(\tau) &= R_{xx}(\tau)*[h(\tau)*h(-\tau)] \\
&= S_{xx}(0)\delta(\tau) * [h(\tau)*h(-\tau)] \\
&= S_{xx}(0)[h(\tau)*h(-\tau)] \\
&= S_{xx}(0) \int_\alpha h(\alpha)h(\alpha-\tau)d\alpha
\end{align}\]
with WSS white noise input \(x(t)\),
\(R_{xx}(\tau)=S_{xx}(0)\delta(\tau)\),
therefore
Non-stationary Noise
Assuming the noise applied duration is much less than the time
constant, the output voltage does not reach steady-state and WSS
noise analysis does not apply
In order to determine the response of an LTI system to a step
noise input, the problem is more conveniently solved in the
time-domain
That is \[
\sigma^2_y (t)= R_{yy}(t_1,t_2)|_{t_1=t_2=t}=S_{xx}(0)\int_{-\infty}^t
|h(\tau)|^2d\tau
\]
\(t\), the upper limit of
integration is just intuitive, which lacks strict derivation
Because stable systems have impulse responses that decay to
zero as time goes to infinity, the output
noise variance approaches the WSS result as time approaches
infinity
Frequency-domain Analysis
Because the definition of the PSD assumes that the variance of the
noise process is independent of time, the PSD of a non-stationary
process is not very meaningful
Pharr, Matt; Humphreys, Greg. (28 June 2010). Physically Based
Rendering: From Theory to Implementation. Morgan Kaufmann. ISBN
978-0-12-375079-2. Chapter
7 (Sampling and reconstruction)
Alan V Oppenheim, Ronald W. Schafer. Discrete-Time Signal Processing,
3rd edition
we get \(C_\text{out,eq}=
(1+\frac{1}{A_v})C_c\simeq C_c\)
cascode compensation
Of course, , if the capacitance at the gate of \(M_1\) is taken into account, pole splitting
is less pronounced.
including \(r_\text{o2}\)
\[
\frac{V_{out}}{I_{in}} \approx
\frac{-g_{m1}R_SR_L(g_{m2}+C_Cs)}{\frac{R_S+r_\text{o2}}{r_\text{o2}}R_LC_LC_Cs^2+g_{m1}g_{m2}R_LR_SC_Cs+g_{m2}}
\] The poles as
and zero is not affected, which is \(\omega_z =\frac{g_{m2}}{C_C}\)
the above model simulation result is shown below
the zero is located between two poles
take into the capacitance at the gate of \(M_1\) and all other second-order effect
intuitive analysis of zero
miller compensation
zero in the right half plane \[
g_\text{m1}V_P = sC_c V_P
\]
cascode compensation
zero in the left half plane \[
g_\text{m2}V_X = - sC_c V_X
\]
How to Mitigate Impact of
Zero
dominant pole\[
\omega_\text{p,d} = \frac {1} {R_\text{eq}g_\text{m9}R_{L}C_{c}}
\]first nondominant pole\[
\omega_\text{p,nd} = \frac {g_\text{m4}R_\text{eq}g_\text{m9}} {C_L}
\]zero\[
\omega_\text{z} = (g_\text{m4}R_\text{eq})(\frac {g_\text{m9}} {C_c})
\] a much greater magnitude than \(g_\text{m9}/C_C\)
Lectures
EE 240B: Advanced Analog Circuit Design, Prof. Bernhard E. Boser [OTA
II, Multi-Stage]
Papers
B. K. Ahuja, "An improved frequency compensation technique for CMOS
operational amplifiers," in IEEE Journal of Solid-State Circuits, vol.
18, no. 6, pp. 629-633, Dec. 1983, doi: 10.1109/JSSC.1983.1052012.
D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS
op amps with improved PSRR and common-mode input range," in IEEE Journal
of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984, doi:
10.1109/JSSC.1984.1052246.
Abo, Andrew & Gray, Paul. (1999). A 1.5V, 10-bit, 14MS/s CMOS
Pipeline Analog-to-Digital Converter.
Book's chapters
Design of analog CMOS integrated circuits, Behzad Razavi
10.5 Compensation of Two-Stage Op Amps
10.7 Other Compensation Techniques
Analog Design Essentials, Willy M.C. Sansen
chapter #5 Stability of operational amplifiers - Compensation of
positive zero
Analysis and Design of Analog Integrated Circuits 5th Edition, Paul
R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer
9.4.3 Two-Stage MOS Amplifier Compensation
CMOS Analog Circuit Design 3rd Edition, Phillip E. Allen, Douglas R.
Holberg
6.2.2 Miller Compensation of the Two-Stage Op Amp
Ahuja variations
reference
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\[
(\Delta V_i - \Delta V_x) C_1 = \Delta V_x \cdot C_2
\] Then \[
\Delta V_x = \frac{C_1}{C_1+C_2}\Delta V_i
\]
\[\begin{align}
V_x(s) &= \frac{C_1+C_2}{RC_1C_2}\cdot
\frac{1}{s+\frac{C_1+C_2}{RC_1C_2}}\cdot V_i(s) \\
&= \frac{1}{\tau}\cdot \frac{1}{s+\frac{1}{\tau}}\cdot \frac{1}{s}\\
&= \frac{1}{\tau}\cdot \tau(\frac{1}{s} -
\frac{1}{s+\frac{1}{\tau}})=\frac{1}{s} - \frac{1}{s+\frac{1}{\tau}}
\end{align}\]
\[
\Delta E_{tot} = \frac{1}{2}\cdot\frac{3}{4}C\cdot
V_{ref}^2 - \frac{1}{2}\cdot C\cdot V_{ref}^2 = -\frac{1}{8}CV_{ref}^2
\]
\[
-V_{in}\cdot 2^N C = V_c (2^N C + C_p)
\] Then \(V_c = -\frac{2^N C}{2^N C +
C_p}V_{in}\), i.e. this capacitance reduce the voltage amplitude
by the factor
